178 lines
3.5 KiB
VHDL
Executable File
178 lines
3.5 KiB
VHDL
Executable File
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity shift_unit is
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port(
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a : in std_logic_vector(31 downto 0);
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b : in std_logic_vector(4 downto 0);
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op : in std_logic_vector(2 downto 0);
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r : out std_logic_vector(31 downto 0)
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);
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end shift_unit;
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architecture synth of shift_unit is
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--signal sb : std_logic_vector(4 downto 0);
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signal sl : std_logic_vector(31 downto 0);
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signal sr : std_logic_vector(31 downto 0);
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signal sar : std_logic_vector(31 downto 0);
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begin
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shift_l : process(a,b,op)
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variable v : std_logic_vector(31 downto 0);
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begin
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--if(op(0) = '0') then
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-- sb <= b;
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--else
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-- sb <= std_logic_vector(unsigned(not b)+1);
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--end if;
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v := a;
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-- shift by 1
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if(b(0) = '1')then
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if(op(1)='1') then
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v := v(30 downto 0) & '0';
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else
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v := v(30 downto 0) & v(31);
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end if;
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end if;
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-- shift by 2
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if(b(1) = '1') then
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if(op(1)='1') then
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v := v(29 downto 0) & (1 downto 0 => '0');
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else
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v := v(29 downto 0) & v(31 downto 30);
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end if;
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end if;
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-- shift by 4
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if (b(2) = '1') then
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if(op(1)='1') then
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v := v(27 downto 0) & (3 downto 0 => '0');
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else
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v := v(27 downto 0) & v(31 downto 28);
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end if;
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end if;
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-- shift by 8
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if(b(3) = '1') then
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if(op(1)='1') then
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v := v(23 downto 0) & (7 downto 0 => '0');
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else
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v := v(23 downto 0) & v(31 downto 24);
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end if;
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end if;
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-- shift by 16
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if(b(4) = '1') then
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if(op(1)='1') then
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v := v(15 downto 0) & (15 downto 0 => '0');
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else
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v := v(15 downto 0) & v(31 downto 16);
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end if;
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end if;
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sl <= v;
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end process;
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shift_r : process(a,b,op)
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variable v : std_logic_vector(31 downto 0);
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begin
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--if(op(0) = '0') then
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-- sb <= b;
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--else
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-- sb <= std_logic_vector(unsigned(not b)+1);
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--end if;
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v := a;
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-- shift by 1
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if(b(0) = '1')then
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if(op(1)='1') then
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v := '0' & v(31 downto 1);
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else
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v := v(1) & v(31 downto 1);
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end if;
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end if;
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-- shift by 2
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if(b(1) = '1') then
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if(op(1)='1') then
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v := (1 downto 0 => '0') & v(31 downto 2);
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else
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v := v(1 downto 0) & v(31 downto 2);
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end if;
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end if;
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-- shift by 4
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if (b(2) = '1') then
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if(op(1)='1') then
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v := (3 downto 0 => '0') & v(31 downto 4);
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else
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v := v(3 downto 0) & v(31 downto 4);
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end if;
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end if;
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-- shift by 8
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if(b(3) = '1') then
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if(op(1)='1') then
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v := (7 downto 0 => '0') & v(31 downto 8);
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else
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v := v(7 downto 0) & v(31 downto 8);
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end if;
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end if;
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-- shift by 16
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if(b(4) = '1') then
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if(op(1)='1') then
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v := (15 downto 0 => '0') & v(31 downto 16);
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else
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v := v(15 downto 0) & v(31 downto 16);
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end if;
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end if;
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sr <= v;
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end process;
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shift_ar : process(a,b,op)
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variable v : std_logic_vector(31 downto 0);
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begin
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--if(op(0) = '0') then
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-- sb <= b;
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--else
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-- sb <= std_logic_vector(unsigned(not b)+1);
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--end if;
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v := a;
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-- shift by 1
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if(b(0) = '1')then
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v := v(31) & (v(31) & v(30 downto 1));
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end if;
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-- shift by 2
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if(b(1) = '1') then
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v := v(31) & ((1 downto 0 => v(31)) & v(30 downto 2));
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end if;
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-- shift by 4
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if (b(2) = '1') then
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v := v(31) & ((3 downto 0 => v(31)) & v(30 downto 4));
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end if;
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-- shift by 8
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if(b(3) = '1') then
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v := v(31) & ((7 downto 0 => v(31)) & v(30 downto 8));
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end if;
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-- shift by 16
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if(b(4) = '1') then
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v := v(31) & ((15 downto 0 => v(31)) & v(30 downto 16));
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end if;
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sar <= v;
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end process;
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r<= sar when op = "111" else
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sl when op(0)='0' else
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sr;
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end synth;
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