library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity shift_unit is
    port(
        a  : in  std_logic_vector(31 downto 0);
        b  : in  std_logic_vector(4 downto 0);
        op : in  std_logic_vector(2 downto 0);
        r  : out std_logic_vector(31 downto 0)
    );
end shift_unit;

architecture synth of shift_unit is
	
	--signal sb : std_logic_vector(4 downto 0);
	signal sl : std_logic_vector(31 downto 0);
	signal sr : std_logic_vector(31 downto 0);
	signal sar : std_logic_vector(31 downto 0);
	
begin

	shift_l : process(a,b,op)
		variable v : std_logic_vector(31 downto 0);
	begin
		
		--if(op(0) = '0') then
		--	sb <= b;
		--else
		--	sb <=  std_logic_vector(unsigned(not b)+1);
		--end if;
	
		v := a;
		-- shift by 1
		if(b(0) = '1')then
			if(op(1)='1') then
				v := v(30 downto 0) & '0';
			else
			   v := v(30 downto 0) & v(31);
			end if;
		end if;
		-- shift by 2
		if(b(1) = '1') then
			if(op(1)='1') then
				v := v(29 downto 0) & (1 downto 0 => '0');
			else
			   v := v(29 downto 0) & v(31 downto 30);
			end if;
		end if;
		-- shift by 4
		if (b(2) = '1') then
			if(op(1)='1') then
				v := v(27 downto 0) & (3 downto 0 => '0');
			else
			   v := v(27 downto 0) & v(31 downto 28);
			end if;
		end if;
		-- shift by 8
		if(b(3) = '1') then
			if(op(1)='1') then
				v := v(23 downto 0) & (7 downto 0 => '0');
			else
			   v := v(23 downto 0) & v(31 downto 24);
			end if;
		end if;
		-- shift by 16
		if(b(4) = '1') then
			if(op(1)='1') then
				v := v(15 downto 0) & (15 downto 0 => '0');
			else
			   v := v(15 downto 0) & v(31 downto 16);
			end if;
		end if;		
		
		sl <= v;

	end process;
		
	shift_r : process(a,b,op)
		variable v : std_logic_vector(31 downto 0);
	begin
		
		--if(op(0) = '0') then
		--	sb <= b;
		--else
		--	sb <=  std_logic_vector(unsigned(not b)+1);
		--end if;
	
		v := a;
		-- shift by 1
		if(b(0) = '1')then
			if(op(1)='1') then
				v := '0' & v(31 downto 1);
			else
			   v := v(1) & v(31 downto 1);
			end if;
		end if;
		-- shift by 2
		if(b(1) = '1') then
			if(op(1)='1') then
				v := (1 downto 0 => '0') & v(31 downto 2);
			else
			   v := v(1 downto 0) & v(31 downto 2);
			end if;
		end if;
		-- shift by 4
		if (b(2) = '1') then
			if(op(1)='1') then
				v := (3 downto 0 => '0') & v(31 downto 4);
			else
			   v :=  v(3 downto 0) & v(31 downto 4);
			end if;
		end if;
		-- shift by 8
		if(b(3) = '1') then
			if(op(1)='1') then
				v := (7 downto 0 => '0') & v(31 downto 8);
			else
			   v := v(7 downto 0) & v(31 downto 8);
			end if;
		end if;
		-- shift by 16
		if(b(4) = '1') then
			if(op(1)='1') then
				v := (15 downto 0 => '0') & v(31 downto 16);
			else
			   v := v(15 downto 0) & v(31 downto 16);
			end if;
		end if;

		sr <= v;

	end process;
	
	
	shift_ar : process(a,b,op)
		variable v : std_logic_vector(31 downto 0);
	begin
		
		--if(op(0) = '0') then
		--	sb <= b;
		--else
		--	sb <=  std_logic_vector(unsigned(not b)+1);
		--end if;
	
		v := a;
		-- shift by 1
		if(b(0) = '1')then
				v := v(31) & (v(31) & v(30 downto 1));
		end if;
		-- shift by 2
		if(b(1) = '1') then
				v := v(31) & ((1 downto 0 => v(31)) & v(30 downto 2));
		end if;
		-- shift by 4
		if (b(2) = '1') then
				v := v(31) & ((3 downto 0 => v(31)) & v(30 downto 4));
		end if;
		-- shift by 8
		if(b(3) = '1') then
				v := v(31) & ((7 downto 0 => v(31)) & v(30 downto 8));
		end if;
		-- shift by 16
		if(b(4) = '1') then
				v := v(31) & ((15 downto 0 => v(31)) & v(30 downto 16));
		end if;

		sar <= v;

	end process;
	
	r<= sar when op = "111" else
		 sl when op(0)='0' else
		 sr;
		

end synth;