96 lines
2.3 KiB
VHDL
96 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity WSDriver_tb is
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end WSDriver_tb;
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architecture test of WSDriver_tb is
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constant CLK_PERIOD : time := 20 ns;
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constant N_LED_MAX : integer := 255;
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signal clk : std_logic := '0';
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signal rst_n : std_logic;
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signal led_wr_in : std_logic := '0';
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signal addr_in : std_logic_vector(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0) := (others => '0');
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signal led_in : std_logic_vector(23 downto 0) := (others => '0');
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signal n_wr_in : std_logic := '0';
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signal n_in : std_logic_vector(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0) := (others => '0');
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signal ws_out : std_logic;
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signal ready_out : std_logic;
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begin
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-- Instantiate DUT
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dut : entity work.WSDriver
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generic map (
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F_CLK => 50000000,
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N_LED_MAX => 255
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)
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port map(
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clk => clk,
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rst_n => rst_n,
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led_wr_in => led_wr_in,
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addr_in => addr_in,
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led_in => led_in,
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n_wr_in => n_wr_in,
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n_in => n_in,
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ws_out => ws_out,
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ready_out => ready_out
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);
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-- Clocking process
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clk_generation : process
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begin
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clk <= not clk;
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wait for CLK_PERIOD / 2;
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end process;
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tb : process
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procedure wait_ready is
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begin
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if ready_out /= '1' then
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wait until ready_out = '1';
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end if;
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end procedure wait_ready;
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procedure finish is
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begin
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wait until falling_edge(clk);
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wait_ready;
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wait;
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end procedure finish ;
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begin
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-- Reset
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rst_n <= '0';
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wait for CLK_PERIOD * 2.5;
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rst_n <= '1';
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wait for CLK_PERIOD * 2;
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-- Test set N
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n_in <= std_logic_vector(to_unsigned(3, n_in'length));
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n_wr_in <= '1';
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wait for CLK_PERIOD;
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n_wr_in <= '0';
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wait_ready;
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-- Test write LED value
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addr_in <= std_logic_vector(to_unsigned(0, n_in'length));
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led_in <= "110011001100110011001100";
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led_wr_in <= '1';
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wait for CLK_PERIOD;
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led_wr_in <= '0';
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-- Test finished
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wait_ready;
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finish;
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end process;
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end; |