library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;


entity WSDriver_tb is
end WSDriver_tb;

architecture test of WSDriver_tb is
    constant CLK_PERIOD : time := 20 ns;
    constant N_LED_MAX : integer := 255;

    signal clk : std_logic := '0';
    signal rst_n : std_logic;

    signal led_wr_in   : std_logic := '0';
    signal addr_in     : std_logic_vector(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0) := (others => '0');
    signal led_in      : std_logic_vector(23 downto 0) := (others => '0');

    signal n_wr_in     : std_logic := '0';
    signal n_in        : std_logic_vector(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0) := (others => '0');

    signal ws_out : std_logic;
    signal ready_out : std_logic;

begin
    -- Instantiate DUT
    dut : entity work.WSDriver
    generic map (
        F_CLK => 50000000,
        N_LED_MAX => 255
    )
    port map(
        clk => clk,
        rst_n => rst_n,
        led_wr_in => led_wr_in,
        addr_in => addr_in,
        led_in => led_in,
        n_wr_in => n_wr_in,
        n_in => n_in,
        ws_out => ws_out,
        ready_out => ready_out
    );

    -- Clocking process
    clk_generation : process
    begin
        clk <= not clk;
        wait for CLK_PERIOD / 2;
    end process;

    tb : process 
        procedure wait_ready is
            begin
                if ready_out /= '1' then
                    wait until ready_out = '1';
                end if;
        end procedure wait_ready;

        procedure finish is
        begin
            wait until falling_edge(clk);
            wait_ready;
            wait; 
        end procedure finish ;

    begin
        -- Reset
        rst_n <= '0';
        wait for CLK_PERIOD * 2.5;
        rst_n <= '1';
        wait for CLK_PERIOD * 2;

        -- Test set N
        n_in <= std_logic_vector(to_unsigned(3, n_in'length));
        n_wr_in <= '1';
        wait for CLK_PERIOD;
        n_wr_in <= '0';
        wait_ready;


        -- Test write LED value
        addr_in <= std_logic_vector(to_unsigned(0, n_in'length));
        led_in <= "110011001100110011001100";
        led_wr_in <= '1';
        wait for CLK_PERIOD;
        led_wr_in <= '0';
        
        -- Test finished
        wait_ready;
        finish;

    end process;

end;