274 lines
14 KiB
Plaintext
Executable File
274 lines
14 KiB
Plaintext
Executable File
../vhdl/ROM_Block.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ROM_Block.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity ROM_Block
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-- Compiling architecture SYN of rom_block
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} {} {}} ../vhdl/comparator.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/comparator.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity comparator
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-- Compiling architecture synth of comparator
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} {} {}} ../testbench/check_functions.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/check_functions.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package std_logic_textio
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-- Compiling package check_functions
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-- Compiling package body check_functions
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-- Loading package check_functions
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** Warning: E:/cs208/testbench/check_functions.vhd(49): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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** Warning: E:/cs208/testbench/check_functions.vhd(59): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(65): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(67): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(68): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(83): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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** Warning: E:/cs208/testbench/check_functions.vhd(93): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(99): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(101): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(102): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(117): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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** Warning: E:/cs208/testbench/check_functions.vhd(127): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(133): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(135): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(136): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(151): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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** Warning: E:/cs208/testbench/check_functions.vhd(161): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(167): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(169): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
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** Warning: E:/cs208/testbench/check_functions.vhd(170): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
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} {} {}} ../vhdl/extend.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/extend.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity extend
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-- Compiling architecture synth of extend
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} {} {}} ../vhdl/mux2x5.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x5.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity mux2x5
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-- Compiling architecture synth of mux2x5
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} {} {}} ../vhdl/ALU.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ALU.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity ALU
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-- Compiling architecture bdf_type of ALU
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} {} {}} ../vhdl/add_sub.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/add_sub.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package NUMERIC_STD
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-- Compiling entity add_sub
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-- Compiling architecture synth of add_sub
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} {} {}} ../vhdl/PC.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/PC.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package NUMERIC_STD
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-- Compiling entity PC
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-- Compiling architecture synth of PC
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} {} {}} ../vhdl/multiplexer.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/multiplexer.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity multiplexer
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-- Compiling architecture synth of multiplexer
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} {} {}} ../vhdl/IR.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/IR.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity IR
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-- Compiling architecture synth of IR
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} {} {}} ../vhdl/controller.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/controller.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity controller
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-- Compiling architecture synth of controller
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} {} {}} ../vhdl/register_file.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/register_file.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package NUMERIC_STD
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-- Compiling entity register_file
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-- Compiling architecture synth of register_file
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} {} {}} ../vhdl/ROM.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ROM.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package NUMERIC_STD
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-- Compiling entity ROM
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-- Compiling architecture synth of ROM
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} {} {}} ../vhdl/buttons.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/buttons.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package NUMERIC_STD
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-- Compiling entity buttons
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-- Compiling architecture synth of buttons
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} {} {}} ../testbench/tb_Extend.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_Extend.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package std_logic_textio
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-- Loading package check_functions
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-- Compiling entity tb_Extend
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-- Compiling architecture testbench of tb_Extend
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** Warning: E:/cs208/testbench/tb_Extend.vhd(40): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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** Warning: E:/cs208/testbench/tb_Extend.vhd(42): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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} {} {}} ../vhdl/RAM.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/RAM.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package NUMERIC_STD
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-- Compiling entity RAM
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-- Compiling architecture synth of RAM
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} {} {}} ../vhdl/LEDs.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/LEDs.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package NUMERIC_STD
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-- Compiling entity LEDs
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-- Compiling architecture synth of LEDs
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} {} {}} ../vhdl/CPU.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/CPU.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity CPU
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-- Compiling architecture bdf_type of CPU
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} {} {}} ../testbench/tb_GECKO.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_GECKO.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity tb_GECKO
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-- Compiling architecture testbench of tb_GECKO
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-- Loading entity GECKO
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} {} {}} ../vhdl/GECKO.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/GECKO.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity GECKO
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-- Compiling architecture bdf_type of GECKO
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} {} {}} ../vhdl/mux2x32.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x32.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity mux2x32
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-- Compiling architecture synth of mux2x32
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} {} {}} ../testbench/tb_IR.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_IR.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package std_logic_textio
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-- Loading package check_functions
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-- Compiling entity tb_IR
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-- Compiling architecture testbench of tb_IR
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** Warning: E:/cs208/testbench/tb_IR.vhd(42): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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** Warning: E:/cs208/testbench/tb_IR.vhd(44): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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} {} {}} ../testbench/tb_PC.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_PC.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package std_logic_textio
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-- Loading package check_functions
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-- Compiling entity tb_PC
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-- Compiling architecture testbench of tb_PC
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** Warning: E:/cs208/testbench/tb_PC.vhd(57): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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** Warning: E:/cs208/testbench/tb_PC.vhd(59): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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} {} {}} ../vhdl/mux2x16.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x16.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity mux2x16
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-- Compiling architecture synth of mux2x16
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} {} {}} ../testbench/tb_Controller.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_Controller.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package NUMERIC_STD
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-- Loading package std_logic_textio
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-- Loading package check_functions
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-- Compiling entity tb_Controller
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-- Compiling architecture testbench of tb_Controller
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** Warning: E:/cs208/testbench/tb_Controller.vhd(129): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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** Warning: E:/cs208/testbench/tb_Controller.vhd(130): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
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} {} {}} ../vhdl/logic_unit.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/logic_unit.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity logic_unit
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-- Compiling architecture synth of logic_unit
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} {} {}} ../vhdl/shift_unit.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/shift_unit.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package NUMERIC_STD
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-- Compiling entity shift_unit
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-- Compiling architecture synth of shift_unit
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} {} {}} ../vhdl/decoder.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/decoder.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity decoder
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-- Compiling architecture synth of decoder
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} {} {}}
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