epfl-archive/cs208-ca/modelsim/multicycle_niosII.cr.mti

../vhdl/ROM_Block.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ROM_Block.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ROM_Block
-- Compiling architecture SYN of rom_block

} {} {}} ../vhdl/comparator.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/comparator.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity comparator
-- Compiling architecture synth of comparator

} {} {}} ../testbench/check_functions.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/check_functions.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Compiling package check_functions
-- Compiling package body check_functions
-- Loading package check_functions
** Warning: E:/cs208/testbench/check_functions.vhd(49): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(59): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(65): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(67): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(68): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(83): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(93): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(99): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(101): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(102): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(117): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(127): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(133): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(135): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(136): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(151): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(161): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(167): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(169): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(170): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".

} {} {}} ../vhdl/extend.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/extend.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity extend
-- Compiling architecture synth of extend

} {} {}} ../vhdl/mux2x5.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x5.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x5
-- Compiling architecture synth of mux2x5

} {} {}} ../vhdl/ALU.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ALU.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ALU
-- Compiling architecture bdf_type of ALU

} {} {}} ../vhdl/add_sub.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/add_sub.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity add_sub
-- Compiling architecture synth of add_sub

} {} {}} ../vhdl/PC.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/PC.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity PC
-- Compiling architecture synth of PC

} {} {}} ../vhdl/multiplexer.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/multiplexer.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity multiplexer
-- Compiling architecture synth of multiplexer

} {} {}} ../vhdl/IR.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/IR.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity IR
-- Compiling architecture synth of IR

} {} {}} ../vhdl/controller.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/controller.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity controller
-- Compiling architecture synth of controller

} {} {}} ../vhdl/register_file.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/register_file.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity register_file
-- Compiling architecture synth of register_file

} {} {}} ../vhdl/ROM.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ROM.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity ROM
-- Compiling architecture synth of ROM

} {} {}} ../vhdl/buttons.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/buttons.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity buttons
-- Compiling architecture synth of buttons

} {} {}} ../testbench/tb_Extend.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_Extend.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_Extend
-- Compiling architecture testbench of tb_Extend
** Warning: E:/cs208/testbench/tb_Extend.vhd(40): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_Extend.vhd(42): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.

} {} {}} ../vhdl/RAM.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/RAM.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity RAM
-- Compiling architecture synth of RAM

} {} {}} ../vhdl/LEDs.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/LEDs.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity LEDs
-- Compiling architecture synth of LEDs

} {} {}} ../vhdl/CPU.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/CPU.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity CPU
-- Compiling architecture bdf_type of CPU

} {} {}} ../testbench/tb_GECKO.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_GECKO.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity tb_GECKO
-- Compiling architecture testbench of tb_GECKO
-- Loading entity GECKO

} {} {}} ../vhdl/GECKO.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/GECKO.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity GECKO
-- Compiling architecture bdf_type of GECKO

} {} {}} ../vhdl/mux2x32.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x32.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x32
-- Compiling architecture synth of mux2x32

} {} {}} ../testbench/tb_IR.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_IR.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_IR
-- Compiling architecture testbench of tb_IR
** Warning: E:/cs208/testbench/tb_IR.vhd(42): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_IR.vhd(44): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.

} {} {}} ../testbench/tb_PC.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_PC.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_PC
-- Compiling architecture testbench of tb_PC
** Warning: E:/cs208/testbench/tb_PC.vhd(57): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_PC.vhd(59): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.

} {} {}} ../vhdl/mux2x16.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x16.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x16
-- Compiling architecture synth of mux2x16

} {} {}} ../testbench/tb_Controller.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_Controller.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_Controller
-- Compiling architecture testbench of tb_Controller
** Warning: E:/cs208/testbench/tb_Controller.vhd(129): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_Controller.vhd(130): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.

} {} {}} ../vhdl/logic_unit.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/logic_unit.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity logic_unit
-- Compiling architecture synth of logic_unit

} {} {}} ../vhdl/shift_unit.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/shift_unit.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity shift_unit
-- Compiling architecture synth of shift_unit

} {} {}} ../vhdl/decoder.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/decoder.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity decoder
-- Compiling architecture synth of decoder

} {} {}}