Disabled external gits
This commit is contained in:
1067 files changed
+102374
-6
No files matched your search
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
+7
@@ -0,0 +1,7 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543268781242 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543268781242 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 22:46:21 2018 " "Processing started: Mon Nov 26 22:46:21 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543268781242 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1543268781242 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=on --write_settings_files=off GECKO -c GECKO " "Command: quartus_asm --read_settings_files=on --write_settings_files=off GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1543268781242 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1543268782929 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1543268783929 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1543268784117 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4705 " "Peak virtual memory: 4705 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543268785476 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 22:46:25 2018 " "Processing ended: Mon Nov 26 22:46:25 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543268785476 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543268785476 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543268785476 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1543268785476 ""}
|
||||
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
+176
@@ -0,0 +1,176 @@
|
||||
v1
|
||||
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
|
||||
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
|
||||
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
|
||||
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
|
||||
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
|
||||
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
|
||||
IO_RULES_MATRIX,Total Pass,135;0;135;0;0;135;135;0;135;135;0;0;0;0;7;0;0;7;0;0;0;0;0;0;0;0;0;135;0;0,
|
||||
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,Total Inapplicable,0;135;0;135;135;0;0;135;0;0;135;135;135;135;128;135;135;128;135;135;135;135;135;135;135;135;135;0;135;135,
|
||||
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,row1[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row6[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row7[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,row8[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[30],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[29],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[28],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[27],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[26],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[25],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[24],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[23],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[22],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[21],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[20],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[19],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[18],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,seg_out[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,in_buttons[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,in_buttons[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,in_buttons[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,in_buttons[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,in_buttons[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,reset_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_SUMMARY,Total I/O Rules,30,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
|
||||
Executable
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
Executable
+3
@@ -0,0 +1,3 @@
|
||||
Quartus_Version = Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
|
||||
Version_Index = 469919232
|
||||
Creation_Time = Mon Nov 26 21:57:04 2018
|
||||
Executable
+50
@@ -0,0 +1,50 @@
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1543265880814 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1543265880892 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GECKO EP4CE30F23C8 " "Selected device EP4CE30F23C8 for design \"GECKO\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1543265880944 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1543265881046 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1543265881046 ""}
|
||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1543265881347 ""}
|
||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1543265881363 ""}
|
||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F23C8 " "Device EP4CE15F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1543265881990 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F23C8 " "Device EP4CE40F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1543265881990 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F23C8 " "Device EP4CE55F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1543265881990 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F23C8 " "Device EP4CE75F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1543265881990 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F23C8 " "Device EP4CE115F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1543265881990 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1543265881990 ""}
|
||||
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 5567 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1543265882015 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 5569 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1543265882015 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 5571 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1543265882015 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 5573 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1543265882015 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1543265882015 ""}
|
||||
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1543265882047 ""}
|
||||
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1543265882238 ""}
|
||||
{ "Info" "ISTA_SDC_FOUND" "GECKO.sdc " "Reading SDC File: 'GECKO.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1543265883651 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1543265883651 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1543265883683 ""}
|
||||
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1543265883683 ""}
|
||||
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1543265883683 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1543265883683 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 clk " " 20.000 clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1543265883683 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1543265883683 ""}
|
||||
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN T1 (CLK3, DIFFCLK_1n)) " "Automatically promoted node clk~input (placed in PIN T1 (CLK3, DIFFCLK_1n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1543265883933 ""} } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 352 -24 144 368 "clk" "" } } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 5554 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1543265883933 ""}
|
||||
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset_n~input (placed in PIN AB11 (CLK14, DIFFCLK_6n)) " "Automatically promoted node reset_n~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1543265883933 ""} } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 368 -24 144 384 "reset_n" "" } } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 5560 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1543265883933 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1543265884589 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1543265884589 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1543265884589 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1543265884604 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1543265884604 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1543265884604 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1543265884604 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1543265884620 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1543265884729 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1543265884729 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1543265884729 ""}
|
||||
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "BUTTONS\[4\] " "Node \"BUTTONS\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTONS\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1543265885011 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "BUTTONS\[5\] " "Node \"BUTTONS\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTONS\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1543265885011 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "BUTTONS\[6\] " "Node \"BUTTONS\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTONS\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1543265885011 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_BA\[0\] " "Node \"SDRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1543265885011 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_BA\[1\] " "Node \"SDRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1543265885011 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_CKE " "Node \"SDRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1543265885011 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_CLK " "Node \"SDRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1543265885011 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_DQM\[0\] " "Node \"SDRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1543265885011 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_DQM\[1\] " "Node \"SDRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1543265885011 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[0\] " "Node \"SDRAM_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1543265885011 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[10\] " "Node \"SDRAM_D\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_Line truncated
|
||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1543265885042 ""}
|
||||
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1543265885058 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1543265886308 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1543265886865 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1543265886912 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1543265891919 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:05 " "Fitter placement operations ending: elapsed time is 00:00:05" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1543265891919 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1543265892716 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "24 X34_Y22 X44_Y32 " "Router estimated peak interconnect usage is 24% of the available device resources in the region that extends from location X34_Y22 to location X44_Y32" { } { { "loc" "" { Generic "F:/kkk/quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 24% of the available device resources in the region that extends from location X34_Y22 to location X44_Y32"} { { 12 { 0 ""} 34 22 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1543265895679 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1543265895679 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1543265958716 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1543265958716 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1543265958716 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:01:05 " "Fitter routing operations ending: elapsed time is 00:01:05" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1543265958841 ""}
|
||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 2.39 " "Total time spent on timing analysis during the Fitter is 2.39 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1543265959466 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1543265959481 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1543265959950 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1543265959950 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1543265960591 ""}
|
||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1543265961481 ""}
|
||||
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1543265962231 ""}
|
||||
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "7 Cyclone IV E " "7 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk 3.3-V LVTTL T1 " "Pin clk uses I/O standard 3.3-V LVTTL at T1" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { clk } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 352 -24 144 368 "clk" "" } } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 159 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1543265962262 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[0\] 3.3-V LVTTL B11 " "Pin in_buttons\[0\] uses I/O standard 3.3-V LVTTL at B11" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[0] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[0\]" } } } } { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 208 1560 1576 376 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 42 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1543265962262 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[1\] 3.3-V LVTTL A11 " "Pin in_buttons\[1\] uses I/O standard 3.3-V LVTTL at A11" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[1] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[1\]" } } } } { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 208 1560 1576 376 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 41 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1543265962262 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[2\] 3.3-V LVTTL B12 " "Pin in_buttons\[2\] uses I/O standard 3.3-V LVTTL at B12" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[2] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[2\]" } } } } { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 208 1560 1576 376 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 40 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1543265962262 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[3\] 3.3-V LVTTL A12 " "Pin in_buttons\[3\] uses I/O standard 3.3-V LVTTL at A12" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[3] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[3\]" } } } } { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 208 1560 1576 376 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 39 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1543265962262 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[4\] 3.3-V LVTTL G22 " "Pin in_buttons\[4\] uses I/O standard 3.3-V LVTTL at G22" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[4] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[4\]" } } } } { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 208 1560 1576 376 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "F:/kkk/quartus/" { { 0 { 0 ""} 0 38 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1543265962262 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "reset_n 3.3-V LVTTL AB11 Line truncated
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/kkk/quartus/GECKO.fit.smsg " "Generated suppressed messages file F:/kkk/quartus/GECKO.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1543265962669 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 60 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 60 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5647 " "Peak virtual memory: 5647 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543265964247 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 21:59:24 2018 " "Processing ended: Mon Nov 26 21:59:24 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543265964247 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:25 " "Elapsed time: 00:01:25" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543265964247 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:35 " "Total CPU time (on all processors): 00:01:35" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543265964247 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1543265964247 ""}
|
||||
Executable
+2266
File diff suppressed because it is too large.
Load diff
Executable
BIN
Binary file not shown.
Executable
+210
@@ -0,0 +1,210 @@
|
||||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst1</TD>
|
||||
<TD >26</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst3</TD>
|
||||
<TD >19</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst2</TD>
|
||||
<TD >43</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >RAM_0|ram_inst</TD>
|
||||
<TD >46</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >RAM_0</TD>
|
||||
<TD >46</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >ROM_0|ROM_inst|iD_s_30739CAe_5A20DAf5_E|altsyncram_component|auto_generated</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >ROM_0|ROM_inst|iD_s_30739CAe_5A20DAf5_E</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >ROM_0|ROM_inst</TD>
|
||||
<TD >13</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >ROM_0</TD>
|
||||
<TD >13</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >decoder_0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >LEDs_0</TD>
|
||||
<TD >39</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >128</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
Executable
BIN
Binary file not shown.
Executable
+18
@@ -0,0 +1,18 @@
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+-----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; inst1 ; 26 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; inst3 ; 19 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; inst2 ; 43 ; 0 ; 32 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; RAM_0|ram_inst ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; RAM_0 ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; ROM_0|ROM_inst|iD_s_30739CAe_5A20DAf5_E|altsyncram_component|auto_generated ; 11 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; ROM_0|ROM_inst|iD_s_30739CAe_5A20DAf5_E ; 11 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; ROM_0|ROM_inst ; 13 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; ROM_0 ; 13 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; inst ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; decoder_0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; LEDs_0 ; 39 ; 0 ; 0 ; 0 ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+-----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
+1
@@ -0,0 +1 @@
|
||||
v1
|
||||
Executable
+46
@@ -0,0 +1,46 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543265857431 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543265857431 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 21:57:37 2018 " "Processing started: Mon Nov 26 21:57:37 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543265857431 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265857431 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GECKO -c GECKO " "Command: quartus_map --read_settings_files=on --write_settings_files=off GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265857431 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1543265858574 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1543265858574 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder-decoder_0.qxp 1 1 " "Found 1 design units, including 1 entities, in source file decoder-decoder_0.qxp" { { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Found entity 1: decoder" { } { { "decoder-decoder_0.qxp" "" { Text "F:/kkk/quartus/decoder-decoder_0.qxp" -1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265869509 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265869509 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu-inst.qxp 1 1 " "Found 1 design units, including 1 entities, in source file cpu-inst.qxp" { { "Info" "ISGN_ENTITY_NAME" "1 CPU " "Found entity 1: CPU" { } { { "CPU-inst.qxp" "" { Text "F:/kkk/quartus/CPU-inst.qxp" -1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265870134 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265870134 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gecko.bdf 1 1 " "Found 1 design units, including 1 entities, in source file gecko.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 GECKO " "Found entity 1: GECKO" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265870290 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265870290 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/kkk/vhdl/buttons.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /kkk/vhdl/buttons.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 buttons-synth " "Found design unit 1: buttons-synth" { } { { "../vhdl/buttons.vhd" "" { Text "F:/kkk/vhdl/buttons.vhd" 22 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265870900 ""} { "Info" "ISGN_ENTITY_NAME" "1 buttons " "Found entity 1: buttons" { } { { "../vhdl/buttons.vhd" "" { Text "F:/kkk/vhdl/buttons.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265870900 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265870900 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/kkk/vhdl/leds.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /kkk/vhdl/leds.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LEDs-synth " "Found design unit 1: LEDs-synth" { } { { "../vhdl/LEDs.vhd" "" { Text "F:/kkk/vhdl/LEDs.vhd" 22 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265870931 ""} { "Info" "ISGN_ENTITY_NAME" "1 LEDs " "Found entity 1: LEDs" { } { { "../vhdl/LEDs.vhd" "" { Text "F:/kkk/vhdl/LEDs.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265870931 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265870931 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/kkk/vhdl/ram.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /kkk/vhdl/ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RAM-synth " "Found design unit 1: RAM-synth" { } { { "../vhdl/RAM.vhd" "" { Text "F:/kkk/vhdl/RAM.vhd" 1 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265870946 ""} { "Info" "ISGN_ENTITY_NAME" "1 RAM " "Found entity 1: RAM" { } { { "../vhdl/RAM.vhd" "" { Text "F:/kkk/vhdl/RAM.vhd" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265870946 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265870946 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/kkk/vhdl/rom.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /kkk/vhdl/rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ROM-synth " "Found design unit 1: ROM-synth" { } { { "../vhdl/ROM.vhd" "" { Text "F:/kkk/vhdl/ROM.vhd" 1 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871087 ""} { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" { } { { "../vhdl/ROM.vhd" "" { Text "F:/kkk/vhdl/ROM.vhd" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871087 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265871087 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/kkk/vhdl/rom_block.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /kkk/vhdl/rom_block.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom_block-SYN " "Found design unit 1: rom_block-SYN" { } { { "../vhdl/ROM_Block.vhd" "" { Text "F:/kkk/vhdl/ROM_Block.vhd" 52 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871103 ""} { "Info" "ISGN_ENTITY_NAME" "1 ROM_Block " "Found entity 1: ROM_Block" { } { { "../vhdl/ROM_Block.vhd" "" { Text "F:/kkk/vhdl/ROM_Block.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871103 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265871103 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/kkk/vhdl/ram_obfuscated.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /kkk/vhdl/ram_obfuscated.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 iD_s_B88A4C5_7e3415fF_E-ID_s_10643F3B_2fc543eB_E " "Found design unit 1: iD_s_B88A4C5_7e3415fF_E-ID_s_10643F3B_2fc543eB_E" { } { { "../vhdl/RAM_obfuscated.vhd" "" { Text "F:/kkk/vhdl/RAM_obfuscated.vhd" 1 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871290 ""} { "Info" "ISGN_ENTITY_NAME" "1 ID_S_B88a4C5_7E3415Ff_e " "Found entity 1: ID_S_B88a4C5_7E3415Ff_e" { } { { "../vhdl/RAM_obfuscated.vhd" "" { Text "F:/kkk/vhdl/RAM_obfuscated.vhd" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871290 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265871290 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/kkk/vhdl/rom_obfuscated.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /kkk/vhdl/rom_obfuscated.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 id_s_B88a693_7E3412f0_E-id_s_455b727d_1f58D85f_e " "Found design unit 1: id_s_B88a693_7E3412f0_E-id_s_455b727d_1f58D85f_e" { } { { "../vhdl/ROM_obfuscated.vhd" "" { Text "F:/kkk/vhdl/ROM_obfuscated.vhd" 1 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871446 ""} { "Info" "ISGN_ENTITY_NAME" "1 iD_S_b88a693_7e3412F0_e " "Found entity 1: iD_S_b88a693_7e3412F0_e" { } { { "../vhdl/ROM_obfuscated.vhd" "" { Text "F:/kkk/vhdl/ROM_obfuscated.vhd" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871446 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265871446 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/kkk/vhdl/seven_seg.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /kkk/vhdl/seven_seg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seven_seg-rtl " "Found design unit 1: seven_seg-rtl" { } { { "../vhdl/seven_seg.vhd" "" { Text "F:/kkk/vhdl/seven_seg.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871603 ""} { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "../vhdl/seven_seg.vhd" "" { Text "F:/kkk/vhdl/seven_seg.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871603 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265871603 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/kkk/vhdl/randgen.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /kkk/vhdl/randgen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 randgen-rtl " "Found design unit 1: randgen-rtl" { } { { "../vhdl/randgen.vhd" "" { Text "F:/kkk/vhdl/randgen.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871618 ""} { "Info" "ISGN_ENTITY_NAME" "1 randgen " "Found entity 1: randgen" { } { { "../vhdl/randgen.vhd" "" { Text "F:/kkk/vhdl/randgen.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265871618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265871618 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GECKO " "Elaborating entity \"GECKO\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1543265871962 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LEDs LEDs:LEDs_0 " "Elaborating entity \"LEDs\" for hierarchy \"LEDs:LEDs_0\"" { } { { "GECKO.bdf" "LEDs_0" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 160 1040 1176 336 "LEDs_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265872150 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:decoder_0 " "Elaborating entity \"decoder\" for hierarchy \"decoder:decoder_0\"" { } { { "GECKO.bdf" "decoder_0" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 96 408 544 232 "decoder_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265872306 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CPU CPU:inst " "Elaborating entity \"CPU\" for hierarchy \"CPU:inst\"" { } { { "GECKO.bdf" "inst" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265872571 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:ROM_0 " "Elaborating entity \"ROM\" for hierarchy \"ROM:ROM_0\"" { } { { "GECKO.bdf" "ROM_0" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 176 616 736 296 "ROM_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265872993 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "iD_S_b88a693_7e3412F0_e ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst " "Elaborating entity \"iD_S_b88a693_7e3412F0_e\" for hierarchy \"ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\"" { } { { "../vhdl/ROM.vhd" "ROM_inst" { Text "F:/kkk/vhdl/ROM.vhd" 1 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265873009 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM_Block ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\|ROM_Block:iD_s_30739CAe_5A20DAf5_E " "Elaborating entity \"ROM_Block\" for hierarchy \"ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\|ROM_Block:iD_s_30739CAe_5A20DAf5_E\"" { } { { "../vhdl/ROM_obfuscated.vhd" "iD_s_30739CAe_5A20DAf5_E" { Text "F:/kkk/vhdl/ROM_obfuscated.vhd" 1 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265873009 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\|ROM_Block:iD_s_30739CAe_5A20DAf5_E\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\|ROM_Block:iD_s_30739CAe_5A20DAf5_E\|altsyncram:altsyncram_component\"" { } { { "../vhdl/ROM_Block.vhd" "altsyncram_component" { Text "F:/kkk/vhdl/ROM_Block.vhd" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265873228 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\|ROM_Block:iD_s_30739CAe_5A20DAf5_E\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\|ROM_Block:iD_s_30739CAe_5A20DAf5_E\|altsyncram:altsyncram_component\"" { } { { "../vhdl/ROM_Block.vhd" "" { Text "F:/kkk/vhdl/ROM_Block.vhd" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265873259 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\|ROM_Block:iD_s_30739CAe_5A20DAf5_E\|altsyncram:altsyncram_component " "Instantiated megafunction \"ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\|ROM_Block:iD_s_30739CAe_5A20DAf5_E\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ../quartus/ROM.hex " "Parameter \"init_file\" = \"../quartus/ROM.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265873259 ""} } { { "../vhdl/ROM_Block.vhd" "" { Text "F:/kkk/vhdl/ROM_Block.vhd" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1543265873259 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rna1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_rna1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rna1 " "Found entity 1: altsyncram_rna1" { } { { "db/altsyncram_rna1.tdf" "" { Text "F:/kkk/quartus/db/altsyncram_rna1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265873353 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265873353 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_rna1 ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\|ROM_Block:iD_s_30739CAe_5A20DAf5_E\|altsyncram:altsyncram_component\|altsyncram_rna1:auto_generated " "Elaborating entity \"altsyncram_rna1\" for hierarchy \"ROM:ROM_0\|iD_S_b88a693_7e3412F0_e:ROM_inst\|ROM_Block:iD_s_30739CAe_5A20DAf5_E\|altsyncram:altsyncram_component\|altsyncram_rna1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265873368 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM RAM:RAM_0 " "Elaborating entity \"RAM\" for hierarchy \"RAM:RAM_0\"" { } { { "GECKO.bdf" "RAM_0" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 176 816 960 296 "RAM_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265873478 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ID_S_B88a4C5_7E3415Ff_e RAM:RAM_0\|ID_S_B88a4C5_7E3415Ff_e:ram_inst " "Elaborating entity \"ID_S_B88a4C5_7E3415Ff_e\" for hierarchy \"RAM:RAM_0\|ID_S_B88a4C5_7E3415Ff_e:ram_inst\"" { } { { "../vhdl/RAM.vhd" "ram_inst" { Text "F:/kkk/vhdl/RAM.vhd" 1 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265873587 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "buttons buttons:inst2 " "Elaborating entity \"buttons\" for hierarchy \"buttons:inst2\"" { } { { "GECKO.bdf" "inst2" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 144 1344 1544 320 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265873587 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "randgen randgen:inst3 " "Elaborating entity \"randgen\" for hierarchy \"randgen:inst3\"" { } { { "GECKO.bdf" "inst3" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 496 928 1136 608 "inst3" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265873603 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg:inst1 " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg:inst1\"" { } { { "GECKO.bdf" "inst1" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 80 1608 1720 296 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265873618 ""}
|
||||
{ "Warning" "WSGN_TIMING_DRIVEN_SYNTHESIS_IMPORTED_PARTITION" "" "Synthesis found one or more imported partitions that will be treated as black boxes for timing analysis during synthesis" { } { } 0 12240 "Synthesis found one or more imported partitions that will be treated as black boxes for timing analysis during synthesis" 0 0 "Analysis & Synthesis" 0 -1 1543265874493 ""}
|
||||
{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[31\]\" " "Converted tri-state node \"rddata\[31\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[30\]\" " "Converted tri-state node \"rddata\[30\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[29\]\" " "Converted tri-state node \"rddata\[29\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[28\]\" " "Converted tri-state node \"rddata\[28\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[27\]\" " "Converted tri-state node \"rddata\[27\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[26\]\" " "Converted tri-state node \"rddata\[26\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[25\]\" " "Converted tri-state node \"rddata\[25\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[24\]\" " "Converted tri-state node \"rddata\[24\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[23\]\" " "Converted tri-state node \"rddata\[23\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[22\]\" " "Converted tri-state node \"rddata\[22\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[21\]\" " "Converted tri-state node \"rddata\[21\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[20\]\" " "Converted tri-state node \"rddata\[20\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[19\]\" " "Converted tri-state node \"rddata\[19\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[18\]\" " "Converted tri-state node \"rddata\[18\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1543265874759 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[17\]\" " "Converted tri-state node \"rddata\[17\]\" into a selector" { } { { "GECKO.bdf" "" { Schematic "F:/kkk/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } Line truncated
|
||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "RAM:RAM_0\|ID_S_B88a4C5_7E3415Ff_e:ram_inst\|Id_S_B889004_7e48Ff67_e_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"RAM:RAM_0\|ID_S_B88a4C5_7E3415Ff_e:ram_inst\|Id_S_B889004_7e48Ff67_e_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE SINGLE_PORT " "Parameter OPERATION_MODE set to SINGLE_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1543265875071 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 32 " "Parameter WIDTH_A set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1543265875071 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 10 " "Parameter WIDTHAD_A set to 10" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1543265875071 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 1024 " "Parameter NUMWORDS_A set to 1024" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1543265875071 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Parameter OUTDATA_REG_A set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1543265875071 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1543265875071 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Parameter OUTDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1543265875071 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1543265875071 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1543265875071 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1543265875071 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1543265875071 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "RAM:RAM_0\|ID_S_B88a4C5_7E3415Ff_e:ram_inst\|altsyncram:Id_S_B889004_7e48Ff67_e_rtl_0 " "Elaborated megafunction instantiation \"RAM:RAM_0\|ID_S_B88a4C5_7E3415Ff_e:ram_inst\|altsyncram:Id_S_B889004_7e48Ff67_e_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265875149 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "RAM:RAM_0\|ID_S_B88a4C5_7E3415Ff_e:ram_inst\|altsyncram:Id_S_B889004_7e48Ff67_e_rtl_0 " "Instantiated megafunction \"RAM:RAM_0\|ID_S_B88a4C5_7E3415Ff_e:ram_inst\|altsyncram:Id_S_B889004_7e48Ff67_e_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE SINGLE_PORT " "Parameter \"OPERATION_MODE\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265875149 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 32 " "Parameter \"WIDTH_A\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265875149 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 10 " "Parameter \"WIDTHAD_A\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265875149 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 1024 " "Parameter \"NUMWORDS_A\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265875149 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265875149 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265875149 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265875149 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265875149 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1543265875149 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1543265875149 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vh41.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_vh41.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vh41 " "Found entity 1: altsyncram_vh41" { } { { "db/altsyncram_vh41.tdf" "" { Text "F:/kkk/quartus/db/altsyncram_vh41.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1543265875259 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265875259 ""}
|
||||
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "../vhdl/LEDs.vhd" "" { Text "F:/kkk/vhdl/LEDs.vhd" 90 -1 0 } } { "../vhdl/buttons.vhd" "" { Text "F:/kkk/vhdl/buttons.vhd" 37 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1543265875852 ""}
|
||||
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1543265875852 ""}
|
||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265876040 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1543265877618 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1543265877618 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "3876 " "Implemented 3876 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "7 " "Implemented 7 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1543265878008 ""} { "Info" "ICUT_CUT_TM_OPINS" "128 " "Implemented 128 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1543265878008 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3677 " "Implemented 3677 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1543265878008 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1543265878008 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1543265878008 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4846 " "Peak virtual memory: 4846 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543265878118 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 21:57:58 2018 " "Processing ended: Mon Nov 26 21:57:58 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543265878118 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Elapsed time: 00:00:21" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543265878118 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:30 " "Total CPU time (on all processors): 00:00:30" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543265878118 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1543265878118 ""}
|
||||
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
+1
@@ -0,0 +1 @@
|
||||
v1
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543268778497 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "MIF/HEX Update Quartus Prime " "Running Quartus Prime MIF/HEX Update" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543268778513 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 22:46:17 2018 " "Processing started: Mon Nov 26 22:46:17 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543268778513 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1543268778513 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb GECKO -c GECKO --update_mif " "Command: quartus_cdb GECKO -c GECKO --update_mif" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1543268778513 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1543268778684 ""}
|
||||
{ "Info" "IQATM_MIFS_PROCESSED" "" "Processed the following Memory Initialization File(s)" { { "Info" "IQATM_PROCESSED_MIF_CONTENT" "F:/kkk/quartus/ROM.hex " "Processed Memory Initialization File F:/kkk/quartus/ROM.hex" { } { { "ROM.hex" "" { Text "F:/kkk/quartus/ROM.hex" 0 0 0 } } } 0 39025 "Processed Memory Initialization File %1!s!" 0 0 "Design Software" 0 -1 1543268779929 ""} } { } 0 39024 "Processed the following Memory Initialization File(s)" 0 0 "Design Software" 0 -1 1543268779929 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "MIF/HEX Update 0 s 1 Quartus Prime " "Quartus Prime MIF/HEX Update was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4753 " "Peak virtual memory: 4753 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543268780007 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 22:46:20 2018 " "Processing ended: Mon Nov 26 22:46:20 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543268780007 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543268780007 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543268780007 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1543268780007 ""}
|
||||
Executable
BIN
Binary file not shown.
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
Binary file not shown.
+1
@@ -0,0 +1 @@
|
||||
DONE
|
||||
Executable
+37
@@ -0,0 +1,37 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543265970637 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543265970637 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 21:59:29 2018 " "Processing started: Mon Nov 26 21:59:29 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543265970637 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1543265970637 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GECKO -c GECKO " "Command: quartus_sta GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1543265970637 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #2" { } { } 0 0 "qsta_default_script.tcl version: #2" 0 0 "Timing Analyzer" 0 0 1543265970934 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1543265972012 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1543265972012 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265972106 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265972106 ""}
|
||||
{ "Info" "ISTA_SDC_FOUND" "GECKO.sdc " "Reading SDC File: 'GECKO.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1543265972730 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Timing Analyzer" 0 -1 1543265972746 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1543265972840 ""}
|
||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1543265972840 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1543265972887 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.781 " "Worst-case setup slack is 0.781" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.781 0.000 clk " " 0.781 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973027 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265973027 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.451 " "Worst-case hold slack is 0.451" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973059 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973059 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.451 0.000 clk " " 0.451 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973059 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265973059 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265973074 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265973074 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.623 " "Worst-case minimum pulse width slack is 9.623" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.623 0.000 clk " " 9.623 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973090 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265973090 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1543265973277 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1543265973309 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1543265974058 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1543265974340 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.672 " "Worst-case setup slack is 1.672" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974480 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974480 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.672 0.000 clk " " 1.672 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974480 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265974480 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.400 " "Worst-case hold slack is 0.400" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.400 0.000 clk " " 0.400 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974558 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265974558 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265974574 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265974590 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.618 " "Worst-case minimum pulse width slack is 9.618" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974605 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974605 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.618 0.000 clk " " 9.618 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974605 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265974605 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1543265974855 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1543265975121 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 11.492 " "Worst-case setup slack is 11.492" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 11.492 0.000 clk " " 11.492 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975183 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265975183 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.185 " "Worst-case hold slack is 0.185" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.185 0.000 clk " " 0.185 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975246 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265975246 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265975262 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265975293 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.206 " "Worst-case minimum pulse width slack is 9.206" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975308 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975308 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.206 0.000 clk " " 9.206 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975308 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265975308 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1543265976246 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1543265976246 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4843 " "Peak virtual memory: 4843 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543265976668 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 21:59:36 2018 " "Processing ended: Mon Nov 26 21:59:36 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543265976668 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543265976668 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543265976668 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1543265976668 ""}
|
||||
Executable
BIN
Binary file not shown.
Binary file not shown.
BIN
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Executable
+6
@@ -0,0 +1,6 @@
|
||||
start_full_compilation:s:00:00:09
|
||||
start_analysis_synthesis:s:00:00:00-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:00-start_full_compilation
|
||||
start_assembler:s:00:00:06-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:00-start_full_compilation
|
||||
Executable
BIN
Binary file not shown.
+42
@@ -0,0 +1,42 @@
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; Quartus Prime QXP Design File ;
|
||||
+------------------+---------------------------------------------------------+
|
||||
; Field ; Value ;
|
||||
+------------------+---------------------------------------------------------+
|
||||
; Entity ; CPU ;
|
||||
; Case Sensitive ; ;
|
||||
; QXP Source ; CPU-inst.qxp ;
|
||||
; Software Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
|
||||
; Date ; Mon Oct 16 16:25:59 2017 ;
|
||||
; Contents ; Netlist Only ;
|
||||
; Family ; EP4CE30F23C8 ;
|
||||
; Device ; CYCLONEIVE3_V1F484C8 ;
|
||||
+------------------+---------------------------------------------------------+
|
||||
|
||||
+------------------------------------------------------------+
|
||||
; Boundary Ports ;
|
||||
+----------------+--------+----------------------------------+
|
||||
; Port Name ; Type ; Default Value ;
|
||||
+----------------+--------+----------------------------------+
|
||||
; write ; output ; X ;
|
||||
; clk ; input ; 1 ;
|
||||
; reset_n ; input ; 1 ;
|
||||
; rddata [31:0] ; input ; 11111111111111111111111111111111 ;
|
||||
; read ; output ; X ;
|
||||
; address [15:0] ; output ; XXXXXXXXXXXXXXXX ;
|
||||
; wrdata [31:0] ; output ; XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ;
|
||||
+----------------+--------+----------------------------------+
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; Quartus Prime QXP Design File ;
|
||||
+------------------+---------------------------------------------------------+
|
||||
; Field ; Value ;
|
||||
+------------------+---------------------------------------------------------+
|
||||
; Entity ; decoder ;
|
||||
; Case Sensitive ; ;
|
||||
; QXP Source ; decoder-decoder_0.qxp ;
|
||||
; Software Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
|
||||
; Date ; Mon Oct 16 17:05:41 2017 ;
|
||||
; Contents ; Netlist Only ;
|
||||
; Family ; EP4CE30F23C8 ;
|
||||
; Device ; CYCLONEIVE3_V1F484C8 ;
|
||||
+------------------+---------------------------------------------------------+
|
||||
|
||||
+--------------------------------------------+
|
||||
; Boundary Ports ;
|
||||
+----------------+--------+------------------+
|
||||
; Port Name ; Type ; Default Value ;
|
||||
+----------------+--------+------------------+
|
||||
; address [15:0] ; input ; 0000000000000000 ;
|
||||
; cs_Buttons ; output ; 0 ;
|
||||
; cs_LEDS ; output ; 0 ;
|
||||
; cs_RAM ; output ; 0 ;
|
||||
; cs_ROM ; output ; 0 ;
|
||||
+----------------+--------+------------------+
|
||||
+549
@@ -0,0 +1,549 @@
|
||||
{
|
||||
"partitions" : [
|
||||
{
|
||||
"name" : "Top",
|
||||
"pins" : [
|
||||
{
|
||||
"name" : "row1[11]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[10]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[9]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[8]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row1[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[11]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[10]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[9]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[8]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row2[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[11]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[10]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[9]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[8]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row3[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[11]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[10]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[9]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[8]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row4[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[11]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[10]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[9]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[8]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row5[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[11]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[10]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[9]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[8]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row6[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[11]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[10]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[9]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[8]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row7[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[11]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[10]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[9]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[8]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "row8[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[31]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[30]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[29]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[28]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[27]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[26]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[25]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[24]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[23]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[22]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[21]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[20]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[19]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[18]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[17]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[16]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[15]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[14]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[13]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[12]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[11]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[10]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[9]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[8]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "seg_out[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "clk",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "in_buttons[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "in_buttons[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "in_buttons[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "in_buttons[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "in_buttons[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "reset_n",
|
||||
"strict" : false
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.atm
|
||||
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.hdbx
|
||||
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.qxp_info
|
||||
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.logdb
|
||||
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.scidsc
|
||||
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.map.kpt
|
||||
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.dpi
|
||||
+715
@@ -0,0 +1,715 @@
|
||||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="../quartus/ROM.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=32 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 18.0 cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 4
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_rna1
|
||||
(
|
||||
address_a[9..0] : input;
|
||||
clock0 : input;
|
||||
q_a[31..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a18 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 18,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a19 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 19,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a20 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 20,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a21 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 21,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a22 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 22,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a23 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 23,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a24 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 24,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a25 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 25,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a26 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 26,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a27 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 27,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a28 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 28,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a29 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 29,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a30 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 30,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a31 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "../quartus/ROM.hex",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 31,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[9..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[31..0].clk0 = clock0;
|
||||
ram_block1a[31..0].portaaddr[] = ( address_a_wire[9..0]);
|
||||
ram_block1a[31..0].portare = B"11111111111111111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
+750
@@ -0,0 +1,750 @@
|
||||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=32 WIDTHAD_A=10 WRCONTROL_ACLR_A="NONE" address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 18.0 cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 4
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_vh41
|
||||
(
|
||||
address_a[9..0] : input;
|
||||
clock0 : input;
|
||||
data_a[31..0] : input;
|
||||
q_a[31..0] : output;
|
||||
wren_a : input;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a18 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 18,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a19 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 19,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a20 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 20,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a21 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 21,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a22 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 22,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a23 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 23,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a24 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 24,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a25 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 25,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a26 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 26,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a27 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 27,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a28 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 28,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a29 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 29,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a30 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 30,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a31 : cycloneive_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "single_port",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
||||
PORT_A_BYTE_SIZE = 1,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "none",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 31,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 32,
|
||||
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[9..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[31..0].clk0 = clock0;
|
||||
ram_block1a[31..0].portaaddr[] = ( address_a_wire[9..0]);
|
||||
ram_block1a[0].portadatain[] = ( data_a[0..0]);
|
||||
ram_block1a[1].portadatain[] = ( data_a[1..1]);
|
||||
ram_block1a[2].portadatain[] = ( data_a[2..2]);
|
||||
ram_block1a[3].portadatain[] = ( data_a[3..3]);
|
||||
ram_block1a[4].portadatain[] = ( data_a[4..4]);
|
||||
ram_block1a[5].portadatain[] = ( data_a[5..5]);
|
||||
ram_block1a[6].portadatain[] = ( data_a[6..6]);
|
||||
ram_block1a[7].portadatain[] = ( data_a[7..7]);
|
||||
ram_block1a[8].portadatain[] = ( data_a[8..8]);
|
||||
ram_block1a[9].portadatain[] = ( data_a[9..9]);
|
||||
ram_block1a[10].portadatain[] = ( data_a[10..10]);
|
||||
ram_block1a[11].portadatain[] = ( data_a[11..11]);
|
||||
ram_block1a[12].portadatain[] = ( data_a[12..12]);
|
||||
ram_block1a[13].portadatain[] = ( data_a[13..13]);
|
||||
ram_block1a[14].portadatain[] = ( data_a[14..14]);
|
||||
ram_block1a[15].portadatain[] = ( data_a[15..15]);
|
||||
ram_block1a[16].portadatain[] = ( data_a[16..16]);
|
||||
ram_block1a[17].portadatain[] = ( data_a[17..17]);
|
||||
ram_block1a[18].portadatain[] = ( data_a[18..18]);
|
||||
ram_block1a[19].portadatain[] = ( data_a[19..19]);
|
||||
ram_block1a[20].portadatain[] = ( data_a[20..20]);
|
||||
ram_block1a[21].portadatain[] = ( data_a[21..21]);
|
||||
ram_block1a[22].portadatain[] = ( data_a[22..22]);
|
||||
ram_block1a[23].portadatain[] = ( data_a[23..23]);
|
||||
ram_block1a[24].portadatain[] = ( data_a[24..24]);
|
||||
ram_block1a[25].portadatain[] = ( data_a[25..25]);
|
||||
ram_block1a[26].portadatain[] = ( data_a[26..26]);
|
||||
ram_block1a[27].portadatain[] = ( data_a[27..27]);
|
||||
ram_block1a[28].portadatain[] = ( data_a[28..28]);
|
||||
ram_block1a[29].portadatain[] = ( data_a[29..29]);
|
||||
ram_block1a[30].portadatain[] = ( data_a[30..30]);
|
||||
ram_block1a[31].portadatain[] = ( data_a[31..31]);
|
||||
ram_block1a[31..0].portare = B"11111111111111111111111111111111";
|
||||
ram_block1a[31..0].portawe = wren_a;
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
+19
@@ -0,0 +1,19 @@
|
||||
{ "Info" "IFLOW_NO_RECOMPILE_NEEDED" "Analysis & Synthesis " "Smart recompilation skipped module Analysis & Synthesis because it is not required" { } { } 0 293003 "Smart recompilation skipped module %1!s! because it is not required" 0 0 "Design Software" 0 -1 1543268082663 ""}
|
||||
{ "Info" "IFLOW_NO_RECOMPILE_NEEDED" "Fitter " "Smart recompilation skipped module Fitter because it is not required" { } { } 0 293003 "Smart recompilation skipped module %1!s! because it is not required" 0 0 "Design Software" 0 -1 1543268082679 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543268083694 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "MIF/HEX Update Quartus Prime " "Running Quartus Prime MIF/HEX Update" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543268083741 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 22:34:43 2018 " "Processing started: Mon Nov 26 22:34:43 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543268083741 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1543268083741 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb GECKO -c GECKO --update_mif " "Command: quartus_cdb GECKO -c GECKO --update_mif" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1543268083741 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1543268083976 ""}
|
||||
{ "Info" "IQATM_MIFS_PROCESSED" "" "Processed the following Memory Initialization File(s)" { { "Info" "IQATM_PROCESSED_MIF_CONTENT" "F:/kkk/quartus/ROM.hex " "Processed Memory Initialization File F:/kkk/quartus/ROM.hex" { } { { "ROM.hex" "" { Text "F:/kkk/quartus/ROM.hex" 0 0 0 } } } 0 39025 "Processed Memory Initialization File %1!s!" 0 0 "Design Software" 0 -1 1543268084647 ""} } { } 0 39024 "Processed the following Memory Initialization File(s)" 0 0 "Design Software" 0 -1 1543268084647 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "MIF/HEX Update 0 s 1 Quartus Prime " "Quartus Prime MIF/HEX Update was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4753 " "Peak virtual memory: 4753 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543268084741 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 22:34:44 2018 " "Processing ended: Mon Nov 26 22:34:44 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543268084741 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543268084741 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543268084741 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1543268084741 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543268085928 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543268085928 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 22:34:45 2018 " "Processing started: Mon Nov 26 22:34:45 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543268085928 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1543268085928 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=on --write_settings_files=off GECKO -c GECKO " "Command: quartus_asm --read_settings_files=on --write_settings_files=off GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1543268085928 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1543268087272 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1543268088210 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1543268088506 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4705 " "Peak virtual memory: 4705 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543268089913 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 22:34:49 2018 " "Processing ended: Mon Nov 26 22:34:49 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543268089913 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543268089913 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543268089913 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1543268089913 ""}
|
||||
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1543268090756 ""}
|
||||
{ "Info" "IFLOW_NO_RECOMPILE_NEEDED" "Timing Analyzer " "Smart recompilation skipped module Timing Analyzer because it is not required" { } { } 0 293003 "Smart recompilation skipped module %1!s! because it is not required" 0 0 "Assembler" 0 -1 1543268090756 ""}
|
||||
{ "Info" "IFLOW_TURN_OFF_SMART_RECOMPILE" "" "Some modules have been skipped due to smart recompilation. You can turn off smart recompilation under Compilation Process Settings in the Settings dialog to fully recompile your design" { } { } 0 18207 "Some modules have been skipped due to smart recompilation. You can turn off smart recompilation under Compilation Process Settings in the Settings dialog to fully recompile your design" 0 0 "Assembler" 0 -1 1543268090756 ""}
|
||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2 s " "Quartus Prime Full Compilation was successful. 0 errors, 2 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1543268090756 ""}
|
||||
Reference in new issue
Block a user