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Disabled external gits

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This commit is contained in:
choelzl
2022-04-07 18:43:21 +02:00
parent 182267a8cb
commit 88cb3426ad
1067 changed files with 102374 additions and 6 deletions
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cs208-ca_bonus/quartus/db/.cmp.kpt Executable file
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cs208-ca_bonus/quartus/db/GECKO.(0).cnf.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(2).cnf.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(3).cnf.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(4).cnf.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(5).cnf.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(6).cnf.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(6).cnf.hdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(7).cnf.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(7).cnf.hdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(8).cnf.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(8).cnf.hdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(9).cnf.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.(9).cnf.hdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.asm.qmsg Executable file
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543268781242 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543268781242 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 22:46:21 2018 " "Processing started: Mon Nov 26 22:46:21 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543268781242 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1543268781242 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=on --write_settings_files=off GECKO -c GECKO " "Command: quartus_asm --read_settings_files=on --write_settings_files=off GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1543268781242 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1543268782929 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1543268783929 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1543268784117 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4705 " "Peak virtual memory: 4705 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543268785476 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 22:46:25 2018 " "Processing ended: Mon Nov 26 22:46:25 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543268785476 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543268785476 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543268785476 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1543268785476 ""}

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cs208-ca_bonus/quartus/db/GECKO.asm.rdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.asm_labs.ddb Executable file
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cs208-ca_bonus/quartus/db/GECKO.cmp.bpm Executable file
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cs208-ca_bonus/quartus/db/GECKO.cmp.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.cmp.hdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.cmp.idb Executable file
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cs208-ca_bonus/quartus/db/GECKO.cmp.logdb Executable file
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v1
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,135;0;135;0;0;135;135;0;135;135;0;0;0;0;7;0;0;7;0;0;0;0;0;0;0;0;0;135;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,0;135;0;135;135;0;0;135;0;0;135;135;135;135;128;135;135;128;135;135;135;135;135;135;135;135;135;0;135;135,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,row1[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row6[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row7[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,row8[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[30],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[29],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[28],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[27],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[26],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[25],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[24],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[23],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[22],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[21],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[20],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[19],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[18],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,seg_out[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,in_buttons[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,in_buttons[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,in_buttons[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,in_buttons[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,in_buttons[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,reset_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,

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cs208-ca_bonus/quartus/db/GECKO.cmp.rdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.cmp_merge.kpt Executable file
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cs208-ca_bonus/quartus/db/GECKO.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd Executable file
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cs208-ca_bonus/quartus/db/GECKO.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd Executable file
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cs208-ca_bonus/quartus/db/GECKO.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd Executable file
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3
cs208-ca_bonus/quartus/db/GECKO.db_info Executable file
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Quartus_Version = Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
Version_Index = 469919232
Creation_Time = Mon Nov 26 21:57:04 2018

50
cs208-ca_bonus/quartus/db/GECKO.fit.qmsg Executable file
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2266
cs208-ca_bonus/quartus/db/GECKO.hier_info Executable file
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cs208-ca_bonus/quartus/db/GECKO.hif Executable file
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cs208-ca_bonus/quartus/db/GECKO.lpc.html Executable file
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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >inst1</TD>
<TD >26</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst3</TD>
<TD >19</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst2</TD>
<TD >43</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >RAM_0|ram_inst</TD>
<TD >46</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >RAM_0</TD>
<TD >46</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ROM_0|ROM_inst|iD_s_30739CAe_5A20DAf5_E|altsyncram_component|auto_generated</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ROM_0|ROM_inst|iD_s_30739CAe_5A20DAf5_E</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ROM_0|ROM_inst</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ROM_0</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >decoder_0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >LEDs_0</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >128</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>

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cs208-ca_bonus/quartus/db/GECKO.lpc.rdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.lpc.txt Executable file
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; inst1 ; 26 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst3 ; 19 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst2 ; 43 ; 0 ; 32 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; RAM_0|ram_inst ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; RAM_0 ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; ROM_0|ROM_inst|iD_s_30739CAe_5A20DAf5_E|altsyncram_component|auto_generated ; 11 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; ROM_0|ROM_inst|iD_s_30739CAe_5A20DAf5_E ; 11 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; ROM_0|ROM_inst ; 13 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; ROM_0 ; 13 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; decoder_0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; LEDs_0 ; 39 ; 0 ; 0 ; 0 ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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cs208-ca_bonus/quartus/db/GECKO.map.ammdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.map.bpm Executable file
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cs208-ca_bonus/quartus/db/GECKO.map.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.map.hdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.map.kpt Executable file
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cs208-ca_bonus/quartus/db/GECKO.map.logdb Executable file
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v1

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cs208-ca_bonus/quartus/db/GECKO.map.qmsg Executable file
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cs208-ca_bonus/quartus/db/GECKO.map.rdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.map_bb.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.map_bb.hdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.map_bb.logdb Executable file
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v1

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cs208-ca_bonus/quartus/db/GECKO.mif_update.qmsg Executable file
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543268778497 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "MIF/HEX Update Quartus Prime " "Running Quartus Prime MIF/HEX Update" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543268778513 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 22:46:17 2018 " "Processing started: Mon Nov 26 22:46:17 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543268778513 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1543268778513 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb GECKO -c GECKO --update_mif " "Command: quartus_cdb GECKO -c GECKO --update_mif" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1543268778513 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1543268778684 ""}
{ "Info" "IQATM_MIFS_PROCESSED" "" "Processed the following Memory Initialization File(s)" { { "Info" "IQATM_PROCESSED_MIF_CONTENT" "F:/kkk/quartus/ROM.hex " "Processed Memory Initialization File F:/kkk/quartus/ROM.hex" { } { { "ROM.hex" "" { Text "F:/kkk/quartus/ROM.hex" 0 0 0 } } } 0 39025 "Processed Memory Initialization File %1!s!" 0 0 "Design Software" 0 -1 1543268779929 ""} } { } 0 39024 "Processed the following Memory Initialization File(s)" 0 0 "Design Software" 0 -1 1543268779929 ""}
{ "Info" "IQEXE_ERROR_COUNT" "MIF/HEX Update 0 s 1 Quartus Prime " "Quartus Prime MIF/HEX Update was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4753 " "Peak virtual memory: 4753 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543268780007 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 22:46:20 2018 " "Processing ended: Mon Nov 26 22:46:20 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543268780007 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543268780007 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543268780007 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1543268780007 ""}

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cs208-ca_bonus/quartus/db/GECKO.pre_map.hdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.root_partition.map.reg_db.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.routing.rdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.rtlv.hdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.rtlv_sg.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.rtlv_sg_swap.cdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.sld_design_entry.sci Executable file
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cs208-ca_bonus/quartus/db/GECKO.sld_design_entry_dsc.sci Executable file
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cs208-ca_bonus/quartus/db/GECKO.smart_action.txt Executable file
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DONE

37
cs208-ca_bonus/quartus/db/GECKO.sta.qmsg Executable file
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543265970637 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543265970637 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 21:59:29 2018 " "Processing started: Mon Nov 26 21:59:29 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543265970637 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1543265970637 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GECKO -c GECKO " "Command: quartus_sta GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1543265970637 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #2" { } { } 0 0 "qsta_default_script.tcl version: #2" 0 0 "Timing Analyzer" 0 0 1543265970934 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1543265972012 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1543265972012 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265972106 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265972106 ""}
{ "Info" "ISTA_SDC_FOUND" "GECKO.sdc " "Reading SDC File: 'GECKO.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1543265972730 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Timing Analyzer" 0 -1 1543265972746 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1543265972840 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1543265972840 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1543265972887 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.781 " "Worst-case setup slack is 0.781" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.781 0.000 clk " " 0.781 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973027 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265973027 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.451 " "Worst-case hold slack is 0.451" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973059 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973059 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.451 0.000 clk " " 0.451 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973059 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265973059 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265973074 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265973074 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.623 " "Worst-case minimum pulse width slack is 9.623" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.623 0.000 clk " " 9.623 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265973090 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265973090 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1543265973277 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1543265973309 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1543265974058 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1543265974340 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.672 " "Worst-case setup slack is 1.672" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974480 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974480 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.672 0.000 clk " " 1.672 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974480 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265974480 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.400 " "Worst-case hold slack is 0.400" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.400 0.000 clk " " 0.400 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974558 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265974558 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265974574 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265974590 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.618 " "Worst-case minimum pulse width slack is 9.618" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974605 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974605 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.618 0.000 clk " " 9.618 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265974605 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265974605 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1543265974855 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1543265975121 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 11.492 " "Worst-case setup slack is 11.492" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 11.492 0.000 clk " " 11.492 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975183 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265975183 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.185 " "Worst-case hold slack is 0.185" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.185 0.000 clk " " 0.185 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975246 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265975246 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265975262 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543265975293 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.206 " "Worst-case minimum pulse width slack is 9.206" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975308 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975308 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.206 0.000 clk " " 9.206 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543265975308 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543265975308 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1543265976246 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1543265976246 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4843 " "Peak virtual memory: 4843 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543265976668 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 21:59:36 2018 " "Processing ended: Mon Nov 26 21:59:36 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543265976668 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543265976668 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543265976668 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1543265976668 ""}

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cs208-ca_bonus/quartus/db/GECKO.sta.rdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.sta_cmp.8_slow_1200mv_85c.tdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.tis_db_list.ddb Executable file
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cs208-ca_bonus/quartus/db/GECKO.tiscmp.fast_1200mv_0c.ddb Executable file
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cs208-ca_bonus/quartus/db/GECKO.tiscmp.fastest_slow_1200mv_0c.ddb Executable file
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cs208-ca_bonus/quartus/db/GECKO.tiscmp.fastest_slow_1200mv_85c.ddb Executable file
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cs208-ca_bonus/quartus/db/GECKO.tiscmp.slow_1200mv_0c.ddb Executable file
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cs208-ca_bonus/quartus/db/GECKO.tiscmp.slow_1200mv_85c.ddb Executable file
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cs208-ca_bonus/quartus/db/GECKO.tmw_info Executable file
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start_full_compilation:s:00:00:09
start_analysis_synthesis:s:00:00:00-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:00-start_full_compilation
start_assembler:s:00:00:06-start_full_compilation
start_timing_analyzer:s:00:00:00-start_full_compilation

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cs208-ca_bonus/quartus/db/GECKO.vpr.ammdb Executable file
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cs208-ca_bonus/quartus/db/GECKO.work.CPU.qxp.txt Executable file
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Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------+
; Quartus Prime QXP Design File ;
+------------------+---------------------------------------------------------+
; Field ; Value ;
+------------------+---------------------------------------------------------+
; Entity ; CPU ;
; Case Sensitive ; ;
; QXP Source ; CPU-inst.qxp ;
; Software Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
; Date ; Mon Oct 16 16:25:59 2017 ;
; Contents ; Netlist Only ;
; Family ; EP4CE30F23C8 ;
; Device ; CYCLONEIVE3_V1F484C8 ;
+------------------+---------------------------------------------------------+
+------------------------------------------------------------+
; Boundary Ports ;
+----------------+--------+----------------------------------+
; Port Name ; Type ; Default Value ;
+----------------+--------+----------------------------------+
; write ; output ; X ;
; clk ; input ; 1 ;
; reset_n ; input ; 1 ;
; rddata [31:0] ; input ; 11111111111111111111111111111111 ;
; read ; output ; X ;
; address [15:0] ; output ; XXXXXXXXXXXXXXXX ;
; wrdata [31:0] ; output ; XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ;
+----------------+--------+----------------------------------+

40
cs208-ca_bonus/quartus/db/GECKO.work.decoder.qxp.txt Executable file
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Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------+
; Quartus Prime QXP Design File ;
+------------------+---------------------------------------------------------+
; Field ; Value ;
+------------------+---------------------------------------------------------+
; Entity ; decoder ;
; Case Sensitive ; ;
; QXP Source ; decoder-decoder_0.qxp ;
; Software Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
; Date ; Mon Oct 16 17:05:41 2017 ;
; Contents ; Netlist Only ;
; Family ; EP4CE30F23C8 ;
; Device ; CYCLONEIVE3_V1F484C8 ;
+------------------+---------------------------------------------------------+
+--------------------------------------------+
; Boundary Ports ;
+----------------+--------+------------------+
; Port Name ; Type ; Default Value ;
+----------------+--------+------------------+
; address [15:0] ; input ; 0000000000000000 ;
; cs_Buttons ; output ; 0 ;
; cs_LEDS ; output ; 0 ;
; cs_RAM ; output ; 0 ;
; cs_ROM ; output ; 0 ;
+----------------+--------+------------------+

549
cs208-ca_bonus/quartus/db/GECKO_partition_pins.json Executable file
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@@ -0,0 +1,549 @@
{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "row1[11]",
"strict" : false
},
{
"name" : "row1[10]",
"strict" : false
},
{
"name" : "row1[9]",
"strict" : false
},
{
"name" : "row1[8]",
"strict" : false
},
{
"name" : "row1[7]",
"strict" : false
},
{
"name" : "row1[6]",
"strict" : false
},
{
"name" : "row1[5]",
"strict" : false
},
{
"name" : "row1[4]",
"strict" : false
},
{
"name" : "row1[3]",
"strict" : false
},
{
"name" : "row1[2]",
"strict" : false
},
{
"name" : "row1[1]",
"strict" : false
},
{
"name" : "row1[0]",
"strict" : false
},
{
"name" : "row2[11]",
"strict" : false
},
{
"name" : "row2[10]",
"strict" : false
},
{
"name" : "row2[9]",
"strict" : false
},
{
"name" : "row2[8]",
"strict" : false
},
{
"name" : "row2[7]",
"strict" : false
},
{
"name" : "row2[6]",
"strict" : false
},
{
"name" : "row2[5]",
"strict" : false
},
{
"name" : "row2[4]",
"strict" : false
},
{
"name" : "row2[3]",
"strict" : false
},
{
"name" : "row2[2]",
"strict" : false
},
{
"name" : "row2[1]",
"strict" : false
},
{
"name" : "row2[0]",
"strict" : false
},
{
"name" : "row3[11]",
"strict" : false
},
{
"name" : "row3[10]",
"strict" : false
},
{
"name" : "row3[9]",
"strict" : false
},
{
"name" : "row3[8]",
"strict" : false
},
{
"name" : "row3[7]",
"strict" : false
},
{
"name" : "row3[6]",
"strict" : false
},
{
"name" : "row3[5]",
"strict" : false
},
{
"name" : "row3[4]",
"strict" : false
},
{
"name" : "row3[3]",
"strict" : false
},
{
"name" : "row3[2]",
"strict" : false
},
{
"name" : "row3[1]",
"strict" : false
},
{
"name" : "row3[0]",
"strict" : false
},
{
"name" : "row4[11]",
"strict" : false
},
{
"name" : "row4[10]",
"strict" : false
},
{
"name" : "row4[9]",
"strict" : false
},
{
"name" : "row4[8]",
"strict" : false
},
{
"name" : "row4[7]",
"strict" : false
},
{
"name" : "row4[6]",
"strict" : false
},
{
"name" : "row4[5]",
"strict" : false
},
{
"name" : "row4[4]",
"strict" : false
},
{
"name" : "row4[3]",
"strict" : false
},
{
"name" : "row4[2]",
"strict" : false
},
{
"name" : "row4[1]",
"strict" : false
},
{
"name" : "row4[0]",
"strict" : false
},
{
"name" : "row5[11]",
"strict" : false
},
{
"name" : "row5[10]",
"strict" : false
},
{
"name" : "row5[9]",
"strict" : false
},
{
"name" : "row5[8]",
"strict" : false
},
{
"name" : "row5[7]",
"strict" : false
},
{
"name" : "row5[6]",
"strict" : false
},
{
"name" : "row5[5]",
"strict" : false
},
{
"name" : "row5[4]",
"strict" : false
},
{
"name" : "row5[3]",
"strict" : false
},
{
"name" : "row5[2]",
"strict" : false
},
{
"name" : "row5[1]",
"strict" : false
},
{
"name" : "row5[0]",
"strict" : false
},
{
"name" : "row6[11]",
"strict" : false
},
{
"name" : "row6[10]",
"strict" : false
},
{
"name" : "row6[9]",
"strict" : false
},
{
"name" : "row6[8]",
"strict" : false
},
{
"name" : "row6[7]",
"strict" : false
},
{
"name" : "row6[6]",
"strict" : false
},
{
"name" : "row6[5]",
"strict" : false
},
{
"name" : "row6[4]",
"strict" : false
},
{
"name" : "row6[3]",
"strict" : false
},
{
"name" : "row6[2]",
"strict" : false
},
{
"name" : "row6[1]",
"strict" : false
},
{
"name" : "row6[0]",
"strict" : false
},
{
"name" : "row7[11]",
"strict" : false
},
{
"name" : "row7[10]",
"strict" : false
},
{
"name" : "row7[9]",
"strict" : false
},
{
"name" : "row7[8]",
"strict" : false
},
{
"name" : "row7[7]",
"strict" : false
},
{
"name" : "row7[6]",
"strict" : false
},
{
"name" : "row7[5]",
"strict" : false
},
{
"name" : "row7[4]",
"strict" : false
},
{
"name" : "row7[3]",
"strict" : false
},
{
"name" : "row7[2]",
"strict" : false
},
{
"name" : "row7[1]",
"strict" : false
},
{
"name" : "row7[0]",
"strict" : false
},
{
"name" : "row8[11]",
"strict" : false
},
{
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"strict" : false
},
{
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"strict" : false
},
{
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"strict" : false
},
{
"name" : "row8[7]",
"strict" : false
},
{
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"strict" : false
},
{
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"strict" : false
},
{
"name" : "row8[4]",
"strict" : false
},
{
"name" : "row8[3]",
"strict" : false
},
{
"name" : "row8[2]",
"strict" : false
},
{
"name" : "row8[1]",
"strict" : false
},
{
"name" : "row8[0]",
"strict" : false
},
{
"name" : "seg_out[31]",
"strict" : false
},
{
"name" : "seg_out[30]",
"strict" : false
},
{
"name" : "seg_out[29]",
"strict" : false
},
{
"name" : "seg_out[28]",
"strict" : false
},
{
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"strict" : false
},
{
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"strict" : false
},
{
"name" : "seg_out[25]",
"strict" : false
},
{
"name" : "seg_out[24]",
"strict" : false
},
{
"name" : "seg_out[23]",
"strict" : false
},
{
"name" : "seg_out[22]",
"strict" : false
},
{
"name" : "seg_out[21]",
"strict" : false
},
{
"name" : "seg_out[20]",
"strict" : false
},
{
"name" : "seg_out[19]",
"strict" : false
},
{
"name" : "seg_out[18]",
"strict" : false
},
{
"name" : "seg_out[17]",
"strict" : false
},
{
"name" : "seg_out[16]",
"strict" : false
},
{
"name" : "seg_out[15]",
"strict" : false
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{
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"strict" : false
},
{
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"strict" : false
},
{
"name" : "seg_out[12]",
"strict" : false
},
{
"name" : "seg_out[11]",
"strict" : false
},
{
"name" : "seg_out[10]",
"strict" : false
},
{
"name" : "seg_out[9]",
"strict" : false
},
{
"name" : "seg_out[8]",
"strict" : false
},
{
"name" : "seg_out[7]",
"strict" : false
},
{
"name" : "seg_out[6]",
"strict" : false
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{
"name" : "seg_out[5]",
"strict" : false
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{
"name" : "seg_out[4]",
"strict" : false
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{
"name" : "seg_out[3]",
"strict" : false
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{
"name" : "seg_out[2]",
"strict" : false
},
{
"name" : "seg_out[1]",
"strict" : false
},
{
"name" : "seg_out[0]",
"strict" : false
},
{
"name" : "clk",
"strict" : false
},
{
"name" : "in_buttons[0]",
"strict" : false
},
{
"name" : "in_buttons[1]",
"strict" : false
},
{
"name" : "in_buttons[2]",
"strict" : false
},
{
"name" : "in_buttons[3]",
"strict" : false
},
{
"name" : "in_buttons[4]",
"strict" : false
},
{
"name" : "reset_n",
"strict" : false
}
]
}
]
}

7
cs208-ca_bonus/quartus/db/GECKO_tmp_qic_import/qic_export_file_list Executable file
View File

@@ -0,0 +1,7 @@
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.atm
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.hdbx
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.qxp_info
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.logdb
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.scidsc
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.map.kpt
/home/asiatici/Downloads/03-obfuscated/quartus/db/GECKO_tmp_qic_export/GECKO.map.dpi

715
cs208-ca_bonus/quartus/db/altsyncram_rna1.tdf Executable file
View File

@@ -0,0 +1,715 @@
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="../quartus/ROM.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=32 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 18.0 cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 4
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_rna1
(
address_a[9..0] : input;
clock0 : input;
q_a[31..0] : output;
)
VARIABLE
ram_block1a0 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 9,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 10,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 11,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 12,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 13,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a16 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a17 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a18 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a19 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a20 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a21 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a22 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a23 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a24 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a25 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 25,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a26 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a27 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a28 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 28,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a29 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 29,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a30 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 30,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a31 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "../quartus/ROM.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 31,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[9..0] : WIRE;
BEGIN
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].portaaddr[] = ( address_a_wire[9..0]);
ram_block1a[31..0].portare = B"11111111111111111111111111111111";
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
END;
--VALID FILE

750
cs208-ca_bonus/quartus/db/altsyncram_vh41.tdf Executable file
View File

@@ -0,0 +1,750 @@
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=32 WIDTHAD_A=10 WRCONTROL_ACLR_A="NONE" address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 18.0 cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 4
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_vh41
(
address_a[9..0] : input;
clock0 : input;
data_a[31..0] : input;
q_a[31..0] : output;
wren_a : input;
)
VARIABLE
ram_block1a0 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 9,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 10,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 11,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 12,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 13,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a16 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a17 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a18 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a19 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a20 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a21 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a22 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a23 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a24 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a25 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 25,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a26 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a27 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a28 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 28,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a29 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 29,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a30 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 30,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a31 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 31,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[9..0] : WIRE;
BEGIN
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].portaaddr[] = ( address_a_wire[9..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[8..8]);
ram_block1a[9].portadatain[] = ( data_a[9..9]);
ram_block1a[10].portadatain[] = ( data_a[10..10]);
ram_block1a[11].portadatain[] = ( data_a[11..11]);
ram_block1a[12].portadatain[] = ( data_a[12..12]);
ram_block1a[13].portadatain[] = ( data_a[13..13]);
ram_block1a[14].portadatain[] = ( data_a[14..14]);
ram_block1a[15].portadatain[] = ( data_a[15..15]);
ram_block1a[16].portadatain[] = ( data_a[16..16]);
ram_block1a[17].portadatain[] = ( data_a[17..17]);
ram_block1a[18].portadatain[] = ( data_a[18..18]);
ram_block1a[19].portadatain[] = ( data_a[19..19]);
ram_block1a[20].portadatain[] = ( data_a[20..20]);
ram_block1a[21].portadatain[] = ( data_a[21..21]);
ram_block1a[22].portadatain[] = ( data_a[22..22]);
ram_block1a[23].portadatain[] = ( data_a[23..23]);
ram_block1a[24].portadatain[] = ( data_a[24..24]);
ram_block1a[25].portadatain[] = ( data_a[25..25]);
ram_block1a[26].portadatain[] = ( data_a[26..26]);
ram_block1a[27].portadatain[] = ( data_a[27..27]);
ram_block1a[28].portadatain[] = ( data_a[28..28]);
ram_block1a[29].portadatain[] = ( data_a[29..29]);
ram_block1a[30].portadatain[] = ( data_a[30..30]);
ram_block1a[31].portadatain[] = ( data_a[31..31]);
ram_block1a[31..0].portare = B"11111111111111111111111111111111";
ram_block1a[31..0].portawe = wren_a;
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
END;
--VALID FILE

19
cs208-ca_bonus/quartus/db/prev_cmp_GECKO.qmsg Executable file
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{ "Info" "IFLOW_NO_RECOMPILE_NEEDED" "Analysis & Synthesis " "Smart recompilation skipped module Analysis & Synthesis because it is not required" { } { } 0 293003 "Smart recompilation skipped module %1!s! because it is not required" 0 0 "Design Software" 0 -1 1543268082663 ""}
{ "Info" "IFLOW_NO_RECOMPILE_NEEDED" "Fitter " "Smart recompilation skipped module Fitter because it is not required" { } { } 0 293003 "Smart recompilation skipped module %1!s! because it is not required" 0 0 "Design Software" 0 -1 1543268082679 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543268083694 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "MIF/HEX Update Quartus Prime " "Running Quartus Prime MIF/HEX Update" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543268083741 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 22:34:43 2018 " "Processing started: Mon Nov 26 22:34:43 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543268083741 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1543268083741 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb GECKO -c GECKO --update_mif " "Command: quartus_cdb GECKO -c GECKO --update_mif" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1543268083741 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1543268083976 ""}
{ "Info" "IQATM_MIFS_PROCESSED" "" "Processed the following Memory Initialization File(s)" { { "Info" "IQATM_PROCESSED_MIF_CONTENT" "F:/kkk/quartus/ROM.hex " "Processed Memory Initialization File F:/kkk/quartus/ROM.hex" { } { { "ROM.hex" "" { Text "F:/kkk/quartus/ROM.hex" 0 0 0 } } } 0 39025 "Processed Memory Initialization File %1!s!" 0 0 "Design Software" 0 -1 1543268084647 ""} } { } 0 39024 "Processed the following Memory Initialization File(s)" 0 0 "Design Software" 0 -1 1543268084647 ""}
{ "Info" "IQEXE_ERROR_COUNT" "MIF/HEX Update 0 s 1 Quartus Prime " "Quartus Prime MIF/HEX Update was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4753 " "Peak virtual memory: 4753 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543268084741 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 22:34:44 2018 " "Processing ended: Mon Nov 26 22:34:44 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543268084741 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543268084741 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543268084741 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1543268084741 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543268085928 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543268085928 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 22:34:45 2018 " "Processing started: Mon Nov 26 22:34:45 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543268085928 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1543268085928 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=on --write_settings_files=off GECKO -c GECKO " "Command: quartus_asm --read_settings_files=on --write_settings_files=off GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1543268085928 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1543268087272 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1543268088210 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1543268088506 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4705 " "Peak virtual memory: 4705 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543268089913 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 22:34:49 2018 " "Processing ended: Mon Nov 26 22:34:49 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543268089913 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543268089913 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543268089913 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1543268089913 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1543268090756 ""}
{ "Info" "IFLOW_NO_RECOMPILE_NEEDED" "Timing Analyzer " "Smart recompilation skipped module Timing Analyzer because it is not required" { } { } 0 293003 "Smart recompilation skipped module %1!s! because it is not required" 0 0 "Assembler" 0 -1 1543268090756 ""}
{ "Info" "IFLOW_TURN_OFF_SMART_RECOMPILE" "" "Some modules have been skipped due to smart recompilation. You can turn off smart recompilation under Compilation Process Settings in the Settings dialog to fully recompile your design" { } { } 0 18207 "Some modules have been skipped due to smart recompilation. You can turn off smart recompilation under Compilation Process Settings in the Settings dialog to fully recompile your design" 0 0 "Assembler" 0 -1 1543268090756 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2 s " "Quartus Prime Full Compilation was successful. 0 errors, 2 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1543268090756 ""}