2267 lines
88 KiB
Plaintext
Executable File
2267 lines
88 KiB
Plaintext
Executable File
|GECKO
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row1[0] <= out_LEDs[0].DB_MAX_OUTPUT_PORT_TYPE
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row1[1] <= out_LEDs[1].DB_MAX_OUTPUT_PORT_TYPE
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row1[2] <= out_LEDs[2].DB_MAX_OUTPUT_PORT_TYPE
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row1[3] <= out_LEDs[3].DB_MAX_OUTPUT_PORT_TYPE
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row1[4] <= out_LEDs[4].DB_MAX_OUTPUT_PORT_TYPE
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row1[5] <= out_LEDs[5].DB_MAX_OUTPUT_PORT_TYPE
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row1[6] <= out_LEDs[6].DB_MAX_OUTPUT_PORT_TYPE
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row1[7] <= out_LEDs[7].DB_MAX_OUTPUT_PORT_TYPE
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row1[8] <= out_LEDs[8].DB_MAX_OUTPUT_PORT_TYPE
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row1[9] <= out_LEDs[9].DB_MAX_OUTPUT_PORT_TYPE
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row1[10] <= out_LEDs[10].DB_MAX_OUTPUT_PORT_TYPE
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row1[11] <= out_LEDs[11].DB_MAX_OUTPUT_PORT_TYPE
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clk => LEDs:LEDs_0.clk
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clk => CPU:inst.clk
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clk => ROM:ROM_0.clk
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clk => RAM:RAM_0.clk
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clk => buttons:inst2.clk
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clk => randgen:inst3.clk
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clk => seven_seg:inst1.clk
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reset_n => LEDs:LEDs_0.reset_n
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reset_n => CPU:inst.reset_n
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reset_n => buttons:inst2.reset_n
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reset_n => randgen:inst3.reset_n
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reset_n => seven_seg:inst1.reset_n
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in_buttons[0] => buttons:inst2.buttons[0]
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in_buttons[1] => buttons:inst2.buttons[1]
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in_buttons[2] => buttons:inst2.buttons[2]
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in_buttons[3] => buttons:inst2.buttons[3]
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in_buttons[4] => buttons:inst2.buttons[4]
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row2[0] <= out_LEDs[12].DB_MAX_OUTPUT_PORT_TYPE
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row2[1] <= out_LEDs[13].DB_MAX_OUTPUT_PORT_TYPE
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row2[2] <= out_LEDs[14].DB_MAX_OUTPUT_PORT_TYPE
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row2[3] <= out_LEDs[15].DB_MAX_OUTPUT_PORT_TYPE
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row2[4] <= out_LEDs[16].DB_MAX_OUTPUT_PORT_TYPE
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row2[5] <= out_LEDs[17].DB_MAX_OUTPUT_PORT_TYPE
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row2[6] <= out_LEDs[18].DB_MAX_OUTPUT_PORT_TYPE
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row2[7] <= out_LEDs[19].DB_MAX_OUTPUT_PORT_TYPE
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row2[8] <= out_LEDs[20].DB_MAX_OUTPUT_PORT_TYPE
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row2[9] <= out_LEDs[21].DB_MAX_OUTPUT_PORT_TYPE
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row2[10] <= out_LEDs[22].DB_MAX_OUTPUT_PORT_TYPE
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row2[11] <= out_LEDs[23].DB_MAX_OUTPUT_PORT_TYPE
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row3[0] <= out_LEDs[24].DB_MAX_OUTPUT_PORT_TYPE
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row3[1] <= out_LEDs[25].DB_MAX_OUTPUT_PORT_TYPE
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row3[2] <= out_LEDs[26].DB_MAX_OUTPUT_PORT_TYPE
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row3[3] <= out_LEDs[27].DB_MAX_OUTPUT_PORT_TYPE
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row3[4] <= out_LEDs[28].DB_MAX_OUTPUT_PORT_TYPE
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row3[5] <= out_LEDs[29].DB_MAX_OUTPUT_PORT_TYPE
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row3[6] <= out_LEDs[30].DB_MAX_OUTPUT_PORT_TYPE
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row3[7] <= out_LEDs[31].DB_MAX_OUTPUT_PORT_TYPE
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row3[8] <= out_LEDs[32].DB_MAX_OUTPUT_PORT_TYPE
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row3[9] <= out_LEDs[33].DB_MAX_OUTPUT_PORT_TYPE
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row3[10] <= out_LEDs[34].DB_MAX_OUTPUT_PORT_TYPE
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row3[11] <= out_LEDs[35].DB_MAX_OUTPUT_PORT_TYPE
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row4[0] <= out_LEDs[36].DB_MAX_OUTPUT_PORT_TYPE
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row4[1] <= out_LEDs[37].DB_MAX_OUTPUT_PORT_TYPE
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row4[2] <= out_LEDs[38].DB_MAX_OUTPUT_PORT_TYPE
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row4[3] <= out_LEDs[39].DB_MAX_OUTPUT_PORT_TYPE
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row4[4] <= out_LEDs[40].DB_MAX_OUTPUT_PORT_TYPE
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row4[5] <= out_LEDs[41].DB_MAX_OUTPUT_PORT_TYPE
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row4[6] <= out_LEDs[42].DB_MAX_OUTPUT_PORT_TYPE
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row4[7] <= out_LEDs[43].DB_MAX_OUTPUT_PORT_TYPE
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row4[8] <= out_LEDs[44].DB_MAX_OUTPUT_PORT_TYPE
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row4[9] <= out_LEDs[45].DB_MAX_OUTPUT_PORT_TYPE
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row4[10] <= out_LEDs[46].DB_MAX_OUTPUT_PORT_TYPE
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row4[11] <= out_LEDs[47].DB_MAX_OUTPUT_PORT_TYPE
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row5[0] <= out_LEDs[48].DB_MAX_OUTPUT_PORT_TYPE
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row5[1] <= out_LEDs[49].DB_MAX_OUTPUT_PORT_TYPE
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row5[2] <= out_LEDs[50].DB_MAX_OUTPUT_PORT_TYPE
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row5[3] <= out_LEDs[51].DB_MAX_OUTPUT_PORT_TYPE
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row5[4] <= out_LEDs[52].DB_MAX_OUTPUT_PORT_TYPE
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row5[5] <= out_LEDs[53].DB_MAX_OUTPUT_PORT_TYPE
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row5[6] <= out_LEDs[54].DB_MAX_OUTPUT_PORT_TYPE
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row5[7] <= out_LEDs[55].DB_MAX_OUTPUT_PORT_TYPE
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row5[8] <= out_LEDs[56].DB_MAX_OUTPUT_PORT_TYPE
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row5[9] <= out_LEDs[57].DB_MAX_OUTPUT_PORT_TYPE
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row5[10] <= out_LEDs[58].DB_MAX_OUTPUT_PORT_TYPE
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row5[11] <= out_LEDs[59].DB_MAX_OUTPUT_PORT_TYPE
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row6[0] <= out_LEDs[60].DB_MAX_OUTPUT_PORT_TYPE
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row6[1] <= out_LEDs[61].DB_MAX_OUTPUT_PORT_TYPE
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row6[2] <= out_LEDs[62].DB_MAX_OUTPUT_PORT_TYPE
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row6[3] <= out_LEDs[63].DB_MAX_OUTPUT_PORT_TYPE
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row6[4] <= out_LEDs[64].DB_MAX_OUTPUT_PORT_TYPE
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row6[5] <= out_LEDs[65].DB_MAX_OUTPUT_PORT_TYPE
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row6[6] <= out_LEDs[66].DB_MAX_OUTPUT_PORT_TYPE
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row6[7] <= out_LEDs[67].DB_MAX_OUTPUT_PORT_TYPE
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row6[8] <= out_LEDs[68].DB_MAX_OUTPUT_PORT_TYPE
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row6[9] <= out_LEDs[69].DB_MAX_OUTPUT_PORT_TYPE
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row6[10] <= out_LEDs[70].DB_MAX_OUTPUT_PORT_TYPE
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row6[11] <= out_LEDs[71].DB_MAX_OUTPUT_PORT_TYPE
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row7[0] <= out_LEDs[72].DB_MAX_OUTPUT_PORT_TYPE
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row7[1] <= out_LEDs[73].DB_MAX_OUTPUT_PORT_TYPE
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row7[2] <= out_LEDs[74].DB_MAX_OUTPUT_PORT_TYPE
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row7[3] <= out_LEDs[75].DB_MAX_OUTPUT_PORT_TYPE
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row7[4] <= out_LEDs[76].DB_MAX_OUTPUT_PORT_TYPE
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row7[5] <= out_LEDs[77].DB_MAX_OUTPUT_PORT_TYPE
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row7[6] <= out_LEDs[78].DB_MAX_OUTPUT_PORT_TYPE
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row7[7] <= out_LEDs[79].DB_MAX_OUTPUT_PORT_TYPE
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row7[8] <= out_LEDs[80].DB_MAX_OUTPUT_PORT_TYPE
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row7[9] <= out_LEDs[81].DB_MAX_OUTPUT_PORT_TYPE
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row7[10] <= out_LEDs[82].DB_MAX_OUTPUT_PORT_TYPE
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row7[11] <= out_LEDs[83].DB_MAX_OUTPUT_PORT_TYPE
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row8[0] <= out_LEDs[84].DB_MAX_OUTPUT_PORT_TYPE
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row8[1] <= out_LEDs[85].DB_MAX_OUTPUT_PORT_TYPE
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row8[2] <= out_LEDs[86].DB_MAX_OUTPUT_PORT_TYPE
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row8[3] <= out_LEDs[87].DB_MAX_OUTPUT_PORT_TYPE
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row8[4] <= out_LEDs[88].DB_MAX_OUTPUT_PORT_TYPE
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row8[5] <= out_LEDs[89].DB_MAX_OUTPUT_PORT_TYPE
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row8[6] <= out_LEDs[90].DB_MAX_OUTPUT_PORT_TYPE
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row8[7] <= out_LEDs[91].DB_MAX_OUTPUT_PORT_TYPE
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row8[8] <= out_LEDs[92].DB_MAX_OUTPUT_PORT_TYPE
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row8[9] <= out_LEDs[93].DB_MAX_OUTPUT_PORT_TYPE
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row8[10] <= out_LEDs[94].DB_MAX_OUTPUT_PORT_TYPE
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row8[11] <= out_LEDs[95].DB_MAX_OUTPUT_PORT_TYPE
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seg_out[0] <= seven_seg:inst1.seg_out[0]
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seg_out[1] <= seven_seg:inst1.seg_out[1]
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seg_out[2] <= seven_seg:inst1.seg_out[2]
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seg_out[3] <= seven_seg:inst1.seg_out[3]
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seg_out[4] <= seven_seg:inst1.seg_out[4]
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seg_out[5] <= seven_seg:inst1.seg_out[5]
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seg_out[6] <= seven_seg:inst1.seg_out[6]
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seg_out[7] <= seven_seg:inst1.seg_out[7]
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seg_out[8] <= seven_seg:inst1.seg_out[8]
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seg_out[9] <= seven_seg:inst1.seg_out[9]
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seg_out[10] <= seven_seg:inst1.seg_out[10]
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seg_out[11] <= seven_seg:inst1.seg_out[11]
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seg_out[12] <= seven_seg:inst1.seg_out[12]
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seg_out[13] <= seven_seg:inst1.seg_out[13]
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seg_out[14] <= seven_seg:inst1.seg_out[14]
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seg_out[15] <= seven_seg:inst1.seg_out[15]
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seg_out[16] <= seven_seg:inst1.seg_out[16]
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seg_out[17] <= seven_seg:inst1.seg_out[17]
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seg_out[18] <= seven_seg:inst1.seg_out[18]
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seg_out[19] <= seven_seg:inst1.seg_out[19]
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seg_out[20] <= seven_seg:inst1.seg_out[20]
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seg_out[21] <= seven_seg:inst1.seg_out[21]
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seg_out[22] <= seven_seg:inst1.seg_out[22]
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seg_out[23] <= seven_seg:inst1.seg_out[23]
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seg_out[24] <= seven_seg:inst1.seg_out[24]
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seg_out[25] <= seven_seg:inst1.seg_out[25]
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seg_out[26] <= seven_seg:inst1.seg_out[26]
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seg_out[27] <= seven_seg:inst1.seg_out[27]
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seg_out[28] <= seven_seg:inst1.seg_out[28]
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seg_out[29] <= seven_seg:inst1.seg_out[29]
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seg_out[30] <= seven_seg:inst1.seg_out[30]
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seg_out[31] <= seven_seg:inst1.seg_out[31]
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|GECKO|LEDs:LEDs_0
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clk => duty_cycle[0].CLK
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clk => duty_cycle[1].CLK
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clk => duty_cycle[2].CLK
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clk => duty_cycle[3].CLK
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clk => duty_cycle[4].CLK
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clk => duty_cycle[5].CLK
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clk => duty_cycle[6].CLK
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clk => duty_cycle[7].CLK
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clk => LEDs_reg[0].CLK
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clk => LEDs_reg[1].CLK
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clk => LEDs_reg[2].CLK
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clk => LEDs_reg[3].CLK
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clk => LEDs_reg[4].CLK
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clk => LEDs_reg[5].CLK
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clk => LEDs_reg[6].CLK
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clk => LEDs_reg[7].CLK
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clk => LEDs_reg[8].CLK
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clk => LEDs_reg[9].CLK
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clk => LEDs_reg[10].CLK
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clk => LEDs_reg[11].CLK
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clk => LEDs_reg[12].CLK
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clk => LEDs_reg[13].CLK
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clk => LEDs_reg[14].CLK
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clk => LEDs_reg[15].CLK
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clk => LEDs_reg[16].CLK
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clk => LEDs_reg[17].CLK
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clk => LEDs_reg[18].CLK
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clk => LEDs_reg[19].CLK
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clk => LEDs_reg[20].CLK
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clk => LEDs_reg[21].CLK
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clk => LEDs_reg[22].CLK
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clk => LEDs_reg[23].CLK
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clk => LEDs_reg[24].CLK
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clk => LEDs_reg[25].CLK
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clk => LEDs_reg[26].CLK
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clk => LEDs_reg[27].CLK
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clk => LEDs_reg[28].CLK
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clk => LEDs_reg[29].CLK
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clk => LEDs_reg[30].CLK
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clk => LEDs_reg[31].CLK
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clk => LEDs_reg[32].CLK
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clk => LEDs_reg[33].CLK
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clk => LEDs_reg[34].CLK
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clk => LEDs_reg[35].CLK
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clk => LEDs_reg[36].CLK
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clk => LEDs_reg[37].CLK
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clk => LEDs_reg[38].CLK
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clk => LEDs_reg[39].CLK
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clk => LEDs_reg[40].CLK
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clk => LEDs_reg[41].CLK
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clk => LEDs_reg[42].CLK
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clk => LEDs_reg[43].CLK
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clk => LEDs_reg[44].CLK
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clk => LEDs_reg[45].CLK
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clk => LEDs_reg[46].CLK
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clk => LEDs_reg[47].CLK
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clk => LEDs_reg[48].CLK
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clk => LEDs_reg[49].CLK
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clk => LEDs_reg[50].CLK
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clk => LEDs_reg[51].CLK
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clk => LEDs_reg[52].CLK
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clk => LEDs_reg[53].CLK
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clk => LEDs_reg[54].CLK
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clk => LEDs_reg[55].CLK
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clk => LEDs_reg[56].CLK
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clk => LEDs_reg[57].CLK
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clk => LEDs_reg[58].CLK
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clk => LEDs_reg[59].CLK
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clk => LEDs_reg[60].CLK
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clk => LEDs_reg[61].CLK
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clk => LEDs_reg[62].CLK
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clk => LEDs_reg[63].CLK
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clk => LEDs_reg[64].CLK
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clk => LEDs_reg[65].CLK
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clk => LEDs_reg[66].CLK
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clk => LEDs_reg[67].CLK
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clk => LEDs_reg[68].CLK
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clk => LEDs_reg[69].CLK
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clk => LEDs_reg[70].CLK
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clk => LEDs_reg[71].CLK
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clk => LEDs_reg[72].CLK
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clk => LEDs_reg[73].CLK
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clk => LEDs_reg[74].CLK
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clk => LEDs_reg[75].CLK
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clk => LEDs_reg[76].CLK
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clk => LEDs_reg[77].CLK
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clk => LEDs_reg[78].CLK
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clk => LEDs_reg[79].CLK
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clk => LEDs_reg[80].CLK
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clk => LEDs_reg[81].CLK
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clk => LEDs_reg[82].CLK
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clk => LEDs_reg[83].CLK
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clk => LEDs_reg[84].CLK
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clk => LEDs_reg[85].CLK
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clk => LEDs_reg[86].CLK
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clk => LEDs_reg[87].CLK
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clk => LEDs_reg[88].CLK
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clk => LEDs_reg[89].CLK
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clk => LEDs_reg[90].CLK
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clk => LEDs_reg[91].CLK
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clk => LEDs_reg[92].CLK
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clk => LEDs_reg[93].CLK
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clk => LEDs_reg[94].CLK
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clk => LEDs_reg[95].CLK
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clk => counter[0].CLK
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clk => counter[1].CLK
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clk => counter[2].CLK
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clk => counter[3].CLK
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clk => counter[4].CLK
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clk => counter[5].CLK
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clk => counter[6].CLK
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clk => counter[7].CLK
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clk => reg_address[0].CLK
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clk => reg_address[1].CLK
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clk => reg_read.CLK
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reset_n => duty_cycle[0].PRESET
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reset_n => duty_cycle[1].PRESET
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reset_n => duty_cycle[2].PRESET
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reset_n => duty_cycle[3].PRESET
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reset_n => duty_cycle[4].ACLR
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reset_n => duty_cycle[5].ACLR
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reset_n => duty_cycle[6].ACLR
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reset_n => duty_cycle[7].ACLR
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reset_n => LEDs_reg[0].ACLR
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reset_n => LEDs_reg[1].ACLR
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reset_n => LEDs_reg[2].ACLR
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reset_n => LEDs_reg[3].ACLR
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reset_n => LEDs_reg[4].ACLR
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reset_n => LEDs_reg[5].ACLR
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reset_n => LEDs_reg[6].ACLR
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reset_n => LEDs_reg[7].ACLR
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reset_n => LEDs_reg[8].ACLR
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reset_n => LEDs_reg[9].ACLR
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reset_n => LEDs_reg[10].ACLR
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reset_n => LEDs_reg[11].ACLR
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reset_n => LEDs_reg[12].ACLR
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reset_n => LEDs_reg[13].ACLR
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reset_n => LEDs_reg[14].ACLR
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reset_n => LEDs_reg[15].ACLR
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reset_n => LEDs_reg[16].ACLR
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reset_n => LEDs_reg[17].ACLR
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reset_n => LEDs_reg[18].ACLR
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reset_n => LEDs_reg[19].ACLR
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reset_n => LEDs_reg[20].ACLR
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reset_n => LEDs_reg[21].ACLR
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reset_n => LEDs_reg[22].ACLR
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reset_n => LEDs_reg[23].ACLR
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reset_n => LEDs_reg[24].ACLR
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reset_n => LEDs_reg[25].ACLR
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reset_n => LEDs_reg[26].ACLR
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reset_n => LEDs_reg[27].ACLR
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reset_n => LEDs_reg[28].ACLR
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reset_n => LEDs_reg[29].ACLR
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reset_n => LEDs_reg[30].ACLR
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reset_n => LEDs_reg[31].ACLR
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reset_n => LEDs_reg[32].ACLR
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reset_n => LEDs_reg[33].ACLR
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reset_n => LEDs_reg[34].ACLR
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reset_n => LEDs_reg[35].ACLR
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reset_n => LEDs_reg[36].ACLR
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reset_n => LEDs_reg[37].ACLR
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reset_n => LEDs_reg[38].ACLR
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reset_n => LEDs_reg[39].ACLR
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reset_n => LEDs_reg[40].ACLR
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reset_n => LEDs_reg[41].ACLR
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reset_n => LEDs_reg[42].ACLR
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reset_n => LEDs_reg[43].ACLR
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reset_n => LEDs_reg[44].ACLR
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reset_n => LEDs_reg[45].ACLR
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reset_n => LEDs_reg[46].ACLR
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reset_n => LEDs_reg[47].ACLR
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reset_n => LEDs_reg[48].ACLR
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reset_n => LEDs_reg[49].ACLR
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reset_n => LEDs_reg[50].ACLR
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reset_n => LEDs_reg[51].ACLR
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reset_n => LEDs_reg[52].ACLR
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reset_n => LEDs_reg[53].ACLR
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reset_n => LEDs_reg[54].ACLR
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reset_n => LEDs_reg[55].ACLR
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reset_n => LEDs_reg[56].ACLR
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reset_n => LEDs_reg[57].ACLR
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reset_n => LEDs_reg[58].ACLR
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reset_n => LEDs_reg[59].ACLR
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reset_n => LEDs_reg[60].ACLR
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reset_n => LEDs_reg[61].ACLR
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reset_n => LEDs_reg[62].ACLR
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reset_n => LEDs_reg[63].ACLR
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reset_n => LEDs_reg[64].ACLR
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reset_n => LEDs_reg[65].ACLR
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reset_n => LEDs_reg[66].ACLR
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reset_n => LEDs_reg[67].ACLR
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reset_n => LEDs_reg[68].ACLR
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reset_n => LEDs_reg[69].ACLR
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reset_n => LEDs_reg[70].ACLR
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reset_n => LEDs_reg[71].ACLR
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reset_n => LEDs_reg[72].ACLR
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reset_n => LEDs_reg[73].ACLR
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reset_n => LEDs_reg[74].ACLR
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reset_n => LEDs_reg[75].ACLR
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reset_n => LEDs_reg[76].ACLR
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reset_n => LEDs_reg[77].ACLR
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reset_n => LEDs_reg[78].ACLR
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reset_n => LEDs_reg[79].ACLR
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reset_n => LEDs_reg[80].ACLR
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reset_n => LEDs_reg[81].ACLR
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reset_n => LEDs_reg[82].ACLR
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reset_n => LEDs_reg[83].ACLR
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reset_n => LEDs_reg[84].ACLR
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reset_n => LEDs_reg[85].ACLR
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reset_n => LEDs_reg[86].ACLR
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reset_n => LEDs_reg[87].ACLR
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reset_n => LEDs_reg[88].ACLR
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reset_n => LEDs_reg[89].ACLR
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reset_n => LEDs_reg[90].ACLR
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reset_n => LEDs_reg[91].ACLR
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reset_n => LEDs_reg[92].ACLR
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reset_n => LEDs_reg[93].ACLR
|
|
reset_n => LEDs_reg[94].ACLR
|
|
reset_n => LEDs_reg[95].ACLR
|
|
reset_n => counter[0].ACLR
|
|
reset_n => counter[1].ACLR
|
|
reset_n => counter[2].ACLR
|
|
reset_n => counter[3].ACLR
|
|
reset_n => counter[4].ACLR
|
|
reset_n => counter[5].ACLR
|
|
reset_n => counter[6].ACLR
|
|
reset_n => counter[7].ACLR
|
|
reset_n => reg_address[0].ACLR
|
|
reset_n => reg_address[1].ACLR
|
|
reset_n => reg_read.ACLR
|
|
cs => reg_read.IN0
|
|
cs => process_3.IN0
|
|
read => reg_read.IN1
|
|
write => process_3.IN1
|
|
address[0] => Mux32.IN1
|
|
address[0] => Mux33.IN1
|
|
address[0] => Mux34.IN1
|
|
address[0] => Mux35.IN1
|
|
address[0] => Mux36.IN1
|
|
address[0] => Mux37.IN1
|
|
address[0] => Mux38.IN1
|
|
address[0] => Mux39.IN1
|
|
address[0] => Mux40.IN1
|
|
address[0] => Mux41.IN1
|
|
address[0] => Mux42.IN1
|
|
address[0] => Mux43.IN1
|
|
address[0] => Mux44.IN1
|
|
address[0] => Mux45.IN1
|
|
address[0] => Mux46.IN1
|
|
address[0] => Mux47.IN1
|
|
address[0] => Mux48.IN1
|
|
address[0] => Mux49.IN1
|
|
address[0] => Mux50.IN1
|
|
address[0] => Mux51.IN1
|
|
address[0] => Mux52.IN1
|
|
address[0] => Mux53.IN1
|
|
address[0] => Mux54.IN1
|
|
address[0] => Mux55.IN1
|
|
address[0] => Mux56.IN1
|
|
address[0] => Mux57.IN1
|
|
address[0] => Mux58.IN1
|
|
address[0] => Mux59.IN1
|
|
address[0] => Mux60.IN1
|
|
address[0] => Mux61.IN1
|
|
address[0] => Mux62.IN1
|
|
address[0] => Mux63.IN1
|
|
address[0] => Mux64.IN1
|
|
address[0] => Mux65.IN1
|
|
address[0] => Mux66.IN1
|
|
address[0] => Mux67.IN1
|
|
address[0] => Mux68.IN1
|
|
address[0] => Mux69.IN1
|
|
address[0] => Mux70.IN1
|
|
address[0] => Mux71.IN1
|
|
address[0] => Mux72.IN1
|
|
address[0] => Mux73.IN1
|
|
address[0] => Mux74.IN1
|
|
address[0] => Mux75.IN1
|
|
address[0] => Mux76.IN1
|
|
address[0] => Mux77.IN1
|
|
address[0] => Mux78.IN1
|
|
address[0] => Mux79.IN1
|
|
address[0] => Mux80.IN1
|
|
address[0] => Mux81.IN1
|
|
address[0] => Mux82.IN1
|
|
address[0] => Mux83.IN1
|
|
address[0] => Mux84.IN1
|
|
address[0] => Mux85.IN1
|
|
address[0] => Mux86.IN1
|
|
address[0] => Mux87.IN1
|
|
address[0] => Mux88.IN1
|
|
address[0] => Mux89.IN1
|
|
address[0] => Mux90.IN1
|
|
address[0] => Mux91.IN1
|
|
address[0] => Mux92.IN1
|
|
address[0] => Mux93.IN1
|
|
address[0] => Mux94.IN1
|
|
address[0] => Mux95.IN1
|
|
address[0] => Mux96.IN1
|
|
address[0] => Mux97.IN1
|
|
address[0] => Mux98.IN1
|
|
address[0] => Mux99.IN1
|
|
address[0] => Mux100.IN1
|
|
address[0] => Mux101.IN1
|
|
address[0] => Mux102.IN1
|
|
address[0] => Mux103.IN1
|
|
address[0] => Mux104.IN1
|
|
address[0] => Mux105.IN1
|
|
address[0] => Mux106.IN1
|
|
address[0] => Mux107.IN1
|
|
address[0] => Mux108.IN1
|
|
address[0] => Mux109.IN1
|
|
address[0] => Mux110.IN1
|
|
address[0] => Mux111.IN1
|
|
address[0] => Mux112.IN1
|
|
address[0] => Mux113.IN1
|
|
address[0] => Mux114.IN1
|
|
address[0] => Mux115.IN1
|
|
address[0] => Mux116.IN1
|
|
address[0] => Mux117.IN1
|
|
address[0] => Mux118.IN1
|
|
address[0] => Mux119.IN1
|
|
address[0] => Mux120.IN1
|
|
address[0] => Mux121.IN1
|
|
address[0] => Mux122.IN1
|
|
address[0] => Mux123.IN1
|
|
address[0] => Mux124.IN1
|
|
address[0] => Mux125.IN1
|
|
address[0] => Mux126.IN1
|
|
address[0] => Mux127.IN1
|
|
address[0] => Mux128.IN1
|
|
address[0] => Mux129.IN1
|
|
address[0] => Mux130.IN1
|
|
address[0] => Mux131.IN1
|
|
address[0] => Mux132.IN1
|
|
address[0] => Mux133.IN1
|
|
address[0] => Mux134.IN1
|
|
address[0] => Mux135.IN1
|
|
address[0] => reg_address[0].DATAIN
|
|
address[0] => Equal0.IN1
|
|
address[1] => Mux32.IN0
|
|
address[1] => Mux33.IN0
|
|
address[1] => Mux34.IN0
|
|
address[1] => Mux35.IN0
|
|
address[1] => Mux36.IN0
|
|
address[1] => Mux37.IN0
|
|
address[1] => Mux38.IN0
|
|
address[1] => Mux39.IN0
|
|
address[1] => Mux40.IN0
|
|
address[1] => Mux41.IN0
|
|
address[1] => Mux42.IN0
|
|
address[1] => Mux43.IN0
|
|
address[1] => Mux44.IN0
|
|
address[1] => Mux45.IN0
|
|
address[1] => Mux46.IN0
|
|
address[1] => Mux47.IN0
|
|
address[1] => Mux48.IN0
|
|
address[1] => Mux49.IN0
|
|
address[1] => Mux50.IN0
|
|
address[1] => Mux51.IN0
|
|
address[1] => Mux52.IN0
|
|
address[1] => Mux53.IN0
|
|
address[1] => Mux54.IN0
|
|
address[1] => Mux55.IN0
|
|
address[1] => Mux56.IN0
|
|
address[1] => Mux57.IN0
|
|
address[1] => Mux58.IN0
|
|
address[1] => Mux59.IN0
|
|
address[1] => Mux60.IN0
|
|
address[1] => Mux61.IN0
|
|
address[1] => Mux62.IN0
|
|
address[1] => Mux63.IN0
|
|
address[1] => Mux64.IN0
|
|
address[1] => Mux65.IN0
|
|
address[1] => Mux66.IN0
|
|
address[1] => Mux67.IN0
|
|
address[1] => Mux68.IN0
|
|
address[1] => Mux69.IN0
|
|
address[1] => Mux70.IN0
|
|
address[1] => Mux71.IN0
|
|
address[1] => Mux72.IN0
|
|
address[1] => Mux73.IN0
|
|
address[1] => Mux74.IN0
|
|
address[1] => Mux75.IN0
|
|
address[1] => Mux76.IN0
|
|
address[1] => Mux77.IN0
|
|
address[1] => Mux78.IN0
|
|
address[1] => Mux79.IN0
|
|
address[1] => Mux80.IN0
|
|
address[1] => Mux81.IN0
|
|
address[1] => Mux82.IN0
|
|
address[1] => Mux83.IN0
|
|
address[1] => Mux84.IN0
|
|
address[1] => Mux85.IN0
|
|
address[1] => Mux86.IN0
|
|
address[1] => Mux87.IN0
|
|
address[1] => Mux88.IN0
|
|
address[1] => Mux89.IN0
|
|
address[1] => Mux90.IN0
|
|
address[1] => Mux91.IN0
|
|
address[1] => Mux92.IN0
|
|
address[1] => Mux93.IN0
|
|
address[1] => Mux94.IN0
|
|
address[1] => Mux95.IN0
|
|
address[1] => Mux96.IN0
|
|
address[1] => Mux97.IN0
|
|
address[1] => Mux98.IN0
|
|
address[1] => Mux99.IN0
|
|
address[1] => Mux100.IN0
|
|
address[1] => Mux101.IN0
|
|
address[1] => Mux102.IN0
|
|
address[1] => Mux103.IN0
|
|
address[1] => Mux104.IN0
|
|
address[1] => Mux105.IN0
|
|
address[1] => Mux106.IN0
|
|
address[1] => Mux107.IN0
|
|
address[1] => Mux108.IN0
|
|
address[1] => Mux109.IN0
|
|
address[1] => Mux110.IN0
|
|
address[1] => Mux111.IN0
|
|
address[1] => Mux112.IN0
|
|
address[1] => Mux113.IN0
|
|
address[1] => Mux114.IN0
|
|
address[1] => Mux115.IN0
|
|
address[1] => Mux116.IN0
|
|
address[1] => Mux117.IN0
|
|
address[1] => Mux118.IN0
|
|
address[1] => Mux119.IN0
|
|
address[1] => Mux120.IN0
|
|
address[1] => Mux121.IN0
|
|
address[1] => Mux122.IN0
|
|
address[1] => Mux123.IN0
|
|
address[1] => Mux124.IN0
|
|
address[1] => Mux125.IN0
|
|
address[1] => Mux126.IN0
|
|
address[1] => Mux127.IN0
|
|
address[1] => Mux128.IN0
|
|
address[1] => Mux129.IN0
|
|
address[1] => Mux130.IN0
|
|
address[1] => Mux131.IN0
|
|
address[1] => Mux132.IN0
|
|
address[1] => Mux133.IN0
|
|
address[1] => Mux134.IN0
|
|
address[1] => Mux135.IN0
|
|
address[1] => reg_address[1].DATAIN
|
|
address[1] => Equal0.IN0
|
|
rddata[0] <= rddata[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[1] <= rddata[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[2] <= rddata[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[3] <= rddata[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[4] <= rddata[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[5] <= rddata[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[6] <= rddata[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[7] <= rddata[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[8] <= rddata[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[9] <= rddata[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[10] <= rddata[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[11] <= rddata[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[12] <= rddata[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[13] <= rddata[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[14] <= rddata[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[15] <= rddata[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[16] <= rddata[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[17] <= rddata[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[18] <= rddata[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[19] <= rddata[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[20] <= rddata[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[21] <= rddata[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[22] <= rddata[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[23] <= rddata[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[24] <= rddata[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[25] <= rddata[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[26] <= rddata[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[27] <= rddata[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[28] <= rddata[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[29] <= rddata[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[30] <= rddata[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[31] <= rddata[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
wrdata[0] => Mux63.IN2
|
|
wrdata[0] => Mux95.IN2
|
|
wrdata[0] => Mux127.IN2
|
|
wrdata[0] => Mux135.IN2
|
|
wrdata[1] => Mux62.IN2
|
|
wrdata[1] => Mux94.IN2
|
|
wrdata[1] => Mux126.IN2
|
|
wrdata[1] => Mux134.IN2
|
|
wrdata[2] => Mux61.IN2
|
|
wrdata[2] => Mux93.IN2
|
|
wrdata[2] => Mux125.IN2
|
|
wrdata[2] => Mux133.IN2
|
|
wrdata[3] => Mux60.IN2
|
|
wrdata[3] => Mux92.IN2
|
|
wrdata[3] => Mux124.IN2
|
|
wrdata[3] => Mux132.IN2
|
|
wrdata[4] => Mux59.IN2
|
|
wrdata[4] => Mux91.IN2
|
|
wrdata[4] => Mux123.IN2
|
|
wrdata[4] => Mux131.IN2
|
|
wrdata[5] => Mux58.IN2
|
|
wrdata[5] => Mux90.IN2
|
|
wrdata[5] => Mux122.IN2
|
|
wrdata[5] => Mux130.IN2
|
|
wrdata[6] => Mux57.IN2
|
|
wrdata[6] => Mux89.IN2
|
|
wrdata[6] => Mux121.IN2
|
|
wrdata[6] => Mux129.IN2
|
|
wrdata[7] => Mux56.IN2
|
|
wrdata[7] => Mux88.IN2
|
|
wrdata[7] => Mux120.IN2
|
|
wrdata[7] => Mux128.IN2
|
|
wrdata[8] => Mux55.IN2
|
|
wrdata[8] => Mux87.IN2
|
|
wrdata[8] => Mux119.IN2
|
|
wrdata[9] => Mux54.IN2
|
|
wrdata[9] => Mux86.IN2
|
|
wrdata[9] => Mux118.IN2
|
|
wrdata[10] => Mux53.IN2
|
|
wrdata[10] => Mux85.IN2
|
|
wrdata[10] => Mux117.IN2
|
|
wrdata[11] => Mux52.IN2
|
|
wrdata[11] => Mux84.IN2
|
|
wrdata[11] => Mux116.IN2
|
|
wrdata[12] => Mux51.IN2
|
|
wrdata[12] => Mux83.IN2
|
|
wrdata[12] => Mux115.IN2
|
|
wrdata[13] => Mux50.IN2
|
|
wrdata[13] => Mux82.IN2
|
|
wrdata[13] => Mux114.IN2
|
|
wrdata[14] => Mux49.IN2
|
|
wrdata[14] => Mux81.IN2
|
|
wrdata[14] => Mux113.IN2
|
|
wrdata[15] => Mux48.IN2
|
|
wrdata[15] => Mux80.IN2
|
|
wrdata[15] => Mux112.IN2
|
|
wrdata[16] => Mux47.IN2
|
|
wrdata[16] => Mux79.IN2
|
|
wrdata[16] => Mux111.IN2
|
|
wrdata[17] => Mux46.IN2
|
|
wrdata[17] => Mux78.IN2
|
|
wrdata[17] => Mux110.IN2
|
|
wrdata[18] => Mux45.IN2
|
|
wrdata[18] => Mux77.IN2
|
|
wrdata[18] => Mux109.IN2
|
|
wrdata[19] => Mux44.IN2
|
|
wrdata[19] => Mux76.IN2
|
|
wrdata[19] => Mux108.IN2
|
|
wrdata[20] => Mux43.IN2
|
|
wrdata[20] => Mux75.IN2
|
|
wrdata[20] => Mux107.IN2
|
|
wrdata[21] => Mux42.IN2
|
|
wrdata[21] => Mux74.IN2
|
|
wrdata[21] => Mux106.IN2
|
|
wrdata[22] => Mux41.IN2
|
|
wrdata[22] => Mux73.IN2
|
|
wrdata[22] => Mux105.IN2
|
|
wrdata[23] => Mux40.IN2
|
|
wrdata[23] => Mux72.IN2
|
|
wrdata[23] => Mux104.IN2
|
|
wrdata[24] => Mux39.IN2
|
|
wrdata[24] => Mux71.IN2
|
|
wrdata[24] => Mux103.IN2
|
|
wrdata[25] => Mux38.IN2
|
|
wrdata[25] => Mux70.IN2
|
|
wrdata[25] => Mux102.IN2
|
|
wrdata[26] => Mux37.IN2
|
|
wrdata[26] => Mux69.IN2
|
|
wrdata[26] => Mux101.IN2
|
|
wrdata[27] => Mux36.IN2
|
|
wrdata[27] => Mux68.IN2
|
|
wrdata[27] => Mux100.IN2
|
|
wrdata[28] => Mux35.IN2
|
|
wrdata[28] => Mux67.IN2
|
|
wrdata[28] => Mux99.IN2
|
|
wrdata[29] => Mux34.IN2
|
|
wrdata[29] => Mux66.IN2
|
|
wrdata[29] => Mux98.IN2
|
|
wrdata[30] => Mux33.IN2
|
|
wrdata[30] => Mux65.IN2
|
|
wrdata[30] => Mux97.IN2
|
|
wrdata[31] => Mux32.IN2
|
|
wrdata[31] => Mux64.IN2
|
|
wrdata[31] => Mux96.IN2
|
|
LEDs[0] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[1] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[2] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[3] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[4] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[5] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[6] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[7] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[8] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[9] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[10] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[11] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[12] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[13] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[14] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[15] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[16] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[17] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[18] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[19] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[20] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[21] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[22] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[23] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[24] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[25] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[26] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[27] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[28] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[29] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[30] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[31] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[32] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[33] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[34] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[35] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[36] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[37] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[38] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[39] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[40] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[41] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[42] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[43] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[44] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[45] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[46] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[47] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[48] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[49] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[50] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[51] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[52] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[53] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[54] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[55] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[56] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[57] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[58] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[59] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[60] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[61] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[62] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[63] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[64] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[65] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[66] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[67] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[68] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[69] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[70] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[71] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[72] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[73] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[74] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[75] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[76] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[77] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[78] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[79] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[80] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[81] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[82] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[83] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[84] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[85] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[86] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[87] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[88] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[89] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[90] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[91] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[92] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[93] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[94] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
LEDs[95] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|GECKO|decoder:decoder_0
|
|
address[0] => ~NO_FANOUT~
|
|
address[1] => ~NO_FANOUT~
|
|
address[2] => ~NO_FANOUT~
|
|
address[3] => ~NO_FANOUT~
|
|
address[4] => ~NO_FANOUT~
|
|
address[5] => ~NO_FANOUT~
|
|
address[6] => ~NO_FANOUT~
|
|
address[7] => ~NO_FANOUT~
|
|
address[8] => ~NO_FANOUT~
|
|
address[9] => ~NO_FANOUT~
|
|
address[10] => ~NO_FANOUT~
|
|
address[11] => ~NO_FANOUT~
|
|
address[12] => ~NO_FANOUT~
|
|
address[13] => ~NO_FANOUT~
|
|
address[14] => ~NO_FANOUT~
|
|
address[15] => ~NO_FANOUT~
|
|
cs_Buttons <= <GND>
|
|
cs_LEDS <= <GND>
|
|
cs_RAM <= <GND>
|
|
cs_ROM <= <GND>
|
|
|
|
|
|
|GECKO|CPU:inst
|
|
write <= <GND>
|
|
clk => ~NO_FANOUT~
|
|
reset_n => ~NO_FANOUT~
|
|
rddata[0] => ~NO_FANOUT~
|
|
rddata[1] => ~NO_FANOUT~
|
|
rddata[2] => ~NO_FANOUT~
|
|
rddata[3] => ~NO_FANOUT~
|
|
rddata[4] => ~NO_FANOUT~
|
|
rddata[5] => ~NO_FANOUT~
|
|
rddata[6] => ~NO_FANOUT~
|
|
rddata[7] => ~NO_FANOUT~
|
|
rddata[8] => ~NO_FANOUT~
|
|
rddata[9] => ~NO_FANOUT~
|
|
rddata[10] => ~NO_FANOUT~
|
|
rddata[11] => ~NO_FANOUT~
|
|
rddata[12] => ~NO_FANOUT~
|
|
rddata[13] => ~NO_FANOUT~
|
|
rddata[14] => ~NO_FANOUT~
|
|
rddata[15] => ~NO_FANOUT~
|
|
rddata[16] => ~NO_FANOUT~
|
|
rddata[17] => ~NO_FANOUT~
|
|
rddata[18] => ~NO_FANOUT~
|
|
rddata[19] => ~NO_FANOUT~
|
|
rddata[20] => ~NO_FANOUT~
|
|
rddata[21] => ~NO_FANOUT~
|
|
rddata[22] => ~NO_FANOUT~
|
|
rddata[23] => ~NO_FANOUT~
|
|
rddata[24] => ~NO_FANOUT~
|
|
rddata[25] => ~NO_FANOUT~
|
|
rddata[26] => ~NO_FANOUT~
|
|
rddata[27] => ~NO_FANOUT~
|
|
rddata[28] => ~NO_FANOUT~
|
|
rddata[29] => ~NO_FANOUT~
|
|
rddata[30] => ~NO_FANOUT~
|
|
rddata[31] => ~NO_FANOUT~
|
|
read <= <GND>
|
|
address[0] <= <GND>
|
|
address[1] <= <GND>
|
|
address[2] <= <GND>
|
|
address[3] <= <GND>
|
|
address[4] <= <GND>
|
|
address[5] <= <GND>
|
|
address[6] <= <GND>
|
|
address[7] <= <GND>
|
|
address[8] <= <GND>
|
|
address[9] <= <GND>
|
|
address[10] <= <GND>
|
|
address[11] <= <GND>
|
|
address[12] <= <GND>
|
|
address[13] <= <GND>
|
|
address[14] <= <GND>
|
|
address[15] <= <GND>
|
|
wrdata[0] <= <GND>
|
|
wrdata[1] <= <GND>
|
|
wrdata[2] <= <GND>
|
|
wrdata[3] <= <GND>
|
|
wrdata[4] <= <GND>
|
|
wrdata[5] <= <GND>
|
|
wrdata[6] <= <GND>
|
|
wrdata[7] <= <GND>
|
|
wrdata[8] <= <GND>
|
|
wrdata[9] <= <GND>
|
|
wrdata[10] <= <GND>
|
|
wrdata[11] <= <GND>
|
|
wrdata[12] <= <GND>
|
|
wrdata[13] <= <GND>
|
|
wrdata[14] <= <GND>
|
|
wrdata[15] <= <GND>
|
|
wrdata[16] <= <GND>
|
|
wrdata[17] <= <GND>
|
|
wrdata[18] <= <GND>
|
|
wrdata[19] <= <GND>
|
|
wrdata[20] <= <GND>
|
|
wrdata[21] <= <GND>
|
|
wrdata[22] <= <GND>
|
|
wrdata[23] <= <GND>
|
|
wrdata[24] <= <GND>
|
|
wrdata[25] <= <GND>
|
|
wrdata[26] <= <GND>
|
|
wrdata[27] <= <GND>
|
|
wrdata[28] <= <GND>
|
|
wrdata[29] <= <GND>
|
|
wrdata[30] <= <GND>
|
|
wrdata[31] <= <GND>
|
|
|
|
|
|
|GECKO|ROM:ROM_0
|
|
clk => iD_S_b88a693_7e3412F0_e:ROM_inst.iD_S_B88665F_7e7082e6_e
|
|
cs => iD_S_b88a693_7e3412F0_e:ROM_inst.Id_S_59777b_7FFCe7eC_E
|
|
read => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_c89sdnc7u_sda09scah_E
|
|
address[0] => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_daf34r31df1d_0y8wefh80_E[0]
|
|
address[1] => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_daf34r31df1d_0y8wefh80_E[1]
|
|
address[2] => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_daf34r31df1d_0y8wefh80_E[2]
|
|
address[3] => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_daf34r31df1d_0y8wefh80_E[3]
|
|
address[4] => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_daf34r31df1d_0y8wefh80_E[4]
|
|
address[5] => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_daf34r31df1d_0y8wefh80_E[5]
|
|
address[6] => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_daf34r31df1d_0y8wefh80_E[6]
|
|
address[7] => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_daf34r31df1d_0y8wefh80_E[7]
|
|
address[8] => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_daf34r31df1d_0y8wefh80_E[8]
|
|
address[9] => iD_S_b88a693_7e3412F0_e:ROM_inst.id_s_daf34r31df1d_0y8wefh80_E[9]
|
|
rddata[0] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[0]
|
|
rddata[1] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[1]
|
|
rddata[2] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[2]
|
|
rddata[3] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[3]
|
|
rddata[4] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[4]
|
|
rddata[5] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[5]
|
|
rddata[6] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[6]
|
|
rddata[7] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[7]
|
|
rddata[8] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[8]
|
|
rddata[9] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[9]
|
|
rddata[10] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[10]
|
|
rddata[11] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[11]
|
|
rddata[12] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[12]
|
|
rddata[13] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[13]
|
|
rddata[14] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[14]
|
|
rddata[15] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[15]
|
|
rddata[16] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[16]
|
|
rddata[17] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[17]
|
|
rddata[18] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[18]
|
|
rddata[19] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[19]
|
|
rddata[20] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[20]
|
|
rddata[21] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[21]
|
|
rddata[22] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[22]
|
|
rddata[23] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[23]
|
|
rddata[24] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[24]
|
|
rddata[25] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[25]
|
|
rddata[26] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[26]
|
|
rddata[27] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[27]
|
|
rddata[28] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[28]
|
|
rddata[29] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[29]
|
|
rddata[30] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[30]
|
|
rddata[31] <= iD_S_b88a693_7e3412F0_e:ROM_inst.ID_S_191530b5_24e2B0Bf_E[31]
|
|
|
|
|
|
|GECKO|ROM:ROM_0|iD_S_b88a693_7e3412F0_e:ROM_inst
|
|
iD_S_B88665F_7e7082e6_e => ROM_Block:iD_s_30739CAe_5A20DAf5_E.clOCK
|
|
iD_S_B88665F_7e7082e6_e => Id_S_294e5c0d_762308e6_E.CLK
|
|
Id_S_59777b_7FFCe7eC_E => Id_S_294e5c0d_762308e6_E.IN0
|
|
id_s_c89sdnc7u_sda09scah_E => Id_S_294e5c0d_762308e6_E.IN1
|
|
id_s_daf34r31df1d_0y8wefh80_E[0] => ROM_Block:iD_s_30739CAe_5A20DAf5_E.address[0]
|
|
id_s_daf34r31df1d_0y8wefh80_E[1] => ROM_Block:iD_s_30739CAe_5A20DAf5_E.address[1]
|
|
id_s_daf34r31df1d_0y8wefh80_E[2] => ROM_Block:iD_s_30739CAe_5A20DAf5_E.address[2]
|
|
id_s_daf34r31df1d_0y8wefh80_E[3] => ROM_Block:iD_s_30739CAe_5A20DAf5_E.address[3]
|
|
id_s_daf34r31df1d_0y8wefh80_E[4] => ROM_Block:iD_s_30739CAe_5A20DAf5_E.address[4]
|
|
id_s_daf34r31df1d_0y8wefh80_E[5] => ROM_Block:iD_s_30739CAe_5A20DAf5_E.address[5]
|
|
id_s_daf34r31df1d_0y8wefh80_E[6] => ROM_Block:iD_s_30739CAe_5A20DAf5_E.address[6]
|
|
id_s_daf34r31df1d_0y8wefh80_E[7] => ROM_Block:iD_s_30739CAe_5A20DAf5_E.address[7]
|
|
id_s_daf34r31df1d_0y8wefh80_E[8] => ROM_Block:iD_s_30739CAe_5A20DAf5_E.address[8]
|
|
id_s_daf34r31df1d_0y8wefh80_E[9] => ROM_Block:iD_s_30739CAe_5A20DAf5_E.address[9]
|
|
ID_S_191530b5_24e2B0Bf_E[0] <= ID_S_191530b5_24e2B0Bf_E[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[1] <= ID_S_191530b5_24e2B0Bf_E[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[2] <= ID_S_191530b5_24e2B0Bf_E[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[3] <= ID_S_191530b5_24e2B0Bf_E[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[4] <= ID_S_191530b5_24e2B0Bf_E[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[5] <= ID_S_191530b5_24e2B0Bf_E[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[6] <= ID_S_191530b5_24e2B0Bf_E[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[7] <= ID_S_191530b5_24e2B0Bf_E[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[8] <= ID_S_191530b5_24e2B0Bf_E[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[9] <= ID_S_191530b5_24e2B0Bf_E[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[10] <= ID_S_191530b5_24e2B0Bf_E[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[11] <= ID_S_191530b5_24e2B0Bf_E[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[12] <= ID_S_191530b5_24e2B0Bf_E[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[13] <= ID_S_191530b5_24e2B0Bf_E[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[14] <= ID_S_191530b5_24e2B0Bf_E[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[15] <= ID_S_191530b5_24e2B0Bf_E[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[16] <= ID_S_191530b5_24e2B0Bf_E[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[17] <= ID_S_191530b5_24e2B0Bf_E[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[18] <= ID_S_191530b5_24e2B0Bf_E[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[19] <= ID_S_191530b5_24e2B0Bf_E[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[20] <= ID_S_191530b5_24e2B0Bf_E[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[21] <= ID_S_191530b5_24e2B0Bf_E[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[22] <= ID_S_191530b5_24e2B0Bf_E[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[23] <= ID_S_191530b5_24e2B0Bf_E[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[24] <= ID_S_191530b5_24e2B0Bf_E[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[25] <= ID_S_191530b5_24e2B0Bf_E[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[26] <= ID_S_191530b5_24e2B0Bf_E[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[27] <= ID_S_191530b5_24e2B0Bf_E[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[28] <= ID_S_191530b5_24e2B0Bf_E[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[29] <= ID_S_191530b5_24e2B0Bf_E[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[30] <= ID_S_191530b5_24e2B0Bf_E[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530b5_24e2B0Bf_E[31] <= ID_S_191530b5_24e2B0Bf_E[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|GECKO|ROM:ROM_0|iD_S_b88a693_7e3412F0_e:ROM_inst|ROM_Block:iD_s_30739CAe_5A20DAf5_E
|
|
address[0] => altsyncram:altsyncram_component.address_a[0]
|
|
address[1] => altsyncram:altsyncram_component.address_a[1]
|
|
address[2] => altsyncram:altsyncram_component.address_a[2]
|
|
address[3] => altsyncram:altsyncram_component.address_a[3]
|
|
address[4] => altsyncram:altsyncram_component.address_a[4]
|
|
address[5] => altsyncram:altsyncram_component.address_a[5]
|
|
address[6] => altsyncram:altsyncram_component.address_a[6]
|
|
address[7] => altsyncram:altsyncram_component.address_a[7]
|
|
address[8] => altsyncram:altsyncram_component.address_a[8]
|
|
address[9] => altsyncram:altsyncram_component.address_a[9]
|
|
clock => altsyncram:altsyncram_component.clock0
|
|
q[0] <= altsyncram:altsyncram_component.q_a[0]
|
|
q[1] <= altsyncram:altsyncram_component.q_a[1]
|
|
q[2] <= altsyncram:altsyncram_component.q_a[2]
|
|
q[3] <= altsyncram:altsyncram_component.q_a[3]
|
|
q[4] <= altsyncram:altsyncram_component.q_a[4]
|
|
q[5] <= altsyncram:altsyncram_component.q_a[5]
|
|
q[6] <= altsyncram:altsyncram_component.q_a[6]
|
|
q[7] <= altsyncram:altsyncram_component.q_a[7]
|
|
q[8] <= altsyncram:altsyncram_component.q_a[8]
|
|
q[9] <= altsyncram:altsyncram_component.q_a[9]
|
|
q[10] <= altsyncram:altsyncram_component.q_a[10]
|
|
q[11] <= altsyncram:altsyncram_component.q_a[11]
|
|
q[12] <= altsyncram:altsyncram_component.q_a[12]
|
|
q[13] <= altsyncram:altsyncram_component.q_a[13]
|
|
q[14] <= altsyncram:altsyncram_component.q_a[14]
|
|
q[15] <= altsyncram:altsyncram_component.q_a[15]
|
|
q[16] <= altsyncram:altsyncram_component.q_a[16]
|
|
q[17] <= altsyncram:altsyncram_component.q_a[17]
|
|
q[18] <= altsyncram:altsyncram_component.q_a[18]
|
|
q[19] <= altsyncram:altsyncram_component.q_a[19]
|
|
q[20] <= altsyncram:altsyncram_component.q_a[20]
|
|
q[21] <= altsyncram:altsyncram_component.q_a[21]
|
|
q[22] <= altsyncram:altsyncram_component.q_a[22]
|
|
q[23] <= altsyncram:altsyncram_component.q_a[23]
|
|
q[24] <= altsyncram:altsyncram_component.q_a[24]
|
|
q[25] <= altsyncram:altsyncram_component.q_a[25]
|
|
q[26] <= altsyncram:altsyncram_component.q_a[26]
|
|
q[27] <= altsyncram:altsyncram_component.q_a[27]
|
|
q[28] <= altsyncram:altsyncram_component.q_a[28]
|
|
q[29] <= altsyncram:altsyncram_component.q_a[29]
|
|
q[30] <= altsyncram:altsyncram_component.q_a[30]
|
|
q[31] <= altsyncram:altsyncram_component.q_a[31]
|
|
|
|
|
|
|GECKO|ROM:ROM_0|iD_S_b88a693_7e3412F0_e:ROM_inst|ROM_Block:iD_s_30739CAe_5A20DAf5_E|altsyncram:altsyncram_component
|
|
wren_a => ~NO_FANOUT~
|
|
rden_a => ~NO_FANOUT~
|
|
wren_b => ~NO_FANOUT~
|
|
rden_b => ~NO_FANOUT~
|
|
data_a[0] => ~NO_FANOUT~
|
|
data_a[1] => ~NO_FANOUT~
|
|
data_a[2] => ~NO_FANOUT~
|
|
data_a[3] => ~NO_FANOUT~
|
|
data_a[4] => ~NO_FANOUT~
|
|
data_a[5] => ~NO_FANOUT~
|
|
data_a[6] => ~NO_FANOUT~
|
|
data_a[7] => ~NO_FANOUT~
|
|
data_a[8] => ~NO_FANOUT~
|
|
data_a[9] => ~NO_FANOUT~
|
|
data_a[10] => ~NO_FANOUT~
|
|
data_a[11] => ~NO_FANOUT~
|
|
data_a[12] => ~NO_FANOUT~
|
|
data_a[13] => ~NO_FANOUT~
|
|
data_a[14] => ~NO_FANOUT~
|
|
data_a[15] => ~NO_FANOUT~
|
|
data_a[16] => ~NO_FANOUT~
|
|
data_a[17] => ~NO_FANOUT~
|
|
data_a[18] => ~NO_FANOUT~
|
|
data_a[19] => ~NO_FANOUT~
|
|
data_a[20] => ~NO_FANOUT~
|
|
data_a[21] => ~NO_FANOUT~
|
|
data_a[22] => ~NO_FANOUT~
|
|
data_a[23] => ~NO_FANOUT~
|
|
data_a[24] => ~NO_FANOUT~
|
|
data_a[25] => ~NO_FANOUT~
|
|
data_a[26] => ~NO_FANOUT~
|
|
data_a[27] => ~NO_FANOUT~
|
|
data_a[28] => ~NO_FANOUT~
|
|
data_a[29] => ~NO_FANOUT~
|
|
data_a[30] => ~NO_FANOUT~
|
|
data_a[31] => ~NO_FANOUT~
|
|
data_b[0] => ~NO_FANOUT~
|
|
address_a[0] => altsyncram_rna1:auto_generated.address_a[0]
|
|
address_a[1] => altsyncram_rna1:auto_generated.address_a[1]
|
|
address_a[2] => altsyncram_rna1:auto_generated.address_a[2]
|
|
address_a[3] => altsyncram_rna1:auto_generated.address_a[3]
|
|
address_a[4] => altsyncram_rna1:auto_generated.address_a[4]
|
|
address_a[5] => altsyncram_rna1:auto_generated.address_a[5]
|
|
address_a[6] => altsyncram_rna1:auto_generated.address_a[6]
|
|
address_a[7] => altsyncram_rna1:auto_generated.address_a[7]
|
|
address_a[8] => altsyncram_rna1:auto_generated.address_a[8]
|
|
address_a[9] => altsyncram_rna1:auto_generated.address_a[9]
|
|
address_b[0] => ~NO_FANOUT~
|
|
addressstall_a => ~NO_FANOUT~
|
|
addressstall_b => ~NO_FANOUT~
|
|
clock0 => altsyncram_rna1:auto_generated.clock0
|
|
clock1 => ~NO_FANOUT~
|
|
clocken0 => ~NO_FANOUT~
|
|
clocken1 => ~NO_FANOUT~
|
|
clocken2 => ~NO_FANOUT~
|
|
clocken3 => ~NO_FANOUT~
|
|
aclr0 => ~NO_FANOUT~
|
|
aclr1 => ~NO_FANOUT~
|
|
byteena_a[0] => ~NO_FANOUT~
|
|
byteena_b[0] => ~NO_FANOUT~
|
|
q_a[0] <= altsyncram_rna1:auto_generated.q_a[0]
|
|
q_a[1] <= altsyncram_rna1:auto_generated.q_a[1]
|
|
q_a[2] <= altsyncram_rna1:auto_generated.q_a[2]
|
|
q_a[3] <= altsyncram_rna1:auto_generated.q_a[3]
|
|
q_a[4] <= altsyncram_rna1:auto_generated.q_a[4]
|
|
q_a[5] <= altsyncram_rna1:auto_generated.q_a[5]
|
|
q_a[6] <= altsyncram_rna1:auto_generated.q_a[6]
|
|
q_a[7] <= altsyncram_rna1:auto_generated.q_a[7]
|
|
q_a[8] <= altsyncram_rna1:auto_generated.q_a[8]
|
|
q_a[9] <= altsyncram_rna1:auto_generated.q_a[9]
|
|
q_a[10] <= altsyncram_rna1:auto_generated.q_a[10]
|
|
q_a[11] <= altsyncram_rna1:auto_generated.q_a[11]
|
|
q_a[12] <= altsyncram_rna1:auto_generated.q_a[12]
|
|
q_a[13] <= altsyncram_rna1:auto_generated.q_a[13]
|
|
q_a[14] <= altsyncram_rna1:auto_generated.q_a[14]
|
|
q_a[15] <= altsyncram_rna1:auto_generated.q_a[15]
|
|
q_a[16] <= altsyncram_rna1:auto_generated.q_a[16]
|
|
q_a[17] <= altsyncram_rna1:auto_generated.q_a[17]
|
|
q_a[18] <= altsyncram_rna1:auto_generated.q_a[18]
|
|
q_a[19] <= altsyncram_rna1:auto_generated.q_a[19]
|
|
q_a[20] <= altsyncram_rna1:auto_generated.q_a[20]
|
|
q_a[21] <= altsyncram_rna1:auto_generated.q_a[21]
|
|
q_a[22] <= altsyncram_rna1:auto_generated.q_a[22]
|
|
q_a[23] <= altsyncram_rna1:auto_generated.q_a[23]
|
|
q_a[24] <= altsyncram_rna1:auto_generated.q_a[24]
|
|
q_a[25] <= altsyncram_rna1:auto_generated.q_a[25]
|
|
q_a[26] <= altsyncram_rna1:auto_generated.q_a[26]
|
|
q_a[27] <= altsyncram_rna1:auto_generated.q_a[27]
|
|
q_a[28] <= altsyncram_rna1:auto_generated.q_a[28]
|
|
q_a[29] <= altsyncram_rna1:auto_generated.q_a[29]
|
|
q_a[30] <= altsyncram_rna1:auto_generated.q_a[30]
|
|
q_a[31] <= altsyncram_rna1:auto_generated.q_a[31]
|
|
q_b[0] <= <GND>
|
|
eccstatus[0] <= <GND>
|
|
eccstatus[1] <= <GND>
|
|
eccstatus[2] <= <GND>
|
|
|
|
|
|
|GECKO|ROM:ROM_0|iD_S_b88a693_7e3412F0_e:ROM_inst|ROM_Block:iD_s_30739CAe_5A20DAf5_E|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated
|
|
address_a[0] => ram_block1a0.PORTAADDR
|
|
address_a[0] => ram_block1a1.PORTAADDR
|
|
address_a[0] => ram_block1a2.PORTAADDR
|
|
address_a[0] => ram_block1a3.PORTAADDR
|
|
address_a[0] => ram_block1a4.PORTAADDR
|
|
address_a[0] => ram_block1a5.PORTAADDR
|
|
address_a[0] => ram_block1a6.PORTAADDR
|
|
address_a[0] => ram_block1a7.PORTAADDR
|
|
address_a[0] => ram_block1a8.PORTAADDR
|
|
address_a[0] => ram_block1a9.PORTAADDR
|
|
address_a[0] => ram_block1a10.PORTAADDR
|
|
address_a[0] => ram_block1a11.PORTAADDR
|
|
address_a[0] => ram_block1a12.PORTAADDR
|
|
address_a[0] => ram_block1a13.PORTAADDR
|
|
address_a[0] => ram_block1a14.PORTAADDR
|
|
address_a[0] => ram_block1a15.PORTAADDR
|
|
address_a[0] => ram_block1a16.PORTAADDR
|
|
address_a[0] => ram_block1a17.PORTAADDR
|
|
address_a[0] => ram_block1a18.PORTAADDR
|
|
address_a[0] => ram_block1a19.PORTAADDR
|
|
address_a[0] => ram_block1a20.PORTAADDR
|
|
address_a[0] => ram_block1a21.PORTAADDR
|
|
address_a[0] => ram_block1a22.PORTAADDR
|
|
address_a[0] => ram_block1a23.PORTAADDR
|
|
address_a[0] => ram_block1a24.PORTAADDR
|
|
address_a[0] => ram_block1a25.PORTAADDR
|
|
address_a[0] => ram_block1a26.PORTAADDR
|
|
address_a[0] => ram_block1a27.PORTAADDR
|
|
address_a[0] => ram_block1a28.PORTAADDR
|
|
address_a[0] => ram_block1a29.PORTAADDR
|
|
address_a[0] => ram_block1a30.PORTAADDR
|
|
address_a[0] => ram_block1a31.PORTAADDR
|
|
address_a[1] => ram_block1a0.PORTAADDR1
|
|
address_a[1] => ram_block1a1.PORTAADDR1
|
|
address_a[1] => ram_block1a2.PORTAADDR1
|
|
address_a[1] => ram_block1a3.PORTAADDR1
|
|
address_a[1] => ram_block1a4.PORTAADDR1
|
|
address_a[1] => ram_block1a5.PORTAADDR1
|
|
address_a[1] => ram_block1a6.PORTAADDR1
|
|
address_a[1] => ram_block1a7.PORTAADDR1
|
|
address_a[1] => ram_block1a8.PORTAADDR1
|
|
address_a[1] => ram_block1a9.PORTAADDR1
|
|
address_a[1] => ram_block1a10.PORTAADDR1
|
|
address_a[1] => ram_block1a11.PORTAADDR1
|
|
address_a[1] => ram_block1a12.PORTAADDR1
|
|
address_a[1] => ram_block1a13.PORTAADDR1
|
|
address_a[1] => ram_block1a14.PORTAADDR1
|
|
address_a[1] => ram_block1a15.PORTAADDR1
|
|
address_a[1] => ram_block1a16.PORTAADDR1
|
|
address_a[1] => ram_block1a17.PORTAADDR1
|
|
address_a[1] => ram_block1a18.PORTAADDR1
|
|
address_a[1] => ram_block1a19.PORTAADDR1
|
|
address_a[1] => ram_block1a20.PORTAADDR1
|
|
address_a[1] => ram_block1a21.PORTAADDR1
|
|
address_a[1] => ram_block1a22.PORTAADDR1
|
|
address_a[1] => ram_block1a23.PORTAADDR1
|
|
address_a[1] => ram_block1a24.PORTAADDR1
|
|
address_a[1] => ram_block1a25.PORTAADDR1
|
|
address_a[1] => ram_block1a26.PORTAADDR1
|
|
address_a[1] => ram_block1a27.PORTAADDR1
|
|
address_a[1] => ram_block1a28.PORTAADDR1
|
|
address_a[1] => ram_block1a29.PORTAADDR1
|
|
address_a[1] => ram_block1a30.PORTAADDR1
|
|
address_a[1] => ram_block1a31.PORTAADDR1
|
|
address_a[2] => ram_block1a0.PORTAADDR2
|
|
address_a[2] => ram_block1a1.PORTAADDR2
|
|
address_a[2] => ram_block1a2.PORTAADDR2
|
|
address_a[2] => ram_block1a3.PORTAADDR2
|
|
address_a[2] => ram_block1a4.PORTAADDR2
|
|
address_a[2] => ram_block1a5.PORTAADDR2
|
|
address_a[2] => ram_block1a6.PORTAADDR2
|
|
address_a[2] => ram_block1a7.PORTAADDR2
|
|
address_a[2] => ram_block1a8.PORTAADDR2
|
|
address_a[2] => ram_block1a9.PORTAADDR2
|
|
address_a[2] => ram_block1a10.PORTAADDR2
|
|
address_a[2] => ram_block1a11.PORTAADDR2
|
|
address_a[2] => ram_block1a12.PORTAADDR2
|
|
address_a[2] => ram_block1a13.PORTAADDR2
|
|
address_a[2] => ram_block1a14.PORTAADDR2
|
|
address_a[2] => ram_block1a15.PORTAADDR2
|
|
address_a[2] => ram_block1a16.PORTAADDR2
|
|
address_a[2] => ram_block1a17.PORTAADDR2
|
|
address_a[2] => ram_block1a18.PORTAADDR2
|
|
address_a[2] => ram_block1a19.PORTAADDR2
|
|
address_a[2] => ram_block1a20.PORTAADDR2
|
|
address_a[2] => ram_block1a21.PORTAADDR2
|
|
address_a[2] => ram_block1a22.PORTAADDR2
|
|
address_a[2] => ram_block1a23.PORTAADDR2
|
|
address_a[2] => ram_block1a24.PORTAADDR2
|
|
address_a[2] => ram_block1a25.PORTAADDR2
|
|
address_a[2] => ram_block1a26.PORTAADDR2
|
|
address_a[2] => ram_block1a27.PORTAADDR2
|
|
address_a[2] => ram_block1a28.PORTAADDR2
|
|
address_a[2] => ram_block1a29.PORTAADDR2
|
|
address_a[2] => ram_block1a30.PORTAADDR2
|
|
address_a[2] => ram_block1a31.PORTAADDR2
|
|
address_a[3] => ram_block1a0.PORTAADDR3
|
|
address_a[3] => ram_block1a1.PORTAADDR3
|
|
address_a[3] => ram_block1a2.PORTAADDR3
|
|
address_a[3] => ram_block1a3.PORTAADDR3
|
|
address_a[3] => ram_block1a4.PORTAADDR3
|
|
address_a[3] => ram_block1a5.PORTAADDR3
|
|
address_a[3] => ram_block1a6.PORTAADDR3
|
|
address_a[3] => ram_block1a7.PORTAADDR3
|
|
address_a[3] => ram_block1a8.PORTAADDR3
|
|
address_a[3] => ram_block1a9.PORTAADDR3
|
|
address_a[3] => ram_block1a10.PORTAADDR3
|
|
address_a[3] => ram_block1a11.PORTAADDR3
|
|
address_a[3] => ram_block1a12.PORTAADDR3
|
|
address_a[3] => ram_block1a13.PORTAADDR3
|
|
address_a[3] => ram_block1a14.PORTAADDR3
|
|
address_a[3] => ram_block1a15.PORTAADDR3
|
|
address_a[3] => ram_block1a16.PORTAADDR3
|
|
address_a[3] => ram_block1a17.PORTAADDR3
|
|
address_a[3] => ram_block1a18.PORTAADDR3
|
|
address_a[3] => ram_block1a19.PORTAADDR3
|
|
address_a[3] => ram_block1a20.PORTAADDR3
|
|
address_a[3] => ram_block1a21.PORTAADDR3
|
|
address_a[3] => ram_block1a22.PORTAADDR3
|
|
address_a[3] => ram_block1a23.PORTAADDR3
|
|
address_a[3] => ram_block1a24.PORTAADDR3
|
|
address_a[3] => ram_block1a25.PORTAADDR3
|
|
address_a[3] => ram_block1a26.PORTAADDR3
|
|
address_a[3] => ram_block1a27.PORTAADDR3
|
|
address_a[3] => ram_block1a28.PORTAADDR3
|
|
address_a[3] => ram_block1a29.PORTAADDR3
|
|
address_a[3] => ram_block1a30.PORTAADDR3
|
|
address_a[3] => ram_block1a31.PORTAADDR3
|
|
address_a[4] => ram_block1a0.PORTAADDR4
|
|
address_a[4] => ram_block1a1.PORTAADDR4
|
|
address_a[4] => ram_block1a2.PORTAADDR4
|
|
address_a[4] => ram_block1a3.PORTAADDR4
|
|
address_a[4] => ram_block1a4.PORTAADDR4
|
|
address_a[4] => ram_block1a5.PORTAADDR4
|
|
address_a[4] => ram_block1a6.PORTAADDR4
|
|
address_a[4] => ram_block1a7.PORTAADDR4
|
|
address_a[4] => ram_block1a8.PORTAADDR4
|
|
address_a[4] => ram_block1a9.PORTAADDR4
|
|
address_a[4] => ram_block1a10.PORTAADDR4
|
|
address_a[4] => ram_block1a11.PORTAADDR4
|
|
address_a[4] => ram_block1a12.PORTAADDR4
|
|
address_a[4] => ram_block1a13.PORTAADDR4
|
|
address_a[4] => ram_block1a14.PORTAADDR4
|
|
address_a[4] => ram_block1a15.PORTAADDR4
|
|
address_a[4] => ram_block1a16.PORTAADDR4
|
|
address_a[4] => ram_block1a17.PORTAADDR4
|
|
address_a[4] => ram_block1a18.PORTAADDR4
|
|
address_a[4] => ram_block1a19.PORTAADDR4
|
|
address_a[4] => ram_block1a20.PORTAADDR4
|
|
address_a[4] => ram_block1a21.PORTAADDR4
|
|
address_a[4] => ram_block1a22.PORTAADDR4
|
|
address_a[4] => ram_block1a23.PORTAADDR4
|
|
address_a[4] => ram_block1a24.PORTAADDR4
|
|
address_a[4] => ram_block1a25.PORTAADDR4
|
|
address_a[4] => ram_block1a26.PORTAADDR4
|
|
address_a[4] => ram_block1a27.PORTAADDR4
|
|
address_a[4] => ram_block1a28.PORTAADDR4
|
|
address_a[4] => ram_block1a29.PORTAADDR4
|
|
address_a[4] => ram_block1a30.PORTAADDR4
|
|
address_a[4] => ram_block1a31.PORTAADDR4
|
|
address_a[5] => ram_block1a0.PORTAADDR5
|
|
address_a[5] => ram_block1a1.PORTAADDR5
|
|
address_a[5] => ram_block1a2.PORTAADDR5
|
|
address_a[5] => ram_block1a3.PORTAADDR5
|
|
address_a[5] => ram_block1a4.PORTAADDR5
|
|
address_a[5] => ram_block1a5.PORTAADDR5
|
|
address_a[5] => ram_block1a6.PORTAADDR5
|
|
address_a[5] => ram_block1a7.PORTAADDR5
|
|
address_a[5] => ram_block1a8.PORTAADDR5
|
|
address_a[5] => ram_block1a9.PORTAADDR5
|
|
address_a[5] => ram_block1a10.PORTAADDR5
|
|
address_a[5] => ram_block1a11.PORTAADDR5
|
|
address_a[5] => ram_block1a12.PORTAADDR5
|
|
address_a[5] => ram_block1a13.PORTAADDR5
|
|
address_a[5] => ram_block1a14.PORTAADDR5
|
|
address_a[5] => ram_block1a15.PORTAADDR5
|
|
address_a[5] => ram_block1a16.PORTAADDR5
|
|
address_a[5] => ram_block1a17.PORTAADDR5
|
|
address_a[5] => ram_block1a18.PORTAADDR5
|
|
address_a[5] => ram_block1a19.PORTAADDR5
|
|
address_a[5] => ram_block1a20.PORTAADDR5
|
|
address_a[5] => ram_block1a21.PORTAADDR5
|
|
address_a[5] => ram_block1a22.PORTAADDR5
|
|
address_a[5] => ram_block1a23.PORTAADDR5
|
|
address_a[5] => ram_block1a24.PORTAADDR5
|
|
address_a[5] => ram_block1a25.PORTAADDR5
|
|
address_a[5] => ram_block1a26.PORTAADDR5
|
|
address_a[5] => ram_block1a27.PORTAADDR5
|
|
address_a[5] => ram_block1a28.PORTAADDR5
|
|
address_a[5] => ram_block1a29.PORTAADDR5
|
|
address_a[5] => ram_block1a30.PORTAADDR5
|
|
address_a[5] => ram_block1a31.PORTAADDR5
|
|
address_a[6] => ram_block1a0.PORTAADDR6
|
|
address_a[6] => ram_block1a1.PORTAADDR6
|
|
address_a[6] => ram_block1a2.PORTAADDR6
|
|
address_a[6] => ram_block1a3.PORTAADDR6
|
|
address_a[6] => ram_block1a4.PORTAADDR6
|
|
address_a[6] => ram_block1a5.PORTAADDR6
|
|
address_a[6] => ram_block1a6.PORTAADDR6
|
|
address_a[6] => ram_block1a7.PORTAADDR6
|
|
address_a[6] => ram_block1a8.PORTAADDR6
|
|
address_a[6] => ram_block1a9.PORTAADDR6
|
|
address_a[6] => ram_block1a10.PORTAADDR6
|
|
address_a[6] => ram_block1a11.PORTAADDR6
|
|
address_a[6] => ram_block1a12.PORTAADDR6
|
|
address_a[6] => ram_block1a13.PORTAADDR6
|
|
address_a[6] => ram_block1a14.PORTAADDR6
|
|
address_a[6] => ram_block1a15.PORTAADDR6
|
|
address_a[6] => ram_block1a16.PORTAADDR6
|
|
address_a[6] => ram_block1a17.PORTAADDR6
|
|
address_a[6] => ram_block1a18.PORTAADDR6
|
|
address_a[6] => ram_block1a19.PORTAADDR6
|
|
address_a[6] => ram_block1a20.PORTAADDR6
|
|
address_a[6] => ram_block1a21.PORTAADDR6
|
|
address_a[6] => ram_block1a22.PORTAADDR6
|
|
address_a[6] => ram_block1a23.PORTAADDR6
|
|
address_a[6] => ram_block1a24.PORTAADDR6
|
|
address_a[6] => ram_block1a25.PORTAADDR6
|
|
address_a[6] => ram_block1a26.PORTAADDR6
|
|
address_a[6] => ram_block1a27.PORTAADDR6
|
|
address_a[6] => ram_block1a28.PORTAADDR6
|
|
address_a[6] => ram_block1a29.PORTAADDR6
|
|
address_a[6] => ram_block1a30.PORTAADDR6
|
|
address_a[6] => ram_block1a31.PORTAADDR6
|
|
address_a[7] => ram_block1a0.PORTAADDR7
|
|
address_a[7] => ram_block1a1.PORTAADDR7
|
|
address_a[7] => ram_block1a2.PORTAADDR7
|
|
address_a[7] => ram_block1a3.PORTAADDR7
|
|
address_a[7] => ram_block1a4.PORTAADDR7
|
|
address_a[7] => ram_block1a5.PORTAADDR7
|
|
address_a[7] => ram_block1a6.PORTAADDR7
|
|
address_a[7] => ram_block1a7.PORTAADDR7
|
|
address_a[7] => ram_block1a8.PORTAADDR7
|
|
address_a[7] => ram_block1a9.PORTAADDR7
|
|
address_a[7] => ram_block1a10.PORTAADDR7
|
|
address_a[7] => ram_block1a11.PORTAADDR7
|
|
address_a[7] => ram_block1a12.PORTAADDR7
|
|
address_a[7] => ram_block1a13.PORTAADDR7
|
|
address_a[7] => ram_block1a14.PORTAADDR7
|
|
address_a[7] => ram_block1a15.PORTAADDR7
|
|
address_a[7] => ram_block1a16.PORTAADDR7
|
|
address_a[7] => ram_block1a17.PORTAADDR7
|
|
address_a[7] => ram_block1a18.PORTAADDR7
|
|
address_a[7] => ram_block1a19.PORTAADDR7
|
|
address_a[7] => ram_block1a20.PORTAADDR7
|
|
address_a[7] => ram_block1a21.PORTAADDR7
|
|
address_a[7] => ram_block1a22.PORTAADDR7
|
|
address_a[7] => ram_block1a23.PORTAADDR7
|
|
address_a[7] => ram_block1a24.PORTAADDR7
|
|
address_a[7] => ram_block1a25.PORTAADDR7
|
|
address_a[7] => ram_block1a26.PORTAADDR7
|
|
address_a[7] => ram_block1a27.PORTAADDR7
|
|
address_a[7] => ram_block1a28.PORTAADDR7
|
|
address_a[7] => ram_block1a29.PORTAADDR7
|
|
address_a[7] => ram_block1a30.PORTAADDR7
|
|
address_a[7] => ram_block1a31.PORTAADDR7
|
|
address_a[8] => ram_block1a0.PORTAADDR8
|
|
address_a[8] => ram_block1a1.PORTAADDR8
|
|
address_a[8] => ram_block1a2.PORTAADDR8
|
|
address_a[8] => ram_block1a3.PORTAADDR8
|
|
address_a[8] => ram_block1a4.PORTAADDR8
|
|
address_a[8] => ram_block1a5.PORTAADDR8
|
|
address_a[8] => ram_block1a6.PORTAADDR8
|
|
address_a[8] => ram_block1a7.PORTAADDR8
|
|
address_a[8] => ram_block1a8.PORTAADDR8
|
|
address_a[8] => ram_block1a9.PORTAADDR8
|
|
address_a[8] => ram_block1a10.PORTAADDR8
|
|
address_a[8] => ram_block1a11.PORTAADDR8
|
|
address_a[8] => ram_block1a12.PORTAADDR8
|
|
address_a[8] => ram_block1a13.PORTAADDR8
|
|
address_a[8] => ram_block1a14.PORTAADDR8
|
|
address_a[8] => ram_block1a15.PORTAADDR8
|
|
address_a[8] => ram_block1a16.PORTAADDR8
|
|
address_a[8] => ram_block1a17.PORTAADDR8
|
|
address_a[8] => ram_block1a18.PORTAADDR8
|
|
address_a[8] => ram_block1a19.PORTAADDR8
|
|
address_a[8] => ram_block1a20.PORTAADDR8
|
|
address_a[8] => ram_block1a21.PORTAADDR8
|
|
address_a[8] => ram_block1a22.PORTAADDR8
|
|
address_a[8] => ram_block1a23.PORTAADDR8
|
|
address_a[8] => ram_block1a24.PORTAADDR8
|
|
address_a[8] => ram_block1a25.PORTAADDR8
|
|
address_a[8] => ram_block1a26.PORTAADDR8
|
|
address_a[8] => ram_block1a27.PORTAADDR8
|
|
address_a[8] => ram_block1a28.PORTAADDR8
|
|
address_a[8] => ram_block1a29.PORTAADDR8
|
|
address_a[8] => ram_block1a30.PORTAADDR8
|
|
address_a[8] => ram_block1a31.PORTAADDR8
|
|
address_a[9] => ram_block1a0.PORTAADDR9
|
|
address_a[9] => ram_block1a1.PORTAADDR9
|
|
address_a[9] => ram_block1a2.PORTAADDR9
|
|
address_a[9] => ram_block1a3.PORTAADDR9
|
|
address_a[9] => ram_block1a4.PORTAADDR9
|
|
address_a[9] => ram_block1a5.PORTAADDR9
|
|
address_a[9] => ram_block1a6.PORTAADDR9
|
|
address_a[9] => ram_block1a7.PORTAADDR9
|
|
address_a[9] => ram_block1a8.PORTAADDR9
|
|
address_a[9] => ram_block1a9.PORTAADDR9
|
|
address_a[9] => ram_block1a10.PORTAADDR9
|
|
address_a[9] => ram_block1a11.PORTAADDR9
|
|
address_a[9] => ram_block1a12.PORTAADDR9
|
|
address_a[9] => ram_block1a13.PORTAADDR9
|
|
address_a[9] => ram_block1a14.PORTAADDR9
|
|
address_a[9] => ram_block1a15.PORTAADDR9
|
|
address_a[9] => ram_block1a16.PORTAADDR9
|
|
address_a[9] => ram_block1a17.PORTAADDR9
|
|
address_a[9] => ram_block1a18.PORTAADDR9
|
|
address_a[9] => ram_block1a19.PORTAADDR9
|
|
address_a[9] => ram_block1a20.PORTAADDR9
|
|
address_a[9] => ram_block1a21.PORTAADDR9
|
|
address_a[9] => ram_block1a22.PORTAADDR9
|
|
address_a[9] => ram_block1a23.PORTAADDR9
|
|
address_a[9] => ram_block1a24.PORTAADDR9
|
|
address_a[9] => ram_block1a25.PORTAADDR9
|
|
address_a[9] => ram_block1a26.PORTAADDR9
|
|
address_a[9] => ram_block1a27.PORTAADDR9
|
|
address_a[9] => ram_block1a28.PORTAADDR9
|
|
address_a[9] => ram_block1a29.PORTAADDR9
|
|
address_a[9] => ram_block1a30.PORTAADDR9
|
|
address_a[9] => ram_block1a31.PORTAADDR9
|
|
clock0 => ram_block1a0.CLK0
|
|
clock0 => ram_block1a1.CLK0
|
|
clock0 => ram_block1a2.CLK0
|
|
clock0 => ram_block1a3.CLK0
|
|
clock0 => ram_block1a4.CLK0
|
|
clock0 => ram_block1a5.CLK0
|
|
clock0 => ram_block1a6.CLK0
|
|
clock0 => ram_block1a7.CLK0
|
|
clock0 => ram_block1a8.CLK0
|
|
clock0 => ram_block1a9.CLK0
|
|
clock0 => ram_block1a10.CLK0
|
|
clock0 => ram_block1a11.CLK0
|
|
clock0 => ram_block1a12.CLK0
|
|
clock0 => ram_block1a13.CLK0
|
|
clock0 => ram_block1a14.CLK0
|
|
clock0 => ram_block1a15.CLK0
|
|
clock0 => ram_block1a16.CLK0
|
|
clock0 => ram_block1a17.CLK0
|
|
clock0 => ram_block1a18.CLK0
|
|
clock0 => ram_block1a19.CLK0
|
|
clock0 => ram_block1a20.CLK0
|
|
clock0 => ram_block1a21.CLK0
|
|
clock0 => ram_block1a22.CLK0
|
|
clock0 => ram_block1a23.CLK0
|
|
clock0 => ram_block1a24.CLK0
|
|
clock0 => ram_block1a25.CLK0
|
|
clock0 => ram_block1a26.CLK0
|
|
clock0 => ram_block1a27.CLK0
|
|
clock0 => ram_block1a28.CLK0
|
|
clock0 => ram_block1a29.CLK0
|
|
clock0 => ram_block1a30.CLK0
|
|
clock0 => ram_block1a31.CLK0
|
|
q_a[0] <= ram_block1a0.PORTADATAOUT
|
|
q_a[1] <= ram_block1a1.PORTADATAOUT
|
|
q_a[2] <= ram_block1a2.PORTADATAOUT
|
|
q_a[3] <= ram_block1a3.PORTADATAOUT
|
|
q_a[4] <= ram_block1a4.PORTADATAOUT
|
|
q_a[5] <= ram_block1a5.PORTADATAOUT
|
|
q_a[6] <= ram_block1a6.PORTADATAOUT
|
|
q_a[7] <= ram_block1a7.PORTADATAOUT
|
|
q_a[8] <= ram_block1a8.PORTADATAOUT
|
|
q_a[9] <= ram_block1a9.PORTADATAOUT
|
|
q_a[10] <= ram_block1a10.PORTADATAOUT
|
|
q_a[11] <= ram_block1a11.PORTADATAOUT
|
|
q_a[12] <= ram_block1a12.PORTADATAOUT
|
|
q_a[13] <= ram_block1a13.PORTADATAOUT
|
|
q_a[14] <= ram_block1a14.PORTADATAOUT
|
|
q_a[15] <= ram_block1a15.PORTADATAOUT
|
|
q_a[16] <= ram_block1a16.PORTADATAOUT
|
|
q_a[17] <= ram_block1a17.PORTADATAOUT
|
|
q_a[18] <= ram_block1a18.PORTADATAOUT
|
|
q_a[19] <= ram_block1a19.PORTADATAOUT
|
|
q_a[20] <= ram_block1a20.PORTADATAOUT
|
|
q_a[21] <= ram_block1a21.PORTADATAOUT
|
|
q_a[22] <= ram_block1a22.PORTADATAOUT
|
|
q_a[23] <= ram_block1a23.PORTADATAOUT
|
|
q_a[24] <= ram_block1a24.PORTADATAOUT
|
|
q_a[25] <= ram_block1a25.PORTADATAOUT
|
|
q_a[26] <= ram_block1a26.PORTADATAOUT
|
|
q_a[27] <= ram_block1a27.PORTADATAOUT
|
|
q_a[28] <= ram_block1a28.PORTADATAOUT
|
|
q_a[29] <= ram_block1a29.PORTADATAOUT
|
|
q_a[30] <= ram_block1a30.PORTADATAOUT
|
|
q_a[31] <= ram_block1a31.PORTADATAOUT
|
|
|
|
|
|
|GECKO|RAM:RAM_0
|
|
clk => iD_s_B88A4C5_7e3415fF_E:ram_inst.id_s_b88665f_7e7082e6_E
|
|
cs => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_59777b_7ffcE7Ec_E
|
|
read => iD_s_B88A4C5_7e3415fF_E:ram_inst.id_s_16sgdbnv7_2c8dh7vjdo_E
|
|
write => iD_s_B88A4C5_7e3415fF_E:ram_inst.id_s_c89sdnc7u_sda09scah_E
|
|
address[0] => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_1F2653EB_6eC5B6Be_E[0]
|
|
address[1] => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_1F2653EB_6eC5B6Be_E[1]
|
|
address[2] => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_1F2653EB_6eC5B6Be_E[2]
|
|
address[3] => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_1F2653EB_6eC5B6Be_E[3]
|
|
address[4] => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_1F2653EB_6eC5B6Be_E[4]
|
|
address[5] => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_1F2653EB_6eC5B6Be_E[5]
|
|
address[6] => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_1F2653EB_6eC5B6Be_E[6]
|
|
address[7] => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_1F2653EB_6eC5B6Be_E[7]
|
|
address[8] => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_1F2653EB_6eC5B6Be_E[8]
|
|
address[9] => iD_s_B88A4C5_7e3415fF_E:ram_inst.iD_S_1F2653EB_6eC5B6Be_E[9]
|
|
wrdata[0] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[0]
|
|
wrdata[1] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[1]
|
|
wrdata[2] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[2]
|
|
wrdata[3] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[3]
|
|
wrdata[4] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[4]
|
|
wrdata[5] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[5]
|
|
wrdata[6] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[6]
|
|
wrdata[7] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[7]
|
|
wrdata[8] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[8]
|
|
wrdata[9] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[9]
|
|
wrdata[10] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[10]
|
|
wrdata[11] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[11]
|
|
wrdata[12] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[12]
|
|
wrdata[13] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[13]
|
|
wrdata[14] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[14]
|
|
wrdata[15] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[15]
|
|
wrdata[16] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[16]
|
|
wrdata[17] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[17]
|
|
wrdata[18] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[18]
|
|
wrdata[19] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[19]
|
|
wrdata[20] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[20]
|
|
wrdata[21] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[21]
|
|
wrdata[22] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[22]
|
|
wrdata[23] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[23]
|
|
wrdata[24] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[24]
|
|
wrdata[25] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[25]
|
|
wrdata[26] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[26]
|
|
wrdata[27] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[27]
|
|
wrdata[28] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[28]
|
|
wrdata[29] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[29]
|
|
wrdata[30] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[30]
|
|
wrdata[31] => iD_s_B88A4C5_7e3415fF_E:ram_inst.Id_S_25Bc52e8_112eF888_e[31]
|
|
rddata[0] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[0]
|
|
rddata[1] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[1]
|
|
rddata[2] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[2]
|
|
rddata[3] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[3]
|
|
rddata[4] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[4]
|
|
rddata[5] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[5]
|
|
rddata[6] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[6]
|
|
rddata[7] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[7]
|
|
rddata[8] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[8]
|
|
rddata[9] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[9]
|
|
rddata[10] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[10]
|
|
rddata[11] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[11]
|
|
rddata[12] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[12]
|
|
rddata[13] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[13]
|
|
rddata[14] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[14]
|
|
rddata[15] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[15]
|
|
rddata[16] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[16]
|
|
rddata[17] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[17]
|
|
rddata[18] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[18]
|
|
rddata[19] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[19]
|
|
rddata[20] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[20]
|
|
rddata[21] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[21]
|
|
rddata[22] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[22]
|
|
rddata[23] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[23]
|
|
rddata[24] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[24]
|
|
rddata[25] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[25]
|
|
rddata[26] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[26]
|
|
rddata[27] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[27]
|
|
rddata[28] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[28]
|
|
rddata[29] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[29]
|
|
rddata[30] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[30]
|
|
rddata[31] <= iD_s_B88A4C5_7e3415fF_E:ram_inst.ID_S_191530B5_24e2b0bf_e[31]
|
|
|
|
|
|
|GECKO|RAM:RAM_0|ID_S_B88a4C5_7E3415Ff_e:ram_inst
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~42.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~0.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~1.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~2.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~3.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~4.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~5.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~6.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~7.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~8.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~9.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~10.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~11.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~12.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~13.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~14.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~15.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~16.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~17.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~18.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~19.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~20.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~21.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~22.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~23.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~24.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~25.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~26.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~27.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~28.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~29.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~30.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~31.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~32.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~33.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~34.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~35.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~36.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~37.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~38.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~39.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~40.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e~41.CLK
|
|
id_s_b88665f_7e7082e6_E => ID_S_cC3eE48_281C1fb9_E[0].CLK
|
|
id_s_b88665f_7e7082e6_E => ID_S_cC3eE48_281C1fb9_E[1].CLK
|
|
id_s_b88665f_7e7082e6_E => ID_S_cC3eE48_281C1fb9_E[2].CLK
|
|
id_s_b88665f_7e7082e6_E => ID_S_cC3eE48_281C1fb9_E[3].CLK
|
|
id_s_b88665f_7e7082e6_E => ID_S_cC3eE48_281C1fb9_E[4].CLK
|
|
id_s_b88665f_7e7082e6_E => ID_S_cC3eE48_281C1fb9_E[5].CLK
|
|
id_s_b88665f_7e7082e6_E => ID_S_cC3eE48_281C1fb9_E[6].CLK
|
|
id_s_b88665f_7e7082e6_E => ID_S_cC3eE48_281C1fb9_E[7].CLK
|
|
id_s_b88665f_7e7082e6_E => ID_S_cC3eE48_281C1fb9_E[8].CLK
|
|
id_s_b88665f_7e7082e6_E => ID_S_cC3eE48_281C1fb9_E[9].CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_6f8bcBE_62E8365d_e.CLK
|
|
id_s_b88665f_7e7082e6_E => Id_S_B889004_7e48Ff67_e.CLK0
|
|
iD_S_59777b_7ffcE7Ec_E => Id_S_6f8bcBE_62E8365d_e.IN0
|
|
iD_S_59777b_7ffcE7Ec_E => process_2.IN0
|
|
id_s_16sgdbnv7_2c8dh7vjdo_E => Id_S_6f8bcBE_62E8365d_e.IN1
|
|
id_s_c89sdnc7u_sda09scah_E => process_2.IN1
|
|
iD_S_1F2653EB_6eC5B6Be_E[0] => Id_S_B889004_7e48Ff67_e~9.DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[0] => ID_S_cC3eE48_281C1fb9_E[0].DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[0] => Id_S_B889004_7e48Ff67_e.WADDR
|
|
iD_S_1F2653EB_6eC5B6Be_E[1] => Id_S_B889004_7e48Ff67_e~8.DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[1] => ID_S_cC3eE48_281C1fb9_E[1].DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[1] => Id_S_B889004_7e48Ff67_e.WADDR1
|
|
iD_S_1F2653EB_6eC5B6Be_E[2] => Id_S_B889004_7e48Ff67_e~7.DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[2] => ID_S_cC3eE48_281C1fb9_E[2].DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[2] => Id_S_B889004_7e48Ff67_e.WADDR2
|
|
iD_S_1F2653EB_6eC5B6Be_E[3] => Id_S_B889004_7e48Ff67_e~6.DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[3] => ID_S_cC3eE48_281C1fb9_E[3].DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[3] => Id_S_B889004_7e48Ff67_e.WADDR3
|
|
iD_S_1F2653EB_6eC5B6Be_E[4] => Id_S_B889004_7e48Ff67_e~5.DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[4] => ID_S_cC3eE48_281C1fb9_E[4].DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[4] => Id_S_B889004_7e48Ff67_e.WADDR4
|
|
iD_S_1F2653EB_6eC5B6Be_E[5] => Id_S_B889004_7e48Ff67_e~4.DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[5] => ID_S_cC3eE48_281C1fb9_E[5].DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[5] => Id_S_B889004_7e48Ff67_e.WADDR5
|
|
iD_S_1F2653EB_6eC5B6Be_E[6] => Id_S_B889004_7e48Ff67_e~3.DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[6] => ID_S_cC3eE48_281C1fb9_E[6].DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[6] => Id_S_B889004_7e48Ff67_e.WADDR6
|
|
iD_S_1F2653EB_6eC5B6Be_E[7] => Id_S_B889004_7e48Ff67_e~2.DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[7] => ID_S_cC3eE48_281C1fb9_E[7].DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[7] => Id_S_B889004_7e48Ff67_e.WADDR7
|
|
iD_S_1F2653EB_6eC5B6Be_E[8] => Id_S_B889004_7e48Ff67_e~1.DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[8] => ID_S_cC3eE48_281C1fb9_E[8].DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[8] => Id_S_B889004_7e48Ff67_e.WADDR8
|
|
iD_S_1F2653EB_6eC5B6Be_E[9] => Id_S_B889004_7e48Ff67_e~0.DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[9] => ID_S_cC3eE48_281C1fb9_E[9].DATAIN
|
|
iD_S_1F2653EB_6eC5B6Be_E[9] => Id_S_B889004_7e48Ff67_e.WADDR9
|
|
Id_S_25Bc52e8_112eF888_e[0] => Id_S_B889004_7e48Ff67_e~41.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[0] => Id_S_B889004_7e48Ff67_e.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[1] => Id_S_B889004_7e48Ff67_e~40.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[1] => Id_S_B889004_7e48Ff67_e.DATAIN1
|
|
Id_S_25Bc52e8_112eF888_e[2] => Id_S_B889004_7e48Ff67_e~39.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[2] => Id_S_B889004_7e48Ff67_e.DATAIN2
|
|
Id_S_25Bc52e8_112eF888_e[3] => Id_S_B889004_7e48Ff67_e~38.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[3] => Id_S_B889004_7e48Ff67_e.DATAIN3
|
|
Id_S_25Bc52e8_112eF888_e[4] => Id_S_B889004_7e48Ff67_e~37.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[4] => Id_S_B889004_7e48Ff67_e.DATAIN4
|
|
Id_S_25Bc52e8_112eF888_e[5] => Id_S_B889004_7e48Ff67_e~36.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[5] => Id_S_B889004_7e48Ff67_e.DATAIN5
|
|
Id_S_25Bc52e8_112eF888_e[6] => Id_S_B889004_7e48Ff67_e~35.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[6] => Id_S_B889004_7e48Ff67_e.DATAIN6
|
|
Id_S_25Bc52e8_112eF888_e[7] => Id_S_B889004_7e48Ff67_e~34.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[7] => Id_S_B889004_7e48Ff67_e.DATAIN7
|
|
Id_S_25Bc52e8_112eF888_e[8] => Id_S_B889004_7e48Ff67_e~33.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[8] => Id_S_B889004_7e48Ff67_e.DATAIN8
|
|
Id_S_25Bc52e8_112eF888_e[9] => Id_S_B889004_7e48Ff67_e~32.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[9] => Id_S_B889004_7e48Ff67_e.DATAIN9
|
|
Id_S_25Bc52e8_112eF888_e[10] => Id_S_B889004_7e48Ff67_e~31.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[10] => Id_S_B889004_7e48Ff67_e.DATAIN10
|
|
Id_S_25Bc52e8_112eF888_e[11] => Id_S_B889004_7e48Ff67_e~30.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[11] => Id_S_B889004_7e48Ff67_e.DATAIN11
|
|
Id_S_25Bc52e8_112eF888_e[12] => Id_S_B889004_7e48Ff67_e~29.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[12] => Id_S_B889004_7e48Ff67_e.DATAIN12
|
|
Id_S_25Bc52e8_112eF888_e[13] => Id_S_B889004_7e48Ff67_e~28.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[13] => Id_S_B889004_7e48Ff67_e.DATAIN13
|
|
Id_S_25Bc52e8_112eF888_e[14] => Id_S_B889004_7e48Ff67_e~27.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[14] => Id_S_B889004_7e48Ff67_e.DATAIN14
|
|
Id_S_25Bc52e8_112eF888_e[15] => Id_S_B889004_7e48Ff67_e~26.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[15] => Id_S_B889004_7e48Ff67_e.DATAIN15
|
|
Id_S_25Bc52e8_112eF888_e[16] => Id_S_B889004_7e48Ff67_e~25.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[16] => Id_S_B889004_7e48Ff67_e.DATAIN16
|
|
Id_S_25Bc52e8_112eF888_e[17] => Id_S_B889004_7e48Ff67_e~24.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[17] => Id_S_B889004_7e48Ff67_e.DATAIN17
|
|
Id_S_25Bc52e8_112eF888_e[18] => Id_S_B889004_7e48Ff67_e~23.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[18] => Id_S_B889004_7e48Ff67_e.DATAIN18
|
|
Id_S_25Bc52e8_112eF888_e[19] => Id_S_B889004_7e48Ff67_e~22.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[19] => Id_S_B889004_7e48Ff67_e.DATAIN19
|
|
Id_S_25Bc52e8_112eF888_e[20] => Id_S_B889004_7e48Ff67_e~21.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[20] => Id_S_B889004_7e48Ff67_e.DATAIN20
|
|
Id_S_25Bc52e8_112eF888_e[21] => Id_S_B889004_7e48Ff67_e~20.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[21] => Id_S_B889004_7e48Ff67_e.DATAIN21
|
|
Id_S_25Bc52e8_112eF888_e[22] => Id_S_B889004_7e48Ff67_e~19.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[22] => Id_S_B889004_7e48Ff67_e.DATAIN22
|
|
Id_S_25Bc52e8_112eF888_e[23] => Id_S_B889004_7e48Ff67_e~18.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[23] => Id_S_B889004_7e48Ff67_e.DATAIN23
|
|
Id_S_25Bc52e8_112eF888_e[24] => Id_S_B889004_7e48Ff67_e~17.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[24] => Id_S_B889004_7e48Ff67_e.DATAIN24
|
|
Id_S_25Bc52e8_112eF888_e[25] => Id_S_B889004_7e48Ff67_e~16.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[25] => Id_S_B889004_7e48Ff67_e.DATAIN25
|
|
Id_S_25Bc52e8_112eF888_e[26] => Id_S_B889004_7e48Ff67_e~15.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[26] => Id_S_B889004_7e48Ff67_e.DATAIN26
|
|
Id_S_25Bc52e8_112eF888_e[27] => Id_S_B889004_7e48Ff67_e~14.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[27] => Id_S_B889004_7e48Ff67_e.DATAIN27
|
|
Id_S_25Bc52e8_112eF888_e[28] => Id_S_B889004_7e48Ff67_e~13.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[28] => Id_S_B889004_7e48Ff67_e.DATAIN28
|
|
Id_S_25Bc52e8_112eF888_e[29] => Id_S_B889004_7e48Ff67_e~12.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[29] => Id_S_B889004_7e48Ff67_e.DATAIN29
|
|
Id_S_25Bc52e8_112eF888_e[30] => Id_S_B889004_7e48Ff67_e~11.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[30] => Id_S_B889004_7e48Ff67_e.DATAIN30
|
|
Id_S_25Bc52e8_112eF888_e[31] => Id_S_B889004_7e48Ff67_e~10.DATAIN
|
|
Id_S_25Bc52e8_112eF888_e[31] => Id_S_B889004_7e48Ff67_e.DATAIN31
|
|
ID_S_191530B5_24e2b0bf_e[0] <= ID_S_191530B5_24e2b0bf_e[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[1] <= ID_S_191530B5_24e2b0bf_e[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[2] <= ID_S_191530B5_24e2b0bf_e[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[3] <= ID_S_191530B5_24e2b0bf_e[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[4] <= ID_S_191530B5_24e2b0bf_e[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[5] <= ID_S_191530B5_24e2b0bf_e[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[6] <= ID_S_191530B5_24e2b0bf_e[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[7] <= ID_S_191530B5_24e2b0bf_e[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[8] <= ID_S_191530B5_24e2b0bf_e[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[9] <= ID_S_191530B5_24e2b0bf_e[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[10] <= ID_S_191530B5_24e2b0bf_e[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[11] <= ID_S_191530B5_24e2b0bf_e[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[12] <= ID_S_191530B5_24e2b0bf_e[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[13] <= ID_S_191530B5_24e2b0bf_e[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[14] <= ID_S_191530B5_24e2b0bf_e[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[15] <= ID_S_191530B5_24e2b0bf_e[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[16] <= ID_S_191530B5_24e2b0bf_e[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[17] <= ID_S_191530B5_24e2b0bf_e[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[18] <= ID_S_191530B5_24e2b0bf_e[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[19] <= ID_S_191530B5_24e2b0bf_e[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[20] <= ID_S_191530B5_24e2b0bf_e[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[21] <= ID_S_191530B5_24e2b0bf_e[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[22] <= ID_S_191530B5_24e2b0bf_e[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[23] <= ID_S_191530B5_24e2b0bf_e[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[24] <= ID_S_191530B5_24e2b0bf_e[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[25] <= ID_S_191530B5_24e2b0bf_e[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[26] <= ID_S_191530B5_24e2b0bf_e[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[27] <= ID_S_191530B5_24e2b0bf_e[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[28] <= ID_S_191530B5_24e2b0bf_e[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[29] <= ID_S_191530B5_24e2b0bf_e[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[30] <= ID_S_191530B5_24e2b0bf_e[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
ID_S_191530B5_24e2b0bf_e[31] <= ID_S_191530B5_24e2b0bf_e[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|GECKO|buttons:inst2
|
|
clk => edges[0].CLK
|
|
clk => edges[1].CLK
|
|
clk => edges[2].CLK
|
|
clk => edges[3].CLK
|
|
clk => edges[4].CLK
|
|
clk => buttons_reg[0].CLK
|
|
clk => buttons_reg[1].CLK
|
|
clk => buttons_reg[2].CLK
|
|
clk => buttons_reg[3].CLK
|
|
clk => buttons_reg[4].CLK
|
|
clk => read_reg.CLK
|
|
clk => address_reg.CLK
|
|
reset_n => buttons_reg[0].PRESET
|
|
reset_n => buttons_reg[1].PRESET
|
|
reset_n => buttons_reg[2].PRESET
|
|
reset_n => buttons_reg[3].PRESET
|
|
reset_n => buttons_reg[4].PRESET
|
|
reset_n => read_reg.ACLR
|
|
reset_n => address_reg.ACLR
|
|
reset_n => edges[0].ACLR
|
|
reset_n => edges[1].ACLR
|
|
reset_n => edges[2].ACLR
|
|
reset_n => edges[3].ACLR
|
|
reset_n => edges[4].ACLR
|
|
cs => read_reg.IN0
|
|
cs => process_2.IN0
|
|
read => read_reg.IN1
|
|
write => process_2.IN1
|
|
address => edges.OUTPUTSELECT
|
|
address => edges.OUTPUTSELECT
|
|
address => edges.OUTPUTSELECT
|
|
address => edges.OUTPUTSELECT
|
|
address => edges.OUTPUTSELECT
|
|
address => address_reg.DATAIN
|
|
wrdata[0] => ~NO_FANOUT~
|
|
wrdata[1] => ~NO_FANOUT~
|
|
wrdata[2] => ~NO_FANOUT~
|
|
wrdata[3] => ~NO_FANOUT~
|
|
wrdata[4] => ~NO_FANOUT~
|
|
wrdata[5] => ~NO_FANOUT~
|
|
wrdata[6] => ~NO_FANOUT~
|
|
wrdata[7] => ~NO_FANOUT~
|
|
wrdata[8] => ~NO_FANOUT~
|
|
wrdata[9] => ~NO_FANOUT~
|
|
wrdata[10] => ~NO_FANOUT~
|
|
wrdata[11] => ~NO_FANOUT~
|
|
wrdata[12] => ~NO_FANOUT~
|
|
wrdata[13] => ~NO_FANOUT~
|
|
wrdata[14] => ~NO_FANOUT~
|
|
wrdata[15] => ~NO_FANOUT~
|
|
wrdata[16] => ~NO_FANOUT~
|
|
wrdata[17] => ~NO_FANOUT~
|
|
wrdata[18] => ~NO_FANOUT~
|
|
wrdata[19] => ~NO_FANOUT~
|
|
wrdata[20] => ~NO_FANOUT~
|
|
wrdata[21] => ~NO_FANOUT~
|
|
wrdata[22] => ~NO_FANOUT~
|
|
wrdata[23] => ~NO_FANOUT~
|
|
wrdata[24] => ~NO_FANOUT~
|
|
wrdata[25] => ~NO_FANOUT~
|
|
wrdata[26] => ~NO_FANOUT~
|
|
wrdata[27] => ~NO_FANOUT~
|
|
wrdata[28] => ~NO_FANOUT~
|
|
wrdata[29] => ~NO_FANOUT~
|
|
wrdata[30] => ~NO_FANOUT~
|
|
wrdata[31] => ~NO_FANOUT~
|
|
buttons[0] => rddata.DATAB
|
|
buttons[0] => buttons_reg[0].DATAIN
|
|
buttons[0] => edges.IN1
|
|
buttons[1] => rddata.DATAB
|
|
buttons[1] => buttons_reg[1].DATAIN
|
|
buttons[1] => edges.IN1
|
|
buttons[2] => rddata.DATAB
|
|
buttons[2] => buttons_reg[2].DATAIN
|
|
buttons[2] => edges.IN1
|
|
buttons[3] => rddata.DATAB
|
|
buttons[3] => buttons_reg[3].DATAIN
|
|
buttons[3] => edges.IN1
|
|
buttons[4] => rddata.DATAB
|
|
buttons[4] => buttons_reg[4].DATAIN
|
|
buttons[4] => edges.IN1
|
|
rddata[0] <= rddata[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[1] <= rddata[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[2] <= rddata[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[3] <= rddata[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[4] <= rddata[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[5] <= rddata[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[6] <= rddata[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[7] <= rddata[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[8] <= rddata[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[9] <= rddata[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[10] <= rddata[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[11] <= rddata[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[12] <= rddata[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[13] <= rddata[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[14] <= rddata[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[15] <= rddata[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[16] <= rddata[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[17] <= rddata[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[18] <= rddata[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[19] <= rddata[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[20] <= rddata[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[21] <= rddata[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[22] <= rddata[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[23] <= rddata[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[24] <= rddata[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[25] <= rddata[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[26] <= rddata[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[27] <= rddata[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[28] <= rddata[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[29] <= rddata[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[30] <= rddata[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[31] <= rddata[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|GECKO|randgen:inst3
|
|
address[0] => Equal1.IN13
|
|
address[1] => Equal1.IN12
|
|
address[2] => Equal1.IN11
|
|
address[3] => Equal1.IN10
|
|
address[4] => Equal1.IN15
|
|
address[5] => Equal1.IN9
|
|
address[6] => Equal1.IN8
|
|
address[7] => Equal1.IN7
|
|
address[8] => Equal1.IN6
|
|
address[9] => Equal1.IN5
|
|
address[10] => Equal1.IN4
|
|
address[11] => Equal1.IN3
|
|
address[12] => Equal1.IN2
|
|
address[13] => Equal1.IN14
|
|
address[14] => Equal1.IN1
|
|
address[15] => Equal1.IN0
|
|
read => chipsel.IN1
|
|
rddata[0] <= rddata[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[1] <= rddata[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[2] <= rddata[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[3] <= rddata[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[4] <= rddata[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[5] <= rddata[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[6] <= rddata[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[7] <= rddata[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[8] <= rddata[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[9] <= rddata[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[10] <= rddata[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[11] <= rddata[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[12] <= rddata[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[13] <= rddata[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[14] <= rddata[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[15] <= rddata[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[16] <= rddata[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[17] <= rddata[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[18] <= rddata[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[19] <= rddata[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[20] <= rddata[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[21] <= rddata[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[22] <= rddata[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[23] <= rddata[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[24] <= rddata[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[25] <= rddata[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[26] <= rddata[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[27] <= rddata[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[28] <= rddata[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[29] <= rddata[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[30] <= rddata[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
rddata[31] <= rddata[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
clk => cs.CLK
|
|
clk => rand_q[0].CLK
|
|
clk => rand_q[1].CLK
|
|
clk => rand_q[2].CLK
|
|
clk => rand_q[3].CLK
|
|
clk => rand_q[4].CLK
|
|
clk => rand_q[5].CLK
|
|
clk => rand_q[6].CLK
|
|
clk => rand_q[7].CLK
|
|
clk => rand_q[8].CLK
|
|
clk => rand_q[9].CLK
|
|
clk => rand_q[10].CLK
|
|
clk => rand_q[11].CLK
|
|
clk => rand_q[12].CLK
|
|
clk => rand_q[13].CLK
|
|
clk => rand_q[14].CLK
|
|
clk => rand_q[15].CLK
|
|
clk => rand_q[16].CLK
|
|
clk => rand_q[17].CLK
|
|
clk => rand_q[18].CLK
|
|
clk => rand_q[19].CLK
|
|
clk => rand_q[20].CLK
|
|
clk => rand_q[21].CLK
|
|
clk => rand_q[22].CLK
|
|
clk => rand_q[23].CLK
|
|
clk => rand_q[24].CLK
|
|
clk => rand_q[25].CLK
|
|
clk => rand_q[26].CLK
|
|
clk => rand_q[27].CLK
|
|
clk => rand_q[28].CLK
|
|
clk => rand_q[29].CLK
|
|
clk => rand_q[30].CLK
|
|
clk => rand_q[31].CLK
|
|
reset_n => rand_q[0].ACLR
|
|
reset_n => rand_q[1].ACLR
|
|
reset_n => rand_q[2].ACLR
|
|
reset_n => rand_q[3].ACLR
|
|
reset_n => rand_q[4].ACLR
|
|
reset_n => rand_q[5].ACLR
|
|
reset_n => rand_q[6].ACLR
|
|
reset_n => rand_q[7].ACLR
|
|
reset_n => rand_q[8].ACLR
|
|
reset_n => rand_q[9].ACLR
|
|
reset_n => rand_q[10].ACLR
|
|
reset_n => rand_q[11].ACLR
|
|
reset_n => rand_q[12].ACLR
|
|
reset_n => rand_q[13].ACLR
|
|
reset_n => rand_q[14].ACLR
|
|
reset_n => rand_q[15].ACLR
|
|
reset_n => rand_q[16].ACLR
|
|
reset_n => rand_q[17].ACLR
|
|
reset_n => rand_q[18].ACLR
|
|
reset_n => rand_q[19].ACLR
|
|
reset_n => rand_q[20].ACLR
|
|
reset_n => rand_q[21].ACLR
|
|
reset_n => rand_q[22].ACLR
|
|
reset_n => rand_q[23].ACLR
|
|
reset_n => rand_q[24].ACLR
|
|
reset_n => rand_q[25].ACLR
|
|
reset_n => rand_q[26].ACLR
|
|
reset_n => rand_q[27].ACLR
|
|
reset_n => rand_q[28].ACLR
|
|
reset_n => rand_q[29].ACLR
|
|
reset_n => rand_q[30].ACLR
|
|
reset_n => rand_q[31].ACLR
|
|
reset_n => cs.ACLR
|
|
|
|
|
|
|GECKO|seven_seg:inst1
|
|
address[0] => Equal0.IN10
|
|
address[0] => Equal1.IN9
|
|
address[0] => Equal2.IN11
|
|
address[0] => Equal3.IN10
|
|
address[1] => Equal0.IN9
|
|
address[1] => Equal1.IN8
|
|
address[1] => Equal2.IN10
|
|
address[1] => Equal3.IN9
|
|
address[2] => Equal0.IN8
|
|
address[2] => Equal1.IN15
|
|
address[2] => Equal2.IN9
|
|
address[2] => Equal3.IN15
|
|
address[3] => Equal0.IN15
|
|
address[3] => Equal1.IN14
|
|
address[3] => Equal2.IN8
|
|
address[3] => Equal3.IN8
|
|
address[4] => Equal0.IN14
|
|
address[4] => Equal1.IN13
|
|
address[4] => Equal2.IN7
|
|
address[4] => Equal3.IN7
|
|
address[5] => Equal0.IN7
|
|
address[5] => Equal1.IN7
|
|
address[5] => Equal2.IN15
|
|
address[5] => Equal3.IN14
|
|
address[6] => Equal0.IN6
|
|
address[6] => Equal1.IN6
|
|
address[6] => Equal2.IN6
|
|
address[6] => Equal3.IN6
|
|
address[7] => Equal0.IN13
|
|
address[7] => Equal1.IN12
|
|
address[7] => Equal2.IN14
|
|
address[7] => Equal3.IN13
|
|
address[8] => Equal0.IN12
|
|
address[8] => Equal1.IN11
|
|
address[8] => Equal2.IN13
|
|
address[8] => Equal3.IN12
|
|
address[9] => Equal0.IN5
|
|
address[9] => Equal1.IN5
|
|
address[9] => Equal2.IN5
|
|
address[9] => Equal3.IN5
|
|
address[10] => Equal0.IN4
|
|
address[10] => Equal1.IN4
|
|
address[10] => Equal2.IN4
|
|
address[10] => Equal3.IN4
|
|
address[11] => Equal0.IN3
|
|
address[11] => Equal1.IN3
|
|
address[11] => Equal2.IN3
|
|
address[11] => Equal3.IN3
|
|
address[12] => Equal0.IN11
|
|
address[12] => Equal1.IN10
|
|
address[12] => Equal2.IN12
|
|
address[12] => Equal3.IN11
|
|
address[13] => Equal0.IN2
|
|
address[13] => Equal1.IN2
|
|
address[13] => Equal2.IN2
|
|
address[13] => Equal3.IN2
|
|
address[14] => Equal0.IN1
|
|
address[14] => Equal1.IN1
|
|
address[14] => Equal2.IN1
|
|
address[14] => Equal3.IN1
|
|
address[15] => Equal0.IN0
|
|
address[15] => Equal1.IN0
|
|
address[15] => Equal2.IN0
|
|
address[15] => Equal3.IN0
|
|
wrdata[0] => reg[3][0].DATAIN
|
|
wrdata[0] => reg[2][0].DATAIN
|
|
wrdata[0] => reg[0][0].DATAIN
|
|
wrdata[0] => reg[1][0].DATAIN
|
|
wrdata[1] => reg[3][1].DATAIN
|
|
wrdata[1] => reg[2][1].DATAIN
|
|
wrdata[1] => reg[1][1].DATAIN
|
|
wrdata[1] => reg[0][1].DATAIN
|
|
wrdata[2] => reg[3][2].DATAIN
|
|
wrdata[2] => reg[2][2].DATAIN
|
|
wrdata[2] => reg[1][2].DATAIN
|
|
wrdata[2] => reg[0][2].DATAIN
|
|
wrdata[3] => reg[3][3].DATAIN
|
|
wrdata[3] => reg[2][3].DATAIN
|
|
wrdata[3] => reg[1][3].DATAIN
|
|
wrdata[3] => reg[0][3].DATAIN
|
|
wrdata[4] => reg[3][4].DATAIN
|
|
wrdata[4] => reg[2][4].DATAIN
|
|
wrdata[4] => reg[1][4].DATAIN
|
|
wrdata[4] => reg[0][4].DATAIN
|
|
wrdata[5] => reg[3][5].DATAIN
|
|
wrdata[5] => reg[2][5].DATAIN
|
|
wrdata[5] => reg[1][5].DATAIN
|
|
wrdata[5] => reg[0][5].DATAIN
|
|
wrdata[6] => reg[3][6].DATAIN
|
|
wrdata[6] => reg[2][6].DATAIN
|
|
wrdata[6] => reg[1][6].DATAIN
|
|
wrdata[6] => reg[0][6].DATAIN
|
|
wrdata[7] => reg[3][7].DATAIN
|
|
wrdata[7] => reg[2][7].DATAIN
|
|
wrdata[7] => reg[1][7].DATAIN
|
|
wrdata[7] => reg[0][7].DATAIN
|
|
clk => reg[0][0].CLK
|
|
clk => reg[0][1].CLK
|
|
clk => reg[0][2].CLK
|
|
clk => reg[0][3].CLK
|
|
clk => reg[0][4].CLK
|
|
clk => reg[0][5].CLK
|
|
clk => reg[0][6].CLK
|
|
clk => reg[0][7].CLK
|
|
clk => reg[1][0].CLK
|
|
clk => reg[1][1].CLK
|
|
clk => reg[1][2].CLK
|
|
clk => reg[1][3].CLK
|
|
clk => reg[1][4].CLK
|
|
clk => reg[1][5].CLK
|
|
clk => reg[1][6].CLK
|
|
clk => reg[1][7].CLK
|
|
clk => reg[2][0].CLK
|
|
clk => reg[2][1].CLK
|
|
clk => reg[2][2].CLK
|
|
clk => reg[2][3].CLK
|
|
clk => reg[2][4].CLK
|
|
clk => reg[2][5].CLK
|
|
clk => reg[2][6].CLK
|
|
clk => reg[2][7].CLK
|
|
clk => reg[3][0].CLK
|
|
clk => reg[3][1].CLK
|
|
clk => reg[3][2].CLK
|
|
clk => reg[3][3].CLK
|
|
clk => reg[3][4].CLK
|
|
clk => reg[3][5].CLK
|
|
clk => reg[3][6].CLK
|
|
clk => reg[3][7].CLK
|
|
reset_n => reg[3][0].ACLR
|
|
reset_n => reg[3][1].ACLR
|
|
reset_n => reg[3][2].ACLR
|
|
reset_n => reg[3][3].ACLR
|
|
reset_n => reg[3][4].ACLR
|
|
reset_n => reg[3][5].ACLR
|
|
reset_n => reg[3][6].ACLR
|
|
reset_n => reg[3][7].ACLR
|
|
reset_n => reg[2][0].ACLR
|
|
reset_n => reg[2][1].ACLR
|
|
reset_n => reg[2][2].ACLR
|
|
reset_n => reg[2][3].ACLR
|
|
reset_n => reg[2][4].ACLR
|
|
reset_n => reg[2][5].ACLR
|
|
reset_n => reg[2][6].ACLR
|
|
reset_n => reg[2][7].ACLR
|
|
reset_n => reg[1][0].ACLR
|
|
reset_n => reg[1][1].ACLR
|
|
reset_n => reg[1][2].ACLR
|
|
reset_n => reg[1][3].ACLR
|
|
reset_n => reg[1][4].ACLR
|
|
reset_n => reg[1][5].ACLR
|
|
reset_n => reg[1][6].ACLR
|
|
reset_n => reg[1][7].ACLR
|
|
reset_n => reg[0][0].ACLR
|
|
reset_n => reg[0][1].ACLR
|
|
reset_n => reg[0][2].ACLR
|
|
reset_n => reg[0][3].ACLR
|
|
reset_n => reg[0][4].ACLR
|
|
reset_n => reg[0][5].ACLR
|
|
reset_n => reg[0][6].ACLR
|
|
reset_n => reg[0][7].ACLR
|
|
seg_out[0] <= reg[0][0].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[1] <= reg[0][1].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[2] <= reg[0][2].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[3] <= reg[0][3].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[4] <= reg[0][4].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[5] <= reg[0][5].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[6] <= reg[0][6].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[7] <= reg[0][7].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[8] <= reg[1][0].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[9] <= reg[1][1].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[10] <= reg[1][2].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[11] <= reg[1][3].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[12] <= reg[1][4].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[13] <= reg[1][5].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[14] <= reg[1][6].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[15] <= reg[1][7].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[16] <= reg[2][0].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[17] <= reg[2][1].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[18] <= reg[2][2].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[19] <= reg[2][3].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[20] <= reg[2][4].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[21] <= reg[2][5].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[22] <= reg[2][6].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[23] <= reg[2][7].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[24] <= reg[3][0].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[25] <= reg[3][1].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[26] <= reg[3][2].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[27] <= reg[3][3].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[28] <= reg[3][4].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[29] <= reg[3][5].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[30] <= reg[3][6].DB_MAX_OUTPUT_PORT_TYPE
|
|
seg_out[31] <= reg[3][7].DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|