Disabled external gits
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-- #############################################################################
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-- DE0_Nano_SoC_LT24_top_level.vhd
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--
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-- BOARD : DE0-Nano-SoC from Terasic
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-- Author : Sahand Kashani-Akhavan from Terasic documentation
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-- Revision : 1.2
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-- Creation date : 11/06/2015
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--
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-- Syntax Rule : GROUP_NAME_N[bit]
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--
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-- GROUP : specify a particular interface (ex: SDR_)
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-- NAME : signal name (ex: CONFIG, D, ...)
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-- bit : signal index
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-- _N : to specify an active-low signal
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-- #############################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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entity DE0_Nano_SoC_LT24_top_level is
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port(
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-- ADC
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ADC_CONVST : out std_logic;
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ADC_SCK : out std_logic;
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ADC_SDI : out std_logic;
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ADC_SDO : in std_logic;
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-- ARDUINO
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ARDUINO_IO : inout std_logic_vector(15 downto 0);
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ARDUINO_RESET_N : inout std_logic;
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-- CLOCK
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FPGA_CLK1_50 : in std_logic;
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FPGA_CLK2_50 : in std_logic;
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FPGA_CLK3_50 : in std_logic;
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-- KEY
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KEY_N : in std_logic_vector(1 downto 0);
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-- LED
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LED : out std_logic_vector(7 downto 0);
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-- SW
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SW : in std_logic_vector(3 downto 0);
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-- GPIO_0
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GPIO_0_LT24_ADC_BUSY : in std_logic;
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GPIO_0_LT24_ADC_CS_N : out std_logic;
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GPIO_0_LT24_ADC_DCLK : out std_logic;
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GPIO_0_LT24_ADC_DIN : out std_logic;
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GPIO_0_LT24_ADC_DOUT : in std_logic;
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GPIO_0_LT24_ADC_PENIRQ_N : in std_logic;
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GPIO_0_LT24_CS_N : out std_logic;
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GPIO_0_LT24_D : out std_logic_vector(15 downto 0);
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GPIO_0_LT24_LCD_ON : out std_logic;
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GPIO_0_LT24_RD_N : out std_logic;
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GPIO_0_LT24_RESET_N : out std_logic;
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GPIO_0_LT24_RS : out std_logic;
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GPIO_0_LT24_WR_N : out std_logic;
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-- GPIO_1
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GPIO_1 : inout std_logic_vector(35 downto 0);
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-- HPS
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HPS_CONV_USB_N : inout std_logic;
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HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
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HPS_DDR3_BA : out std_logic_vector(2 downto 0);
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HPS_DDR3_CAS_N : out std_logic;
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HPS_DDR3_CK_N : out std_logic;
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HPS_DDR3_CK_P : out std_logic;
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HPS_DDR3_CKE : out std_logic;
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HPS_DDR3_CS_N : out std_logic;
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HPS_DDR3_DM : out std_logic_vector(3 downto 0);
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HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
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HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
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HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
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HPS_DDR3_ODT : out std_logic;
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HPS_DDR3_RAS_N : out std_logic;
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HPS_DDR3_RESET_N : out std_logic;
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HPS_DDR3_RZQ : in std_logic;
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HPS_DDR3_WE_N : out std_logic;
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HPS_ENET_GTX_CLK : out std_logic;
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HPS_ENET_INT_N : inout std_logic;
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HPS_ENET_MDC : out std_logic;
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HPS_ENET_MDIO : inout std_logic;
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HPS_ENET_RX_CLK : in std_logic;
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HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
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HPS_ENET_RX_DV : in std_logic;
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HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
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HPS_ENET_TX_EN : out std_logic;
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HPS_GSENSOR_INT : inout std_logic;
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HPS_I2C0_SCLK : inout std_logic;
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HPS_I2C0_SDAT : inout std_logic;
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HPS_I2C1_SCLK : inout std_logic;
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HPS_I2C1_SDAT : inout std_logic;
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HPS_KEY_N : inout std_logic;
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HPS_LED : inout std_logic;
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HPS_LTC_GPIO : inout std_logic;
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HPS_SD_CLK : out std_logic;
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HPS_SD_CMD : inout std_logic;
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HPS_SD_DATA : inout std_logic_vector(3 downto 0);
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HPS_SPIM_CLK : out std_logic;
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HPS_SPIM_MISO : in std_logic;
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HPS_SPIM_MOSI : out std_logic;
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HPS_SPIM_SS : inout std_logic;
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HPS_UART_RX : in std_logic;
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HPS_UART_TX : out std_logic;
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HPS_USB_CLKOUT : in std_logic;
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HPS_USB_DATA : inout std_logic_vector(7 downto 0);
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HPS_USB_DIR : in std_logic;
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HPS_USB_NXT : in std_logic;
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HPS_USB_STP : out std_logic
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);
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end entity DE0_Nano_SoC_LT24_top_level;
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architecture rtl of DE0_Nano_SoC_LT24_top_level is
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begin
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end;
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@@ -0,0 +1,129 @@
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-- #############################################################################
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-- DE0_Nano_SoC_TRDB_D5M_LT24_top_level.vhd
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--
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-- BOARD : DE0-Nano-SoC from Terasic
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-- Author : Sahand Kashani-Akhavan from Terasic documentation
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-- Revision : 1.3
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-- Creation date : 11/06/2015
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--
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-- Syntax Rule : GROUP_NAME_N[bit]
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--
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-- GROUP : specify a particular interface (ex: SDR_)
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-- NAME : signal name (ex: CONFIG, D, ...)
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-- bit : signal index
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-- _N : to specify an active-low signal
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-- #############################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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entity DE0_Nano_SoC_TRDB_D5M_LT24_top_level is
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port(
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-- ADC
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ADC_CONVST : out std_logic;
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ADC_SCK : out std_logic;
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ADC_SDI : out std_logic;
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ADC_SDO : in std_logic;
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-- ARDUINO
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ARDUINO_IO : inout std_logic_vector(15 downto 0);
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ARDUINO_RESET_N : inout std_logic;
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-- CLOCK
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FPGA_CLK1_50 : in std_logic;
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FPGA_CLK2_50 : in std_logic;
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FPGA_CLK3_50 : in std_logic;
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-- KEY
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KEY_N : in std_logic_vector(1 downto 0);
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-- LED
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LED : out std_logic_vector(7 downto 0);
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-- SW
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SW : in std_logic_vector(3 downto 0);
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-- GPIO_0
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GPIO_0_LT24_ADC_BUSY : in std_logic;
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GPIO_0_LT24_ADC_CS_N : out std_logic;
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GPIO_0_LT24_ADC_DCLK : out std_logic;
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GPIO_0_LT24_ADC_DIN : out std_logic;
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GPIO_0_LT24_ADC_DOUT : in std_logic;
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GPIO_0_LT24_ADC_PENIRQ_N : in std_logic;
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GPIO_0_LT24_CS_N : out std_logic;
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GPIO_0_LT24_D : out std_logic_vector(15 downto 0);
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GPIO_0_LT24_LCD_ON : out std_logic;
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GPIO_0_LT24_RD_N : out std_logic;
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GPIO_0_LT24_RESET_N : out std_logic;
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GPIO_0_LT24_RS : out std_logic;
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GPIO_0_LT24_WR_N : out std_logic;
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-- GPIO_1
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GPIO_1_D5M_D : in std_logic_vector(11 downto 0);
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GPIO_1_D5M_FVAL : in std_logic;
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GPIO_1_D5M_LVAL : in std_logic;
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GPIO_1_D5M_PIXCLK : in std_logic;
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GPIO_1_D5M_RESET_N : out std_logic;
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GPIO_1_D5M_SCLK : inout std_logic;
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GPIO_1_D5M_SDATA : inout std_logic;
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GPIO_1_D5M_STROBE : in std_logic;
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GPIO_1_D5M_TRIGGER : out std_logic;
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GPIO_1_D5M_XCLKIN : out std_logic;
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-- HPS
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HPS_CONV_USB_N : inout std_logic;
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HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
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HPS_DDR3_BA : out std_logic_vector(2 downto 0);
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HPS_DDR3_CAS_N : out std_logic;
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HPS_DDR3_CK_N : out std_logic;
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HPS_DDR3_CK_P : out std_logic;
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HPS_DDR3_CKE : out std_logic;
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HPS_DDR3_CS_N : out std_logic;
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HPS_DDR3_DM : out std_logic_vector(3 downto 0);
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HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
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HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
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HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
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HPS_DDR3_ODT : out std_logic;
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HPS_DDR3_RAS_N : out std_logic;
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HPS_DDR3_RESET_N : out std_logic;
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HPS_DDR3_RZQ : in std_logic;
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HPS_DDR3_WE_N : out std_logic;
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HPS_ENET_GTX_CLK : out std_logic;
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HPS_ENET_INT_N : inout std_logic;
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HPS_ENET_MDC : out std_logic;
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HPS_ENET_MDIO : inout std_logic;
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HPS_ENET_RX_CLK : in std_logic;
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HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
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HPS_ENET_RX_DV : in std_logic;
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HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
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HPS_ENET_TX_EN : out std_logic;
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HPS_GSENSOR_INT : inout std_logic;
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HPS_I2C0_SCLK : inout std_logic;
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HPS_I2C0_SDAT : inout std_logic;
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HPS_I2C1_SCLK : inout std_logic;
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HPS_I2C1_SDAT : inout std_logic;
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HPS_KEY_N : inout std_logic;
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HPS_LED : inout std_logic;
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HPS_LTC_GPIO : inout std_logic;
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HPS_SD_CLK : out std_logic;
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HPS_SD_CMD : inout std_logic;
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HPS_SD_DATA : inout std_logic_vector(3 downto 0);
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HPS_SPIM_CLK : out std_logic;
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HPS_SPIM_MISO : in std_logic;
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HPS_SPIM_MOSI : out std_logic;
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HPS_SPIM_SS : inout std_logic;
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HPS_UART_RX : in std_logic;
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HPS_UART_TX : out std_logic;
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HPS_USB_CLKOUT : in std_logic;
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HPS_USB_DATA : inout std_logic_vector(7 downto 0);
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HPS_USB_DIR : in std_logic;
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HPS_USB_NXT : in std_logic;
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HPS_USB_STP : out std_logic
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);
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end entity DE0_Nano_SoC_TRDB_D5M_LT24_top_level;
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architecture rtl of DE0_Nano_SoC_TRDB_D5M_LT24_top_level is
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begin
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end;
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@@ -0,0 +1,125 @@
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-- #############################################################################
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-- DE0_Nano_SoC_TRDB_D5M_VGA_top_level.vhd
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--
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-- BOARD : DE0-Nano-SoC from Terasic
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-- Author : Sahand Kashani-Akhavan from Terasic documentation
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-- Revision : 1.2
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-- Creation date : 11/06/2015
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--
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-- Syntax Rule : GROUP_NAME_N[bit]
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--
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-- GROUP : specify a particular interface (ex: SDR_)
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||||
-- NAME : signal name (ex: CONFIG, D, ...)
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||||
-- bit : signal index
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-- _N : to specify an active-low signal
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-- #############################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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entity DE0_Nano_SoC_TRDB_D5M_VGA_top_level is
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port(
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-- ADC
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ADC_CONVST : out std_logic;
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ADC_SCK : out std_logic;
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ADC_SDI : out std_logic;
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ADC_SDO : in std_logic;
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-- ARDUINO
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ARDUINO_IO : inout std_logic_vector(15 downto 0);
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ARDUINO_RESET_N : inout std_logic;
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-- CLOCK
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FPGA_CLK1_50 : in std_logic;
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FPGA_CLK2_50 : in std_logic;
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FPGA_CLK3_50 : in std_logic;
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-- KEY
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KEY_N : in std_logic_vector(1 downto 0);
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-- LED
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LED : out std_logic_vector(7 downto 0);
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-- SW
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SW : in std_logic_vector(3 downto 0);
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-- GPIO_0
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GPIO_0_VGA_VIDEO_R : out std_logic_vector(7 downto 0);
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GPIO_0_VGA_VIDEO_G : out std_logic_vector(7 downto 0);
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GPIO_0_VGA_VIDEO_B : out std_logic_vector(7 downto 0);
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GPIO_0_VGA_VIDEO_HSYNC : out std_logic;
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GPIO_0_VGA_VIDEO_VSYNC : out std_logic;
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GPIO_0_VGA_VIDEO_CLK : out std_logic;
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GPIO_0_VGA_CAM_PAL_VGA_SCL : out std_logic;
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GPIO_0_VGA_CAM_PAL_VGA_SDA : inout std_logic;
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GPIO_0_VGA_BOARD_ID : inout std_logic;
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-- GPIO_1
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GPIO_1_D5M_D : in std_logic_vector(11 downto 0);
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GPIO_1_D5M_FVAL : in std_logic;
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GPIO_1_D5M_LVAL : in std_logic;
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GPIO_1_D5M_PIXCLK : in std_logic;
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GPIO_1_D5M_RESET_N : out std_logic;
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GPIO_1_D5M_SCLK : inout std_logic;
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GPIO_1_D5M_SDATA : inout std_logic;
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GPIO_1_D5M_STROBE : in std_logic;
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GPIO_1_D5M_TRIGGER : out std_logic;
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GPIO_1_D5M_XCLKIN : out std_logic;
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-- HPS
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HPS_CONV_USB_N : inout std_logic;
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HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
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HPS_DDR3_BA : out std_logic_vector(2 downto 0);
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HPS_DDR3_CAS_N : out std_logic;
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HPS_DDR3_CK_N : out std_logic;
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HPS_DDR3_CK_P : out std_logic;
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HPS_DDR3_CKE : out std_logic;
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HPS_DDR3_CS_N : out std_logic;
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HPS_DDR3_DM : out std_logic_vector(3 downto 0);
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HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
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HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
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HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
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HPS_DDR3_ODT : out std_logic;
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HPS_DDR3_RAS_N : out std_logic;
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HPS_DDR3_RESET_N : out std_logic;
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HPS_DDR3_RZQ : in std_logic;
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HPS_DDR3_WE_N : out std_logic;
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HPS_ENET_GTX_CLK : out std_logic;
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HPS_ENET_INT_N : inout std_logic;
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HPS_ENET_MDC : out std_logic;
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HPS_ENET_MDIO : inout std_logic;
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HPS_ENET_RX_CLK : in std_logic;
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HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
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HPS_ENET_RX_DV : in std_logic;
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HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
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HPS_ENET_TX_EN : out std_logic;
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HPS_GSENSOR_INT : inout std_logic;
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HPS_I2C0_SCLK : inout std_logic;
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HPS_I2C0_SDAT : inout std_logic;
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HPS_I2C1_SCLK : inout std_logic;
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HPS_I2C1_SDAT : inout std_logic;
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HPS_KEY_N : inout std_logic;
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HPS_LED : inout std_logic;
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HPS_LTC_GPIO : inout std_logic;
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HPS_SD_CLK : out std_logic;
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HPS_SD_CMD : inout std_logic;
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HPS_SD_DATA : inout std_logic_vector(3 downto 0);
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HPS_SPIM_CLK : out std_logic;
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||||
HPS_SPIM_MISO : in std_logic;
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||||
HPS_SPIM_MOSI : out std_logic;
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||||
HPS_SPIM_SS : inout std_logic;
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||||
HPS_UART_RX : in std_logic;
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||||
HPS_UART_TX : out std_logic;
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||||
HPS_USB_CLKOUT : in std_logic;
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||||
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
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||||
HPS_USB_DIR : in std_logic;
|
||||
HPS_USB_NXT : in std_logic;
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||||
HPS_USB_STP : out std_logic
|
||||
);
|
||||
end entity DE0_Nano_SoC_TRDB_D5M_VGA_top_level;
|
||||
|
||||
architecture rtl of DE0_Nano_SoC_TRDB_D5M_VGA_top_level is
|
||||
|
||||
begin
|
||||
|
||||
end;
|
||||
@@ -0,0 +1,117 @@
|
||||
-- #############################################################################
|
||||
-- DE0_Nano_SoC_TRDB_D5M_top_level.vhd
|
||||
--
|
||||
-- BOARD : DE0-Nano-SoC from Terasic
|
||||
-- Author : Sahand Kashani-Akhavan from Terasic documentation
|
||||
-- Revision : 1.3
|
||||
-- Creation date : 11/06/2015
|
||||
--
|
||||
-- Syntax Rule : GROUP_NAME_N[bit]
|
||||
--
|
||||
-- GROUP : specify a particular interface (ex: SDR_)
|
||||
-- NAME : signal name (ex: CONFIG, D, ...)
|
||||
-- bit : signal index
|
||||
-- _N : to specify an active-low signal
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity DE0_Nano_SoC_TRDB_D5M_top_level is
|
||||
port(
|
||||
-- ADC
|
||||
ADC_CONVST : out std_logic;
|
||||
ADC_SCK : out std_logic;
|
||||
ADC_SDI : out std_logic;
|
||||
ADC_SDO : in std_logic;
|
||||
|
||||
-- ARDUINO
|
||||
ARDUINO_IO : inout std_logic_vector(15 downto 0);
|
||||
ARDUINO_RESET_N : inout std_logic;
|
||||
|
||||
-- CLOCK
|
||||
FPGA_CLK1_50 : in std_logic;
|
||||
FPGA_CLK2_50 : in std_logic;
|
||||
FPGA_CLK3_50 : in std_logic;
|
||||
|
||||
-- KEY
|
||||
KEY_N : in std_logic_vector(1 downto 0);
|
||||
|
||||
-- LED
|
||||
LED : out std_logic_vector(7 downto 0);
|
||||
|
||||
-- SW
|
||||
SW : in std_logic_vector(3 downto 0);
|
||||
|
||||
-- GPIO_0
|
||||
GPIO_0 : inout std_logic_vector(35 downto 0);
|
||||
|
||||
-- GPIO_1
|
||||
GPIO_1_D5M_D : in std_logic_vector(11 downto 0);
|
||||
GPIO_1_D5M_FVAL : in std_logic;
|
||||
GPIO_1_D5M_LVAL : in std_logic;
|
||||
GPIO_1_D5M_PIXCLK : in std_logic;
|
||||
GPIO_1_D5M_RESET_N : out std_logic;
|
||||
GPIO_1_D5M_SCLK : inout std_logic;
|
||||
GPIO_1_D5M_SDATA : inout std_logic;
|
||||
GPIO_1_D5M_STROBE : in std_logic;
|
||||
GPIO_1_D5M_TRIGGER : out std_logic;
|
||||
GPIO_1_D5M_XCLKIN : out std_logic;
|
||||
|
||||
-- HPS
|
||||
HPS_CONV_USB_N : inout std_logic;
|
||||
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
|
||||
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
|
||||
HPS_DDR3_CAS_N : out std_logic;
|
||||
HPS_DDR3_CK_N : out std_logic;
|
||||
HPS_DDR3_CK_P : out std_logic;
|
||||
HPS_DDR3_CKE : out std_logic;
|
||||
HPS_DDR3_CS_N : out std_logic;
|
||||
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
|
||||
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
|
||||
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
|
||||
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
|
||||
HPS_DDR3_ODT : out std_logic;
|
||||
HPS_DDR3_RAS_N : out std_logic;
|
||||
HPS_DDR3_RESET_N : out std_logic;
|
||||
HPS_DDR3_RZQ : in std_logic;
|
||||
HPS_DDR3_WE_N : out std_logic;
|
||||
HPS_ENET_GTX_CLK : out std_logic;
|
||||
HPS_ENET_INT_N : inout std_logic;
|
||||
HPS_ENET_MDC : out std_logic;
|
||||
HPS_ENET_MDIO : inout std_logic;
|
||||
HPS_ENET_RX_CLK : in std_logic;
|
||||
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
|
||||
HPS_ENET_RX_DV : in std_logic;
|
||||
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
|
||||
HPS_ENET_TX_EN : out std_logic;
|
||||
HPS_GSENSOR_INT : inout std_logic;
|
||||
HPS_I2C0_SCLK : inout std_logic;
|
||||
HPS_I2C0_SDAT : inout std_logic;
|
||||
HPS_I2C1_SCLK : inout std_logic;
|
||||
HPS_I2C1_SDAT : inout std_logic;
|
||||
HPS_KEY_N : inout std_logic;
|
||||
HPS_LED : inout std_logic;
|
||||
HPS_LTC_GPIO : inout std_logic;
|
||||
HPS_SD_CLK : out std_logic;
|
||||
HPS_SD_CMD : inout std_logic;
|
||||
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
|
||||
HPS_SPIM_CLK : out std_logic;
|
||||
HPS_SPIM_MISO : in std_logic;
|
||||
HPS_SPIM_MOSI : out std_logic;
|
||||
HPS_SPIM_SS : inout std_logic;
|
||||
HPS_UART_RX : in std_logic;
|
||||
HPS_UART_TX : out std_logic;
|
||||
HPS_USB_CLKOUT : in std_logic;
|
||||
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
|
||||
HPS_USB_DIR : in std_logic;
|
||||
HPS_USB_NXT : in std_logic;
|
||||
HPS_USB_STP : out std_logic
|
||||
);
|
||||
end entity DE0_Nano_SoC_TRDB_D5M_top_level;
|
||||
|
||||
architecture rtl of DE0_Nano_SoC_TRDB_D5M_top_level is
|
||||
|
||||
begin
|
||||
|
||||
end;
|
||||
@@ -0,0 +1,123 @@
|
||||
-- #############################################################################
|
||||
-- DE0_Nano_SoC_top_level.vhd
|
||||
--
|
||||
-- BOARD : DE0-Nano-SoC from Terasic
|
||||
-- Author : Sahand Kashani-Akhavan from Terasic documentation
|
||||
-- Revision : 1.1
|
||||
-- Creation date : 11/06/2015
|
||||
--
|
||||
-- Syntax Rule : GROUP_NAME_N[bit]
|
||||
--
|
||||
-- GROUP : specify a particular interface (ex: SDR_)
|
||||
-- NAME : signal name (ex: CONFIG, D, ...)
|
||||
-- bit : signal index
|
||||
-- _N : to specify an active-low signal
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity DE0_Nano_SoC_top_level is
|
||||
port(
|
||||
-- ADC
|
||||
--ADC_CONVST : out std_logic;
|
||||
--ADC_SCK : out std_logic;
|
||||
--ADC_SDI : out std_logic;
|
||||
--ADC_SDO : in std_logic;
|
||||
|
||||
-- ARDUINO
|
||||
--ARDUINO_IO : inout std_logic_vector(15 downto 0);
|
||||
--ARDUINO_RESET_N : inout std_logic;
|
||||
|
||||
-- CLOCK
|
||||
FPGA_CLK1_50 : in std_logic;
|
||||
--FPGA_CLK2_50 : in std_logic;
|
||||
--FPGA_CLK3_50 : in std_logic;
|
||||
|
||||
-- KEY
|
||||
KEY_N : in std_logic_vector(1 downto 0);
|
||||
|
||||
-- LED
|
||||
--LED : out std_logic_vector(7 downto 0);
|
||||
|
||||
-- SW
|
||||
--SW : in std_logic_vector(3 downto 0);
|
||||
|
||||
-- GPIO_0
|
||||
GPIO_0 : inout std_logic_vector(35 downto 0)
|
||||
|
||||
-- GPIO_1
|
||||
--GPIO_1 : inout std_logic_vector(35 downto 0);
|
||||
|
||||
-- HPS
|
||||
--HPS_CONV_USB_N : inout std_logic;
|
||||
--HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
|
||||
--HPS_DDR3_BA : out std_logic_vector(2 downto 0);
|
||||
--HPS_DDR3_CAS_N : out std_logic;
|
||||
--HPS_DDR3_CK_N : out std_logic;
|
||||
--HPS_DDR3_CK_P : out std_logic;
|
||||
--HPS_DDR3_CKE : out std_logic;
|
||||
--HPS_DDR3_CS_N : out std_logic;
|
||||
--HPS_DDR3_DM : out std_logic_vector(3 downto 0);
|
||||
--HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
|
||||
--HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
|
||||
--HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
|
||||
--HPS_DDR3_ODT : out std_logic;
|
||||
--HPS_DDR3_RAS_N : out std_logic;
|
||||
--HPS_DDR3_RESET_N : out std_logic;
|
||||
--HPS_DDR3_RZQ : in std_logic;
|
||||
--HPS_DDR3_WE_N : out std_logic;
|
||||
--HPS_ENET_GTX_CLK : out std_logic;
|
||||
--HPS_ENET_INT_N : inout std_logic;
|
||||
--HPS_ENET_MDC : out std_logic;
|
||||
--HPS_ENET_MDIO : inout std_logic;
|
||||
--HPS_ENET_RX_CLK : in std_logic;
|
||||
--HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
|
||||
--HPS_ENET_RX_DV : in std_logic;
|
||||
--HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
|
||||
--HPS_ENET_TX_EN : out std_logic;
|
||||
--HPS_GSENSOR_INT : inout std_logic;
|
||||
--HPS_I2C0_SCLK : inout std_logic;
|
||||
--HPS_I2C0_SDAT : inout std_logic;
|
||||
--HPS_I2C1_SCLK : inout std_logic;
|
||||
--HPS_I2C1_SDAT : inout std_logic;
|
||||
--HPS_KEY_N : inout std_logic;
|
||||
--HPS_LED : inout std_logic;
|
||||
--HPS_LTC_GPIO : inout std_logic;
|
||||
--HPS_SD_CLK : out std_logic;
|
||||
--HPS_SD_CMD : inout std_logic;
|
||||
--HPS_SD_DATA : inout std_logic_vector(3 downto 0);
|
||||
--HPS_SPIM_CLK : out std_logic;
|
||||
--HPS_SPIM_MISO : in std_logic;
|
||||
--HPS_SPIM_MOSI : out std_logic;
|
||||
--HPS_SPIM_SS : inout std_logic;
|
||||
--HPS_UART_RX : in std_logic;
|
||||
--HPS_UART_TX : out std_logic;
|
||||
--HPS_USB_CLKOUT : in std_logic;
|
||||
--HPS_USB_DATA : inout std_logic_vector(7 downto 0);
|
||||
--HPS_USB_DIR : in std_logic;
|
||||
--HPS_USB_NXT : in std_logic;
|
||||
--HPS_USB_STP : out std_logic
|
||||
);
|
||||
end entity DE0_Nano_SoC_top_level;
|
||||
|
||||
architecture rtl of DE0_Nano_SoC_top_level is
|
||||
|
||||
component system is
|
||||
port (
|
||||
clk_clk : in std_logic := 'X'; -- clk
|
||||
reset_reset_n : in std_logic := 'X'; -- reset_n
|
||||
ws28xx_0_conduit_end_ws : out std_logic := 'X' -- export
|
||||
);
|
||||
end component system;
|
||||
|
||||
|
||||
|
||||
begin
|
||||
u0 : component system
|
||||
port map (
|
||||
clk_clk => FPGA_CLK1_50, -- clk.clk
|
||||
reset_reset_n => KEY_N(0), -- reset.reset_n
|
||||
ws28xx_0_conduit_end_ws => GPIO_0(0) -- ws28xx_0_conduit_end.export
|
||||
);
|
||||
end;
|
||||
@@ -0,0 +1,114 @@
|
||||
-- #############################################################################
|
||||
-- DE0_Nano_Soc_7_segment_extension_board.vhd
|
||||
--
|
||||
-- BOARD : DE0-Nano-SoC from Terasic
|
||||
-- Author : Florian Depraz
|
||||
-- : Sahand Kashani-Akhavan from Terasic documentation
|
||||
-- Revision : 1.0
|
||||
-- Creation date : 27/10/2016
|
||||
--
|
||||
-- Syntax Rule : GROUP_NAME_N[bit]
|
||||
--
|
||||
-- GROUP : specify a particular interface (ex: SDR_)
|
||||
-- NAME : signal name (ex: CONFIG, D, ...)
|
||||
-- bit : signal index
|
||||
-- _N : to specify an active-low signal
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity DE0_Nano_Soc_7_segment_extension is
|
||||
port(
|
||||
-- ADC
|
||||
ADC_CONVST : out std_logic;
|
||||
ADC_SCK : out std_logic;
|
||||
ADC_SDI : out std_logic;
|
||||
ADC_SDO : in std_logic;
|
||||
|
||||
-- ARDUINO
|
||||
ARDUINO_IO : inout std_logic_vector(15 downto 0);
|
||||
ARDUINO_RESET_N : inout std_logic;
|
||||
|
||||
-- CLOCK
|
||||
FPGA_CLK1_50 : in std_logic;
|
||||
FPGA_CLK2_50 : in std_logic;
|
||||
FPGA_CLK3_50 : in std_logic;
|
||||
|
||||
-- KEY
|
||||
KEY_N : in std_logic_vector(1 downto 0);
|
||||
|
||||
-- LED
|
||||
LED : out std_logic_vector(7 downto 0);
|
||||
|
||||
-- SW
|
||||
SW : in std_logic_vector(3 downto 0);
|
||||
|
||||
-- GPIO_0
|
||||
GPIO_0 : inout std_logic_vector(35 downto 0);
|
||||
|
||||
-- Extension board 7 segments
|
||||
SelSeg : out std_logic_vector(7 downto 0);
|
||||
Reset_Led : out std_logic;
|
||||
nSelDig : out std_logic_vector(5 downto 0);
|
||||
SwLed : in std_logic_vector(7 downto 0);
|
||||
nButton : in std_logic_vector(3 downto 0)
|
||||
LedButton : out std_logic_vector(3 downto 0);
|
||||
|
||||
-- HPS
|
||||
HPS_CONV_USB_N : inout std_logic;
|
||||
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
|
||||
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
|
||||
HPS_DDR3_CAS_N : out std_logic;
|
||||
HPS_DDR3_CK_N : out std_logic;
|
||||
HPS_DDR3_CK_P : out std_logic;
|
||||
HPS_DDR3_CKE : out std_logic;
|
||||
HPS_DDR3_CS_N : out std_logic;
|
||||
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
|
||||
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
|
||||
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
|
||||
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
|
||||
HPS_DDR3_ODT : out std_logic;
|
||||
HPS_DDR3_RAS_N : out std_logic;
|
||||
HPS_DDR3_RESET_N : out std_logic;
|
||||
HPS_DDR3_RZQ : in std_logic;
|
||||
HPS_DDR3_WE_N : out std_logic;
|
||||
HPS_ENET_GTX_CLK : out std_logic;
|
||||
HPS_ENET_INT_N : inout std_logic;
|
||||
HPS_ENET_MDC : out std_logic;
|
||||
HPS_ENET_MDIO : inout std_logic;
|
||||
HPS_ENET_RX_CLK : in std_logic;
|
||||
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
|
||||
HPS_ENET_RX_DV : in std_logic;
|
||||
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
|
||||
HPS_ENET_TX_EN : out std_logic;
|
||||
HPS_GSENSOR_INT : inout std_logic;
|
||||
HPS_I2C0_SCLK : inout std_logic;
|
||||
HPS_I2C0_SDAT : inout std_logic;
|
||||
HPS_I2C1_SCLK : inout std_logic;
|
||||
HPS_I2C1_SDAT : inout std_logic;
|
||||
HPS_KEY_N : inout std_logic;
|
||||
HPS_LED : inout std_logic;
|
||||
HPS_LTC_GPIO : inout std_logic;
|
||||
HPS_SD_CLK : out std_logic;
|
||||
HPS_SD_CMD : inout std_logic;
|
||||
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
|
||||
HPS_SPIM_CLK : out std_logic;
|
||||
HPS_SPIM_MISO : in std_logic;
|
||||
HPS_SPIM_MOSI : out std_logic;
|
||||
HPS_SPIM_SS : inout std_logic;
|
||||
HPS_UART_RX : in std_logic;
|
||||
HPS_UART_TX : out std_logic;
|
||||
HPS_USB_CLKOUT : in std_logic;
|
||||
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
|
||||
HPS_USB_DIR : in std_logic;
|
||||
HPS_USB_NXT : in std_logic;
|
||||
HPS_USB_STP : out std_logic
|
||||
);
|
||||
end entity DE0_Nano_Soc_7_segment_extension;
|
||||
|
||||
architecture rtl of DE0_Nano_Soc_7_segment_extension is
|
||||
begin
|
||||
|
||||
|
||||
end;
|
||||
@@ -0,0 +1,36 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity ClkGen is
|
||||
generic (
|
||||
F_OUT : natural; -- Hz
|
||||
F_CLK : natural -- Hz
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst_n : in std_logic;
|
||||
clk_o : out std_logic;
|
||||
en : in std_logic
|
||||
);
|
||||
end ClkGen;
|
||||
|
||||
architecture Behavioral of ClkGen is
|
||||
constant CNT_MAX : integer := integer(floor(real(F_CLK) / real(F_OUT))) - 1;
|
||||
signal counter_reg, counter_next: integer range CNT_MAX downto 0;
|
||||
begin
|
||||
counter_next <= CNT_MAX when counter_reg = 0 else counter_reg - 1;
|
||||
process(clk, rst_n) begin
|
||||
if rising_edge(clk) then
|
||||
if rst_n = '0' then
|
||||
counter_reg <= CNT_MAX;
|
||||
else
|
||||
if en = '1' then
|
||||
counter_reg <= counter_next;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
clk_o <= '1' when counter_reg = 0 and en = '1' else '0';
|
||||
end Behavioral; -- Behavioral
|
||||
@@ -0,0 +1,89 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity WS28XX is
|
||||
port(
|
||||
clk:in std_logic;
|
||||
nReset:in std_logic;
|
||||
|
||||
--Internalinterface(i.e.Avalonslave).
|
||||
address:in std_logic;
|
||||
write:in std_logic;
|
||||
writedata:in std_logic_vector(31 downto 0);
|
||||
|
||||
--Externalinterface(i.e.conduit).
|
||||
lout:out std_logic
|
||||
);
|
||||
|
||||
end WS28XX;
|
||||
|
||||
|
||||
architecture comp of WS28XX is
|
||||
|
||||
signal led_i : std_logic_vector(7 downto 0);
|
||||
signal led_v : std_logic_vector(23 downto 0);
|
||||
signal led_wr : std_logic;
|
||||
|
||||
signal led_n : std_logic_vector(7 downto 0);
|
||||
signal led_n_wr : std_logic;
|
||||
|
||||
signal ready : std_logic;
|
||||
begin
|
||||
|
||||
--WSDriver.
|
||||
l0 : entity work.WSDriver
|
||||
generic map (
|
||||
F_CLK => 50000000,
|
||||
N_LED_MAX => 255
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
rst_n => nReset,
|
||||
|
||||
-- LED address and LED value
|
||||
led_wr_in => led_wr,
|
||||
led_in => led_v,
|
||||
addr_in => led_i,
|
||||
|
||||
-- Write-enable & value of N bits to keep active
|
||||
n_wr_in => led_n_wr,
|
||||
n_in => led_n,
|
||||
|
||||
-- Output 1-bit line for WS2812 strip
|
||||
ws_out => lout,
|
||||
|
||||
-- Low while shifting LED values
|
||||
ready_out => ready
|
||||
);
|
||||
|
||||
|
||||
led_i <= writedata(31 downto 24);
|
||||
led_v <= writedata(23 downto 0);
|
||||
led_n <= writedata(7 downto 0);
|
||||
|
||||
--Avalon slave - write to registers.
|
||||
process(write,address,nReset)
|
||||
begin
|
||||
if nReset = '0' then
|
||||
led_wr <= '0';
|
||||
led_n_wr <= '0';
|
||||
else
|
||||
led_wr <= '0';
|
||||
led_n_wr <= '0';
|
||||
|
||||
if write = '1' then
|
||||
case address is
|
||||
when '0' =>
|
||||
led_wr <= '1';
|
||||
when '1' =>
|
||||
led_n_wr <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end comp;
|
||||
@@ -0,0 +1,134 @@
|
||||
# TCL File Generated by Component Editor 18.1
|
||||
# Fri Oct 30 13:47:37 CET 2020
|
||||
# DO NOT MODIFY
|
||||
|
||||
|
||||
#
|
||||
# WS28XX "WS28XX" v1.0
|
||||
# 2020.10.30.13:47:37
|
||||
#
|
||||
#
|
||||
|
||||
#
|
||||
# request TCL package from ACDS 16.1
|
||||
#
|
||||
package require -exact qsys 16.1
|
||||
|
||||
|
||||
#
|
||||
# module WS28XX
|
||||
#
|
||||
set_module_property DESCRIPTION ""
|
||||
set_module_property NAME WS28XX
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property INTERNAL false
|
||||
set_module_property OPAQUE_ADDRESS_MAP true
|
||||
set_module_property AUTHOR ""
|
||||
set_module_property DISPLAY_NAME WS28XX
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
set_module_property EDITABLE true
|
||||
set_module_property REPORT_TO_TALKBACK false
|
||||
set_module_property ALLOW_GREYBOX_GENERATION false
|
||||
set_module_property REPORT_HIERARCHY false
|
||||
|
||||
|
||||
#
|
||||
# file sets
|
||||
#
|
||||
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
|
||||
set_fileset_property QUARTUS_SYNTH TOP_LEVEL WS28XX
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
|
||||
add_fileset_file WS28XX.vhd VHDL PATH WS28XX.vhd TOP_LEVEL_FILE
|
||||
|
||||
|
||||
#
|
||||
# parameters
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# display items
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# connection point avalon_slave
|
||||
#
|
||||
add_interface avalon_slave avalon end
|
||||
set_interface_property avalon_slave addressUnits WORDS
|
||||
set_interface_property avalon_slave associatedClock clock_sink
|
||||
set_interface_property avalon_slave associatedReset reset_sink
|
||||
set_interface_property avalon_slave bitsPerSymbol 8
|
||||
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
|
||||
set_interface_property avalon_slave burstcountUnits WORDS
|
||||
set_interface_property avalon_slave explicitAddressSpan 0
|
||||
set_interface_property avalon_slave holdTime 0
|
||||
set_interface_property avalon_slave linewrapBursts false
|
||||
set_interface_property avalon_slave maximumPendingReadTransactions 0
|
||||
set_interface_property avalon_slave maximumPendingWriteTransactions 0
|
||||
set_interface_property avalon_slave readLatency 0
|
||||
set_interface_property avalon_slave readWaitTime 1
|
||||
set_interface_property avalon_slave setupTime 0
|
||||
set_interface_property avalon_slave timingUnits Cycles
|
||||
set_interface_property avalon_slave writeWaitTime 0
|
||||
set_interface_property avalon_slave ENABLED true
|
||||
set_interface_property avalon_slave EXPORT_OF ""
|
||||
set_interface_property avalon_slave PORT_NAME_MAP ""
|
||||
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port avalon_slave address address Input 2
|
||||
add_interface_port avalon_slave write write Input 1
|
||||
add_interface_port avalon_slave writedata writedata Input 32
|
||||
add_interface_port avalon_slave read read Input 1
|
||||
add_interface_port avalon_slave readdata readdata Output 32
|
||||
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
|
||||
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
|
||||
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
|
||||
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
|
||||
|
||||
|
||||
#
|
||||
# connection point clock_sink
|
||||
#
|
||||
add_interface clock_sink clock end
|
||||
set_interface_property clock_sink clockRate 0
|
||||
set_interface_property clock_sink ENABLED true
|
||||
set_interface_property clock_sink EXPORT_OF ""
|
||||
set_interface_property clock_sink PORT_NAME_MAP ""
|
||||
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property clock_sink SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port clock_sink clk clk Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point reset_sink
|
||||
#
|
||||
add_interface reset_sink reset end
|
||||
set_interface_property reset_sink associatedClock clock_sink
|
||||
set_interface_property reset_sink synchronousEdges DEASSERT
|
||||
set_interface_property reset_sink ENABLED true
|
||||
set_interface_property reset_sink EXPORT_OF ""
|
||||
set_interface_property reset_sink PORT_NAME_MAP ""
|
||||
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port reset_sink nReset reset_n Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point ws_out_source
|
||||
#
|
||||
add_interface ws_out_source conduit end
|
||||
set_interface_property ws_out_source associatedClock clock_sink
|
||||
set_interface_property ws_out_source associatedReset ""
|
||||
set_interface_property ws_out_source ENABLED true
|
||||
set_interface_property ws_out_source EXPORT_OF ""
|
||||
set_interface_property ws_out_source PORT_NAME_MAP ""
|
||||
set_interface_property ws_out_source CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property ws_out_source SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port ws_out_source lout new_signal Output 1
|
||||
|
||||
@@ -0,0 +1,213 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity WSDriver is
|
||||
generic (
|
||||
F_CLK : natural; -- Board frequency in Hz
|
||||
N_LED_MAX : natural -- Maximum number of LEDs to instantiate
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst_n : in std_logic;
|
||||
|
||||
-- LED address and LED value
|
||||
led_wr_in : in std_logic;
|
||||
led_in : in std_logic_vector(23 downto 0);
|
||||
addr_in : in std_logic_vector(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0);
|
||||
|
||||
-- Write-enable and value of N LEDs to keep active/addressable
|
||||
n_wr_in : in std_logic;
|
||||
n_in : in std_logic_vector(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0);
|
||||
|
||||
-- Output 1-bit line for WS2812 strip
|
||||
ws_out : out std_logic;
|
||||
|
||||
-- Output Ready
|
||||
ready_out : out std_logic
|
||||
);
|
||||
end WSDriver;
|
||||
|
||||
architecture Behavioral of WSDriver is
|
||||
constant F_WS : real := 1.0/((0.3)*10**(-6.0));
|
||||
constant T_RES_US : real := 50.0*10**(-6.0);
|
||||
constant RES_TICKS : integer := integer(ceil(T_RES_US*F_WS));
|
||||
|
||||
constant BITS_PER_LED : integer := 24;
|
||||
|
||||
subtype LED is std_logic_vector(BITS_PER_LED - 1 downto 0);
|
||||
type LED_array is array (natural range 0 to N_LED_MAX - 1) of LED;
|
||||
|
||||
type State is (ready, tx, reset);
|
||||
|
||||
signal ws_clk : std_logic;
|
||||
signal led_idx_reg, led_idx_next : natural range 0 to N_LED_MAX - 1;
|
||||
signal bit_idx_reg, bit_idx_next : natural range 0 to N_LED_MAX - 1;
|
||||
signal state_reg, state_next : State;
|
||||
|
||||
constant WS_CLKS_PER_BIT : integer := 4;
|
||||
signal ws_cntr_reg, ws_cntr_next : integer range WS_CLKS_PER_BIT - 1 downto 0;
|
||||
signal ws_en : std_logic;
|
||||
|
||||
signal leds_reg, leds_next : LED_array;
|
||||
|
||||
-- Register for maintaining the set of driven LEDs
|
||||
signal n_leds_reg, n_leds_next : unsigned(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0) := (others => '0');
|
||||
|
||||
-- Currently accessed LED
|
||||
signal current_led : LED;
|
||||
|
||||
-- Trailing reset counter
|
||||
signal reset_cntr_reg, reset_cntr_next : integer range RES_TICKS - 1 downto 0;
|
||||
|
||||
-- Detecting wr_in assertions
|
||||
signal wr_in_detec_reg, wr_in_detec_next : std_logic := '0';
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- Next-state LED and Bit index process
|
||||
process (all) begin
|
||||
bit_idx_next <= bit_idx_reg;
|
||||
led_idx_next <= led_idx_reg;
|
||||
reset_cntr_next <= reset_cntr_reg;
|
||||
state_next <= state_reg;
|
||||
wr_in_detec_next <= wr_in_detec_reg;
|
||||
|
||||
-- Latch wr_in value, to ensure re-transition to tx state if wr_in occured
|
||||
-- during a non-ready state.
|
||||
if led_wr_in = '1' then
|
||||
wr_in_detec_next <= '1';
|
||||
end if;
|
||||
|
||||
case state_reg is
|
||||
-- STATE READY
|
||||
when ready =>
|
||||
bit_idx_next <= BITS_PER_LED - 1;
|
||||
led_idx_next <= 0;
|
||||
|
||||
if n_leds_reg /= 0 and wr_in_detec_reg = '1' then
|
||||
wr_in_detec_next <= '0';
|
||||
state_next <= tx;
|
||||
end if;
|
||||
|
||||
-- STATE TX
|
||||
when tx =>
|
||||
if ws_cntr_reg = (WS_CLKS_PER_BIT - 1) and ws_clk ='1' then
|
||||
if bit_idx_reg = 0 then
|
||||
-- Transition to next LED
|
||||
bit_idx_next <= BITS_PER_LED - 1;
|
||||
led_idx_next <= led_idx_reg + 1;
|
||||
else
|
||||
-- Bit was fully shifted, transition to next bit
|
||||
bit_idx_next <= bit_idx_reg - 1;
|
||||
end if;
|
||||
|
||||
-- All LEDs fully shifted out (+last bit of last led)? transition to ready
|
||||
if bit_idx_reg = 0 and led_idx_reg + 1 = n_leds_reg then
|
||||
state_next <= reset;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- STATE TRAILING RESET
|
||||
when reset =>
|
||||
if ws_clk ='1' then
|
||||
if reset_cntr_reg = RES_TICKS - 1 then
|
||||
reset_cntr_next <= 0;
|
||||
state_next <= ready;
|
||||
else
|
||||
reset_cntr_next <= reset_cntr_reg + 1;
|
||||
end if;
|
||||
end if;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Currently accessed LED multiplexer
|
||||
current_led <= leds_reg(led_idx_reg) when state_reg = tx else (others => '0');
|
||||
|
||||
-- Next state WS counter
|
||||
process (state_reg, ws_cntr_reg, ws_clk) begin
|
||||
ws_cntr_next <= ws_cntr_reg;
|
||||
if state_reg = ready or state_reg = reset then
|
||||
ws_cntr_next <= 0;
|
||||
elsif ws_clk = '1' then
|
||||
if ws_cntr_reg /= (WS_CLKS_PER_BIT - 1) then
|
||||
ws_cntr_next <= ws_cntr_reg + 1;
|
||||
else
|
||||
ws_cntr_next <= 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Next-state LED values
|
||||
process(led_wr_in, led_in, leds_reg, addr_in, n_wr_in, n_in) begin
|
||||
leds_next <= leds_reg;
|
||||
n_leds_next <= n_leds_reg;
|
||||
|
||||
if led_wr_in = '1' then
|
||||
leds_next(to_integer(unsigned(addr_in))) <= led_in;
|
||||
end if;
|
||||
-- Set N LEDs precedes LED write operation
|
||||
if n_wr_in = '1' then
|
||||
n_leds_next <= unsigned(n_in);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- WS output clock
|
||||
clkgen_ent : entity work.ClkGen
|
||||
generic map (
|
||||
F_CLK => F_CLK,
|
||||
F_OUT => integer(F_WS)
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
clk_o => ws_clk,
|
||||
en => ws_en
|
||||
);
|
||||
|
||||
-- Only enable ws clock gen when required
|
||||
ws_en <= '1' when state_reg /= ready else '0';
|
||||
|
||||
-- Clocking logic
|
||||
process(clk) begin
|
||||
if rising_edge(clk) then
|
||||
if rst_n = '0' then
|
||||
ws_cntr_reg <= 0;
|
||||
leds_reg <= (others => (others => '0'));
|
||||
n_leds_reg <= (others => '0');
|
||||
wr_in_detec_reg <= '0';
|
||||
bit_idx_reg <= BITS_PER_LED - 1;
|
||||
state_reg <= ready;
|
||||
led_idx_reg <= 0;
|
||||
reset_cntr_reg <= 0;
|
||||
else
|
||||
ws_cntr_reg <= ws_cntr_next;
|
||||
leds_reg <= leds_next;
|
||||
n_leds_reg <= n_leds_next;
|
||||
wr_in_detec_reg <= wr_in_detec_next;
|
||||
bit_idx_reg <= bit_idx_next;
|
||||
state_reg <= state_next;
|
||||
led_idx_reg <= led_idx_next;
|
||||
reset_cntr_reg <= reset_cntr_next;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- WS2811 output bit sequence
|
||||
process(state_reg, ws_cntr_reg) begin
|
||||
ws_out <= '0';
|
||||
if state_reg = tx then
|
||||
case ws_cntr_reg is
|
||||
when 0 => ws_out <= '1';
|
||||
when 1 => ws_out <= current_led(bit_idx_reg);
|
||||
when 2 => ws_out <= '0';
|
||||
when 3 => ws_out <= '0';
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ready_out <= '1' when state_reg = ready else '0';
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,96 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
|
||||
entity WSDriver_tb is
|
||||
end WSDriver_tb;
|
||||
|
||||
architecture test of WSDriver_tb is
|
||||
constant CLK_PERIOD : time := 20 ns;
|
||||
constant N_LED_MAX : integer := 255;
|
||||
|
||||
signal clk : std_logic := '0';
|
||||
signal rst_n : std_logic;
|
||||
|
||||
signal led_wr_in : std_logic := '0';
|
||||
signal addr_in : std_logic_vector(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0) := (others => '0');
|
||||
signal led_in : std_logic_vector(23 downto 0) := (others => '0');
|
||||
|
||||
signal n_wr_in : std_logic := '0';
|
||||
signal n_in : std_logic_vector(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0) := (others => '0');
|
||||
|
||||
signal ws_out : std_logic;
|
||||
signal ready_out : std_logic;
|
||||
|
||||
begin
|
||||
-- Instantiate DUT
|
||||
dut : entity work.WSDriver
|
||||
generic map (
|
||||
F_CLK => 50000000,
|
||||
N_LED_MAX => 255
|
||||
)
|
||||
port map(
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
led_wr_in => led_wr_in,
|
||||
addr_in => addr_in,
|
||||
led_in => led_in,
|
||||
n_wr_in => n_wr_in,
|
||||
n_in => n_in,
|
||||
ws_out => ws_out,
|
||||
ready_out => ready_out
|
||||
);
|
||||
|
||||
-- Clocking process
|
||||
clk_generation : process
|
||||
begin
|
||||
clk <= not clk;
|
||||
wait for CLK_PERIOD / 2;
|
||||
end process;
|
||||
|
||||
tb : process
|
||||
procedure wait_ready is
|
||||
begin
|
||||
if ready_out /= '1' then
|
||||
wait until ready_out = '1';
|
||||
end if;
|
||||
end procedure wait_ready;
|
||||
|
||||
procedure finish is
|
||||
begin
|
||||
wait until falling_edge(clk);
|
||||
wait_ready;
|
||||
wait;
|
||||
end procedure finish ;
|
||||
|
||||
begin
|
||||
-- Reset
|
||||
rst_n <= '0';
|
||||
wait for CLK_PERIOD * 2.5;
|
||||
rst_n <= '1';
|
||||
wait for CLK_PERIOD * 2;
|
||||
|
||||
-- Test set N
|
||||
n_in <= std_logic_vector(to_unsigned(3, n_in'length));
|
||||
n_wr_in <= '1';
|
||||
wait for CLK_PERIOD;
|
||||
n_wr_in <= '0';
|
||||
wait_ready;
|
||||
|
||||
|
||||
-- Test write LED value
|
||||
addr_in <= std_logic_vector(to_unsigned(0, n_in'length));
|
||||
led_in <= "110011001100110011001100";
|
||||
led_wr_in <= '1';
|
||||
wait for CLK_PERIOD;
|
||||
led_wr_in <= '0';
|
||||
|
||||
-- Test finished
|
||||
wait_ready;
|
||||
finish;
|
||||
|
||||
end process;
|
||||
|
||||
end;
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,52 @@
|
||||
# A gitignore for Altera Quartus II that tries to ignore almost all of the
|
||||
# automatically Quartus-generated files. This primarily leaves the project,
|
||||
# settings, source, and constraint files to be added. The files ignored do not
|
||||
# include the bulk of the MegaFunction Wizard generated files which enables
|
||||
# a cloned repository to be used (usually) immediately without regenerating
|
||||
# Altera IP blocks.
|
||||
|
||||
# Need to keep all HDL files and timing constraint files
|
||||
# *.vhd
|
||||
# *.v
|
||||
# *.sdc
|
||||
|
||||
# ignore Quartus II generated folders
|
||||
*_sim
|
||||
db
|
||||
greybox_tmp
|
||||
incremental_db
|
||||
simulation
|
||||
testbench
|
||||
timing
|
||||
synthesis
|
||||
.qsys_edit
|
||||
|
||||
# ignore Quartus II generated files
|
||||
*_generation_script*
|
||||
*_inst.vhd
|
||||
*.bak
|
||||
*.cmp
|
||||
*.done
|
||||
*.eqn
|
||||
*.hex
|
||||
*.html
|
||||
*.jdi
|
||||
*.jpg
|
||||
*.mif
|
||||
*.pin
|
||||
*.pof
|
||||
*.ptf.*
|
||||
*.qar
|
||||
*.qarlog
|
||||
*.qws
|
||||
*.rpt
|
||||
*.smsg
|
||||
*.sof
|
||||
*.sopc_builder
|
||||
*.summary
|
||||
*.tcl
|
||||
*.txt # Explicitly add any text files used
|
||||
*~
|
||||
*example*
|
||||
*sopc_*
|
||||
PLLJ_PLLSPE_INFO.txt # The generated PLL specification file
|
||||
@@ -0,0 +1,94 @@
|
||||
io_4iomodule_c5_index: 42gpio_index: 2
|
||||
io_4iomodule_c5_index: 41gpio_index: 369
|
||||
io_4iomodule_c5_index: 27gpio_index: 6
|
||||
io_4iomodule_c5_index: 1gpio_index: 365
|
||||
io_4iomodule_c5_index: 22gpio_index: 10
|
||||
io_4iomodule_c5_index: 6gpio_index: 361
|
||||
io_4iomodule_c5_index: 28gpio_index: 14
|
||||
io_4iomodule_c5_index: 24gpio_index: 357
|
||||
io_4iomodule_c5_index: 21gpio_index: 19
|
||||
io_4iomodule_c5_index: 25gpio_index: 353
|
||||
io_4iomodule_c5_index: 23gpio_index: 22
|
||||
io_4iomodule_c5_index: 15gpio_index: 349
|
||||
io_4iomodule_c5_index: 13gpio_index: 27
|
||||
io_4iomodule_c5_index: 34gpio_index: 345
|
||||
io_4iomodule_c5_index: 39gpio_index: 30
|
||||
io_4iomodule_c5_index: 19gpio_index: 341
|
||||
io_4iomodule_c5_index: 5gpio_index: 35
|
||||
io_4iomodule_c5_index: 10gpio_index: 337
|
||||
io_4iomodule_c5_index: 9gpio_index: 38
|
||||
io_4iomodule_c5_index: 36gpio_index: 333
|
||||
io_4iomodule_c5_index: 17gpio_index: 43
|
||||
io_4iomodule_c5_index: 40gpio_index: 329
|
||||
io_4iomodule_c5_index: 16gpio_index: 46
|
||||
io_4iomodule_c5_index: 43gpio_index: 325
|
||||
io_4iomodule_a_index: 13gpio_index: 321
|
||||
io_4iomodule_c5_index: 2gpio_index: 51
|
||||
io_4iomodule_a_index: 15gpio_index: 317
|
||||
io_4iomodule_a_index: 8gpio_index: 313
|
||||
io_4iomodule_c5_index: 32gpio_index: 54
|
||||
io_4iomodule_a_index: 5gpio_index: 309
|
||||
io_4iomodule_c5_index: 8gpio_index: 59
|
||||
io_4iomodule_a_index: 11gpio_index: 305
|
||||
io_4iomodule_c5_index: 4gpio_index: 62
|
||||
io_4iomodule_a_index: 3gpio_index: 301
|
||||
io_4iomodule_c5_index: 30gpio_index: 67
|
||||
io_4iomodule_a_index: 7gpio_index: 297
|
||||
io_4iomodule_c5_index: 0gpio_index: 70
|
||||
io_4iomodule_a_index: 0gpio_index: 293
|
||||
io_4iomodule_c5_index: 31gpio_index: 75
|
||||
io_4iomodule_a_index: 12gpio_index: 289
|
||||
io_4iomodule_c5_index: 26gpio_index: 78
|
||||
io_4iomodule_a_index: 4gpio_index: 285
|
||||
io_4iomodule_a_index: 10gpio_index: 281
|
||||
io_4iomodule_c5_index: 3gpio_index: 83
|
||||
io_4iomodule_a_index: 16gpio_index: 277
|
||||
io_4iomodule_c5_index: 18gpio_index: 86
|
||||
io_4iomodule_c5_index: 37gpio_index: 91
|
||||
io_4iomodule_a_index: 14gpio_index: 273
|
||||
io_4iomodule_a_index: 1gpio_index: 269
|
||||
io_4iomodule_c5_index: 33gpio_index: 94
|
||||
io_4iomodule_c5_index: 20gpio_index: 99
|
||||
io_4iomodule_a_index: 2gpio_index: 265
|
||||
io_4iomodule_c5_index: 7gpio_index: 102
|
||||
io_4iomodule_a_index: 9gpio_index: 261
|
||||
io_4iomodule_a_index: 6gpio_index: 257
|
||||
io_4iomodule_c5_index: 11gpio_index: 107
|
||||
io_4iomodule_a_index: 17gpio_index: 253
|
||||
io_4iomodule_c5_index: 38gpio_index: 110
|
||||
io_4iomodule_c5_index: 14gpio_index: 115
|
||||
io_4iomodule_c5_index: 29gpio_index: 118
|
||||
io_4iomodule_c5_index: 12gpio_index: 123
|
||||
io_4iomodule_c5_index: 35gpio_index: 126
|
||||
io_4iomodule_h_c5_index: 0gpio_index: 129
|
||||
io_4iomodule_h_c5_index: 1gpio_index: 133
|
||||
io_4iomodule_h_c5_index: 3gpio_index: 137
|
||||
io_4iomodule_h_c5_index: 2gpio_index: 141
|
||||
io_4iomodule_h_index: 20gpio_index: 144
|
||||
io_4iomodule_h_index: 24gpio_index: 148
|
||||
io_4iomodule_h_index: 12gpio_index: 152
|
||||
io_4iomodule_h_index: 10gpio_index: 156
|
||||
io_4iomodule_h_index: 0gpio_index: 160
|
||||
io_4iomodule_vref_h_index: 0gpio_index: 164
|
||||
io_4iomodule_h_index: 22gpio_index: 167
|
||||
io_4iomodule_h_index: 6gpio_index: 171
|
||||
io_4iomodule_h_index: 16gpio_index: 175
|
||||
io_4iomodule_h_index: 2gpio_index: 179
|
||||
io_4iomodule_h_index: 5gpio_index: 183
|
||||
io_4iomodule_h_index: 3gpio_index: 187
|
||||
io_4iomodule_h_index: 14gpio_index: 191
|
||||
io_4iomodule_h_index: 7gpio_index: 195
|
||||
io_4iomodule_h_index: 18gpio_index: 199
|
||||
io_4iomodule_h_index: 11gpio_index: 203
|
||||
io_4iomodule_h_index: 9gpio_index: 207
|
||||
io_4iomodule_h_index: 13gpio_index: 211
|
||||
io_4iomodule_h_index: 23gpio_index: 215
|
||||
io_4iomodule_vref_h_index: 1gpio_index: 219
|
||||
io_4iomodule_h_index: 21gpio_index: 222
|
||||
io_4iomodule_h_index: 8gpio_index: 226
|
||||
io_4iomodule_h_index: 25gpio_index: 230
|
||||
io_4iomodule_h_index: 1gpio_index: 234
|
||||
io_4iomodule_h_index: 15gpio_index: 238
|
||||
io_4iomodule_h_index: 19gpio_index: 242
|
||||
io_4iomodule_h_index: 17gpio_index: 246
|
||||
io_4iomodule_h_index: 4gpio_index: 250
|
||||
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
||||
# Date created = 09:04:57 October 23, 2020
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "18.1"
|
||||
DATE = "09:04:57 October 23, 2020"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "lab2"
|
||||
@@ -0,0 +1,897 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
||||
# Date created = 09:04:57 October 23, 2020
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# lab2_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name DEVICE 5CSEMA4U23C6
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_top_level
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:57 OCTOBER 23, 2020"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
|
||||
set_location_assignment PIN_U9 -to ADC_CONVST
|
||||
set_location_assignment PIN_V10 -to ADC_SCK
|
||||
set_location_assignment PIN_AC4 -to ADC_SDI
|
||||
set_location_assignment PIN_AD4 -to ADC_SDO
|
||||
set_location_assignment PIN_AG13 -to ARDUINO_IO[0]
|
||||
set_location_assignment PIN_AG13 -to ARDUINO_IO_0
|
||||
set_location_assignment PIN_AF13 -to ARDUINO_IO[1]
|
||||
set_location_assignment PIN_AF13 -to ARDUINO_IO_1
|
||||
set_location_assignment PIN_AG10 -to ARDUINO_IO[2]
|
||||
set_location_assignment PIN_AG10 -to ARDUINO_IO_2
|
||||
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
|
||||
set_location_assignment PIN_AG9 -to ARDUINO_IO_3
|
||||
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
|
||||
set_location_assignment PIN_U14 -to ARDUINO_IO_4
|
||||
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
|
||||
set_location_assignment PIN_U13 -to ARDUINO_IO_5
|
||||
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
|
||||
set_location_assignment PIN_AG8 -to ARDUINO_IO_6
|
||||
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
|
||||
set_location_assignment PIN_AH8 -to ARDUINO_IO_7
|
||||
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
|
||||
set_location_assignment PIN_AF17 -to ARDUINO_IO_8
|
||||
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
|
||||
set_location_assignment PIN_AE15 -to ARDUINO_IO_9
|
||||
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
|
||||
set_location_assignment PIN_AF15 -to ARDUINO_IO_10
|
||||
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
|
||||
set_location_assignment PIN_AG16 -to ARDUINO_IO_11
|
||||
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
|
||||
set_location_assignment PIN_AH11 -to ARDUINO_IO_12
|
||||
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
|
||||
set_location_assignment PIN_AH12 -to ARDUINO_IO_13
|
||||
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
|
||||
set_location_assignment PIN_AH9 -to ARDUINO_IO_14
|
||||
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
|
||||
set_location_assignment PIN_AG11 -to ARDUINO_IO_15
|
||||
set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
|
||||
set_location_assignment PIN_V11 -to FPGA_CLK1_50
|
||||
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
|
||||
set_location_assignment PIN_E11 -to FPGA_CLK3_50
|
||||
set_location_assignment PIN_C6 -to HPS_CONV_USB_N
|
||||
set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0]
|
||||
set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0
|
||||
set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1]
|
||||
set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1
|
||||
set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2]
|
||||
set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2
|
||||
set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3]
|
||||
set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3
|
||||
set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4]
|
||||
set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4
|
||||
set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5]
|
||||
set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5
|
||||
set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6]
|
||||
set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6
|
||||
set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7]
|
||||
set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7
|
||||
set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8]
|
||||
set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8
|
||||
set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9]
|
||||
set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9
|
||||
set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10]
|
||||
set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10
|
||||
set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11]
|
||||
set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11
|
||||
set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12]
|
||||
set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12
|
||||
set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13]
|
||||
set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13
|
||||
set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14]
|
||||
set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14
|
||||
set_location_assignment PIN_A27 -to HPS_DDR3_BA[0]
|
||||
set_location_assignment PIN_A27 -to HPS_DDR3_BA_0
|
||||
set_location_assignment PIN_H25 -to HPS_DDR3_BA[1]
|
||||
set_location_assignment PIN_H25 -to HPS_DDR3_BA_1
|
||||
set_location_assignment PIN_G25 -to HPS_DDR3_BA[2]
|
||||
set_location_assignment PIN_G25 -to HPS_DDR3_BA_2
|
||||
set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N
|
||||
set_location_assignment PIN_L28 -to HPS_DDR3_CKE
|
||||
set_location_assignment PIN_N20 -to HPS_DDR3_CK_N
|
||||
set_location_assignment PIN_N21 -to HPS_DDR3_CK_P
|
||||
set_location_assignment PIN_L21 -to HPS_DDR3_CS_N
|
||||
set_location_assignment PIN_G28 -to HPS_DDR3_DM[0]
|
||||
set_location_assignment PIN_G28 -to HPS_DDR3_DM_0
|
||||
set_location_assignment PIN_P28 -to HPS_DDR3_DM[1]
|
||||
set_location_assignment PIN_P28 -to HPS_DDR3_DM_1
|
||||
set_location_assignment PIN_W28 -to HPS_DDR3_DM[2]
|
||||
set_location_assignment PIN_W28 -to HPS_DDR3_DM_2
|
||||
set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3]
|
||||
set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3
|
||||
set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0]
|
||||
set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0
|
||||
set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1]
|
||||
set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1
|
||||
set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2]
|
||||
set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2
|
||||
set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3]
|
||||
set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3
|
||||
set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4]
|
||||
set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4
|
||||
set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5]
|
||||
set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5
|
||||
set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6]
|
||||
set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6
|
||||
set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7]
|
||||
set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7
|
||||
set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8]
|
||||
set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8
|
||||
set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9]
|
||||
set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9
|
||||
set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10]
|
||||
set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10
|
||||
set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11]
|
||||
set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11
|
||||
set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12]
|
||||
set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12
|
||||
set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13]
|
||||
set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13
|
||||
set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14]
|
||||
set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14
|
||||
set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15]
|
||||
set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15
|
||||
set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16]
|
||||
set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16
|
||||
set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17]
|
||||
set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17
|
||||
set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18]
|
||||
set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18
|
||||
set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19]
|
||||
set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19
|
||||
set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20]
|
||||
set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20
|
||||
set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21]
|
||||
set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21
|
||||
set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22]
|
||||
set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22
|
||||
set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23]
|
||||
set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23
|
||||
set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24]
|
||||
set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24
|
||||
set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25]
|
||||
set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25
|
||||
set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26]
|
||||
set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26
|
||||
set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27]
|
||||
set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27
|
||||
set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28]
|
||||
set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28
|
||||
set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29]
|
||||
set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29
|
||||
set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30]
|
||||
set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30
|
||||
set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31]
|
||||
set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31
|
||||
set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0]
|
||||
set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0
|
||||
set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1]
|
||||
set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1
|
||||
set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2]
|
||||
set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2
|
||||
set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3]
|
||||
set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3
|
||||
set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0]
|
||||
set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0
|
||||
set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1]
|
||||
set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1
|
||||
set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2]
|
||||
set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2
|
||||
set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3]
|
||||
set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3
|
||||
set_location_assignment PIN_D28 -to HPS_DDR3_ODT
|
||||
set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N
|
||||
set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N
|
||||
set_location_assignment PIN_D25 -to HPS_DDR3_RZQ
|
||||
set_location_assignment PIN_E25 -to HPS_DDR3_WE_N
|
||||
set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK
|
||||
set_location_assignment PIN_B14 -to HPS_ENET_INT_N
|
||||
set_location_assignment PIN_A13 -to HPS_ENET_MDC
|
||||
set_location_assignment PIN_E16 -to HPS_ENET_MDIO
|
||||
set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK
|
||||
set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0]
|
||||
set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0
|
||||
set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1]
|
||||
set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1
|
||||
set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2]
|
||||
set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2
|
||||
set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3]
|
||||
set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3
|
||||
set_location_assignment PIN_J13 -to HPS_ENET_RX_DV
|
||||
set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0]
|
||||
set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0
|
||||
set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1]
|
||||
set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1
|
||||
set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2]
|
||||
set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2
|
||||
set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3]
|
||||
set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3
|
||||
set_location_assignment PIN_A12 -to HPS_ENET_TX_EN
|
||||
set_location_assignment PIN_A17 -to HPS_GSENSOR_INT
|
||||
set_location_assignment PIN_C18 -to HPS_I2C0_SCLK
|
||||
set_location_assignment PIN_A19 -to HPS_I2C0_SDAT
|
||||
set_location_assignment PIN_K18 -to HPS_I2C1_SCLK
|
||||
set_location_assignment PIN_A21 -to HPS_I2C1_SDAT
|
||||
set_location_assignment PIN_J18 -to HPS_KEY_N
|
||||
set_location_assignment PIN_A20 -to HPS_LED
|
||||
set_location_assignment PIN_H13 -to HPS_LTC_GPIO
|
||||
set_location_assignment PIN_B8 -to HPS_SD_CLK
|
||||
set_location_assignment PIN_D14 -to HPS_SD_CMD
|
||||
set_location_assignment PIN_C13 -to HPS_SD_DATA[0]
|
||||
set_location_assignment PIN_C13 -to HPS_SD_DATA_0
|
||||
set_location_assignment PIN_B6 -to HPS_SD_DATA[1]
|
||||
set_location_assignment PIN_B6 -to HPS_SD_DATA_1
|
||||
set_location_assignment PIN_B11 -to HPS_SD_DATA[2]
|
||||
set_location_assignment PIN_B11 -to HPS_SD_DATA_2
|
||||
set_location_assignment PIN_B9 -to HPS_SD_DATA[3]
|
||||
set_location_assignment PIN_B9 -to HPS_SD_DATA_3
|
||||
set_location_assignment PIN_C19 -to HPS_SPIM_CLK
|
||||
set_location_assignment PIN_B19 -to HPS_SPIM_MISO
|
||||
set_location_assignment PIN_B16 -to HPS_SPIM_MOSI
|
||||
set_location_assignment PIN_C16 -to HPS_SPIM_SS
|
||||
set_location_assignment PIN_A22 -to HPS_UART_RX
|
||||
set_location_assignment PIN_B21 -to HPS_UART_TX
|
||||
set_location_assignment PIN_G4 -to HPS_USB_CLKOUT
|
||||
set_location_assignment PIN_C10 -to HPS_USB_DATA[0]
|
||||
set_location_assignment PIN_C10 -to HPS_USB_DATA_0
|
||||
set_location_assignment PIN_F5 -to HPS_USB_DATA[1]
|
||||
set_location_assignment PIN_F5 -to HPS_USB_DATA_1
|
||||
set_location_assignment PIN_C9 -to HPS_USB_DATA[2]
|
||||
set_location_assignment PIN_C9 -to HPS_USB_DATA_2
|
||||
set_location_assignment PIN_C4 -to HPS_USB_DATA[3]
|
||||
set_location_assignment PIN_C4 -to HPS_USB_DATA_3
|
||||
set_location_assignment PIN_C8 -to HPS_USB_DATA[4]
|
||||
set_location_assignment PIN_C8 -to HPS_USB_DATA_4
|
||||
set_location_assignment PIN_D4 -to HPS_USB_DATA[5]
|
||||
set_location_assignment PIN_D4 -to HPS_USB_DATA_5
|
||||
set_location_assignment PIN_C7 -to HPS_USB_DATA[6]
|
||||
set_location_assignment PIN_C7 -to HPS_USB_DATA_6
|
||||
set_location_assignment PIN_F4 -to HPS_USB_DATA[7]
|
||||
set_location_assignment PIN_F4 -to HPS_USB_DATA_7
|
||||
set_location_assignment PIN_E5 -to HPS_USB_DIR
|
||||
set_location_assignment PIN_D5 -to HPS_USB_NXT
|
||||
set_location_assignment PIN_C5 -to HPS_USB_STP
|
||||
set_location_assignment PIN_AH17 -to KEY_N[0]
|
||||
set_location_assignment PIN_AH17 -to KEY_N_0
|
||||
set_location_assignment PIN_AH16 -to KEY_N[1]
|
||||
set_location_assignment PIN_AH16 -to KEY_N_1
|
||||
set_location_assignment PIN_W15 -to LED[0]
|
||||
set_location_assignment PIN_W15 -to LED_0
|
||||
set_location_assignment PIN_AA24 -to LED[1]
|
||||
set_location_assignment PIN_AA24 -to LED_1
|
||||
set_location_assignment PIN_V16 -to LED[2]
|
||||
set_location_assignment PIN_V16 -to LED_2
|
||||
set_location_assignment PIN_V15 -to LED[3]
|
||||
set_location_assignment PIN_V15 -to LED_3
|
||||
set_location_assignment PIN_AF26 -to LED[4]
|
||||
set_location_assignment PIN_AF26 -to LED_4
|
||||
set_location_assignment PIN_AE26 -to LED[5]
|
||||
set_location_assignment PIN_AE26 -to LED_5
|
||||
set_location_assignment PIN_Y16 -to LED[6]
|
||||
set_location_assignment PIN_Y16 -to LED_6
|
||||
set_location_assignment PIN_AA23 -to LED[7]
|
||||
set_location_assignment PIN_AA23 -to LED_7
|
||||
set_location_assignment PIN_L10 -to SW[0]
|
||||
set_location_assignment PIN_L10 -to SW_0
|
||||
set_location_assignment PIN_L9 -to SW[1]
|
||||
set_location_assignment PIN_L9 -to SW_1
|
||||
set_location_assignment PIN_H6 -to SW[2]
|
||||
set_location_assignment PIN_H6 -to SW_2
|
||||
set_location_assignment PIN_H5 -to SW[3]
|
||||
set_location_assignment PIN_H5 -to SW_3
|
||||
set_location_assignment PIN_V12 -to GPIO_0[0]
|
||||
set_location_assignment PIN_V12 -to GPIO_0_0
|
||||
set_location_assignment PIN_AF7 -to GPIO_0[1]
|
||||
set_location_assignment PIN_AF7 -to GPIO_0_1
|
||||
set_location_assignment PIN_W12 -to GPIO_0[2]
|
||||
set_location_assignment PIN_W12 -to GPIO_0_2
|
||||
set_location_assignment PIN_AF8 -to GPIO_0[3]
|
||||
set_location_assignment PIN_AF8 -to GPIO_0_3
|
||||
set_location_assignment PIN_Y8 -to GPIO_0[4]
|
||||
set_location_assignment PIN_Y8 -to GPIO_0_4
|
||||
set_location_assignment PIN_AB4 -to GPIO_0[5]
|
||||
set_location_assignment PIN_AB4 -to GPIO_0_5
|
||||
set_location_assignment PIN_W8 -to GPIO_0[6]
|
||||
set_location_assignment PIN_W8 -to GPIO_0_6
|
||||
set_location_assignment PIN_Y4 -to GPIO_0[7]
|
||||
set_location_assignment PIN_Y4 -to GPIO_0_7
|
||||
set_location_assignment PIN_Y5 -to GPIO_0[8]
|
||||
set_location_assignment PIN_Y5 -to GPIO_0_8
|
||||
set_location_assignment PIN_U11 -to GPIO_0[9]
|
||||
set_location_assignment PIN_U11 -to GPIO_0_9
|
||||
set_location_assignment PIN_T8 -to GPIO_0[10]
|
||||
set_location_assignment PIN_T8 -to GPIO_0_10
|
||||
set_location_assignment PIN_T12 -to GPIO_0[11]
|
||||
set_location_assignment PIN_T12 -to GPIO_0_11
|
||||
set_location_assignment PIN_AH5 -to GPIO_0[12]
|
||||
set_location_assignment PIN_AH5 -to GPIO_0_12
|
||||
set_location_assignment PIN_AH6 -to GPIO_0[13]
|
||||
set_location_assignment PIN_AH6 -to GPIO_0_13
|
||||
set_location_assignment PIN_AH4 -to GPIO_0[14]
|
||||
set_location_assignment PIN_AH4 -to GPIO_0_14
|
||||
set_location_assignment PIN_AG5 -to GPIO_0[15]
|
||||
set_location_assignment PIN_AG5 -to GPIO_0_15
|
||||
set_location_assignment PIN_AH3 -to GPIO_0[16]
|
||||
set_location_assignment PIN_AH3 -to GPIO_0_16
|
||||
set_location_assignment PIN_AH2 -to GPIO_0[17]
|
||||
set_location_assignment PIN_AH2 -to GPIO_0_17
|
||||
set_location_assignment PIN_AF4 -to GPIO_0[18]
|
||||
set_location_assignment PIN_AF4 -to GPIO_0_18
|
||||
set_location_assignment PIN_AG6 -to GPIO_0[19]
|
||||
set_location_assignment PIN_AG6 -to GPIO_0_19
|
||||
set_location_assignment PIN_AF5 -to GPIO_0[20]
|
||||
set_location_assignment PIN_AF5 -to GPIO_0_20
|
||||
set_location_assignment PIN_AE4 -to GPIO_0[21]
|
||||
set_location_assignment PIN_AE4 -to GPIO_0_21
|
||||
set_location_assignment PIN_T13 -to GPIO_0[22]
|
||||
set_location_assignment PIN_T13 -to GPIO_0_22
|
||||
set_location_assignment PIN_T11 -to GPIO_0[23]
|
||||
set_location_assignment PIN_T11 -to GPIO_0_23
|
||||
set_location_assignment PIN_AE7 -to GPIO_0[24]
|
||||
set_location_assignment PIN_AE7 -to GPIO_0_24
|
||||
set_location_assignment PIN_AF6 -to GPIO_0[25]
|
||||
set_location_assignment PIN_AF6 -to GPIO_0_25
|
||||
set_location_assignment PIN_AF9 -to GPIO_0[26]
|
||||
set_location_assignment PIN_AF9 -to GPIO_0_26
|
||||
set_location_assignment PIN_AE8 -to GPIO_0[27]
|
||||
set_location_assignment PIN_AE8 -to GPIO_0_27
|
||||
set_location_assignment PIN_AD10 -to GPIO_0[28]
|
||||
set_location_assignment PIN_AD10 -to GPIO_0_28
|
||||
set_location_assignment PIN_AE9 -to GPIO_0[29]
|
||||
set_location_assignment PIN_AE9 -to GPIO_0_29
|
||||
set_location_assignment PIN_AD11 -to GPIO_0[30]
|
||||
set_location_assignment PIN_AD11 -to GPIO_0_30
|
||||
set_location_assignment PIN_AF10 -to GPIO_0[31]
|
||||
set_location_assignment PIN_AF10 -to GPIO_0_31
|
||||
set_location_assignment PIN_AD12 -to GPIO_0[32]
|
||||
set_location_assignment PIN_AD12 -to GPIO_0_32
|
||||
set_location_assignment PIN_AE11 -to GPIO_0[33]
|
||||
set_location_assignment PIN_AE11 -to GPIO_0_33
|
||||
set_location_assignment PIN_AF11 -to GPIO_0[34]
|
||||
set_location_assignment PIN_AF11 -to GPIO_0_34
|
||||
set_location_assignment PIN_AE12 -to GPIO_0[35]
|
||||
set_location_assignment PIN_AE12 -to GPIO_0_35
|
||||
set_location_assignment PIN_Y15 -to GPIO_1[0]
|
||||
set_location_assignment PIN_Y15 -to GPIO_1_0
|
||||
set_location_assignment PIN_AG28 -to GPIO_1[1]
|
||||
set_location_assignment PIN_AG28 -to GPIO_1_1
|
||||
set_location_assignment PIN_AA15 -to GPIO_1[2]
|
||||
set_location_assignment PIN_AA15 -to GPIO_1_2
|
||||
set_location_assignment PIN_AH27 -to GPIO_1[3]
|
||||
set_location_assignment PIN_AH27 -to GPIO_1_3
|
||||
set_location_assignment PIN_AG26 -to GPIO_1[4]
|
||||
set_location_assignment PIN_AG26 -to GPIO_1_4
|
||||
set_location_assignment PIN_AH24 -to GPIO_1[5]
|
||||
set_location_assignment PIN_AH24 -to GPIO_1_5
|
||||
set_location_assignment PIN_AF23 -to GPIO_1[6]
|
||||
set_location_assignment PIN_AF23 -to GPIO_1_6
|
||||
set_location_assignment PIN_AE22 -to GPIO_1[7]
|
||||
set_location_assignment PIN_AE22 -to GPIO_1_7
|
||||
set_location_assignment PIN_AF21 -to GPIO_1[8]
|
||||
set_location_assignment PIN_AF21 -to GPIO_1_8
|
||||
set_location_assignment PIN_AG20 -to GPIO_1[9]
|
||||
set_location_assignment PIN_AG20 -to GPIO_1_9
|
||||
set_location_assignment PIN_AG19 -to GPIO_1[10]
|
||||
set_location_assignment PIN_AG19 -to GPIO_1_10
|
||||
set_location_assignment PIN_AF20 -to GPIO_1[11]
|
||||
set_location_assignment PIN_AF20 -to GPIO_1_11
|
||||
set_location_assignment PIN_AC23 -to GPIO_1[12]
|
||||
set_location_assignment PIN_AC23 -to GPIO_1_12
|
||||
set_location_assignment PIN_AG18 -to GPIO_1[13]
|
||||
set_location_assignment PIN_AG18 -to GPIO_1_13
|
||||
set_location_assignment PIN_AH26 -to GPIO_1[14]
|
||||
set_location_assignment PIN_AH26 -to GPIO_1_14
|
||||
set_location_assignment PIN_AA19 -to GPIO_1[15]
|
||||
set_location_assignment PIN_AA19 -to GPIO_1_15
|
||||
set_location_assignment PIN_AG24 -to GPIO_1[16]
|
||||
set_location_assignment PIN_AG24 -to GPIO_1_16
|
||||
set_location_assignment PIN_AF25 -to GPIO_1[17]
|
||||
set_location_assignment PIN_AF25 -to GPIO_1_17
|
||||
set_location_assignment PIN_AH23 -to GPIO_1[18]
|
||||
set_location_assignment PIN_AH23 -to GPIO_1_18
|
||||
set_location_assignment PIN_AG23 -to GPIO_1[19]
|
||||
set_location_assignment PIN_AG23 -to GPIO_1_19
|
||||
set_location_assignment PIN_AE19 -to GPIO_1[20]
|
||||
set_location_assignment PIN_AE19 -to GPIO_1_20
|
||||
set_location_assignment PIN_AF18 -to GPIO_1[21]
|
||||
set_location_assignment PIN_AF18 -to GPIO_1_21
|
||||
set_location_assignment PIN_AD19 -to GPIO_1[22]
|
||||
set_location_assignment PIN_AD19 -to GPIO_1_22
|
||||
set_location_assignment PIN_AE20 -to GPIO_1[23]
|
||||
set_location_assignment PIN_AE20 -to GPIO_1_23
|
||||
set_location_assignment PIN_AE24 -to GPIO_1[24]
|
||||
set_location_assignment PIN_AE24 -to GPIO_1_24
|
||||
set_location_assignment PIN_AD20 -to GPIO_1[25]
|
||||
set_location_assignment PIN_AD20 -to GPIO_1_25
|
||||
set_location_assignment PIN_AF22 -to GPIO_1[26]
|
||||
set_location_assignment PIN_AF22 -to GPIO_1_26
|
||||
set_location_assignment PIN_AH22 -to GPIO_1[27]
|
||||
set_location_assignment PIN_AH22 -to GPIO_1_27
|
||||
set_location_assignment PIN_AH19 -to GPIO_1[28]
|
||||
set_location_assignment PIN_AH19 -to GPIO_1_28
|
||||
set_location_assignment PIN_AH21 -to GPIO_1[29]
|
||||
set_location_assignment PIN_AH21 -to GPIO_1_29
|
||||
set_location_assignment PIN_AG21 -to GPIO_1[30]
|
||||
set_location_assignment PIN_AG21 -to GPIO_1_30
|
||||
set_location_assignment PIN_AH18 -to GPIO_1[31]
|
||||
set_location_assignment PIN_AH18 -to GPIO_1_31
|
||||
set_location_assignment PIN_AD23 -to GPIO_1[32]
|
||||
set_location_assignment PIN_AD23 -to GPIO_1_32
|
||||
set_location_assignment PIN_AE23 -to GPIO_1[33]
|
||||
set_location_assignment PIN_AE23 -to GPIO_1_33
|
||||
set_location_assignment PIN_AA18 -to GPIO_1[34]
|
||||
set_location_assignment PIN_AA18 -to GPIO_1_34
|
||||
set_location_assignment PIN_AC22 -to GPIO_1[35]
|
||||
set_location_assignment PIN_AC22 -to GPIO_1_35
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_8
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_9
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_10
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_11
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_12
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_13
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_14
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_15
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_10
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_11
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_12
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_13
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_14
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_15
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_16
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_17
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_18
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_19
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_20
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_21
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_22
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_23
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_24
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_25
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_26
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_27
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_28
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_29
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_30
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_31
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_32
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_33
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_34
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_35
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_8
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_9
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_10
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_11
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_12
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_13
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_14
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_15
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_16
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_17
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_18
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_19
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_20
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_21
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_22
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_23
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_24
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_25
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_26
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_27
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_28
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_29
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_30
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_31
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_32
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_33
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_34
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_35
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_8
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_9
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3
|
||||
set_global_assignment -name SMART_RECOMPILE OFF
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name VHDL_FILE ../hdl/WS28XX/WSDriver.vhd
|
||||
set_global_assignment -name VHDL_FILE ../hdl/WS28XX/WS28XX.vhd
|
||||
set_global_assignment -name VHDL_FILE ../hdl/WS28XX/ClkGen.vhd
|
||||
set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_top_level.vhd
|
||||
set_global_assignment -name QSYS_FILE system.qsys
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -0,0 +1,490 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags=""
|
||||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element WS28XX_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "4";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element WS28XX_0.avalon_slave_0
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "266240";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element clk_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element jtag_uart_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "3";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element jtag_uart_0.avalon_jtag_slave
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "266248";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element nios2_gen2_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "1";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element nios2_gen2_0.debug_mem_slave
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "264192";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element onchip_memory2_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "2";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element onchip_memory2_0.s1
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "131072";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<parameter name="device" value="5CSEMA4U23C6" />
|
||||
<parameter name="deviceFamily" value="Cyclone V" />
|
||||
<parameter name="deviceSpeedGrade" value="6" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="false" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="1" />
|
||||
<parameter name="projectName" value="lab2.qpf" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
|
||||
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
|
||||
<interface
|
||||
name="ws28xx_0_conduit_end"
|
||||
internal="WS28XX_0.conduit_end"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="ws28xx_0_ws_out_source" internal="WS28XX_0.ws_out_source" />
|
||||
<module name="WS28XX_0" kind="WS28XX" version="1.0" enabled="1" />
|
||||
<module name="clk_0" kind="clock_source" version="18.1" enabled="1">
|
||||
<parameter name="clockFrequency" value="50000000" />
|
||||
<parameter name="clockFrequencyKnown" value="true" />
|
||||
<parameter name="inputClockFrequency" value="0" />
|
||||
<parameter name="resetSynchronousEdges" value="NONE" />
|
||||
</module>
|
||||
<module
|
||||
name="jtag_uart_0"
|
||||
kind="altera_avalon_jtag_uart"
|
||||
version="18.1"
|
||||
enabled="1">
|
||||
<parameter name="allowMultipleConnections" value="false" />
|
||||
<parameter name="avalonSpec" value="2.0" />
|
||||
<parameter name="clkFreq" value="50000000" />
|
||||
<parameter name="hubInstanceID" value="0" />
|
||||
<parameter name="readBufferDepth" value="64" />
|
||||
<parameter name="readIRQThreshold" value="8" />
|
||||
<parameter name="simInputCharacterStream" value="" />
|
||||
<parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
|
||||
<parameter name="useRegistersForReadBuffer" value="false" />
|
||||
<parameter name="useRegistersForWriteBuffer" value="false" />
|
||||
<parameter name="useRelativePathForSimFile" value="false" />
|
||||
<parameter name="writeBufferDepth" value="64" />
|
||||
<parameter name="writeIRQThreshold" value="8" />
|
||||
</module>
|
||||
<module
|
||||
name="nios2_gen2_0"
|
||||
kind="altera_nios2_gen2"
|
||||
version="18.1"
|
||||
enabled="1">
|
||||
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
|
||||
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
|
||||
<parameter name="AUTO_DEVICE" value="5CSEMA4U23C6" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
|
||||
<parameter name="bht_ramBlockType" value="Automatic" />
|
||||
<parameter name="breakOffset" value="32" />
|
||||
<parameter name="breakSlave" value="None" />
|
||||
<parameter name="cdx_enabled" value="false" />
|
||||
<parameter name="clockFrequency" value="50000000" />
|
||||
<parameter name="cpuArchRev" value="1" />
|
||||
<parameter name="cpuID" value="0" />
|
||||
<parameter name="cpuReset" value="false" />
|
||||
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
|
||||
<parameter name="customInstSlavesSystemInfo_nios_a" value="<info/>" />
|
||||
<parameter name="customInstSlavesSystemInfo_nios_b" value="<info/>" />
|
||||
<parameter name="customInstSlavesSystemInfo_nios_c" value="<info/>" />
|
||||
<parameter name="dataAddrWidth" value="19" />
|
||||
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
|
||||
<parameter name="dataMasterHighPerformanceMapParam" value="" />
|
||||
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x3F400' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2_0.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='WS28XX_0.avalon_slave_0' start='0x41000' end='0x41008' type='WS28XX.avalon_slave_0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x41008' end='0x41010' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
|
||||
<parameter name="data_master_high_performance_paddr_base" value="0" />
|
||||
<parameter name="data_master_high_performance_paddr_size" value="0" />
|
||||
<parameter name="data_master_paddr_base" value="0" />
|
||||
<parameter name="data_master_paddr_size" value="0" />
|
||||
<parameter name="dcache_bursts" value="false" />
|
||||
<parameter name="dcache_numTCDM" value="0" />
|
||||
<parameter name="dcache_ramBlockType" value="Automatic" />
|
||||
<parameter name="dcache_size" value="2048" />
|
||||
<parameter name="dcache_tagramBlockType" value="Automatic" />
|
||||
<parameter name="dcache_victim_buf_impl" value="ram" />
|
||||
<parameter name="debug_OCIOnchipTrace" value="_128" />
|
||||
<parameter name="debug_assignJtagInstanceID" value="false" />
|
||||
<parameter name="debug_datatrigger" value="0" />
|
||||
<parameter name="debug_debugReqSignals" value="false" />
|
||||
<parameter name="debug_enabled" value="true" />
|
||||
<parameter name="debug_hwbreakpoint" value="0" />
|
||||
<parameter name="debug_jtagInstanceID" value="0" />
|
||||
<parameter name="debug_traceStorage" value="onchip_trace" />
|
||||
<parameter name="debug_traceType" value="none" />
|
||||
<parameter name="debug_triggerArming" value="true" />
|
||||
<parameter name="deviceFamilyName" value="Cyclone V" />
|
||||
<parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DLine truncated
|
||||
<parameter name="dividerType" value="no_div" />
|
||||
<parameter name="exceptionOffset" value="32" />
|
||||
<parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
|
||||
<parameter name="faAddrWidth" value="1" />
|
||||
<parameter name="faSlaveMapParam" value="" />
|
||||
<parameter name="fa_cache_line" value="2" />
|
||||
<parameter name="fa_cache_linesize" value="0" />
|
||||
<parameter name="flash_instruction_master_paddr_base" value="0" />
|
||||
<parameter name="flash_instruction_master_paddr_size" value="0" />
|
||||
<parameter name="icache_burstType" value="None" />
|
||||
<parameter name="icache_numTCIM" value="0" />
|
||||
<parameter name="icache_ramBlockType" value="Automatic" />
|
||||
<parameter name="icache_size" value="4096" />
|
||||
<parameter name="icache_tagramBlockType" value="Automatic" />
|
||||
<parameter name="impl" value="Fast" />
|
||||
<parameter name="instAddrWidth" value="19" />
|
||||
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x3F400' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2_0.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
|
||||
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
|
||||
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
|
||||
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
|
||||
<parameter name="instruction_master_high_performance_paddr_size" value="0" />
|
||||
<parameter name="instruction_master_paddr_base" value="0" />
|
||||
<parameter name="instruction_master_paddr_size" value="0" />
|
||||
<parameter name="internalIrqMaskSystemInfo" value="1" />
|
||||
<parameter name="io_regionbase" value="0" />
|
||||
<parameter name="io_regionsize" value="0" />
|
||||
<parameter name="master_addr_map" value="false" />
|
||||
<parameter name="mmu_TLBMissExcOffset" value="0" />
|
||||
<parameter name="mmu_TLBMissExcSlave" value="None" />
|
||||
<parameter name="mmu_autoAssignTlbPtrSz" value="true" />
|
||||
<parameter name="mmu_enabled" value="false" />
|
||||
<parameter name="mmu_processIDNumBits" value="8" />
|
||||
<parameter name="mmu_ramBlockType" value="Automatic" />
|
||||
<parameter name="mmu_tlbNumWays" value="16" />
|
||||
<parameter name="mmu_tlbPtrSz" value="7" />
|
||||
<parameter name="mmu_udtlbNumEntries" value="6" />
|
||||
<parameter name="mmu_uitlbNumEntries" value="4" />
|
||||
<parameter name="mpu_enabled" value="false" />
|
||||
<parameter name="mpu_minDataRegionSize" value="12" />
|
||||
<parameter name="mpu_minInstRegionSize" value="12" />
|
||||
<parameter name="mpu_numOfDataRegion" value="8" />
|
||||
<parameter name="mpu_numOfInstRegion" value="8" />
|
||||
<parameter name="mpu_useLimit" value="false" />
|
||||
<parameter name="mpx_enabled" value="false" />
|
||||
<parameter name="mul_32_impl" value="2" />
|
||||
<parameter name="mul_64_impl" value="0" />
|
||||
<parameter name="mul_shift_choice" value="0" />
|
||||
<parameter name="ocimem_ramBlockType" value="Automatic" />
|
||||
<parameter name="ocimem_ramInit" value="false" />
|
||||
<parameter name="regfile_ramBlockType" value="Automatic" />
|
||||
<parameter name="register_file_por" value="false" />
|
||||
<parameter name="resetOffset" value="0" />
|
||||
<parameter name="resetSlave" value="onchip_memory2_0.s1" />
|
||||
<parameter name="resetrequest_enabled" value="true" />
|
||||
<parameter name="setting_HBreakTest" value="false" />
|
||||
<parameter name="setting_HDLSimCachesCleared" value="true" />
|
||||
<parameter name="setting_activateMonitors" value="true" />
|
||||
<parameter name="setting_activateTestEndChecker" value="false" />
|
||||
<parameter name="setting_activateTrace" value="false" />
|
||||
<parameter name="setting_allow_break_inst" value="false" />
|
||||
<parameter name="setting_alwaysEncrypt" value="true" />
|
||||
<parameter name="setting_asic_add_scan_mode_input" value="false" />
|
||||
<parameter name="setting_asic_enabled" value="false" />
|
||||
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
|
||||
<parameter name="setting_asic_third_party_synthesis" value="false" />
|
||||
<parameter name="setting_avalonDebugPortPresent" value="false" />
|
||||
<parameter name="setting_bhtPtrSz" value="8" />
|
||||
<parameter name="setting_bigEndian" value="false" />
|
||||
<parameter name="setting_branchpredictiontype" value="Dynamic" />
|
||||
<parameter name="setting_breakslaveoveride" value="false" />
|
||||
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
|
||||
<parameter name="setting_dc_ecc_present" value="true" />
|
||||
<parameter name="setting_disable_tmr_inj" value="false" />
|
||||
<parameter name="setting_disableocitrace" value="false" />
|
||||
<parameter name="setting_dtcm_ecc_present" value="true" />
|
||||
<parameter name="setting_ecc_present" value="false" />
|
||||
<parameter name="setting_ecc_sim_test_ports" value="false" />
|
||||
<parameter name="setting_exportHostDebugPort" value="false" />
|
||||
<parameter name="setting_exportPCB" value="false" />
|
||||
<parameter name="setting_export_large_RAMs" value="false" />
|
||||
<parameter name="setting_exportdebuginfo" value="false" />
|
||||
<parameter name="setting_exportvectors" value="false" />
|
||||
<parameter name="setting_fast_register_read" value="false" />
|
||||
<parameter name="setting_ic_ecc_present" value="true" />
|
||||
<parameter name="setting_interruptControllerType" value="Internal" />
|
||||
<parameter name="setting_itcm_ecc_present" value="true" />
|
||||
<parameter name="setting_mmu_ecc_present" value="true" />
|
||||
<parameter name="setting_oci_export_jtag_signals" value="false" />
|
||||
<parameter name="setting_oci_version" value="1" />
|
||||
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
|
||||
<parameter name="setting_removeRAMinit" value="false" />
|
||||
<parameter name="setting_rf_ecc_present" value="true" />
|
||||
<parameter name="setting_shadowRegisterSets" value="0" />
|
||||
<parameter name="setting_showInternalSettings" value="false" />
|
||||
<parameter name="setting_showUnpublishedSettings" value="false" />
|
||||
<parameter name="setting_support31bitdcachebypass" value="true" />
|
||||
<parameter name="setting_tmr_output_disable" value="false" />
|
||||
<parameter name="setting_usedesignware" value="false" />
|
||||
<parameter name="shift_rot_impl" value="1" />
|
||||
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
|
||||
<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
|
||||
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
|
||||
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
|
||||
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
|
||||
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
|
||||
<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
|
||||
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
|
||||
<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
|
||||
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
|
||||
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
|
||||
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
|
||||
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
|
||||
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
|
||||
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
|
||||
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
|
||||
<parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
|
||||
<parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
|
||||
<parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
|
||||
<parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
|
||||
<parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
|
||||
<parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
|
||||
<parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
|
||||
<parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
|
||||
<parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
|
||||
<parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
|
||||
<parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
|
||||
<parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
|
||||
<parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
|
||||
<parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
|
||||
<parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
|
||||
<parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
|
||||
<parameter name="tmr_enabled" value="false" />
|
||||
<parameter name="tracefilename" value="" />
|
||||
<parameter name="userDefinedSettings" value="" />
|
||||
</module>
|
||||
<module
|
||||
name="onchip_memory2_0"
|
||||
kind="altera_avalon_onchip_memory2"
|
||||
version="18.1"
|
||||
enabled="1">
|
||||
<parameter name="allowInSystemMemoryContentEditor" value="false" />
|
||||
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
|
||||
<parameter name="blockType" value="AUTO" />
|
||||
<parameter name="copyInitFile" value="false" />
|
||||
<parameter name="dataWidth" value="32" />
|
||||
<parameter name="dataWidth2" value="32" />
|
||||
<parameter name="deviceFamily" value="Cyclone V" />
|
||||
<parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPLine truncated
|
||||
<parameter name="dualPort" value="false" />
|
||||
<parameter name="ecc_enabled" value="false" />
|
||||
<parameter name="enPRInitMode" value="false" />
|
||||
<parameter name="enableDiffWidth" value="false" />
|
||||
<parameter name="initMemContent" value="true" />
|
||||
<parameter name="initializationFileName" value="onchip_mem.hex" />
|
||||
<parameter name="instanceID" value="NONE" />
|
||||
<parameter name="memorySize" value="128000" />
|
||||
<parameter name="readDuringWriteMode" value="DONT_CARE" />
|
||||
<parameter name="resetrequest_enabled" value="true" />
|
||||
<parameter name="simAllowMRAMContentsFile" value="false" />
|
||||
<parameter name="simMemInitOnlyFilename" value="0" />
|
||||
<parameter name="singleClockOperation" value="false" />
|
||||
<parameter name="slave1Latency" value="1" />
|
||||
<parameter name="slave2Latency" value="1" />
|
||||
<parameter name="useNonDefaultInitFile" value="false" />
|
||||
<parameter name="useShallowMemBlocks" value="false" />
|
||||
<parameter name="writable" value="true" />
|
||||
</module>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.data_master"
|
||||
end="jtag_uart_0.avalon_jtag_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00041008" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.data_master"
|
||||
end="WS28XX_0.avalon_slave_0">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00041000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.data_master"
|
||||
end="nios2_gen2_0.debug_mem_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00040800" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.data_master"
|
||||
end="onchip_memory2_0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00020000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.instruction_master"
|
||||
end="nios2_gen2_0.debug_mem_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00040800" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.instruction_master"
|
||||
end="onchip_memory2_0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00020000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection kind="clock" version="18.1" start="clk_0.clk" end="nios2_gen2_0.clk" />
|
||||
<connection kind="clock" version="18.1" start="clk_0.clk" end="jtag_uart_0.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="18.1"
|
||||
start="clk_0.clk"
|
||||
end="onchip_memory2_0.clk1" />
|
||||
<connection kind="clock" version="18.1" start="clk_0.clk" end="WS28XX_0.clock" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.irq"
|
||||
end="jtag_uart_0.irq">
|
||||
<parameter name="irqNumber" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="18.1"
|
||||
start="clk_0.clk_reset"
|
||||
end="nios2_gen2_0.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="18.1"
|
||||
start="clk_0.clk_reset"
|
||||
end="jtag_uart_0.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="18.1"
|
||||
start="clk_0.clk_reset"
|
||||
end="onchip_memory2_0.reset1" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="18.1"
|
||||
start="clk_0.clk_reset"
|
||||
end="WS28XX_0.reset_sink" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.debug_reset_request"
|
||||
end="nios2_gen2_0.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.debug_reset_request"
|
||||
end="jtag_uart_0.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.debug_reset_request"
|
||||
end="onchip_memory2_0.reset1" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="18.1"
|
||||
start="nios2_gen2_0.debug_reset_request"
|
||||
end="WS28XX_0.reset_sink" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||||
</system>
|
||||
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