Disabled external gits

cs309-psoc/.gitignore

@@ -0,0 +1,38 @@
+# Specify filepatterns you want git to ignore.
+
+*.o
+*/**/quartus/output_files/
+*/**/quartus/db/
+*/**/incremental_db/
+*/**/simulation/
+*/**/timing/
+*/**/testbench/
+*/**/*_sim/
+
+*/**/nios/*/HAL/
+*/**/nios/*/obj/HAL/
+*/**/synthesis
+*/**/lab_*_bsp/
+*/**/obj
+
+*_generation_script*
+*_inst.vhd
+*.bak
+*.cmp
+*.done
+*.eqn
+*.hex
+*.jdi
+*.mif
+*.pin
+*.pof
+*.ptf.*
+*.qar
+*.qarlog
+*.qws
+*.rpt
+*.smsg
+*.sopc_builder
+*.summary
+*~
+*sopc_*

cs309-psoc/README.md

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+

cs309-psoc/lab_1_0/sw/nios/application/app.c

@@ -0,0 +1,69 @@
+#include <stdlib.h>
+#include <io.h>
+#include <stdio.h>
+#include <inttypes.h>
+#include <stdbool.h>
+#include <unistd.h>
+
+#include "pantilt/pantilt.h"
+#include "system.h"
+
+#define SLEEP_DURATION_US (25000) //  25  ms
+#define PANTILT_STEP_US   (25)    //  25  us
+
+#define PANTILT_PWM_V_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_V_MIN_DUTY_CYCLE_US + PANTILT_PWM_V_MAX_DUTY_CYCLE_US) / 2)
+#define PANTILT_PWM_H_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_H_MIN_DUTY_CYCLE_US + PANTILT_PWM_H_MAX_DUTY_CYCLE_US) / 2)
+
+int main(void) {
+    // Hardware control structures
+    pantilt_dev pantilt = pantilt_inst((void *) PWM_0_BASE, (void *) PWM_1_BASE);
+
+    // Initialize hardware
+    pantilt_init(&pantilt);
+
+    // Center servos.
+    pantilt_configure_vertical(&pantilt, PANTILT_PWM_V_MIN_DUTY_CYCLE_US);
+    pantilt_configure_horizontal(&pantilt, PANTILT_PWM_H_MIN_DUTY_CYCLE_US);
+    pantilt_start_vertical(&pantilt);
+    pantilt_start_horizontal(&pantilt);
+
+    // Rotate servos in "square" motion
+    while (true) {
+        uint32_t v_duty_us = 0;
+        uint32_t h_duty_us = 0;
+
+        // bottom to top
+        v_duty_us = PANTILT_PWM_V_MIN_DUTY_CYCLE_US;
+        do {
+            pantilt_configure_vertical(&pantilt, v_duty_us);
+            v_duty_us += PANTILT_STEP_US;
+            usleep(SLEEP_DURATION_US);
+        } while (v_duty_us <= PANTILT_PWM_V_MAX_DUTY_CYCLE_US);
+
+        // left to right
+        h_duty_us = PANTILT_PWM_H_MIN_DUTY_CYCLE_US;
+        do {
+            pantilt_configure_horizontal(&pantilt, h_duty_us);
+            h_duty_us += PANTILT_STEP_US;
+            usleep(SLEEP_DURATION_US);
+        } while (h_duty_us <= PANTILT_PWM_H_MAX_DUTY_CYCLE_US);
+
+        // top to bottom
+        v_duty_us = PANTILT_PWM_V_MAX_DUTY_CYCLE_US;
+        do {
+            pantilt_configure_vertical(&pantilt, v_duty_us);
+            v_duty_us -= PANTILT_STEP_US;
+            usleep(SLEEP_DURATION_US);
+        } while (PANTILT_PWM_V_MIN_DUTY_CYCLE_US <= v_duty_us);
+
+        // left to right
+        h_duty_us = PANTILT_PWM_H_MAX_DUTY_CYCLE_US;
+        do {
+            pantilt_configure_horizontal(&pantilt, h_duty_us);
+            h_duty_us -= PANTILT_STEP_US;
+            usleep(SLEEP_DURATION_US);
+        } while (PANTILT_PWM_H_MIN_DUTY_CYCLE_US <= h_duty_us);
+    }
+
+    return EXIT_SUCCESS;
+}

cs309-psoc/lab_1_0/sw/nios/application/pantilt/pantilt.c

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+#include "pantilt.h"
+
+/**
+ * pantilt_inst
+ *
+ * Instantiate a pantilt device structure.
+ *
+ * @param pwm_v_base Base address of the vertical PWM component.
+ * @param pwm_h_base Base address of the horizontal PWM component.
+ */
+pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) {
+    pantilt_dev dev;
+    dev.pwm_v = pwm_inst(pwm_v_base);
+    dev.pwm_h = pwm_inst(pwm_h_base);
+
+    return dev;
+}
+
+/**
+ * pantilt_init
+ *
+ * Initializes the pantilt device.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_init(pantilt_dev *dev) {
+    pwm_init(&(dev->pwm_v));
+    pwm_init(&(dev->pwm_h));
+}
+
+/**
+ * pantilt_configure_vertical
+ *
+ * Configure the vertical PWM component.
+ *
+ * @param dev pantilt device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ */
+void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) {
+    // Need to compensate for inverted servo rotation.
+    duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US;
+
+    pwm_configure(&(dev->pwm_v),
+                  duty_cycle,
+                  PANTILT_PWM_PERIOD_US,
+                  PANTILT_PWM_CLOCK_FREQ_HZ);
+}
+
+/**
+ * pantilt_configure_horizontal
+ *
+ * Configure the horizontal PWM component.
+ *
+ * @param dev pantilt device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ */
+void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) {
+    // Need to compensate for inverted servo rotation.
+    duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US;
+
+    pwm_configure(&(dev->pwm_h),
+                  duty_cycle,
+                  PANTILT_PWM_PERIOD_US,
+                  PANTILT_PWM_CLOCK_FREQ_HZ);
+}
+
+/**
+ * pantilt_start_vertical
+ *
+ * Starts the vertical pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_start_vertical(pantilt_dev *dev) {
+    pwm_start(&(dev->pwm_v));
+}
+
+/**
+ * pantilt_start_horizontal
+ *
+ * Starts the horizontal pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_start_horizontal(pantilt_dev *dev) {
+    pwm_start(&(dev->pwm_h));
+}
+
+/**
+ * pantilt_stop_vertical
+ *
+ * Stops the vertical pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_stop_vertical(pantilt_dev *dev) {
+    pwm_stop(&(dev->pwm_v));
+}
+
+/**
+ * pantilt_stop_horizontal
+ *
+ * Stops the horizontal pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_stop_horizontal(pantilt_dev *dev) {
+    pwm_stop(&(dev->pwm_h));
+}

cs309-psoc/lab_1_0/sw/nios/application/pantilt/pantilt.h

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+#ifndef __PANTILT_H__
+#define __PANTILT_H__
+
+#include "pwm/pwm.h"
+
+/* joysticks device structure */
+typedef struct pantilt_dev {
+    pwm_dev pwm_v; /* Vertical PWM device handle */
+    pwm_dev pwm_h; /* Horizontal PWM device handle */
+} pantilt_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+
+#define PANTILT_PWM_CLOCK_FREQ_HZ       (50000000) // 50.00 MHz
+
+#define PANTILT_PWM_PERIOD_US           (25000)    // 25.00 ms
+
+/* Vertical servo */
+#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950)      //  0.95 ms
+#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150)     //  2.15 ms
+
+/* Horizontal servo */
+#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000)     //  1.00 ms
+#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000)     //  2.00 ms
+
+pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base);
+
+void pantilt_init(pantilt_dev *dev);
+
+void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle);
+void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle);
+void pantilt_start_vertical(pantilt_dev *dev);
+void pantilt_start_horizontal(pantilt_dev *dev);
+void pantilt_stop_vertical(pantilt_dev *dev);
+void pantilt_stop_horizontal(pantilt_dev *dev);
+
+#endif /* __PANTILT_H__ */

cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm.c

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+#include <io.h>
+
+#include "pwm.h"
+#include "pwm_regs.h"
+
+#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000))
+
+
+/**
+ * pwm_inst
+ *
+ * Instantiate a pwm device structure.
+ *
+ * @param base Base address of the component.
+ */
+pwm_dev pwm_inst(void *base) {
+    pwm_dev dev;
+
+    dev.base = base;
+
+    return dev;
+}
+
+/**
+ * pwm_init
+ *
+ * Initializes the pwm device. This function stops the controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_init(pwm_dev *dev) {
+    pwm_stop(dev);
+}
+
+/**
+ * pwm_configure
+ *
+ * Configure pwm component.
+ *
+ * @param dev pwm device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ * @param period pwm period in us.
+ * @param module_frequency frequency at which the component is clocked.
+ */
+void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) {
+
+	IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency));
+	IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency));
+}
+
+/**
+ * pwm_start
+ *
+ * Starts the pwm controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_start(pwm_dev *dev) {
+	IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK);
+}
+
+/**
+ * pwm_stop
+ *
+ * Stops the pwm controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_stop(pwm_dev *dev) {
+	IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK);
+}

cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm.h

@@ -0,0 +1,21 @@
+#ifndef __PWM_H__
+#define __PWM_H__
+
+#include <stdint.h>
+
+/* pwm device structure */
+typedef struct pwm_dev {
+    void *base; /* Base address of component */
+} pwm_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+pwm_dev pwm_inst(void *base);
+
+void pwm_init(pwm_dev *dev);
+void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency);
+void pwm_start(pwm_dev *dev);
+void pwm_stop(pwm_dev *dev);
+
+#endif /* __PWM_H__ */

cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm_regs.h

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+#ifndef __PWM_REGS_H__
+#define __PWM_REGS_H__
+
+#define PWM_PERIOD_OFST     (0 * 4) /* RW */
+#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */
+#define PWM_CTRL_OFST       (2 * 4) /* WO */
+
+#define PWM_CTRL_STOP_MASK  (0)
+#define PWM_CTRL_START_MASK (1)
+
+#endif /* __PWM_REGS_H__ */

cs309-psoc/lab_1_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd

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+-- #############################################################################
+-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
+--
+-- BOARD         : PrSoC extension board for DE0-Nano-SoC
+-- Author        : Florian Depraz based on Sahand Kashani-Akhavan work
+-- Revision      : 1.1
+-- Creation date : 06/02/2016
+--
+-- Syntax Rule : GROUP_NAME_N[bit]
+--
+-- GROUP : specify a particular interface (ex: SDR_)
+-- NAME  : signal name (ex: CONFIG, D, ...)
+-- bit   : signal index
+-- _N    : to specify an active-low signal
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity DE0_Nano_SoC_PrSoC_extn_board_top_level is
+    port(
+        -------------------------------
+        -- Comment ALL unused ports. --
+        -------------------------------
+
+        -- CLOCK
+        FPGA_CLK1_50 : in std_logic;
+     -- FPGA_CLK2_50 : in std_logic;
+     -- FPGA_CLK3_50 : in std_logic;
+
+        -- KEY on DE0 Nano SoC
+        KEY_N : in std_logic_vector(1 downto 0);
+
+        -- LEDs on DE0 Nano SoC
+     -- LED : out std_logic_vector(7 downto 0);
+
+        -- SWITCHES on DE0 Nano SoC
+     -- SW : in std_logic_vector(3 downto 0);
+
+        -- Servomotors pwm
+        SERVO_0 : out std_logic;
+        SERVO_1 : out std_logic
+
+        -- ADC Joysticks
+     -- J0_SPI_CS_n : out std_logic;
+     -- J0_SPI_MOSI : out std_logic;
+     -- J0_SPI_MISO : in  std_logic;
+     -- J0_SPI_CLK  : out std_logic;
+
+        -- Lepton
+     -- CAM_TH_SPI_CS_N : out std_logic;
+     -- CAM_TH_MISO     : in  std_logic;
+     -- CAM_TH_MOSI     : out std_logic;
+     -- CAM_TH_CLK      : out std_logic;
+
+        -- PCA9637
+     -- PIO_SCL   : inout std_logic;
+     -- PIO_SDA   : inout std_logic;
+     -- PIO_INT_N : in    std_logic;
+     -- RESET_N   : out   std_logic;
+
+        -- OV7670
+     -- CAM_D       : in  std_logic_vector(9 downto 0);
+     -- CAM_PIX_CLK : in  std_logic;
+     -- CAM_LV      : in  std_logic;
+     -- CAM_FV      : in  std_logic;
+     -- CAM_SYS_CLK : out std_logic;
+
+        -- VGA and LCD shared signals
+     -- VIDEO_CLK   : out std_logic;
+     -- VIDEO_VSYNC : out std_logic;
+     -- VIDEO_HSYNC : out std_logic;
+     -- VIDEO_B     : out std_logic_vector(7 downto 0);
+     -- VIDEO_G     : out std_logic_vector(7 downto 0);
+     -- VIDEO_R     : out std_logic_vector(7 downto 0);
+
+        -- LCD Specific signals
+     -- LCD_DE         : out   std_logic;
+     -- LCD_PIN_DAV_N  :       ? ?? std_logic;
+     -- LCD_DISPLAY_EN : out   std_logic;
+     -- SPI_MISO       : in    std_logic;
+     -- SPI_ENA_N      : out   std_logic;
+     -- SPI_CLK        : out   std_logic;
+     -- SPI_MOSI       : out   std_logic;
+     -- SPI_DAT        : inout std_logic;
+
+        -- I2C TOUCH SCREEN
+     -- TS_SCL : inout std_logic;
+     -- TS_SDA : inout std_logic;
+
+        -- BLUETOOTH (BLE)
+     -- BLT_TXD : in  std_logic;
+     -- BLT_RXD : out std_logic;
+
+        -- I2C For VGA, PAL and OV7670 cameras
+     -- CAM_PAL_VGA_SDA : inout std_logic;
+     -- CAM_PAL_VGA_SCL : inout std_logic;
+
+        -- ONE WIRE
+     -- BOARD_ID : inout std_logic;
+
+        -- PAL Camera
+     -- PAL_VD_VD   : in  std_logic_vector(7 downto 0);
+     -- PAL_VD_VSO  : in  std_logic;
+     -- PAL_VD_HSO  : in  std_logic;
+     -- PAL_VD_CLKO : in  std_logic;
+     -- PAL_PWDN    : out std_logic;
+
+        -- WIFI
+     -- FROM_ESP_TXD : in  std_logic;
+     -- TO_ESP_RXD   : out std_logic;
+
+        -- LED RGB
+     -- LED_BGR : out std_logic;
+
+        -- HPS
+     -- HPS_CONV_USB_N   : inout std_logic;
+     -- HPS_DDR3_ADDR    : out   std_logic_vector(14 downto 0);
+     -- HPS_DDR3_BA      : out   std_logic_vector(2 downto 0);
+     -- HPS_DDR3_CAS_N   : out   std_logic;
+     -- HPS_DDR3_CK_N    : out   std_logic;
+     -- HPS_DDR3_CK_P    : out   std_logic;
+     -- HPS_DDR3_CKE     : out   std_logic;
+     -- HPS_DDR3_CS_N    : out   std_logic;
+     -- HPS_DDR3_DM      : out   std_logic_vector(3 downto 0);
+     -- HPS_DDR3_DQ      : inout std_logic_vector(31 downto 0);
+     -- HPS_DDR3_DQS_N   : inout std_logic_vector(3 downto 0);
+     -- HPS_DDR3_DQS_P   : inout std_logic_vector(3 downto 0);
+     -- HPS_DDR3_ODT     : out   std_logic;
+     -- HPS_DDR3_RAS_N   : out   std_logic;
+     -- HPS_DDR3_RESET_N : out   std_logic;
+     -- HPS_DDR3_RZQ     : in    std_logic;
+     -- HPS_DDR3_WE_N    : out   std_logic;
+     -- HPS_ENET_GTX_CLK : out   std_logic;
+     -- HPS_ENET_INT_N   : inout std_logic;
+     -- HPS_ENET_MDC     : out   std_logic;
+     -- HPS_ENET_MDIO    : inout std_logic;
+     -- HPS_ENET_RX_CLK  : in    std_logic;
+     -- HPS_ENET_RX_DATA : in    std_logic_vector(3 downto 0);
+     -- HPS_ENET_RX_DV   : in    std_logic;
+     -- HPS_ENET_TX_DATA : out   std_logic_vector(3 downto 0);
+     -- HPS_ENET_TX_EN   : out   std_logic;
+     -- HPS_GSENSOR_INT  : inout std_logic;
+     -- HPS_I2C0_SCLK    : inout std_logic;
+     -- HPS_I2C0_SDAT    : inout std_logic;
+     -- HPS_I2C1_SCLK    : inout std_logic;
+     -- HPS_I2C1_SDAT    : inout std_logic;
+     -- HPS_KEY_N        : inout std_logic;
+     -- HPS_LED          : inout std_logic;
+     -- HPS_LTC_GPIO     : inout std_logic;
+     -- HPS_SD_CLK       : out   std_logic;
+     -- HPS_SD_CMD       : inout std_logic;
+     -- HPS_SD_DATA      : inout std_logic_vector(3 downto 0);
+     -- HPS_SPIM_CLK     : out   std_logic;
+     -- HPS_SPIM_MISO    : in    std_logic;
+     -- HPS_SPIM_MOSI    : out   std_logic;
+     -- HPS_SPIM_SS      : inout std_logic;
+     -- HPS_UART_RX      : in    std_logic;
+     -- HPS_UART_TX      : out   std_logic;
+     -- HPS_USB_CLKOUT   : in    std_logic;
+     -- HPS_USB_DATA     : inout std_logic_vector(7 downto 0);
+     -- HPS_USB_DIR      : in    std_logic;
+     -- HPS_USB_NXT      : in    std_logic;
+     -- HPS_USB_STP      : out   std_logic
+    );
+end entity DE0_Nano_SoC_PrSoC_extn_board_top_level;
+
+architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is
+    component soc_system is
+        port (
+            clk_clk               : in  std_logic := 'X';
+            reset_reset_n         : in  std_logic := 'X';
+            pwm_0_conduit_end_pwm : out std_logic;
+            pwm_1_conduit_end_pwm : out std_logic
+        );
+    end component soc_system;
+
+begin
+    soc_system_inst : component soc_system
+    port map (
+        clk_clk               => FPGA_CLK1_50,
+        reset_reset_n         => KEY_N(0),
+        pwm_0_conduit_end_pwm => SERVO_0,
+        pwm_1_conduit_end_pwm => SERVO_1
+    );
+
+end;

cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm.vhd

@@ -0,0 +1,134 @@
+-- #############################################################################
+-- pwm.vhd
+-- =======
+-- PWM memory-mapped Avalon slave interface.
+--
+-- Author        : Cedric Hoelzl (cedric.hoelzl@epfl.ch)
+-- Author        : Antoine Brunner (antoine.brunner@epfl.ch)
+-- Revision      : 0.0.1a_rc1
+-- Last modified : a few billion clock cycles in the past
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pwm_constants.all;
+
+entity pwm is
+    port(
+        -- Avalon Clock interface
+        clk : in std_logic;
+
+        -- Avalon Reset interface
+        reset : in std_logic;
+
+        -- Avalon-MM Slave interface
+        address   : in  std_logic_vector(1 downto 0);
+        read      : in  std_logic;
+        write     : in  std_logic;
+        readdata  : out std_logic_vector(31 downto 0);
+        writedata : in  std_logic_vector(31 downto 0);
+
+        -- Avalon Conduit interface
+        pwm_out : out std_logic
+    );
+end pwm;
+
+architecture rtl of pwm is
+
+    -- The period of the current and next PWM cycle
+    signal reg_next_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length);
+    signal reg_current_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length);
+
+    -- The duty cycle of the current and next PWM cycle
+    signal reg_next_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length);
+    signal reg_current_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length);
+
+    -- The status of the current and next PWM cycle
+    signal reg_prev_ctrl : std_logic := '0';
+    signal reg_current_ctrl : std_logic := '0';
+
+    -- The internal counter of the PWN
+    signal reg_counter : unsigned(writedata'range) := to_unsigned(0, writedata'length);
+
+begin
+
+--Avalon-MM slave write
+process(clk, reset)
+begin
+    if reset = '1' then
+        reg_next_period <= to_unsigned(DEFAULT_PERIOD, writedata'length);
+        reg_next_dutycycle <= to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length);
+        reg_current_ctrl <= '0';
+    elsif rising_edge(clk) then
+        if write = '1' then
+            case address is
+                when REG_PERIOD_OFST => 
+                    if unsigned(writedata) >= to_unsigned(2, writedata'length) then
+                        reg_next_period <= unsigned(writedata);
+                    end if;
+                when REG_DUTY_CYCLE_OFST => 
+                    if (unsigned(writedata) >= to_unsigned(1, writedata'length)) and
+                       (unsigned(writedata) <= reg_next_period) then
+                        reg_next_dutycycle <= unsigned(writedata);
+                    end if;
+                when REG_CTRL_OFST => 
+                    reg_current_ctrl <= writedata(0);
+                when others => null;
+            end case;
+        end if;
+    end if;
+end process;
+
+
+--Avalon-MM slave read
+process(clk, reset)
+begin
+    if rising_edge(clk) then
+        if read = '1' then
+            case address is
+                when REG_PERIOD_OFST => 
+                    readdata <= std_logic_vector(reg_current_period);
+                when REG_DUTY_CYCLE_OFST => 
+                    readdata <= std_logic_vector(reg_current_dutycycle);
+                when others =>
+                    readdata <= (others => '0');
+            end case;
+        end if;
+    end if;
+end process;
+
+-- Internal synchronous logic
+process(clk, reset)
+begin
+    if reset = '1' then
+        reg_counter <= to_unsigned(0, writedata'length);
+        reg_prev_ctrl <= '0';
+    elsif rising_edge(clk) then
+        if ((reg_prev_ctrl = '0') and (reg_current_ctrl = '1')) or
+           (reg_counter = reg_current_period - 1) then
+            reg_current_period <= reg_next_period;
+            reg_current_dutycycle <= reg_next_dutycycle;
+            reg_counter <= to_unsigned(0, writedata'length);
+        elsif (reg_current_ctrl = '1') then
+            reg_counter <= reg_counter + 1;
+        end if;
+        reg_prev_ctrl <= reg_current_ctrl;
+    end if;
+end process;
+
+-- Avalon Conduit interface
+process(clk, reset)
+begin
+    if rising_edge(clk) then
+        if (reg_counter < reg_current_dutycycle) and (reg_current_ctrl = '1') then
+            pwm_out <= '1';
+        else
+            pwm_out <= '0';
+        end if;
+    end if;
+end process;
+
+
+end architecture rtl;

cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm_constants.vhd

@@ -0,0 +1,61 @@
+-- #############################################################################
+-- pwm_constants.vhd
+-- =================
+-- This package contains constants used in the PWM design files.
+--
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 2
+-- Last modified : 2018-02-28
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package pwm_constants is
+    -- Register map
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | RegNo  | Name       | Access | Description                                                                  |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | 0      | PERIOD     | R/W    | Period in clock cycles [2 <= period <= (2**32) - 1].                         |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | This value can be read/written while the unit is in the middle of an ongoing |
+    -- |        |            |        | PWM pulse. To allow safe behaviour, one cannot modify the period of an       |
+    -- |        |            |        | ongoing pulse, so we adopt the following semantics for this register:        |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> WRITING a value in this register indicates the NEW period to apply to the |
+    -- |        |            |        |    next pulse.                                                               |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> READING a value from this register indicates the CURRENT period of the    |
+    -- |        |            |        |    ongoing pulse.                                                            |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | 1      | DUTY_CYCLE | R/W    | Duty cycle of the PWM [1 <= duty cycle <= period]                            |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | This value can be read/written while the unit is in the middle of an ongoing |
+    -- |        |            |        | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an   |
+    -- |        |            |        | ongoing pulse, so we adopt the following semantics for this register:        |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> WRITING a value in this register indicates the NEW duty cycle to apply to |
+    -- |        |            |        |    the next pulse.                                                           |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> READING a value from this register indicates the CURRENT duty cycle of    |
+    -- |        |            |        |    the ongoing pulse.                                                        |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | 2      | CTRL       | WO     | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.|
+    -- |        |            |        |    Writing 1 to this register starts the PWM.                                |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> Reading this register always returns 0.                                   |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    constant REG_PERIOD_OFST     : std_logic_vector(1 downto 0) := "00";
+    constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01";
+    constant REG_CTRL_OFST       : std_logic_vector(1 downto 0) := "10";
+
+    -- Default values of registers after reset (BEFORE writing START to the CTRL
+    -- register with a new configuration)
+    constant DEFAULT_PERIOD     : natural := 4;
+    constant DEFAULT_DUTY_CYCLE : natural := 2;
+end package pwm_constants;
+
+package body pwm_constants is
+
+end package body pwm_constants;

cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm_hw.tcl

@@ -0,0 +1,135 @@
+# TCL File Generated by Component Editor 16.0
+# Tue Feb 28 12:18:00 CET 2017
+# DO NOT MODIFY
+
+
+#
+# pwm "pwm" v1.0
+#  2017.02.28.12:18:00
+# Pan-tilt
+#
+
+#
+# request TCL package from ACDS 16.0
+#
+package require -exact qsys 16.0
+
+
+#
+# module pwm
+#
+set_module_property DESCRIPTION Pan-tilt
+set_module_property NAME pwm
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP Pan-tilt
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME pwm
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE
+add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point clock
+#
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+#
+# connection point reset
+#
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+#
+# connection point avalon_slave_0
+#
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 writedata writedata Input 32
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+
+
+#
+# connection point conduit_end
+#
+add_interface conduit_end conduit end
+set_interface_property conduit_end associatedClock clock
+set_interface_property conduit_end associatedReset ""
+set_interface_property conduit_end ENABLED true
+set_interface_property conduit_end EXPORT_OF ""
+set_interface_property conduit_end PORT_NAME_MAP ""
+set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end pwm_out pwm Output 1

cs309-psoc/lab_1_1/hw/hdl/pantilt/tb/tb_pwm.vhd

@@ -0,0 +1,205 @@
+-- #############################################################################
+-- tb_pwm.vhd
+-- ==========
+-- Testbench for PWM memory-mapped Avalon slave interface.
+--
+-- Modified by   : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 2
+-- Last modified : 2018-02-28
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pwm_constants.all;
+
+entity tb_pwm is
+end entity;
+
+architecture rtl of tb_pwm is
+
+    -- 50 MHz clock
+    constant CLK_PERIOD : time := 20 ns;
+
+    -- Signal used to end simulator when we finished submitting our test cases
+    signal sim_finished : boolean := false;
+
+    -- PWM PORTS
+    signal clk       : std_logic;
+    signal reset     : std_logic;
+    signal address   : std_logic_vector(1 downto 0);
+    signal read      : std_logic;
+    signal write     : std_logic;
+    signal readdata  : std_logic_vector(31 downto 0);
+    signal writedata : std_logic_vector(31 downto 0);
+    signal pwm_out   : std_logic;
+
+    -- Values of registers we are going to use to configure the PWM unit
+    constant CONFIG_PERIOD     : natural := 100;
+    constant CONFIG_DUTY_CYCLE : natural := 20;
+    constant CONFIG_CTRL_START : natural := 1;
+    constant CONFIG_CTRL_STOP  : natural := 0;
+
+begin
+
+    -- Instantiate DUT
+    dut : entity work.pwm
+    port map(
+        clk       => clk,
+        reset     => reset,
+        address   => address,
+        read      => read,
+        write     => write,
+        readdata  => readdata,
+        writedata => writedata,
+        pwm_out   => pwm_out
+    );
+
+    -- Generate clk signal
+    clk_generation : process
+    begin
+        if not sim_finished then
+            clk <= '1';
+            wait for CLK_PERIOD / 2;
+            clk <= '0';
+            wait for CLK_PERIOD / 2;
+        else
+            wait;
+        end if;
+    end process clk_generation;
+
+    -- Test PWM
+    simulation : process
+
+        procedure async_reset is
+        begin
+            wait until rising_edge(clk);
+            wait for CLK_PERIOD / 4;
+
+            reset <= '1';
+            wait for CLK_PERIOD / 2;
+
+            reset <= '0';
+            wait for CLK_PERIOD / 4;
+        end procedure async_reset;
+
+        procedure write_register(constant ofst : in std_logic_vector(1 downto 0);
+                                 constant val  : in natural) is
+        begin
+            wait until rising_edge(clk);
+
+            address   <= ofst;
+            write     <= '1';
+            writedata <= std_logic_vector(to_unsigned(val, writedata'length));
+            wait until rising_edge(clk);
+
+            address   <= (others => '0');
+            write     <= '0';
+            writedata <= (others => '0');
+            wait until rising_edge(clk);
+        end procedure write_register;
+
+        procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is
+        begin
+            wait until rising_edge(clk);
+
+            address <= ofst;
+            read    <= '1';
+            -- The read has a 1 cycle wait-state, so we need to keep the read
+            -- signal high for 2 clock cycles.
+            wait until rising_edge(clk);
+            wait until rising_edge(clk);
+
+            address <= (others => '0');
+            read    <= '0';
+            wait until rising_edge(clk);
+        end procedure read_register;
+
+        procedure read_register_check(constant ofst         : in std_logic_vector(1 downto 0);
+                                      constant expected_val : in natural) is
+        begin
+            read_register(ofst);
+
+            case ofst is
+                when REG_PERIOD_OFST =>
+                    assert to_integer(unsigned(readdata)) = expected_val
+                    report "Unexpected PERIOD: " &
+                    "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " &
+                    "PERIOD_expected = " & integer'image(expected_val)
+                    severity error;
+
+                when REG_DUTY_CYCLE_OFST =>
+                    assert to_integer(unsigned(readdata)) = expected_val
+                    report "Unexpected DUTY_CYCLE: " &
+                    "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " &
+                    "DUTY_CYCLE_expected = " & integer'image(expected_val)
+                    severity error;
+
+                when REG_CTRL_OFST =>
+                    assert to_integer(unsigned(readdata)) = expected_val
+                    report "Unexpected CTRL: " &
+                    "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " &
+                    "CTRL_expected = " & integer'image(expected_val)
+                    severity error;
+
+                when others =>
+                    null;
+            end case;
+        end procedure read_register_check;
+
+    begin
+
+        -- Default values
+        reset     <= '0';
+        address   <= (others => '0');
+        read      <= '0';
+        write     <= '0';
+        writedata <= (others => '0');
+        wait until rising_edge(clk);
+
+        -- Reset the circuit
+        async_reset;
+
+        -- Write desired configuration to PWM Avalon-MM slave.
+        write_register(REG_PERIOD_OFST, CONFIG_PERIOD);
+        write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
+
+        -- Read back configuration from PWM Avalon-MM slave. Note that we have
+        -- not started the PWM unit yet, so the new configuration must not be
+        -- read back at this point (as per the register map).
+        read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD);
+        read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE);
+        read_register_check(REG_CTRL_OFST, 0);
+
+        -- Start PWM
+        write_register(REG_CTRL_OFST, CONFIG_CTRL_START);
+
+        -- Wait until PWM pulses for the first time after we sent START.
+        wait until rising_edge(pwm_out);
+
+        -- Read back configuration from PWM Avalon-MM slave. Now that we have
+        -- started the PWM unit, we should be able to read back the
+        -- configuration we wrote (as per the register map).
+        read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD);
+        read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
+        read_register_check(REG_CTRL_OFST, 0);
+
+        -- Wait for 2 PWM periods to finish
+        wait for 2 * CLK_PERIOD * CONFIG_PERIOD;
+
+        -- Stop PWM.
+        write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP);
+
+        -- Wait for PWM period to finish
+        wait for 1 * CLK_PERIOD * CONFIG_PERIOD;
+
+        -- Instruct "clk_generation" process to halt execution.
+        sim_finished <= true;
+
+        -- Make this process wait indefinitely (it will never re-execute from
+        -- its beginning again).
+        wait;
+    end process simulation;
+end architecture rtl;
+

cs309-psoc/lab_1_1/hw/quartus/ip/components.ipx

@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<library>
+ <!--  date: 2017.02.28.12:24:56 -->
+ <!--  generated by: ip-make-ipx -->
+ <!--   -->
+ <!--     1 in ../../hdl/ -->
+ <!--   -->
+ <component
+   name="pwm"
+   file="../../hdl/pantilt/hdl/pwm_hw.tcl"
+   displayName="pwm"
+   version="1.0"
+   description="Pan-tilt"
+   tags="AUTHORSHIP= /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
+   categories="Pan-tilt"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+</library>

cs309-psoc/lab_1_1/hw/quartus/lab_1_1.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors.  Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+# Date created = 11:03:02  February 05, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "15.1"
+DATE = "11:03:02  February 05, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "lab_1_1"

cs309-psoc/lab_1_1/hw/quartus/lab_1_1.qsf

@@ -0,0 +1,812 @@
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+
+set_global_assignment -name SMART_RECOMPILE OFF
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+
+set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level
+
+set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
+set_global_assignment -name QSYS_FILE soc_system.qsys
+set_global_assignment -name SDC_FILE lab_1_1.sdc
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA4U23C6
+set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+#============================================================
+# ADC
+#============================================================
+set_location_assignment PIN_U9 -to ADC_CONVST
+set_location_assignment PIN_V10 -to ADC_SCK
+set_location_assignment PIN_AC4 -to ADC_SDI
+set_location_assignment PIN_AD4 -to ADC_SDO
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+#============================================================
+# ARDUINO Extention OV7670 CAMERA
+#============================================================
+set_location_assignment PIN_AE15 -to CAM_D[0]
+set_location_assignment PIN_AE15 -to CAM_D_0
+set_location_assignment PIN_AF17 -to CAM_D[1]
+set_location_assignment PIN_AF17 -to CAM_D_1
+set_location_assignment PIN_AH8 -to CAM_D[2]
+set_location_assignment PIN_AH8 -to CAM_D_2
+set_location_assignment PIN_AG8 -to CAM_D[3]
+set_location_assignment PIN_AG8 -to CAM_D_3
+set_location_assignment PIN_U13 -to CAM_D[4]
+set_location_assignment PIN_U13 -to CAM_D_4
+set_location_assignment PIN_U14 -to CAM_D[5]
+set_location_assignment PIN_U14 -to CAM_D_5
+set_location_assignment PIN_AG9 -to CAM_D[6]
+set_location_assignment PIN_AG9 -to CAM_D_6
+set_location_assignment PIN_AG10 -to CAM_D[7]
+set_location_assignment PIN_AG10 -to CAM_D_7
+set_location_assignment PIN_AF13 -to CAM_D[8]
+set_location_assignment PIN_AF13 -to CAM_D_8
+set_location_assignment PIN_AG13 -to CAM_D[9]
+set_location_assignment PIN_AG13 -to CAM_D_9
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9
+
+#============================================================
+# Arduino Extension LEPTON CAMERA THERMAL CAM_TH
+#============================================================
+set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N
+set_location_assignment PIN_AG16 -to CAM_TH_MOSI
+set_location_assignment PIN_AH11 -to CAM_TH_MISO
+set_location_assignment PIN_AH12 -to CAM_TH_CLK
+set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA
+set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL
+
+set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_V11 -to FPGA_CLK1_50
+set_location_assignment PIN_Y13 -to FPGA_CLK2_50
+set_location_assignment PIN_E11 -to FPGA_CLK3_50
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
+
+#============================================================
+# HPS
+#============================================================
+set_location_assignment PIN_C6 -to HPS_CONV_USB_N
+set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0]
+set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0
+set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1]
+set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1
+set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2]
+set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2
+set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3]
+set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3
+set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4]
+set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4
+set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5]
+set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5
+set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6]
+set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6
+set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7]
+set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7
+set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8]
+set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8
+set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9]
+set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9
+set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10]
+set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10
+set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11]
+set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11
+set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12]
+set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12
+set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13]
+set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13
+set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14]
+set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14
+set_location_assignment PIN_A27 -to HPS_DDR3_BA[0]
+set_location_assignment PIN_A27 -to HPS_DDR3_BA_0
+set_location_assignment PIN_H25 -to HPS_DDR3_BA[1]
+set_location_assignment PIN_H25 -to HPS_DDR3_BA_1
+set_location_assignment PIN_G25 -to HPS_DDR3_BA[2]
+set_location_assignment PIN_G25 -to HPS_DDR3_BA_2
+set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N
+set_location_assignment PIN_L28 -to HPS_DDR3_CKE
+set_location_assignment PIN_N20 -to HPS_DDR3_CK_N
+set_location_assignment PIN_N21 -to HPS_DDR3_CK_P
+set_location_assignment PIN_L21 -to HPS_DDR3_CS_N
+set_location_assignment PIN_G28 -to HPS_DDR3_DM[0]
+set_location_assignment PIN_G28 -to HPS_DDR3_DM_0
+set_location_assignment PIN_P28 -to HPS_DDR3_DM[1]
+set_location_assignment PIN_P28 -to HPS_DDR3_DM_1
+set_location_assignment PIN_W28 -to HPS_DDR3_DM[2]
+set_location_assignment PIN_W28 -to HPS_DDR3_DM_2
+set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3]
+set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3
+set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0]
+set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0
+set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1]
+set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1
+set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2]
+set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2
+set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3]
+set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3
+set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4]
+set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4
+set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5]
+set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5
+set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6]
+set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6
+set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7]
+set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7
+set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8]
+set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8
+set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9]
+set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9
+set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10]
+set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10
+set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11]
+set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11
+set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12]
+set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12
+set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13]
+set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13
+set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14]
+set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14
+set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15]
+set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15
+set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16]
+set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16
+set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17]
+set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17
+set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18]
+set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18
+set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19]
+set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19
+set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20]
+set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20
+set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21]
+set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21
+set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22]
+set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22
+set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23]
+set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23
+set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24]
+set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24
+set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25]
+set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25
+set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26]
+set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26
+set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27]
+set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27
+set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28]
+set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28
+set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29]
+set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29
+set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30]
+set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30
+set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31]
+set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31
+set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0]
+set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0
+set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1]
+set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1
+set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2]
+set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2
+set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3]
+set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3
+set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0]
+set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0
+set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1]
+set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1
+set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2]
+set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2
+set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3]
+set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3
+set_location_assignment PIN_D28 -to HPS_DDR3_ODT
+set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N
+set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N
+set_location_assignment PIN_D25 -to HPS_DDR3_RZQ
+set_location_assignment PIN_E25 -to HPS_DDR3_WE_N
+set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK
+set_location_assignment PIN_B14 -to HPS_ENET_INT_N
+set_location_assignment PIN_A13 -to HPS_ENET_MDC
+set_location_assignment PIN_E16 -to HPS_ENET_MDIO
+set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK
+set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0]
+set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0
+set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1]
+set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1
+set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2]
+set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2
+set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3]
+set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3
+set_location_assignment PIN_J13 -to HPS_ENET_RX_DV
+set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0]
+set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0
+set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1]
+set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1
+set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2]
+set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2
+set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3]
+set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3
+set_location_assignment PIN_A12 -to HPS_ENET_TX_EN
+set_location_assignment PIN_A17 -to HPS_GSENSOR_INT
+set_location_assignment PIN_C18 -to HPS_I2C0_SCLK
+set_location_assignment PIN_A19 -to HPS_I2C0_SDAT
+set_location_assignment PIN_K18 -to HPS_I2C1_SCLK
+set_location_assignment PIN_A21 -to HPS_I2C1_SDAT
+set_location_assignment PIN_J18 -to HPS_KEY_N
+set_location_assignment PIN_A20 -to HPS_LED
+set_location_assignment PIN_H13 -to HPS_LTC_GPIO
+set_location_assignment PIN_B8 -to HPS_SD_CLK
+set_location_assignment PIN_D14 -to HPS_SD_CMD
+set_location_assignment PIN_C13 -to HPS_SD_DATA[0]
+set_location_assignment PIN_C13 -to HPS_SD_DATA_0
+set_location_assignment PIN_B6 -to HPS_SD_DATA[1]
+set_location_assignment PIN_B6 -to HPS_SD_DATA_1
+set_location_assignment PIN_B11 -to HPS_SD_DATA[2]
+set_location_assignment PIN_B11 -to HPS_SD_DATA_2
+set_location_assignment PIN_B9 -to HPS_SD_DATA[3]
+set_location_assignment PIN_B9 -to HPS_SD_DATA_3
+set_location_assignment PIN_C19 -to HPS_SPIM_CLK
+set_location_assignment PIN_B19 -to HPS_SPIM_MISO
+set_location_assignment PIN_B16 -to HPS_SPIM_MOSI
+set_location_assignment PIN_C16 -to HPS_SPIM_SS
+set_location_assignment PIN_A22 -to HPS_UART_RX
+set_location_assignment PIN_B21 -to HPS_UART_TX
+set_location_assignment PIN_G4 -to HPS_USB_CLKOUT
+set_location_assignment PIN_C10 -to HPS_USB_DATA[0]
+set_location_assignment PIN_C10 -to HPS_USB_DATA_0
+set_location_assignment PIN_F5 -to HPS_USB_DATA[1]
+set_location_assignment PIN_F5 -to HPS_USB_DATA_1
+set_location_assignment PIN_C9 -to HPS_USB_DATA[2]
+set_location_assignment PIN_C9 -to HPS_USB_DATA_2
+set_location_assignment PIN_C4 -to HPS_USB_DATA[3]
+set_location_assignment PIN_C4 -to HPS_USB_DATA_3
+set_location_assignment PIN_C8 -to HPS_USB_DATA[4]
+set_location_assignment PIN_C8 -to HPS_USB_DATA_4
+set_location_assignment PIN_D4 -to HPS_USB_DATA[5]
+set_location_assignment PIN_D4 -to HPS_USB_DATA_5
+set_location_assignment PIN_C7 -to HPS_USB_DATA[6]
+set_location_assignment PIN_C7 -to HPS_USB_DATA_6
+set_location_assignment PIN_F4 -to HPS_USB_DATA[7]
+set_location_assignment PIN_F4 -to HPS_USB_DATA_7
+set_location_assignment PIN_E5 -to HPS_USB_DIR
+set_location_assignment PIN_D5 -to HPS_USB_NXT
+set_location_assignment PIN_C5 -to HPS_USB_STP
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
+
+#============================================================
+# KEY_N
+#============================================================
+set_location_assignment PIN_AH17 -to KEY_N[0]
+set_location_assignment PIN_AH17 -to KEY_N_0
+set_location_assignment PIN_AH16 -to KEY_N[1]
+set_location_assignment PIN_AH16 -to KEY_N_1
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1
+
+#============================================================
+# LED
+#============================================================
+set_location_assignment PIN_W15 -to LED[0]
+set_location_assignment PIN_W15 -to LED_0
+set_location_assignment PIN_AA24 -to LED[1]
+set_location_assignment PIN_AA24 -to LED_1
+set_location_assignment PIN_V16 -to LED[2]
+set_location_assignment PIN_V16 -to LED_2
+set_location_assignment PIN_V15 -to LED[3]
+set_location_assignment PIN_V15 -to LED_3
+set_location_assignment PIN_AF26 -to LED[4]
+set_location_assignment PIN_AF26 -to LED_4
+set_location_assignment PIN_AE26 -to LED[5]
+set_location_assignment PIN_AE26 -to LED_5
+set_location_assignment PIN_Y16 -to LED[6]
+set_location_assignment PIN_Y16 -to LED_6
+set_location_assignment PIN_AA23 -to LED[7]
+set_location_assignment PIN_AA23 -to LED_7
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_L10 -to SW[0]
+set_location_assignment PIN_L10 -to SW_0
+set_location_assignment PIN_L9 -to SW[1]
+set_location_assignment PIN_L9 -to SW_1
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H6 -to SW_2
+set_location_assignment PIN_H5 -to SW[3]
+set_location_assignment PIN_H5 -to SW_3
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3
+
+#============================================================
+# GPIO_0, GPIO_0 connect to GPIO Default
+#============================================================
+set_location_assignment PIN_V12 -to PIO_INT_N
+set_location_assignment PIN_AE11 -to PIO_SCL
+set_location_assignment PIN_AE12 -to PIO_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA
+
+set_location_assignment PIN_AF7 -to PIR_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT
+
+set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA
+set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL
+set_location_assignment PIN_T11 -to CAM_SYS_CLK
+set_location_assignment PIN_AG6 -to CAM_LV
+set_location_assignment PIN_AH2 -to CAM_PIX_CLK
+set_location_assignment PIN_AE4 -to CAM_FV
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV
+
+set_location_assignment PIN_Y8 -to PAL_VD_HSO
+set_location_assignment PIN_AB4 -to PAL_VD_VSO
+set_location_assignment PIN_AG5 -to PAL_VD_VD[0]
+set_location_assignment PIN_AG5 -to PAL_VD_VD_0
+set_location_assignment PIN_AH5 -to PAL_VD_VD[1]
+set_location_assignment PIN_AH5 -to PAL_VD_VD_1
+set_location_assignment PIN_AH6 -to PAL_VD_VD[2]
+set_location_assignment PIN_AH6 -to PAL_VD_VD_2
+set_location_assignment PIN_T8 -to PAL_VD_VD[3]
+set_location_assignment PIN_T8 -to PAL_VD_VD_3
+set_location_assignment PIN_T12 -to PAL_VD_VD[4]
+set_location_assignment PIN_T12 -to PAL_VD_VD_4
+set_location_assignment PIN_Y5 -to PAL_VD_VD[5]
+set_location_assignment PIN_Y5 -to PAL_VD_VD_5
+set_location_assignment PIN_Y4 -to PAL_VD_VD[6]
+set_location_assignment PIN_Y4 -to PAL_VD_VD_6
+set_location_assignment PIN_W8 -to PAL_VD_VD[7]
+set_location_assignment PIN_W8 -to PAL_VD_VD_7
+set_location_assignment PIN_AH4 -to PAL_VD_CLKO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO
+
+set_location_assignment PIN_AH3 -to SERVO_0
+set_location_assignment PIN_AF4 -to SERVO_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1
+
+set_location_assignment PIN_AD12 -to J0_SPI_CLK
+set_location_assignment PIN_AD11 -to J0_SPI_MISO
+set_location_assignment PIN_AF9 -to J0_SPI_CS_N
+set_location_assignment PIN_AD10 -to J0_SPI_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI
+
+set_location_assignment PIN_AF5 -to FROM_ESP_TXD
+set_location_assignment PIN_T13 -to TO_ESP_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD
+
+set_location_assignment PIN_AE7 -to SPI_MISO
+set_location_assignment PIN_AF6 -to SPI_ENA_N
+set_location_assignment PIN_AE8 -to SPI_CLK
+set_location_assignment PIN_AE9 -to SPI_MOSI
+set_location_assignment PIN_AF10 -to SPI_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT
+
+set_location_assignment PIN_AF11 -to LED_BGR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR
+
+#============================================================
+# GPIO_1, GPIO_1 connect to GPIO Default
+#============================================================
+set_location_assignment PIN_AA15 -to RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N
+
+set_location_assignment PIN_AG28 -to TS_SCL
+set_location_assignment PIN_AH27 -to TS_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA
+
+set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N
+set_location_assignment PIN_AG26 -to LCD_DE
+set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN
+
+set_location_assignment PIN_AH24 -to BLT_TXD
+set_location_assignment PIN_AE22 -to BLT_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD
+
+set_location_assignment PIN_AG20 -to BOARD_ID
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID
+
+set_location_assignment PIN_AF21 -to VIDEO_HSYNC
+set_location_assignment PIN_AG19 -to VIDEO_VSYNC
+set_location_assignment PIN_AF20 -to VIDEO_CLK
+set_location_assignment PIN_AG23 -to VIDEO_B[0]
+set_location_assignment PIN_AG23 -to VIDEO_B_0
+set_location_assignment PIN_AH23 -to VIDEO_B[1]
+set_location_assignment PIN_AH23 -to VIDEO_B_1
+set_location_assignment PIN_AF25 -to VIDEO_B[2]
+set_location_assignment PIN_AF25 -to VIDEO_B_2
+set_location_assignment PIN_AG24 -to VIDEO_B[3]
+set_location_assignment PIN_AG24 -to VIDEO_B_3
+set_location_assignment PIN_AA19 -to VIDEO_B[4]
+set_location_assignment PIN_AA19 -to VIDEO_B_4
+set_location_assignment PIN_AH26 -to VIDEO_B[5]
+set_location_assignment PIN_AH26 -to VIDEO_B_5
+set_location_assignment PIN_AG18 -to VIDEO_B[6]
+set_location_assignment PIN_AG18 -to VIDEO_B_6
+set_location_assignment PIN_AC23 -to VIDEO_B[7]
+set_location_assignment PIN_AC23 -to VIDEO_B_7
+set_location_assignment PIN_AH22 -to VIDEO_G[0]
+set_location_assignment PIN_AH22 -to VIDEO_G_0
+set_location_assignment PIN_AF22 -to VIDEO_G[1]
+set_location_assignment PIN_AF22 -to VIDEO_G_1
+set_location_assignment PIN_AD20 -to VIDEO_G[2]
+set_location_assignment PIN_AD20 -to VIDEO_G_2
+set_location_assignment PIN_AE24 -to VIDEO_G[3]
+set_location_assignment PIN_AE24 -to VIDEO_G_3
+set_location_assignment PIN_AE20 -to VIDEO_G[4]
+set_location_assignment PIN_AE20 -to VIDEO_G_4
+set_location_assignment PIN_AD19 -to VIDEO_G[5]
+set_location_assignment PIN_AD19 -to VIDEO_G_5
+set_location_assignment PIN_AF18 -to VIDEO_G[6]
+set_location_assignment PIN_AF18 -to VIDEO_G_6
+set_location_assignment PIN_AE19 -to VIDEO_G[7]
+set_location_assignment PIN_AE19 -to VIDEO_G_7
+set_location_assignment PIN_AC22 -to VIDEO_R[0]
+set_location_assignment PIN_AC22 -to VIDEO_R_0
+set_location_assignment PIN_AA18 -to VIDEO_R[1]
+set_location_assignment PIN_AA18 -to VIDEO_R_1
+set_location_assignment PIN_AE23 -to VIDEO_R[2]
+set_location_assignment PIN_AE23 -to VIDEO_R_2
+set_location_assignment PIN_AD23 -to VIDEO_R[3]
+set_location_assignment PIN_AD23 -to VIDEO_R_3
+set_location_assignment PIN_AH18 -to VIDEO_R[4]
+set_location_assignment PIN_AH18 -to VIDEO_R_4
+set_location_assignment PIN_AG21 -to VIDEO_R[5]
+set_location_assignment PIN_AG21 -to VIDEO_R_5
+set_location_assignment PIN_AH21 -to VIDEO_R[6]
+set_location_assignment PIN_AH21 -to VIDEO_R_6
+set_location_assignment PIN_AH19 -to VIDEO_R[7]
+set_location_assignment PIN_AH19 -to VIDEO_R_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7

cs309-psoc/lab_1_1/hw/quartus/lab_1_1.sdc

@@ -0,0 +1,6 @@
+create_clock -period 20 [get_ports FPGA_CLK1_50]
+create_clock -period 20 [get_ports FPGA_CLK2_50]
+create_clock -period 20 [get_ports FPGA_CLK3_50]
+
+derive_pll_clocks
+derive_clock_uncertainty

cs309-psoc/lab_1_1/sw/nios/application/app.c

@@ -0,0 +1,69 @@
+#include <stdlib.h>
+#include <io.h>
+#include <stdio.h>
+#include <inttypes.h>
+#include <stdbool.h>
+#include <unistd.h>
+
+#include "pantilt/pantilt.h"
+#include "system.h"
+
+#define SLEEP_DURATION_US (25000) //  25  ms
+#define PANTILT_STEP_US   (25)    //  25  us
+
+#define PANTILT_PWM_V_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_V_MIN_DUTY_CYCLE_US + PANTILT_PWM_V_MAX_DUTY_CYCLE_US) / 2)
+#define PANTILT_PWM_H_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_H_MIN_DUTY_CYCLE_US + PANTILT_PWM_H_MAX_DUTY_CYCLE_US) / 2)
+
+int main(void) {
+    // Hardware control structures
+    pantilt_dev pantilt = pantilt_inst((void *) PWM_0_BASE, (void *) PWM_1_BASE);
+
+    // Initialize hardware
+    pantilt_init(&pantilt);
+
+    // Center servos.
+    pantilt_configure_vertical(&pantilt, PANTILT_PWM_V_MIN_DUTY_CYCLE_US);
+    pantilt_configure_horizontal(&pantilt, PANTILT_PWM_H_MIN_DUTY_CYCLE_US);
+    pantilt_start_vertical(&pantilt);
+    pantilt_start_horizontal(&pantilt);
+
+    // Rotate servos in "square" motion
+    while (true) {
+        uint32_t v_duty_us = 0;
+        uint32_t h_duty_us = 0;
+
+        // bottom to top
+        v_duty_us = PANTILT_PWM_V_MIN_DUTY_CYCLE_US;
+        do {
+            pantilt_configure_vertical(&pantilt, v_duty_us);
+            v_duty_us += PANTILT_STEP_US;
+            usleep(SLEEP_DURATION_US);
+        } while (v_duty_us <= PANTILT_PWM_V_MAX_DUTY_CYCLE_US);
+
+        // left to right
+        h_duty_us = PANTILT_PWM_H_MIN_DUTY_CYCLE_US;
+        do {
+            pantilt_configure_horizontal(&pantilt, h_duty_us);
+            h_duty_us += PANTILT_STEP_US;
+            usleep(SLEEP_DURATION_US);
+        } while (h_duty_us <= PANTILT_PWM_H_MAX_DUTY_CYCLE_US);
+
+        // top to bottom
+        v_duty_us = PANTILT_PWM_V_MAX_DUTY_CYCLE_US;
+        do {
+            pantilt_configure_vertical(&pantilt, v_duty_us);
+            v_duty_us -= PANTILT_STEP_US;
+            usleep(SLEEP_DURATION_US);
+        } while (PANTILT_PWM_V_MIN_DUTY_CYCLE_US <= v_duty_us);
+
+        // left to right
+        h_duty_us = PANTILT_PWM_H_MAX_DUTY_CYCLE_US;
+        do {
+            pantilt_configure_horizontal(&pantilt, h_duty_us);
+            h_duty_us -= PANTILT_STEP_US;
+            usleep(SLEEP_DURATION_US);
+        } while (PANTILT_PWM_H_MIN_DUTY_CYCLE_US <= h_duty_us);
+    }
+
+    return EXIT_SUCCESS;
+}

cs309-psoc/lab_1_1/sw/nios/application/pantilt/pantilt.c

@@ -0,0 +1,109 @@
+#include "pantilt.h"
+
+/**
+ * pantilt_inst
+ *
+ * Instantiate a pantilt device structure.
+ *
+ * @param pwm_v_base Base address of the vertical PWM component.
+ * @param pwm_h_base Base address of the horizontal PWM component.
+ */
+pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) {
+    pantilt_dev dev;
+    dev.pwm_v = pwm_inst(pwm_v_base);
+    dev.pwm_h = pwm_inst(pwm_h_base);
+
+    return dev;
+}
+
+/**
+ * pantilt_init
+ *
+ * Initializes the pantilt device.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_init(pantilt_dev *dev) {
+    pwm_init(&(dev->pwm_v));
+    pwm_init(&(dev->pwm_h));
+}
+
+/**
+ * pantilt_configure_vertical
+ *
+ * Configure the vertical PWM component.
+ *
+ * @param dev pantilt device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ */
+void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) {
+    // Need to compensate for inverted servo rotation.
+    duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US;
+
+    pwm_configure(&(dev->pwm_v),
+                  duty_cycle,
+                  PANTILT_PWM_PERIOD_US,
+                  PANTILT_PWM_CLOCK_FREQ_HZ);
+}
+
+/**
+ * pantilt_configure_horizontal
+ *
+ * Configure the horizontal PWM component.
+ *
+ * @param dev pantilt device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ */
+void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) {
+    // Need to compensate for inverted servo rotation.
+    duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US;
+
+    pwm_configure(&(dev->pwm_h),
+                  duty_cycle,
+                  PANTILT_PWM_PERIOD_US,
+                  PANTILT_PWM_CLOCK_FREQ_HZ);
+}
+
+/**
+ * pantilt_start_vertical
+ *
+ * Starts the vertical pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_start_vertical(pantilt_dev *dev) {
+    pwm_start(&(dev->pwm_v));
+}
+
+/**
+ * pantilt_start_horizontal
+ *
+ * Starts the horizontal pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_start_horizontal(pantilt_dev *dev) {
+    pwm_start(&(dev->pwm_h));
+}
+
+/**
+ * pantilt_stop_vertical
+ *
+ * Stops the vertical pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_stop_vertical(pantilt_dev *dev) {
+    pwm_stop(&(dev->pwm_v));
+}
+
+/**
+ * pantilt_stop_horizontal
+ *
+ * Stops the horizontal pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_stop_horizontal(pantilt_dev *dev) {
+    pwm_stop(&(dev->pwm_h));
+}

cs309-psoc/lab_1_1/sw/nios/application/pantilt/pantilt.h

@@ -0,0 +1,39 @@
+#ifndef __PANTILT_H__
+#define __PANTILT_H__
+
+#include "pwm/pwm.h"
+
+/* joysticks device structure */
+typedef struct pantilt_dev {
+    pwm_dev pwm_v; /* Vertical PWM device handle */
+    pwm_dev pwm_h; /* Horizontal PWM device handle */
+} pantilt_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+
+#define PANTILT_PWM_CLOCK_FREQ_HZ       (50000000) // 50.00 MHz
+
+#define PANTILT_PWM_PERIOD_US           (25000)    // 25.00 ms
+
+/* Vertical servo */
+#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950)      //  0.95 ms
+#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150)     //  2.15 ms
+
+/* Horizontal servo */
+#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000)     //  1.00 ms
+#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000)     //  2.00 ms
+
+pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base);
+
+void pantilt_init(pantilt_dev *dev);
+
+void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle);
+void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle);
+void pantilt_start_vertical(pantilt_dev *dev);
+void pantilt_start_horizontal(pantilt_dev *dev);
+void pantilt_stop_vertical(pantilt_dev *dev);
+void pantilt_stop_horizontal(pantilt_dev *dev);
+
+#endif /* __PANTILT_H__ */

cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm.c

@@ -0,0 +1,71 @@
+#include <io.h>
+
+#include "pwm.h"
+#include "pwm_regs.h"
+
+#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000))
+
+
+/**
+ * pwm_inst
+ *
+ * Instantiate a pwm device structure.
+ *
+ * @param base Base address of the component.
+ */
+pwm_dev pwm_inst(void *base) {
+    pwm_dev dev;
+
+    dev.base = base;
+
+    return dev;
+}
+
+/**
+ * pwm_init
+ *
+ * Initializes the pwm device. This function stops the controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_init(pwm_dev *dev) {
+    pwm_stop(dev);
+}
+
+/**
+ * pwm_configure
+ *
+ * Configure pwm component.
+ *
+ * @param dev pwm device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ * @param period pwm period in us.
+ * @param module_frequency frequency at which the component is clocked.
+ */
+void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) {
+
+	IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency));
+	IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency));
+}
+
+/**
+ * pwm_start
+ *
+ * Starts the pwm controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_start(pwm_dev *dev) {
+	IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK);
+}
+
+/**
+ * pwm_stop
+ *
+ * Stops the pwm controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_stop(pwm_dev *dev) {
+	IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK);
+}

cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm.h

@@ -0,0 +1,21 @@
+#ifndef __PWM_H__
+#define __PWM_H__
+
+#include <stdint.h>
+
+/* pwm device structure */
+typedef struct pwm_dev {
+    void *base; /* Base address of component */
+} pwm_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+pwm_dev pwm_inst(void *base);
+
+void pwm_init(pwm_dev *dev);
+void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency);
+void pwm_start(pwm_dev *dev);
+void pwm_stop(pwm_dev *dev);
+
+#endif /* __PWM_H__ */

cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm_regs.h

@@ -0,0 +1,11 @@
+#ifndef __PWM_REGS_H__
+#define __PWM_REGS_H__
+
+#define PWM_PERIOD_OFST     (0 * 4) /* RW */
+#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */
+#define PWM_CTRL_OFST       (2 * 4) /* WO */
+
+#define PWM_CTRL_STOP_MASK  (0)
+#define PWM_CTRL_START_MASK (1)
+
+#endif /* __PWM_REGS_H__ */

cs309-psoc/lab_1_2/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd

@@ -0,0 +1,195 @@
+-- #############################################################################
+-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
+--
+-- BOARD         : PrSoC extension board for DE0-Nano-SoC
+-- Author        : Florian Depraz based on Sahand Kashani-Akhavan work
+-- Revision      : 1.1
+-- Creation date : 06/02/2016
+--
+-- Syntax Rule : GROUP_NAME_N[bit]
+--
+-- GROUP : specify a particular interface (ex: SDR_)
+-- NAME  : signal name (ex: CONFIG, D, ...)
+-- bit   : signal index
+-- _N    : to specify an active-low signal
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity DE0_Nano_SoC_PrSoC_extn_board_top_level is
+    port(
+        -------------------------------
+        -- Comment ALL unused ports. --
+        -------------------------------
+
+        -- CLOCK
+        FPGA_CLK1_50 : in std_logic;
+     -- FPGA_CLK2_50 : in std_logic;
+     -- FPGA_CLK3_50 : in std_logic;
+
+        -- KEY on DE0 Nano SoC
+        KEY_N : in std_logic_vector(1 downto 0);
+
+        -- LEDs on DE0 Nano SoC
+     -- LED : out std_logic_vector(7 downto 0);
+
+        -- SWITCHES on DE0 Nano SoC
+     -- SW : in std_logic_vector(3 downto 0);
+
+        -- Servomotors pwm
+        SERVO_0 : out std_logic;
+        SERVO_1 : out std_logic;
+
+        -- ADC Joysticks
+        J0_SPI_CS_n : out std_logic;
+        J0_SPI_MOSI : out std_logic;
+        J0_SPI_MISO : in  std_logic;
+        J0_SPI_CLK  : out std_logic
+
+        -- Lepton
+     -- CAM_TH_SPI_CS_N : out std_logic;
+     -- CAM_TH_MISO     : in  std_logic;
+     -- CAM_TH_MOSI     : out std_logic;
+     -- CAM_TH_CLK      : out std_logic;
+
+        -- PCA9637
+     -- PIO_SCL   : inout std_logic;
+     -- PIO_SDA   : inout std_logic;
+     -- PIO_INT_N : in    std_logic;
+     -- RESET_N   : out   std_logic;
+
+        -- OV7670
+     -- CAM_D       : in  std_logic_vector(9 downto 0);
+     -- CAM_PIX_CLK : in  std_logic;
+     -- CAM_LV      : in  std_logic;
+     -- CAM_FV      : in  std_logic;
+     -- CAM_SYS_CLK : out std_logic;
+
+        -- VGA and LCD shared signals
+     -- VIDEO_CLK   : out std_logic;
+     -- VIDEO_VSYNC : out std_logic;
+     -- VIDEO_HSYNC : out std_logic;
+     -- VIDEO_B     : out std_logic_vector(7 downto 0);
+     -- VIDEO_G     : out std_logic_vector(7 downto 0);
+     -- VIDEO_R     : out std_logic_vector(7 downto 0);
+
+        -- LCD Specific signals
+     -- LCD_DE         : out   std_logic;
+     -- LCD_PIN_DAV_N  :       ? ?? std_logic;
+     -- LCD_DISPLAY_EN : out   std_logic;
+     -- SPI_MISO       : in    std_logic;
+     -- SPI_ENA_N      : out   std_logic;
+     -- SPI_CLK        : out   std_logic;
+     -- SPI_MOSI       : out   std_logic;
+     -- SPI_DAT        : inout std_logic;
+
+        -- I2C TOUCH SCREEN
+     -- TS_SCL : inout std_logic;
+     -- TS_SDA : inout std_logic;
+
+        -- BLUETOOTH (BLE)
+     -- BLT_TXD : in  std_logic;
+     -- BLT_RXD : out std_logic;
+
+        -- I2C For VGA, PAL and OV7670 cameras
+     -- CAM_PAL_VGA_SDA : inout std_logic;
+     -- CAM_PAL_VGA_SCL : inout std_logic;
+
+        -- ONE WIRE
+     -- BOARD_ID : inout std_logic;
+
+        -- PAL Camera
+     -- PAL_VD_VD   : in  std_logic_vector(7 downto 0);
+     -- PAL_VD_VSO  : in  std_logic;
+     -- PAL_VD_HSO  : in  std_logic;
+     -- PAL_VD_CLKO : in  std_logic;
+     -- PAL_PWDN    : out std_logic;
+
+        -- WIFI
+     -- FROM_ESP_TXD : in  std_logic;
+     -- TO_ESP_RXD   : out std_logic;
+
+        -- LED RGB
+     -- LED_BGR : out std_logic;
+
+        -- HPS
+     -- HPS_CONV_USB_N   : inout std_logic;
+     -- HPS_DDR3_ADDR    : out   std_logic_vector(14 downto 0);
+     -- HPS_DDR3_BA      : out   std_logic_vector(2 downto 0);
+     -- HPS_DDR3_CAS_N   : out   std_logic;
+     -- HPS_DDR3_CK_N    : out   std_logic;
+     -- HPS_DDR3_CK_P    : out   std_logic;
+     -- HPS_DDR3_CKE     : out   std_logic;
+     -- HPS_DDR3_CS_N    : out   std_logic;
+     -- HPS_DDR3_DM      : out   std_logic_vector(3 downto 0);
+     -- HPS_DDR3_DQ      : inout std_logic_vector(31 downto 0);
+     -- HPS_DDR3_DQS_N   : inout std_logic_vector(3 downto 0);
+     -- HPS_DDR3_DQS_P   : inout std_logic_vector(3 downto 0);
+     -- HPS_DDR3_ODT     : out   std_logic;
+     -- HPS_DDR3_RAS_N   : out   std_logic;
+     -- HPS_DDR3_RESET_N : out   std_logic;
+     -- HPS_DDR3_RZQ     : in    std_logic;
+     -- HPS_DDR3_WE_N    : out   std_logic;
+     -- HPS_ENET_GTX_CLK : out   std_logic;
+     -- HPS_ENET_INT_N   : inout std_logic;
+     -- HPS_ENET_MDC     : out   std_logic;
+     -- HPS_ENET_MDIO    : inout std_logic;
+     -- HPS_ENET_RX_CLK  : in    std_logic;
+     -- HPS_ENET_RX_DATA : in    std_logic_vector(3 downto 0);
+     -- HPS_ENET_RX_DV   : in    std_logic;
+     -- HPS_ENET_TX_DATA : out   std_logic_vector(3 downto 0);
+     -- HPS_ENET_TX_EN   : out   std_logic;
+     -- HPS_GSENSOR_INT  : inout std_logic;
+     -- HPS_I2C0_SCLK    : inout std_logic;
+     -- HPS_I2C0_SDAT    : inout std_logic;
+     -- HPS_I2C1_SCLK    : inout std_logic;
+     -- HPS_I2C1_SDAT    : inout std_logic;
+     -- HPS_KEY_N        : inout std_logic;
+     -- HPS_LED          : inout std_logic;
+     -- HPS_LTC_GPIO     : inout std_logic;
+     -- HPS_SD_CLK       : out   std_logic;
+     -- HPS_SD_CMD       : inout std_logic;
+     -- HPS_SD_DATA      : inout std_logic_vector(3 downto 0);
+     -- HPS_SPIM_CLK     : out   std_logic;
+     -- HPS_SPIM_MISO    : in    std_logic;
+     -- HPS_SPIM_MOSI    : out   std_logic;
+     -- HPS_SPIM_SS      : inout std_logic;
+     -- HPS_UART_RX      : in    std_logic;
+     -- HPS_UART_TX      : out   std_logic;
+     -- HPS_USB_CLKOUT   : in    std_logic;
+     -- HPS_USB_DATA     : inout std_logic_vector(7 downto 0);
+     -- HPS_USB_DIR      : in    std_logic;
+     -- HPS_USB_NXT      : in    std_logic;
+     -- HPS_USB_STP      : out   std_logic
+    );
+end entity DE0_Nano_SoC_PrSoC_extn_board_top_level;
+
+architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is
+    component soc_system is
+        port (
+            clk_clk                    : in  std_logic := 'X';
+            reset_reset_n              : in  std_logic := 'X';
+            pwm_0_conduit_end_pwm      : out std_logic;
+            pwm_1_conduit_end_pwm      : out std_logic;
+            mcp3204_0_conduit_end_cs_n : out std_logic;
+            mcp3204_0_conduit_end_mosi : out std_logic;
+            mcp3204_0_conduit_end_miso : in  std_logic := 'X';
+            mcp3204_0_conduit_end_sclk : out std_logic
+        );
+    end component soc_system;
+
+begin
+    soc_system_inst : component soc_system
+    port map (
+        clk_clk                    => FPGA_CLK1_50,
+        reset_reset_n              => KEY_N(0),
+        pwm_0_conduit_end_pwm      => SERVO_0,
+        pwm_1_conduit_end_pwm      => SERVO_1,
+        mcp3204_0_conduit_end_cs_n => J0_SPI_CS_n,
+        mcp3204_0_conduit_end_mosi => J0_SPI_MOSI,
+        mcp3204_0_conduit_end_miso => J0_SPI_MISO,
+        mcp3204_0_conduit_end_sclk => J0_SPI_CLK
+    );
+
+end;

cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204.vhd

@@ -0,0 +1,138 @@
+-- #############################################################################
+-- mcp3204.vhd
+-- ===========
+-- MCP3204 Avalon-MM slave interface.
+--
+-- Register map
+-- +-------+-----------+--------+------------------------------------+
+-- | RegNo | Name      | Access | Description                        |
+-- +-------+-----------+--------+------------------------------------+
+-- | 0     | CHANNEL_0 | RO     | 12-bit digital value of channel 0. |
+-- +-------+-----------+--------+------------------------------------+
+-- | 1     | CHANNEL_1 | RO     | 12-bit digital value of channel 1. |
+-- +-------+-----------+--------+------------------------------------+
+-- | 2     | CHANNEL_2 | RO     | 12-bit digital value of channel 2. |
+-- +-------+-----------+--------+------------------------------------+
+-- | 3     | CHANNEL_3 | RO     | 12-bit digital value of channel 3. |
+-- +-------+-----------+--------+------------------------------------+
+--
+-- Author        : Philémon Favrod [philemon.favrod@epfl.ch]
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 2
+-- Last modified : 2018-03-06
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity mcp3204 is
+    port(
+        -- Avalon Clock interface
+        clk : in std_logic;
+
+        -- Avalon Reset interface
+        reset : in std_logic;
+
+        -- Avalon-MM Slave interface
+        address  : in  std_logic_vector(1 downto 0);
+        read     : in  std_logic;
+        readdata : out std_logic_vector(31 downto 0);
+
+        -- Avalon Conduit interface
+        CS_N : out std_logic;
+        MOSI : out std_logic;
+        MISO : in  std_logic;
+        SCLK : out std_logic
+    );
+end entity;
+
+architecture arch of mcp3204 is
+    constant NUM_CHANNELS  : positive := 4;
+    constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS))));
+
+    type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range);
+    signal data_reg : data_array;
+
+    signal spi_busy, spi_start, spi_datavalid : std_logic;
+    signal spi_channel                        : std_logic_vector(1 downto 0);
+    signal spi_data                           : std_logic_vector(11 downto 0);
+
+    type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA);
+    signal state : state_t;
+
+    signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0);
+
+begin
+    SPI : entity work.mcp3204_spi
+    port map(
+        clk        => clk,
+        reset      => reset,
+        busy       => spi_busy,
+        start      => spi_start,
+        channel    => spi_channel,
+        data_valid => spi_datavalid,
+        data       => spi_data,
+        SCLK       => SCLK,
+        CS_N       => CS_N,
+        MOSI       => MOSI,
+        MISO       => MISO
+    );
+
+    -- FSM that dictates which channel is being read. The state of the component
+    -- should be thought as the pair (state, channel)
+    p_fsm : process(reset, clk)
+    begin
+        if reset = '1' then
+            state   <= READY;
+            channel <= (others => '0');
+        elsif rising_edge(clk) then
+            case state is
+                when READY =>
+                    if spi_busy = '0' then
+                        state <= INIT_READ_CHANNEL;
+                    end if;
+
+                when INIT_READ_CHANNEL =>
+                    state <= WAIT_FOR_DATA;
+
+                when WAIT_FOR_DATA =>
+                    if spi_datavalid = '1' then
+                        state   <= READY;
+                        channel <= channel + 1;
+                    end if;
+            end case;
+        end if;
+    end process p_fsm;
+
+    -- Updates the internal registers when a new data is available
+    p_data : process(reset, clk)
+    begin
+        if reset = '1' then
+            for i in 0 to NUM_CHANNELS - 1 loop
+                data_reg(i) <= (others => '0');
+            end loop;
+        elsif rising_edge(clk) then
+            if state = WAIT_FOR_DATA and spi_datavalid = '1' then
+                data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data;
+            end if;
+        end if;
+    end process p_data;
+
+    spi_start   <= '1' when state = INIT_READ_CHANNEL else '0';
+    spi_channel <= std_logic_vector(channel);
+
+    -- Interface with the Avalon Switch Fabric
+    p_avalon_read : process(reset, clk)
+    begin
+        if reset = '1' then
+            readdata <= (others => '0');
+        elsif rising_edge(clk) then
+            if read = '1' then
+                readdata <= data_reg(to_integer(unsigned(address)));
+            end if;
+        end if;
+    end process p_avalon_read;
+
+end architecture;

cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204_hw.tcl

@@ -0,0 +1,137 @@
+# TCL File Generated by Component Editor 16.0
+# Sun Feb 05 18:14:06 CET 2017
+# DO NOT MODIFY
+
+
+#
+# mcp3204 "mcp3204" v1.0
+# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.18:14:06
+# 4-Channel 12-Bit A/D Converter with SPI Serial Interface
+#
+
+#
+# request TCL package from ACDS 16.0
+#
+package require -exact qsys 16.0
+
+
+#
+# module mcp3204
+#
+set_module_property DESCRIPTION "4-Channel 12-Bit A/D Converter with SPI Serial Interface"
+set_module_property NAME mcp3204
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP Joystick
+set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan"
+set_module_property DISPLAY_NAME mcp3204
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL mcp3204
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file mcp3204.vhd VHDL PATH mcp3204.vhd TOP_LEVEL_FILE
+add_fileset_file mcp3204_spi.vhd VHDL PATH mcp3204_spi.vhd
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point clock
+#
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+#
+# connection point reset
+#
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+#
+# connection point avalon_slave_0
+#
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+
+
+#
+# connection point conduit_end
+#
+add_interface conduit_end conduit end
+set_interface_property conduit_end associatedClock clock
+set_interface_property conduit_end associatedReset ""
+set_interface_property conduit_end ENABLED true
+set_interface_property conduit_end EXPORT_OF ""
+set_interface_property conduit_end PORT_NAME_MAP ""
+set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end CS_N cs_n Output 1
+add_interface_port conduit_end MOSI mosi Output 1
+add_interface_port conduit_end MISO miso Input 1
+add_interface_port conduit_end SCLK sclk Output 1
+

cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204_spi.vhd

@@ -0,0 +1,161 @@
+-- #############################################################################
+-- mcp3204_spi.vhd
+-- ===============
+-- MCP3204 SPI interface.
+--
+-- Author        : Philémon Favrod [philemon.favrod@epfl.ch]
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Author        : <insert your name> (<insert your e-mail address>)
+-- Revision      : 1
+-- Last modified : <insert date>
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mcp3204_spi is
+    port(
+        -- 50 MHz
+        clk        : in  std_logic;
+        reset      : in  std_logic;
+        busy       : out std_logic;
+        start      : in  std_logic;
+        channel    : in  std_logic_vector(1 downto 0);
+        data_valid : out std_logic;
+        data       : out std_logic_vector(11 downto 0);
+
+        -- 1 MHz
+        SCLK : out std_logic;
+        CS_N : out std_logic;
+        MOSI : out std_logic;
+        MISO : in  std_logic
+    );
+end mcp3204_spi;
+
+architecture rtl of mcp3204_spi is
+    -- The signals that drive the clock divider
+    signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0');  -- need to be able to count until 24
+    signal reg_spi_en              : std_logic            := '0';  -- pulses every 0.5 MHz
+    signal reg_rising_edge_sclk    : std_logic            := '0';
+    signal reg_falling_edge_sclk   : std_logic            := '0';
+    signal reg_sclk : std_logic := '0';
+
+    -- The state related to the FSM
+    type state_type is (IDL, SYN, SND_S, SND_SGL, SND_D, WT, RCV_NB, RCV_D, WB); 
+    signal reg_state, next_state : state_type := IDL; 
+    signal reg_bit_idx : unsigned(3 downto 0) := (others => '0');
+    signal reg_channel : unsigned(1 downto 0);
+
+    -- The register that holds the transmitted data
+    signal reg_data : unsigned(11 downto 0) := (others => '0');
+
+begin
+    clk_divider_generation : process(clk, reset)
+    begin
+        if reset = '1' then
+            reg_clk_divider_counter <= (others => '0');
+        elsif rising_edge(clk) then
+            reg_clk_divider_counter <= reg_clk_divider_counter + 1;
+            reg_spi_en              <= '0';
+            reg_rising_edge_sclk    <= '0';
+            reg_falling_edge_sclk   <= '0';
+
+            if reg_clk_divider_counter = 24 then
+                reg_clk_divider_counter <= (others => '0');
+                reg_spi_en              <= '1';
+
+                if reg_sclk = '0' then
+                    reg_rising_edge_sclk <= '1';
+                elsif reg_sclk = '1' then
+                    reg_falling_edge_sclk <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    SCLK_generation : process(clk, reset)
+    begin
+        if reset = '1' then
+            reg_sclk <= '0';
+        elsif rising_edge(clk) then
+            if reg_spi_en = '1' then
+                reg_sclk <= not reg_sclk;
+            end if;
+        end if;
+    end process;
+
+    STATE_LOGIC : process(clk, reset)
+    begin
+        if reset = '1' then
+            reg_state <= IDL;
+            reg_bit_idx <= (others => '0');
+        elsif rising_edge(clk) then
+            reg_state <= next_state;
+
+            case reg_state is
+                when IDL =>
+                    if next_state = SYN then
+                        reg_channel <= unsigned(channel);
+                    end if;
+                when SND_SGL =>
+                    if next_state = SND_D then
+                        reg_bit_idx <= to_unsigned(2, reg_bit_idx'length);
+                    end if;
+                when RCV_NB =>
+                    if next_state = RCV_D then
+                        reg_bit_idx <= to_unsigned(11, reg_bit_idx'length);
+                    end if;
+                when SND_D | RCV_D =>
+                    if reg_falling_edge_sclk = '1' then
+                        reg_bit_idx <= reg_bit_idx - 1;
+                    end if;
+                when others =>
+                    null;
+            end case;
+        end if;
+    end process;
+
+    -- This is the combinatory logic to compute the next state
+    next_state <=
+        SYN     when reg_state = IDL and start = '1' else
+        SND_S   when reg_state = SYN and reg_falling_edge_sclk = '1' else
+        SND_SGL when reg_state = SND_S and reg_falling_edge_sclk = '1' else
+        SND_D   when reg_state = SND_SGL and reg_falling_edge_sclk = '1' else
+        WT      when reg_state = SND_D and reg_falling_edge_sclk = '1' and reg_bit_idx = 0 else
+        RCV_NB  when reg_state = WT and reg_falling_edge_sclk = '1' else
+        RCV_D   when reg_state = RCV_NB and reg_falling_edge_sclk = '1' else
+        WB      when reg_state = RCV_D and reg_falling_edge_sclk = '1' and reg_bit_idx = 0 else
+        IDL     when reg_state = WB else
+        reg_state;
+        
+    -- This process reads the bits sent from the ADC
+    ADC_READ : process(clk, reset)
+    begin
+        if reset = '1' then
+            reg_data <= (others => '0');
+        elsif rising_edge(clk) then
+            if reg_state = RCV_D and reg_rising_edge_sclk = '1' then
+                reg_data(to_integer(reg_bit_idx)) <= MISO;
+            end if;
+        end if;
+    end process;
+
+    -- This is the combinatory logic to the ADC converter
+    SCLK <= reg_sclk;
+    CS_N <= '1' when reg_state = IDL or reg_state = SYN or reg_state = WB else '0';
+    MOSI <=
+        '1' when reg_state = SND_S or reg_state = SND_SGL else
+        '0' when reg_state = SND_D and reg_bit_idx = 2 else
+        reg_channel(to_integer(reg_bit_idx)) when reg_state = SND_D else
+        '0';
+
+    -- This is the combinatory logic to the SPI manager
+    busy <= '0' when reg_state = IDL else 
+            '1';
+    data_valid <= '1' when reg_state = WB else 
+                  '0';
+    data <= std_logic_vector(reg_data) when reg_state = WB else 
+            (others => '0');
+
+end architecture rtl;

cs309-psoc/lab_1_2/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd

@@ -0,0 +1,103 @@
+-- #############################################################################
+-- tb_mcp3204_spi.vhd
+-- ==================
+-- Testbench for MCP3204 SPI interface.
+--
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 1
+-- Last modified : 2018-03-06
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_mcp3204_spi is
+end entity;
+
+architecture rtl of tb_mcp3204_spi is
+    constant CLK_PERIOD : time      := 20 ns;
+    signal clk          : std_logic := '0';
+    signal reset        : std_logic := '0';
+    signal sim_finished : boolean   := false;
+
+    -- mcp3204_spi ------------------------------------------------------------
+    signal busy       : std_logic                     := '0';
+    signal start      : std_logic                     := '0';
+    signal channel    : std_logic_vector(1 downto 0)  := (others => '0');
+    signal data_valid : std_logic                     := '0';
+    signal data       : std_logic_vector(11 downto 0) := (others => '0');
+    signal SCLK       : std_logic                     := '0';
+    signal CS_N       : std_logic                     := '1';
+    signal MOSI       : std_logic                     := '0';
+    signal MISO       : std_logic                     := '0';
+
+begin
+    duv : entity work.mcp3204_spi
+    port map(
+        clk        => clk,
+        reset      => reset,
+        busy       => busy,
+        start      => start,
+        channel    => channel,
+        data_valid => data_valid,
+        data       => data,
+        SCLK       => SCLK,
+        CS_N       => CS_N,
+        MOSI       => MOSI,
+        MISO       => MISO
+    );
+
+    clk <= not clk after CLK_PERIOD / 2 when not sim_finished;
+
+    sim : process
+        procedure async_reset is
+        begin
+            wait until rising_edge(clk);
+            wait for CLK_PERIOD / 4;
+            reset <= '1';
+
+            wait for CLK_PERIOD / 2;
+            reset <= '0';
+        end procedure async_reset;
+
+        procedure spi_transfer(constant channel_number : natural range 0 to 3) is
+        begin
+            if busy = '1' then
+                wait until busy = '0';
+
+            else
+                wait until falling_edge(clk);
+                start   <= '1';
+                channel <= std_logic_vector(to_unsigned(channel_number, channel'length));
+
+                wait until falling_edge(clk);
+                start   <= '0';
+                channel <= (others => '0');
+
+                wait until rising_edge(data_valid);
+                wait until falling_edge(busy);
+            end if;
+        end procedure spi_transfer;
+
+    begin
+        async_reset;
+
+        MISO <= '1';
+        spi_transfer(0);
+
+        MISO <= '0';
+        spi_transfer(1);
+
+        MISO <= '1';
+        spi_transfer(2);
+
+        MISO <= '0';
+        spi_transfer(3);
+
+        sim_finished <= true;
+        wait;
+    end process sim;
+end architecture rtl;
+
+

cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm.vhd

@@ -0,0 +1,134 @@
+-- #############################################################################
+-- pwm.vhd
+-- =======
+-- PWM memory-mapped Avalon slave interface.
+--
+-- Author        : Cedric Hoelzl (cedric.hoelzl@epfl.ch)
+-- Author        : Antoine Brunner (antoine.brunner@epfl.ch)
+-- Revision      : 0.0.1a_rc1
+-- Last modified : a few billion clock cycles in the past
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pwm_constants.all;
+
+entity pwm is
+    port(
+        -- Avalon Clock interface
+        clk : in std_logic;
+
+        -- Avalon Reset interface
+        reset : in std_logic;
+
+        -- Avalon-MM Slave interface
+        address   : in  std_logic_vector(1 downto 0);
+        read      : in  std_logic;
+        write     : in  std_logic;
+        readdata  : out std_logic_vector(31 downto 0);
+        writedata : in  std_logic_vector(31 downto 0);
+
+        -- Avalon Conduit interface
+        pwm_out : out std_logic
+    );
+end pwm;
+
+architecture rtl of pwm is
+
+    -- The period of the current and next PWM cycle
+    signal reg_next_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length);
+    signal reg_current_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length);
+
+    -- The duty cycle of the current and next PWM cycle
+    signal reg_next_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length);
+    signal reg_current_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length);
+
+    -- The status of the current and next PWM cycle
+    signal reg_prev_ctrl : std_logic := '0';
+    signal reg_current_ctrl : std_logic := '0';
+
+    -- The internal counter of the PWN
+    signal reg_counter : unsigned(writedata'range) := to_unsigned(0, writedata'length);
+
+begin
+
+	--Avalon-MM slave write
+	process(clk, reset)
+	begin
+	    if reset = '1' then
+		reg_next_period <= to_unsigned(DEFAULT_PERIOD, writedata'length);
+		reg_next_dutycycle <= to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length);
+		reg_current_ctrl <= '0';
+	    elsif rising_edge(clk) then
+		if write = '1' then
+		    case address is
+		        when REG_PERIOD_OFST => 
+		            if unsigned(writedata) >= to_unsigned(2, writedata'length) then
+		                reg_next_period <= unsigned(writedata);
+		            end if;
+		        when REG_DUTY_CYCLE_OFST => 
+		            if (unsigned(writedata) >= to_unsigned(1, writedata'length)) and
+		               (unsigned(writedata) <= reg_next_period) then
+		                reg_next_dutycycle <= unsigned(writedata);
+		            end if;
+		        when REG_CTRL_OFST => 
+		            reg_current_ctrl <= writedata(0);
+		        when others => null;
+		    end case;
+		end if;
+	    end if;
+	end process;
+
+
+	--Avalon-MM slave read
+	process(clk, reset)
+	begin
+	    if rising_edge(clk) then
+		if read = '1' then
+		    case address is
+		        when REG_PERIOD_OFST => 
+		            readdata <= std_logic_vector(reg_current_period);
+		        when REG_DUTY_CYCLE_OFST => 
+		            readdata <= std_logic_vector(reg_current_dutycycle);
+		        when others =>
+		            readdata <= (others => '0');
+		    end case;
+		end if;
+	    end if;
+	end process;
+
+	-- Internal synchronous logic
+	process(clk, reset)
+	begin
+	    if reset = '1' then
+		reg_counter <= to_unsigned(0, writedata'length);
+		reg_prev_ctrl <= '0';
+	    elsif rising_edge(clk) then
+		if ((reg_prev_ctrl = '0') and (reg_current_ctrl = '1')) or
+		   (reg_counter = reg_current_period - 1) then
+		    reg_current_period <= reg_next_period;
+		    reg_current_dutycycle <= reg_next_dutycycle;
+		    reg_counter <= to_unsigned(0, writedata'length);
+		elsif (reg_current_ctrl = '1') then
+		    reg_counter <= reg_counter + 1;
+		end if;
+		reg_prev_ctrl <= reg_current_ctrl;
+	    end if;
+	end process;
+
+	-- Avalon Conduit interface
+	process(clk, reset)
+	begin
+	    if rising_edge(clk) then
+
+		if (reg_counter < reg_current_dutycycle) and (reg_current_ctrl = '1') then
+		    pwm_out <= '1';
+		else
+		    pwm_out <= '0';
+		end if;
+	    end if;
+	end process;
+
+end architecture rtl;

cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm_constants.vhd

@@ -0,0 +1,61 @@
+-- #############################################################################
+-- pwm_constants.vhd
+-- =================
+-- This package contains constants used in the PWM design files.
+--
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 2
+-- Last modified : 2018-02-28
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package pwm_constants is
+    -- Register map
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | RegNo  | Name       | Access | Description                                                                  |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | 0      | PERIOD     | R/W    | Period in clock cycles [2 <= period <= (2**32) - 1].                         |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | This value can be read/written while the unit is in the middle of an ongoing |
+    -- |        |            |        | PWM pulse. To allow safe behaviour, one cannot modify the period of an       |
+    -- |        |            |        | ongoing pulse, so we adopt the following semantics for this register:        |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> WRITING a value in this register indicates the NEW period to apply to the |
+    -- |        |            |        |    next pulse.                                                               |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> READING a value from this register indicates the CURRENT period of the    |
+    -- |        |            |        |    ongoing pulse.                                                            |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | 1      | DUTY_CYCLE | R/W    | Duty cycle of the PWM [1 <= duty cycle <= period]                            |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | This value can be read/written while the unit is in the middle of an ongoing |
+    -- |        |            |        | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an   |
+    -- |        |            |        | ongoing pulse, so we adopt the following semantics for this register:        |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> WRITING a value in this register indicates the NEW duty cycle to apply to |
+    -- |        |            |        |    the next pulse.                                                           |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> READING a value from this register indicates the CURRENT duty cycle of    |
+    -- |        |            |        |    the ongoing pulse.                                                        |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | 2      | CTRL       | WO     | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.|
+    -- |        |            |        |    Writing 1 to this register starts the PWM.                                |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> Reading this register always returns 0.                                   |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    constant REG_PERIOD_OFST     : std_logic_vector(1 downto 0) := "00";
+    constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01";
+    constant REG_CTRL_OFST       : std_logic_vector(1 downto 0) := "10";
+
+    -- Default values of registers after reset (BEFORE writing START to the CTRL
+    -- register with a new configuration)
+    constant DEFAULT_PERIOD     : natural := 4;
+    constant DEFAULT_DUTY_CYCLE : natural := 2;
+end package pwm_constants;
+
+package body pwm_constants is
+
+end package body pwm_constants;

cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm_hw.tcl

@@ -0,0 +1,135 @@
+# TCL File Generated by Component Editor 16.0
+# Tue Feb 28 12:18:00 CET 2017
+# DO NOT MODIFY
+
+
+#
+# pwm "pwm" v1.0
+#  2017.02.28.12:18:00
+# Pan-tilt
+#
+
+#
+# request TCL package from ACDS 16.0
+#
+package require -exact qsys 16.0
+
+
+#
+# module pwm
+#
+set_module_property DESCRIPTION Pan-tilt
+set_module_property NAME pwm
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP Pan-tilt
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME pwm
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE
+add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point clock
+#
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+#
+# connection point reset
+#
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+#
+# connection point avalon_slave_0
+#
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 writedata writedata Input 32
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+
+
+#
+# connection point conduit_end
+#
+add_interface conduit_end conduit end
+set_interface_property conduit_end associatedClock clock
+set_interface_property conduit_end associatedReset ""
+set_interface_property conduit_end ENABLED true
+set_interface_property conduit_end EXPORT_OF ""
+set_interface_property conduit_end PORT_NAME_MAP ""
+set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end pwm_out pwm Output 1

cs309-psoc/lab_1_2/hw/hdl/pantilt/tb/tb_pwm.vhd

@@ -0,0 +1,205 @@
+-- #############################################################################
+-- tb_pwm.vhd
+-- ==========
+-- Testbench for PWM memory-mapped Avalon slave interface.
+--
+-- Modified by   : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 2
+-- Last modified : 2018-02-28
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pwm_constants.all;
+
+entity tb_pwm is
+end entity;
+
+architecture rtl of tb_pwm is
+
+    -- 50 MHz clock
+    constant CLK_PERIOD : time := 20 ns;
+
+    -- Signal used to end simulator when we finished submitting our test cases
+    signal sim_finished : boolean := false;
+
+    -- PWM PORTS
+    signal clk       : std_logic;
+    signal reset     : std_logic;
+    signal address   : std_logic_vector(1 downto 0);
+    signal read      : std_logic;
+    signal write     : std_logic;
+    signal readdata  : std_logic_vector(31 downto 0);
+    signal writedata : std_logic_vector(31 downto 0);
+    signal pwm_out   : std_logic;
+
+    -- Values of registers we are going to use to configure the PWM unit
+    constant CONFIG_PERIOD     : natural := 100;
+    constant CONFIG_DUTY_CYCLE : natural := 20;
+    constant CONFIG_CTRL_START : natural := 1;
+    constant CONFIG_CTRL_STOP  : natural := 0;
+
+begin
+
+    -- Instantiate DUT
+    dut : entity work.pwm
+    port map(
+        clk       => clk,
+        reset     => reset,
+        address   => address,
+        read      => read,
+        write     => write,
+        readdata  => readdata,
+        writedata => writedata,
+        pwm_out   => pwm_out
+    );
+
+    -- Generate clk signal
+    clk_generation : process
+    begin
+        if not sim_finished then
+            clk <= '1';
+            wait for CLK_PERIOD / 2;
+            clk <= '0';
+            wait for CLK_PERIOD / 2;
+        else
+            wait;
+        end if;
+    end process clk_generation;
+
+    -- Test PWM
+    simulation : process
+
+        procedure async_reset is
+        begin
+            wait until rising_edge(clk);
+            wait for CLK_PERIOD / 4;
+
+            reset <= '1';
+            wait for CLK_PERIOD / 2;
+
+            reset <= '0';
+            wait for CLK_PERIOD / 4;
+        end procedure async_reset;
+
+        procedure write_register(constant ofst : in std_logic_vector(1 downto 0);
+                                 constant val  : in natural) is
+        begin
+            wait until rising_edge(clk);
+
+            address   <= ofst;
+            write     <= '1';
+            writedata <= std_logic_vector(to_unsigned(val, writedata'length));
+            wait until rising_edge(clk);
+
+            address   <= (others => '0');
+            write     <= '0';
+            writedata <= (others => '0');
+            wait until rising_edge(clk);
+        end procedure write_register;
+
+        procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is
+        begin
+            wait until rising_edge(clk);
+
+            address <= ofst;
+            read    <= '1';
+            -- The read has a 1 cycle wait-state, so we need to keep the read
+            -- signal high for 2 clock cycles.
+            wait until rising_edge(clk);
+            wait until rising_edge(clk);
+
+            address <= (others => '0');
+            read    <= '0';
+            wait until rising_edge(clk);
+        end procedure read_register;
+
+        procedure read_register_check(constant ofst         : in std_logic_vector(1 downto 0);
+                                      constant expected_val : in natural) is
+        begin
+            read_register(ofst);
+
+            case ofst is
+                when REG_PERIOD_OFST =>
+                    assert to_integer(unsigned(readdata)) = expected_val
+                    report "Unexpected PERIOD: " &
+                    "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " &
+                    "PERIOD_expected = " & integer'image(expected_val)
+                    severity error;
+
+                when REG_DUTY_CYCLE_OFST =>
+                    assert to_integer(unsigned(readdata)) = expected_val
+                    report "Unexpected DUTY_CYCLE: " &
+                    "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " &
+                    "DUTY_CYCLE_expected = " & integer'image(expected_val)
+                    severity error;
+
+                when REG_CTRL_OFST =>
+                    assert to_integer(unsigned(readdata)) = expected_val
+                    report "Unexpected CTRL: " &
+                    "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " &
+                    "CTRL_expected = " & integer'image(expected_val)
+                    severity error;
+
+                when others =>
+                    null;
+            end case;
+        end procedure read_register_check;
+
+    begin
+
+        -- Default values
+        reset     <= '0';
+        address   <= (others => '0');
+        read      <= '0';
+        write     <= '0';
+        writedata <= (others => '0');
+        wait until rising_edge(clk);
+
+        -- Reset the circuit
+        async_reset;
+
+        -- Write desired configuration to PWM Avalon-MM slave.
+        write_register(REG_PERIOD_OFST, CONFIG_PERIOD);
+        write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
+
+        -- Read back configuration from PWM Avalon-MM slave. Note that we have
+        -- not started the PWM unit yet, so the new configuration must not be
+        -- read back at this point (as per the register map).
+        read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD);
+        read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE);
+        read_register_check(REG_CTRL_OFST, 0);
+
+        -- Start PWM
+        write_register(REG_CTRL_OFST, CONFIG_CTRL_START);
+
+        -- Wait until PWM pulses for the first time after we sent START.
+        wait until rising_edge(pwm_out);
+
+        -- Read back configuration from PWM Avalon-MM slave. Now that we have
+        -- started the PWM unit, we should be able to read back the
+        -- configuration we wrote (as per the register map).
+        read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD);
+        read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
+        read_register_check(REG_CTRL_OFST, 0);
+
+        -- Wait for 2 PWM periods to finish
+        wait for 2 * CLK_PERIOD * CONFIG_PERIOD;
+
+        -- Stop PWM.
+        write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP);
+
+        -- Wait for PWM period to finish
+        wait for 1 * CLK_PERIOD * CONFIG_PERIOD;
+
+        -- Instruct "clk_generation" process to halt execution.
+        sim_finished <= true;
+
+        -- Make this process wait indefinitely (it will never re-execute from
+        -- its beginning again).
+        wait;
+    end process simulation;
+end architecture rtl;
+

cs309-psoc/lab_1_2/hw/quartus/ip/components.ipx

@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<library>
+ <!--  date: 2017.03.04.21:24:39 -->
+ <!--  generated by: ip-make-ipx -->
+ <!--   -->
+ <!--     2 in ../../hdl/ -->
+ <!--   -->
+ <component
+   name="mcp3204"
+   file="../../hdl/joysticks/hdl/mcp3204_hw.tcl"
+   displayName="mcp3204"
+   version="1.0"
+   description="4-Channel 12-Bit A/D Converter with SPI Serial Interface"
+   tags="AUTHORSHIP=Philemon Favrod &amp; Sahand Kashani-Akhavan /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
+   categories="Joystick"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+ <component
+   name="pwm"
+   file="../../hdl/pantilt/hdl/pwm_hw.tcl"
+   displayName="pwm"
+   version="1.0"
+   description="Pan-tilt"
+   tags="AUTHORSHIP= /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
+   categories="Pan-tilt"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+</library>

cs309-psoc/lab_1_2/hw/quartus/lab_1_2.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors.  Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+# Date created = 11:03:02  February 05, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "15.1"
+DATE = "11:03:02  February 05, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "lab_1_2"

cs309-psoc/lab_1_2/hw/quartus/lab_1_2.qsf

@@ -0,0 +1,812 @@
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+
+set_global_assignment -name SMART_RECOMPILE OFF
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+
+set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level
+
+set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
+set_global_assignment -name QSYS_FILE soc_system.qsys
+set_global_assignment -name SDC_FILE lab_1_2.sdc
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA4U23C6
+set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+#============================================================
+# ADC
+#============================================================
+set_location_assignment PIN_U9 -to ADC_CONVST
+set_location_assignment PIN_V10 -to ADC_SCK
+set_location_assignment PIN_AC4 -to ADC_SDI
+set_location_assignment PIN_AD4 -to ADC_SDO
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+#============================================================
+# ARDUINO Extention OV7670 CAMERA
+#============================================================
+set_location_assignment PIN_AE15 -to CAM_D[0]
+set_location_assignment PIN_AE15 -to CAM_D_0
+set_location_assignment PIN_AF17 -to CAM_D[1]
+set_location_assignment PIN_AF17 -to CAM_D_1
+set_location_assignment PIN_AH8 -to CAM_D[2]
+set_location_assignment PIN_AH8 -to CAM_D_2
+set_location_assignment PIN_AG8 -to CAM_D[3]
+set_location_assignment PIN_AG8 -to CAM_D_3
+set_location_assignment PIN_U13 -to CAM_D[4]
+set_location_assignment PIN_U13 -to CAM_D_4
+set_location_assignment PIN_U14 -to CAM_D[5]
+set_location_assignment PIN_U14 -to CAM_D_5
+set_location_assignment PIN_AG9 -to CAM_D[6]
+set_location_assignment PIN_AG9 -to CAM_D_6
+set_location_assignment PIN_AG10 -to CAM_D[7]
+set_location_assignment PIN_AG10 -to CAM_D_7
+set_location_assignment PIN_AF13 -to CAM_D[8]
+set_location_assignment PIN_AF13 -to CAM_D_8
+set_location_assignment PIN_AG13 -to CAM_D[9]
+set_location_assignment PIN_AG13 -to CAM_D_9
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9
+
+#============================================================
+# Arduino Extension LEPTON CAMERA THERMAL CAM_TH
+#============================================================
+set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N
+set_location_assignment PIN_AG16 -to CAM_TH_MOSI
+set_location_assignment PIN_AH11 -to CAM_TH_MISO
+set_location_assignment PIN_AH12 -to CAM_TH_CLK
+set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA
+set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL
+
+set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_V11 -to FPGA_CLK1_50
+set_location_assignment PIN_Y13 -to FPGA_CLK2_50
+set_location_assignment PIN_E11 -to FPGA_CLK3_50
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
+
+#============================================================
+# HPS
+#============================================================
+set_location_assignment PIN_C6 -to HPS_CONV_USB_N
+set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0]
+set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0
+set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1]
+set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1
+set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2]
+set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2
+set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3]
+set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3
+set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4]
+set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4
+set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5]
+set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5
+set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6]
+set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6
+set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7]
+set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7
+set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8]
+set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8
+set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9]
+set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9
+set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10]
+set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10
+set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11]
+set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11
+set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12]
+set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12
+set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13]
+set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13
+set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14]
+set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14
+set_location_assignment PIN_A27 -to HPS_DDR3_BA[0]
+set_location_assignment PIN_A27 -to HPS_DDR3_BA_0
+set_location_assignment PIN_H25 -to HPS_DDR3_BA[1]
+set_location_assignment PIN_H25 -to HPS_DDR3_BA_1
+set_location_assignment PIN_G25 -to HPS_DDR3_BA[2]
+set_location_assignment PIN_G25 -to HPS_DDR3_BA_2
+set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N
+set_location_assignment PIN_L28 -to HPS_DDR3_CKE
+set_location_assignment PIN_N20 -to HPS_DDR3_CK_N
+set_location_assignment PIN_N21 -to HPS_DDR3_CK_P
+set_location_assignment PIN_L21 -to HPS_DDR3_CS_N
+set_location_assignment PIN_G28 -to HPS_DDR3_DM[0]
+set_location_assignment PIN_G28 -to HPS_DDR3_DM_0
+set_location_assignment PIN_P28 -to HPS_DDR3_DM[1]
+set_location_assignment PIN_P28 -to HPS_DDR3_DM_1
+set_location_assignment PIN_W28 -to HPS_DDR3_DM[2]
+set_location_assignment PIN_W28 -to HPS_DDR3_DM_2
+set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3]
+set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3
+set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0]
+set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0
+set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1]
+set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1
+set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2]
+set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2
+set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3]
+set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3
+set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4]
+set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4
+set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5]
+set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5
+set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6]
+set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6
+set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7]
+set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7
+set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8]
+set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8
+set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9]
+set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9
+set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10]
+set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10
+set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11]
+set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11
+set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12]
+set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12
+set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13]
+set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13
+set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14]
+set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14
+set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15]
+set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15
+set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16]
+set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16
+set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17]
+set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17
+set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18]
+set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18
+set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19]
+set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19
+set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20]
+set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20
+set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21]
+set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21
+set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22]
+set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22
+set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23]
+set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23
+set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24]
+set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24
+set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25]
+set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25
+set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26]
+set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26
+set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27]
+set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27
+set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28]
+set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28
+set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29]
+set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29
+set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30]
+set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30
+set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31]
+set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31
+set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0]
+set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0
+set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1]
+set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1
+set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2]
+set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2
+set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3]
+set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3
+set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0]
+set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0
+set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1]
+set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1
+set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2]
+set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2
+set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3]
+set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3
+set_location_assignment PIN_D28 -to HPS_DDR3_ODT
+set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N
+set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N
+set_location_assignment PIN_D25 -to HPS_DDR3_RZQ
+set_location_assignment PIN_E25 -to HPS_DDR3_WE_N
+set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK
+set_location_assignment PIN_B14 -to HPS_ENET_INT_N
+set_location_assignment PIN_A13 -to HPS_ENET_MDC
+set_location_assignment PIN_E16 -to HPS_ENET_MDIO
+set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK
+set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0]
+set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0
+set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1]
+set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1
+set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2]
+set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2
+set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3]
+set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3
+set_location_assignment PIN_J13 -to HPS_ENET_RX_DV
+set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0]
+set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0
+set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1]
+set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1
+set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2]
+set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2
+set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3]
+set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3
+set_location_assignment PIN_A12 -to HPS_ENET_TX_EN
+set_location_assignment PIN_A17 -to HPS_GSENSOR_INT
+set_location_assignment PIN_C18 -to HPS_I2C0_SCLK
+set_location_assignment PIN_A19 -to HPS_I2C0_SDAT
+set_location_assignment PIN_K18 -to HPS_I2C1_SCLK
+set_location_assignment PIN_A21 -to HPS_I2C1_SDAT
+set_location_assignment PIN_J18 -to HPS_KEY_N
+set_location_assignment PIN_A20 -to HPS_LED
+set_location_assignment PIN_H13 -to HPS_LTC_GPIO
+set_location_assignment PIN_B8 -to HPS_SD_CLK
+set_location_assignment PIN_D14 -to HPS_SD_CMD
+set_location_assignment PIN_C13 -to HPS_SD_DATA[0]
+set_location_assignment PIN_C13 -to HPS_SD_DATA_0
+set_location_assignment PIN_B6 -to HPS_SD_DATA[1]
+set_location_assignment PIN_B6 -to HPS_SD_DATA_1
+set_location_assignment PIN_B11 -to HPS_SD_DATA[2]
+set_location_assignment PIN_B11 -to HPS_SD_DATA_2
+set_location_assignment PIN_B9 -to HPS_SD_DATA[3]
+set_location_assignment PIN_B9 -to HPS_SD_DATA_3
+set_location_assignment PIN_C19 -to HPS_SPIM_CLK
+set_location_assignment PIN_B19 -to HPS_SPIM_MISO
+set_location_assignment PIN_B16 -to HPS_SPIM_MOSI
+set_location_assignment PIN_C16 -to HPS_SPIM_SS
+set_location_assignment PIN_A22 -to HPS_UART_RX
+set_location_assignment PIN_B21 -to HPS_UART_TX
+set_location_assignment PIN_G4 -to HPS_USB_CLKOUT
+set_location_assignment PIN_C10 -to HPS_USB_DATA[0]
+set_location_assignment PIN_C10 -to HPS_USB_DATA_0
+set_location_assignment PIN_F5 -to HPS_USB_DATA[1]
+set_location_assignment PIN_F5 -to HPS_USB_DATA_1
+set_location_assignment PIN_C9 -to HPS_USB_DATA[2]
+set_location_assignment PIN_C9 -to HPS_USB_DATA_2
+set_location_assignment PIN_C4 -to HPS_USB_DATA[3]
+set_location_assignment PIN_C4 -to HPS_USB_DATA_3
+set_location_assignment PIN_C8 -to HPS_USB_DATA[4]
+set_location_assignment PIN_C8 -to HPS_USB_DATA_4
+set_location_assignment PIN_D4 -to HPS_USB_DATA[5]
+set_location_assignment PIN_D4 -to HPS_USB_DATA_5
+set_location_assignment PIN_C7 -to HPS_USB_DATA[6]
+set_location_assignment PIN_C7 -to HPS_USB_DATA_6
+set_location_assignment PIN_F4 -to HPS_USB_DATA[7]
+set_location_assignment PIN_F4 -to HPS_USB_DATA_7
+set_location_assignment PIN_E5 -to HPS_USB_DIR
+set_location_assignment PIN_D5 -to HPS_USB_NXT
+set_location_assignment PIN_C5 -to HPS_USB_STP
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
+
+#============================================================
+# KEY_N
+#============================================================
+set_location_assignment PIN_AH17 -to KEY_N[0]
+set_location_assignment PIN_AH17 -to KEY_N_0
+set_location_assignment PIN_AH16 -to KEY_N[1]
+set_location_assignment PIN_AH16 -to KEY_N_1
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1
+
+#============================================================
+# LED
+#============================================================
+set_location_assignment PIN_W15 -to LED[0]
+set_location_assignment PIN_W15 -to LED_0
+set_location_assignment PIN_AA24 -to LED[1]
+set_location_assignment PIN_AA24 -to LED_1
+set_location_assignment PIN_V16 -to LED[2]
+set_location_assignment PIN_V16 -to LED_2
+set_location_assignment PIN_V15 -to LED[3]
+set_location_assignment PIN_V15 -to LED_3
+set_location_assignment PIN_AF26 -to LED[4]
+set_location_assignment PIN_AF26 -to LED_4
+set_location_assignment PIN_AE26 -to LED[5]
+set_location_assignment PIN_AE26 -to LED_5
+set_location_assignment PIN_Y16 -to LED[6]
+set_location_assignment PIN_Y16 -to LED_6
+set_location_assignment PIN_AA23 -to LED[7]
+set_location_assignment PIN_AA23 -to LED_7
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_L10 -to SW[0]
+set_location_assignment PIN_L10 -to SW_0
+set_location_assignment PIN_L9 -to SW[1]
+set_location_assignment PIN_L9 -to SW_1
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H6 -to SW_2
+set_location_assignment PIN_H5 -to SW[3]
+set_location_assignment PIN_H5 -to SW_3
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3
+
+#============================================================
+# GPIO_0, GPIO_0 connect to GPIO Default
+#============================================================
+set_location_assignment PIN_V12 -to PIO_INT_N
+set_location_assignment PIN_AE11 -to PIO_SCL
+set_location_assignment PIN_AE12 -to PIO_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA
+
+set_location_assignment PIN_AF7 -to PIR_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT
+
+set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA
+set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL
+set_location_assignment PIN_T11 -to CAM_SYS_CLK
+set_location_assignment PIN_AG6 -to CAM_LV
+set_location_assignment PIN_AH2 -to CAM_PIX_CLK
+set_location_assignment PIN_AE4 -to CAM_FV
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV
+
+set_location_assignment PIN_Y8 -to PAL_VD_HSO
+set_location_assignment PIN_AB4 -to PAL_VD_VSO
+set_location_assignment PIN_AG5 -to PAL_VD_VD[0]
+set_location_assignment PIN_AG5 -to PAL_VD_VD_0
+set_location_assignment PIN_AH5 -to PAL_VD_VD[1]
+set_location_assignment PIN_AH5 -to PAL_VD_VD_1
+set_location_assignment PIN_AH6 -to PAL_VD_VD[2]
+set_location_assignment PIN_AH6 -to PAL_VD_VD_2
+set_location_assignment PIN_T8 -to PAL_VD_VD[3]
+set_location_assignment PIN_T8 -to PAL_VD_VD_3
+set_location_assignment PIN_T12 -to PAL_VD_VD[4]
+set_location_assignment PIN_T12 -to PAL_VD_VD_4
+set_location_assignment PIN_Y5 -to PAL_VD_VD[5]
+set_location_assignment PIN_Y5 -to PAL_VD_VD_5
+set_location_assignment PIN_Y4 -to PAL_VD_VD[6]
+set_location_assignment PIN_Y4 -to PAL_VD_VD_6
+set_location_assignment PIN_W8 -to PAL_VD_VD[7]
+set_location_assignment PIN_W8 -to PAL_VD_VD_7
+set_location_assignment PIN_AH4 -to PAL_VD_CLKO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO
+
+set_location_assignment PIN_AH3 -to SERVO_0
+set_location_assignment PIN_AF4 -to SERVO_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1
+
+set_location_assignment PIN_AD12 -to J0_SPI_CLK
+set_location_assignment PIN_AD11 -to J0_SPI_MISO
+set_location_assignment PIN_AF9 -to J0_SPI_CS_N
+set_location_assignment PIN_AD10 -to J0_SPI_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI
+
+set_location_assignment PIN_AF5 -to FROM_ESP_TXD
+set_location_assignment PIN_T13 -to TO_ESP_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD
+
+set_location_assignment PIN_AE7 -to SPI_MISO
+set_location_assignment PIN_AF6 -to SPI_ENA_N
+set_location_assignment PIN_AE8 -to SPI_CLK
+set_location_assignment PIN_AE9 -to SPI_MOSI
+set_location_assignment PIN_AF10 -to SPI_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT
+
+set_location_assignment PIN_AF11 -to LED_BGR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR
+
+#============================================================
+# GPIO_1, GPIO_1 connect to GPIO Default
+#============================================================
+set_location_assignment PIN_AA15 -to RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N
+
+set_location_assignment PIN_AG28 -to TS_SCL
+set_location_assignment PIN_AH27 -to TS_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA
+
+set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N
+set_location_assignment PIN_AG26 -to LCD_DE
+set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN
+
+set_location_assignment PIN_AH24 -to BLT_TXD
+set_location_assignment PIN_AE22 -to BLT_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD
+
+set_location_assignment PIN_AG20 -to BOARD_ID
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID
+
+set_location_assignment PIN_AF21 -to VIDEO_HSYNC
+set_location_assignment PIN_AG19 -to VIDEO_VSYNC
+set_location_assignment PIN_AF20 -to VIDEO_CLK
+set_location_assignment PIN_AG23 -to VIDEO_B[0]
+set_location_assignment PIN_AG23 -to VIDEO_B_0
+set_location_assignment PIN_AH23 -to VIDEO_B[1]
+set_location_assignment PIN_AH23 -to VIDEO_B_1
+set_location_assignment PIN_AF25 -to VIDEO_B[2]
+set_location_assignment PIN_AF25 -to VIDEO_B_2
+set_location_assignment PIN_AG24 -to VIDEO_B[3]
+set_location_assignment PIN_AG24 -to VIDEO_B_3
+set_location_assignment PIN_AA19 -to VIDEO_B[4]
+set_location_assignment PIN_AA19 -to VIDEO_B_4
+set_location_assignment PIN_AH26 -to VIDEO_B[5]
+set_location_assignment PIN_AH26 -to VIDEO_B_5
+set_location_assignment PIN_AG18 -to VIDEO_B[6]
+set_location_assignment PIN_AG18 -to VIDEO_B_6
+set_location_assignment PIN_AC23 -to VIDEO_B[7]
+set_location_assignment PIN_AC23 -to VIDEO_B_7
+set_location_assignment PIN_AH22 -to VIDEO_G[0]
+set_location_assignment PIN_AH22 -to VIDEO_G_0
+set_location_assignment PIN_AF22 -to VIDEO_G[1]
+set_location_assignment PIN_AF22 -to VIDEO_G_1
+set_location_assignment PIN_AD20 -to VIDEO_G[2]
+set_location_assignment PIN_AD20 -to VIDEO_G_2
+set_location_assignment PIN_AE24 -to VIDEO_G[3]
+set_location_assignment PIN_AE24 -to VIDEO_G_3
+set_location_assignment PIN_AE20 -to VIDEO_G[4]
+set_location_assignment PIN_AE20 -to VIDEO_G_4
+set_location_assignment PIN_AD19 -to VIDEO_G[5]
+set_location_assignment PIN_AD19 -to VIDEO_G_5
+set_location_assignment PIN_AF18 -to VIDEO_G[6]
+set_location_assignment PIN_AF18 -to VIDEO_G_6
+set_location_assignment PIN_AE19 -to VIDEO_G[7]
+set_location_assignment PIN_AE19 -to VIDEO_G_7
+set_location_assignment PIN_AC22 -to VIDEO_R[0]
+set_location_assignment PIN_AC22 -to VIDEO_R_0
+set_location_assignment PIN_AA18 -to VIDEO_R[1]
+set_location_assignment PIN_AA18 -to VIDEO_R_1
+set_location_assignment PIN_AE23 -to VIDEO_R[2]
+set_location_assignment PIN_AE23 -to VIDEO_R_2
+set_location_assignment PIN_AD23 -to VIDEO_R[3]
+set_location_assignment PIN_AD23 -to VIDEO_R_3
+set_location_assignment PIN_AH18 -to VIDEO_R[4]
+set_location_assignment PIN_AH18 -to VIDEO_R_4
+set_location_assignment PIN_AG21 -to VIDEO_R[5]
+set_location_assignment PIN_AG21 -to VIDEO_R_5
+set_location_assignment PIN_AH21 -to VIDEO_R[6]
+set_location_assignment PIN_AH21 -to VIDEO_R_6
+set_location_assignment PIN_AH19 -to VIDEO_R[7]
+set_location_assignment PIN_AH19 -to VIDEO_R_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7

cs309-psoc/lab_1_2/hw/quartus/lab_1_2.sdc

@@ -0,0 +1,6 @@
+create_clock -period 20 [get_ports FPGA_CLK1_50]
+create_clock -period 20 [get_ports FPGA_CLK2_50]
+create_clock -period 20 [get_ports FPGA_CLK3_50]
+
+derive_pll_clocks
+derive_clock_uncertainty

cs309-psoc/lab_1_2/sw/nios/application/app.c

@@ -0,0 +1,69 @@
+#include <stdlib.h>
+#include <io.h>
+#include <stdio.h>
+#include <inttypes.h>
+#include <stdbool.h>
+#include <unistd.h>
+
+#include "pantilt/pantilt.h"
+#include "joysticks/joysticks.h"
+#include "system.h"
+
+#define SLEEP_DURATION_US            (100000)   // 100  ms
+
+// Servos
+#define PANTILT_PWM_V_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_V_MIN_DUTY_CYCLE_US + PANTILT_PWM_V_MAX_DUTY_CYCLE_US) / 2)
+#define PANTILT_PWM_H_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_H_MIN_DUTY_CYCLE_US + PANTILT_PWM_H_MAX_DUTY_CYCLE_US) / 2)
+
+uint32_t interpolate(uint32_t input,
+                     uint32_t input_lower_bound,
+                     uint32_t input_upper_bound,
+                     uint32_t output_lower_bound,
+                     uint32_t output_upper_bound) {
+    return (input - input_lower_bound) * (output_upper_bound - output_lower_bound) / (input_upper_bound - input_lower_bound) + output_lower_bound;
+}
+
+int main(void) {
+    // Hardware control structures
+    pantilt_dev pantilt = pantilt_inst((void *) PWM_0_BASE, (void *) PWM_1_BASE);
+    joysticks_dev joysticks = joysticks_inst((void *) MCP3204_0_BASE);
+
+    // Initialize hardware
+    pantilt_init(&pantilt);
+    joysticks_init(&joysticks);
+
+    // Center servos.
+    pantilt_configure_vertical(&pantilt, PANTILT_PWM_V_CENTER_DUTY_CYCLE_US);
+    pantilt_configure_horizontal(&pantilt, PANTILT_PWM_H_CENTER_DUTY_CYCLE_US);
+    pantilt_start_vertical(&pantilt);
+    pantilt_start_horizontal(&pantilt);
+
+    // Control servos with joystick.
+    while (true) {
+        // Read LEFT joystick position
+        uint32_t left_joystick_v = joysticks_read_left_vertical(&joysticks);
+        uint32_t left_joystick_h = joysticks_read_left_horizontal(&joysticks);
+
+        // Interpolate LEFT joystick position between SERVO_x_MIN_DUTY_CYCLE_US
+        // and SERVO_x_MAX_DUTY_CYCLE_US
+        uint32_t pantilt_v_duty_us = interpolate(left_joystick_v,
+                                                JOYSTICKS_MIN_VALUE,
+                                                JOYSTICKS_MAX_VALUE,
+                                                PANTILT_PWM_V_MIN_DUTY_CYCLE_US,
+                                                PANTILT_PWM_V_MAX_DUTY_CYCLE_US);
+        uint32_t pantilt_h_duty_us = interpolate(left_joystick_h,
+                                                JOYSTICKS_MIN_VALUE,
+                                                JOYSTICKS_MAX_VALUE,
+                                                PANTILT_PWM_H_MIN_DUTY_CYCLE_US,
+                                                PANTILT_PWM_H_MAX_DUTY_CYCLE_US);
+
+        // Configure servos with interpolated joystick values
+        pantilt_configure_vertical(&pantilt, pantilt_v_duty_us);
+        pantilt_configure_horizontal(&pantilt, pantilt_h_duty_us);
+
+        // Sleep for a while to avoid excessive sensitivity
+        usleep(SLEEP_DURATION_US);
+    }
+
+    return EXIT_SUCCESS;
+}

cs309-psoc/lab_1_2/sw/nios/application/joysticks/joysticks.c

@@ -0,0 +1,79 @@
+#include "joysticks.h"
+
+#define JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL (0)
+#define JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL (1)
+#define JOYSTICK_LEFT_VRY_MCP3204_CHANNEL  (2)
+#define JOYSTICK_LEFT_VRX_MCP3204_CHANNEL  (3)
+
+/**
+ * joysticks_inst
+ *
+ * Instantiate a joysticks device structure.
+ *
+ * @param base Base address of the MCP3204 component connected to the joysticks.
+ */
+joysticks_dev joysticks_inst(void *mcp3204_base) {
+    joysticks_dev dev;
+    dev.mcp3204 = mcp3204_inst((void *) mcp3204_base);
+
+    return dev;
+}
+
+/**
+ * joysticks_init
+ *
+ * Initializes the joysticks device.
+ *
+ * @param dev joysticks device structure.
+ */
+void joysticks_init(joysticks_dev *dev) {
+    mcp3204_init(&(dev->mcp3204));
+}
+
+/**
+ * joysticks_read_left_vertical
+ *
+ * Returns the vertical position of the left joystick. Return value ranges
+ * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
+ *
+ * @param dev joysticks device structure.
+ */
+uint32_t joysticks_read_left_vertical(joysticks_dev *dev) {
+	return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,LV_CHANNEL);
+}
+
+/**
+ * joysticks_read_left_horizontal
+ *
+ * Returns the horizontal position of the left joystick. Return value ranges
+ * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
+ *
+ * @param dev joysticks device structure.
+ */
+uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) {
+	return mcp3204_read(&dev->mcp3204,LH_CHANNEL);
+}
+
+/**
+ * joysticks_read_right_vertical
+ *
+ * Returns the vertical position of the right joystick. Return value ranges
+ * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
+ *
+ * @param dev joysticks device structure.
+ */
+uint32_t joysticks_read_right_vertical(joysticks_dev *dev) {
+	return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,RV_CHANNEL);
+}
+
+/**
+ * joysticks_read_right_horizontal
+ *
+ * Returns the horizontal position of the left joystick. Return value ranges
+ * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
+ *
+ * @param dev joysticks device structure.
+ */
+uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) {
+	return mcp3204_read(&dev->mcp3204,RH_CHANNEL);
+}

cs309-psoc/lab_1_2/sw/nios/application/joysticks/joysticks.h

@@ -0,0 +1,33 @@
+#ifndef __JOYSTICKS_H__
+#define __JOYSTICKS_H__
+
+#include "mcp3204/mcp3204.h"
+
+/* joysticks device structure */
+typedef struct joysticks_dev {
+    mcp3204_dev mcp3204; /* MCP3204 device handle */
+} joysticks_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+
+#define JOYSTICKS_MIN_VALUE (MCP3204_MIN_VALUE)
+#define JOYSTICKS_MAX_VALUE (MCP3204_MAX_VALUE)
+
+#define LV_CHANNEL 0
+#define LH_CHANNEL 1
+#define RV_CHANNEL 2
+#define RH_CHANNEL 3
+#define CC_CHANNEL "this is a joke"
+
+joysticks_dev joysticks_inst(void *mcp3204_base);
+
+void joysticks_init(joysticks_dev *dev);
+
+uint32_t joysticks_read_left_vertical(joysticks_dev *dev);
+uint32_t joysticks_read_left_horizontal(joysticks_dev *dev);
+uint32_t joysticks_read_right_vertical(joysticks_dev *dev);
+uint32_t joysticks_read_right_horizontal(joysticks_dev *dev);
+
+#endif /* __JOYSTICKS_H__ */

cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204.c

@@ -0,0 +1,44 @@
+#include <assert.h>
+#include <io.h>
+
+#include "mcp3204.h"
+#include "mcp3204_regs.h"
+
+#define MCP3204_NUM_CHANNELS (4)
+
+/**
+ * mcp3204_inst
+ *
+ * Instantiate a mcp3204 device structure.
+ *
+ * @param base Base address of the component.
+ */
+mcp3204_dev mcp3204_inst(void *base) {
+    mcp3204_dev dev;
+    dev.base = base;
+
+    return dev;
+}
+
+/**
+ * mcp3204_init
+ *
+ * Initializes the mcp3204 device.
+ *
+ * @param dev mcp3204 device structure.
+ */
+void mcp3204_init(mcp3204_dev *dev) {
+    return;
+}
+
+/**
+ * mcp3204_read
+ *
+ * Reads the register corresponding to the supplied channel parameter.
+ *
+ * @param dev mcp3204 device structure.
+ * @param channel channel to be read
+ */
+uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) {
+	return channel < 4 ? IORD_32DIRECT(dev->base, channel * 4) : 0;
+}

cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204.h

@@ -0,0 +1,23 @@
+#ifndef __MCP3204_H__
+#define __MCP3204_H__
+
+#include <stdint.h>
+
+/* mcp3204 device structure */
+typedef struct mcp3204_dev {
+    void *base; /* Base address of component */
+} mcp3204_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+
+#define MCP3204_MIN_VALUE (0)
+#define MCP3204_MAX_VALUE (4095)
+
+mcp3204_dev mcp3204_inst(void *base);
+
+void mcp3204_init(mcp3204_dev *dev);
+uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel);
+
+#endif /* __MCP3204_H__ */

cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h

@@ -0,0 +1,9 @@
+#ifndef __MCP3204_REGS_H__
+#define __MCP3204_REGS_H__
+
+#define MCP3204_CHANNEL_0_OFST (0 * 4) /* RO */
+#define MCP3204_CHANNEL_1_OFST (1 * 4) /* RO */
+#define MCP3204_CHANNEL_2_OFST (2 * 4) /* RO */
+#define MCP3204_CHANNEL_3_OFST (3 * 4) /* RO */
+
+#endif /* __MCP3204_REGS_H__ */

cs309-psoc/lab_1_2/sw/nios/application/pantilt/pantilt.c

@@ -0,0 +1,109 @@
+#include "pantilt.h"
+
+/**
+ * pantilt_inst
+ *
+ * Instantiate a pantilt device structure.
+ *
+ * @param pwm_v_base Base address of the vertical PWM component.
+ * @param pwm_h_base Base address of the horizontal PWM component.
+ */
+pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) {
+    pantilt_dev dev;
+    dev.pwm_v = pwm_inst(pwm_v_base);
+    dev.pwm_h = pwm_inst(pwm_h_base);
+
+    return dev;
+}
+
+/**
+ * pantilt_init
+ *
+ * Initializes the pantilt device.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_init(pantilt_dev *dev) {
+    pwm_init(&(dev->pwm_v));
+    pwm_init(&(dev->pwm_h));
+}
+
+/**
+ * pantilt_configure_vertical
+ *
+ * Configure the vertical PWM component.
+ *
+ * @param dev pantilt device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ */
+void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) {
+    // Need to compensate for inverted servo rotation.
+    duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US;
+
+    pwm_configure(&(dev->pwm_v),
+                  duty_cycle,
+                  PANTILT_PWM_PERIOD_US,
+                  PANTILT_PWM_CLOCK_FREQ_HZ);
+}
+
+/**
+ * pantilt_configure_horizontal
+ *
+ * Configure the horizontal PWM component.
+ *
+ * @param dev pantilt device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ */
+void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) {
+    // Need to compensate for inverted servo rotation.
+    duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US;
+
+    pwm_configure(&(dev->pwm_h),
+                  duty_cycle,
+                  PANTILT_PWM_PERIOD_US,
+                  PANTILT_PWM_CLOCK_FREQ_HZ);
+}
+
+/**
+ * pantilt_start_vertical
+ *
+ * Starts the vertical pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_start_vertical(pantilt_dev *dev) {
+    pwm_start(&(dev->pwm_v));
+}
+
+/**
+ * pantilt_start_horizontal
+ *
+ * Starts the horizontal pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_start_horizontal(pantilt_dev *dev) {
+    pwm_start(&(dev->pwm_h));
+}
+
+/**
+ * pantilt_stop_vertical
+ *
+ * Stops the vertical pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_stop_vertical(pantilt_dev *dev) {
+    pwm_stop(&(dev->pwm_v));
+}
+
+/**
+ * pantilt_stop_horizontal
+ *
+ * Stops the horizontal pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_stop_horizontal(pantilt_dev *dev) {
+    pwm_stop(&(dev->pwm_h));
+}

cs309-psoc/lab_1_2/sw/nios/application/pantilt/pantilt.h

@@ -0,0 +1,39 @@
+#ifndef __PANTILT_H__
+#define __PANTILT_H__
+
+#include "pwm/pwm.h"
+
+/* joysticks device structure */
+typedef struct pantilt_dev {
+    pwm_dev pwm_v; /* Vertical PWM device handle */
+    pwm_dev pwm_h; /* Horizontal PWM device handle */
+} pantilt_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+
+#define PANTILT_PWM_CLOCK_FREQ_HZ       (50000000) // 50.00 MHz
+
+#define PANTILT_PWM_PERIOD_US           (25000)    // 25.00 ms
+
+/* Vertical servo */
+#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950)      //  0.95 ms
+#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150)     //  2.15 ms
+
+/* Horizontal servo */
+#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000)     //  1.00 ms
+#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000)     //  2.00 ms
+
+pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base);
+
+void pantilt_init(pantilt_dev *dev);
+
+void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle);
+void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle);
+void pantilt_start_vertical(pantilt_dev *dev);
+void pantilt_start_horizontal(pantilt_dev *dev);
+void pantilt_stop_vertical(pantilt_dev *dev);
+void pantilt_stop_horizontal(pantilt_dev *dev);
+
+#endif /* __PANTILT_H__ */

cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm.c

@@ -0,0 +1,70 @@
+#include <io.h>
+
+#include "pwm.h"
+#include "pwm_regs.h"
+
+#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000))
+
+
+/**
+ * pwm_inst
+ *
+ * Instantiate a pwm device structure.
+ *
+ * @param base Base address of the component.
+ */
+pwm_dev pwm_inst(void *base) {
+    pwm_dev dev;
+
+    dev.base = base;
+
+    return dev;
+}
+
+/**
+ * pwm_init
+ *
+ * Initializes the pwm device. This function stops the controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_init(pwm_dev *dev) {
+    pwm_stop(dev);
+}
+
+/**
+ * pwm_configure
+ *
+ * Configure pwm component.
+ *
+ * @param dev pwm device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ * @param period pwm period in us.
+ * @param module_frequency frequency at which the component is clocked.
+ */
+void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) {
+	IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency));
+	IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency));
+}
+
+/**
+ * pwm_start
+ *
+ * Starts the pwm controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_start(pwm_dev *dev) {
+	IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK);
+}
+
+/**
+ * pwm_stop
+ *
+ * Stops the pwm controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_stop(pwm_dev *dev) {
+	IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK);
+}

cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm.h

@@ -0,0 +1,21 @@
+#ifndef __PWM_H__
+#define __PWM_H__
+
+#include <stdint.h>
+
+/* pwm device structure */
+typedef struct pwm_dev {
+    void *base; /* Base address of component */
+} pwm_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+pwm_dev pwm_inst(void *base);
+
+void pwm_init(pwm_dev *dev);
+void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency);
+void pwm_start(pwm_dev *dev);
+void pwm_stop(pwm_dev *dev);
+
+#endif /* __PWM_H__ */

cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm_regs.h

@@ -0,0 +1,11 @@
+#ifndef __PWM_REGS_H__
+#define __PWM_REGS_H__
+
+#define PWM_PERIOD_OFST     (0 * 4) /* RW */
+#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */
+#define PWM_CTRL_OFST       (2 * 4) /* WO */
+
+#define PWM_CTRL_STOP_MASK  (0)
+#define PWM_CTRL_START_MASK (1)
+
+#endif /* __PWM_REGS_H__ */

cs309-psoc/lab_2_0/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd

@@ -0,0 +1,203 @@
+-- #############################################################################
+-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
+--
+-- BOARD         : PrSoC extension board for DE0-Nano-SoC
+-- Author        : Florian Depraz based on Sahand Kashani-Akhavan work
+-- Revision      : 1.1
+-- Creation date : 06/02/2016
+--
+-- Syntax Rule : GROUP_NAME_N[bit]
+--
+-- GROUP : specify a particular interface (ex: SDR_)
+-- NAME  : signal name (ex: CONFIG, D, ...)
+-- bit   : signal index
+-- _N    : to specify an active-low signal
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity DE0_Nano_SoC_PrSoC_extn_board_top_level is
+    port(
+        -------------------------------
+        -- Comment ALL unused ports. --
+        -------------------------------
+
+        -- CLOCK
+        FPGA_CLK1_50 : in std_logic;
+     -- FPGA_CLK2_50 : in std_logic;
+     -- FPGA_CLK3_50 : in std_logic;
+
+        -- KEY on DE0 Nano SoC
+        KEY_N : in std_logic_vector(1 downto 0);
+
+        -- LEDs on DE0 Nano SoC
+     -- LED : out std_logic_vector(7 downto 0);
+
+        -- SWITCHES on DE0 Nano SoC
+     -- SW : in std_logic_vector(3 downto 0);
+
+        -- Servomotors pwm
+        SERVO_0 : out std_logic;
+        SERVO_1 : out std_logic;
+
+        -- ADC Joysticks
+        J0_SPI_CS_n : out std_logic;
+        J0_SPI_MOSI : out std_logic;
+        J0_SPI_MISO : in  std_logic;
+        J0_SPI_CLK  : out std_logic;
+
+        -- Lepton
+        CAM_TH_SPI_CS_N : out std_logic;
+        CAM_TH_MISO     : in  std_logic;
+        CAM_TH_MOSI     : out std_logic;
+        CAM_TH_CLK      : out std_logic
+
+        -- PCA9637
+     -- PIO_SCL   : inout std_logic;
+     -- PIO_SDA   : inout std_logic;
+     -- PIO_INT_N : in    std_logic;
+     -- RESET_N   : out   std_logic;
+
+        -- OV7670
+     -- CAM_D       : in  std_logic_vector(9 downto 0);
+     -- CAM_PIX_CLK : in  std_logic;
+     -- CAM_LV      : in  std_logic;
+     -- CAM_FV      : in  std_logic;
+     -- CAM_SYS_CLK : out std_logic;
+
+        -- VGA and LCD shared signals
+     -- VIDEO_CLK   : out std_logic;
+     -- VIDEO_VSYNC : out std_logic;
+     -- VIDEO_HSYNC : out std_logic;
+     -- VIDEO_B     : out std_logic_vector(7 downto 0);
+     -- VIDEO_G     : out std_logic_vector(7 downto 0);
+     -- VIDEO_R     : out std_logic_vector(7 downto 0);
+
+        -- LCD Specific signals
+     -- LCD_DE         : out   std_logic;
+     -- LCD_PIN_DAV_N  :       ? ?? std_logic;
+     -- LCD_DISPLAY_EN : out   std_logic;
+     -- SPI_MISO       : in    std_logic;
+     -- SPI_ENA_N      : out   std_logic;
+     -- SPI_CLK        : out   std_logic;
+     -- SPI_MOSI       : out   std_logic;
+     -- SPI_DAT        : inout std_logic;
+
+        -- I2C TOUCH SCREEN
+     -- TS_SCL : inout std_logic;
+     -- TS_SDA : inout std_logic;
+
+        -- BLUETOOTH (BLE)
+     -- BLT_TXD : in  std_logic;
+     -- BLT_RXD : out std_logic;
+
+        -- I2C For VGA, PAL and OV7670 cameras
+     -- CAM_PAL_VGA_SDA : inout std_logic;
+     -- CAM_PAL_VGA_SCL : inout std_logic;
+
+        -- ONE WIRE
+     -- BOARD_ID : inout std_logic;
+
+        -- PAL Camera
+     -- PAL_VD_VD   : in  std_logic_vector(7 downto 0);
+     -- PAL_VD_VSO  : in  std_logic;
+     -- PAL_VD_HSO  : in  std_logic;
+     -- PAL_VD_CLKO : in  std_logic;
+     -- PAL_PWDN    : out std_logic;
+
+        -- WIFI
+     -- FROM_ESP_TXD : in  std_logic;
+     -- TO_ESP_RXD   : out std_logic;
+
+        -- LED RGB
+     -- LED_BGR : out std_logic;
+
+        -- HPS
+     -- HPS_CONV_USB_N   : inout std_logic;
+     -- HPS_DDR3_ADDR    : out   std_logic_vector(14 downto 0);
+     -- HPS_DDR3_BA      : out   std_logic_vector(2 downto 0);
+     -- HPS_DDR3_CAS_N   : out   std_logic;
+     -- HPS_DDR3_CK_N    : out   std_logic;
+     -- HPS_DDR3_CK_P    : out   std_logic;
+     -- HPS_DDR3_CKE     : out   std_logic;
+     -- HPS_DDR3_CS_N    : out   std_logic;
+     -- HPS_DDR3_DM      : out   std_logic_vector(3 downto 0);
+     -- HPS_DDR3_DQ      : inout std_logic_vector(31 downto 0);
+     -- HPS_DDR3_DQS_N   : inout std_logic_vector(3 downto 0);
+     -- HPS_DDR3_DQS_P   : inout std_logic_vector(3 downto 0);
+     -- HPS_DDR3_ODT     : out   std_logic;
+     -- HPS_DDR3_RAS_N   : out   std_logic;
+     -- HPS_DDR3_RESET_N : out   std_logic;
+     -- HPS_DDR3_RZQ     : in    std_logic;
+     -- HPS_DDR3_WE_N    : out   std_logic;
+     -- HPS_ENET_GTX_CLK : out   std_logic;
+     -- HPS_ENET_INT_N   : inout std_logic;
+     -- HPS_ENET_MDC     : out   std_logic;
+     -- HPS_ENET_MDIO    : inout std_logic;
+     -- HPS_ENET_RX_CLK  : in    std_logic;
+     -- HPS_ENET_RX_DATA : in    std_logic_vector(3 downto 0);
+     -- HPS_ENET_RX_DV   : in    std_logic;
+     -- HPS_ENET_TX_DATA : out   std_logic_vector(3 downto 0);
+     -- HPS_ENET_TX_EN   : out   std_logic;
+     -- HPS_GSENSOR_INT  : inout std_logic;
+     -- HPS_I2C0_SCLK    : inout std_logic;
+     -- HPS_I2C0_SDAT    : inout std_logic;
+     -- HPS_I2C1_SCLK    : inout std_logic;
+     -- HPS_I2C1_SDAT    : inout std_logic;
+     -- HPS_KEY_N        : inout std_logic;
+     -- HPS_LED          : inout std_logic;
+     -- HPS_LTC_GPIO     : inout std_logic;
+     -- HPS_SD_CLK       : out   std_logic;
+     -- HPS_SD_CMD       : inout std_logic;
+     -- HPS_SD_DATA      : inout std_logic_vector(3 downto 0);
+     -- HPS_SPIM_CLK     : out   std_logic;
+     -- HPS_SPIM_MISO    : in    std_logic;
+     -- HPS_SPIM_MOSI    : out   std_logic;
+     -- HPS_SPIM_SS      : inout std_logic;
+     -- HPS_UART_RX      : in    std_logic;
+     -- HPS_UART_TX      : out   std_logic;
+     -- HPS_USB_CLKOUT   : in    std_logic;
+     -- HPS_USB_DATA     : inout std_logic_vector(7 downto 0);
+     -- HPS_USB_DIR      : in    std_logic;
+     -- HPS_USB_NXT      : in    std_logic;
+     -- HPS_USB_STP      : out   std_logic
+    );
+end entity DE0_Nano_SoC_PrSoC_extn_board_top_level;
+
+architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is
+    component soc_system is
+        port (
+            clk_clk                    : in  std_logic := 'X';
+            reset_reset_n              : in  std_logic := 'X';
+            pwm_0_conduit_end_pwm      : out std_logic;
+            pwm_1_conduit_end_pwm      : out std_logic;
+            mcp3204_0_conduit_end_cs_n : out std_logic;
+            mcp3204_0_conduit_end_mosi : out std_logic;
+            mcp3204_0_conduit_end_miso : in  std_logic := 'X';
+            mcp3204_0_conduit_end_sclk : out std_logic;
+            lepton_0_spi_cs_n          : out std_logic;
+            lepton_0_spi_mosi          : out std_logic;
+            lepton_0_spi_miso          : in  std_logic := 'X';
+            lepton_0_spi_sclk          : out std_logic
+        );
+    end component soc_system;
+
+begin
+    soc_system_inst : component soc_system
+    port map (
+        clk_clk                    => FPGA_CLK1_50,
+        reset_reset_n              => KEY_N(0),
+        pwm_0_conduit_end_pwm      => SERVO_0,
+        pwm_1_conduit_end_pwm      => SERVO_1,
+        mcp3204_0_conduit_end_cs_n => J0_SPI_CS_n,
+        mcp3204_0_conduit_end_mosi => J0_SPI_MOSI,
+        mcp3204_0_conduit_end_miso => J0_SPI_MISO,
+        mcp3204_0_conduit_end_sclk => J0_SPI_CLK,
+        lepton_0_spi_cs_n          => CAM_TH_SPI_CS_N,
+        lepton_0_spi_mosi          => CAM_TH_MOSI,
+        lepton_0_spi_miso          => CAM_TH_MISO,
+        lepton_0_spi_sclk          => CAM_TH_CLK
+    );
+
+end;

cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204.vhd

@@ -0,0 +1,138 @@
+-- #############################################################################
+-- mcp3204.vhd
+-- ===========
+-- MCP3204 Avalon-MM slave interface.
+--
+-- Register map
+-- +-------+-----------+--------+------------------------------------+
+-- | RegNo | Name      | Access | Description                        |
+-- +-------+-----------+--------+------------------------------------+
+-- | 0     | CHANNEL_0 | RO     | 12-bit digital value of channel 0. |
+-- +-------+-----------+--------+------------------------------------+
+-- | 1     | CHANNEL_1 | RO     | 12-bit digital value of channel 1. |
+-- +-------+-----------+--------+------------------------------------+
+-- | 2     | CHANNEL_2 | RO     | 12-bit digital value of channel 2. |
+-- +-------+-----------+--------+------------------------------------+
+-- | 3     | CHANNEL_3 | RO     | 12-bit digital value of channel 3. |
+-- +-------+-----------+--------+------------------------------------+
+--
+-- Author        : Philémon Favrod [philemon.favrod@epfl.ch]
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 2
+-- Last modified : 2018-03-06
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity mcp3204 is
+    port(
+        -- Avalon Clock interface
+        clk : in std_logic;
+
+        -- Avalon Reset interface
+        reset : in std_logic;
+
+        -- Avalon-MM Slave interface
+        address  : in  std_logic_vector(1 downto 0);
+        read     : in  std_logic;
+        readdata : out std_logic_vector(31 downto 0);
+
+        -- Avalon Conduit interface
+        CS_N : out std_logic;
+        MOSI : out std_logic;
+        MISO : in  std_logic;
+        SCLK : out std_logic
+    );
+end entity;
+
+architecture arch of mcp3204 is
+    constant NUM_CHANNELS  : positive := 4;
+    constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS))));
+
+    type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range);
+    signal data_reg : data_array;
+
+    signal spi_busy, spi_start, spi_datavalid : std_logic;
+    signal spi_channel                        : std_logic_vector(1 downto 0);
+    signal spi_data                           : std_logic_vector(11 downto 0);
+
+    type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA);
+    signal state : state_t;
+
+    signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0);
+
+begin
+    SPI : entity work.mcp3204_spi
+    port map(
+        clk        => clk,
+        reset      => reset,
+        busy       => spi_busy,
+        start      => spi_start,
+        channel    => spi_channel,
+        data_valid => spi_datavalid,
+        data       => spi_data,
+        SCLK       => SCLK,
+        CS_N       => CS_N,
+        MOSI       => MOSI,
+        MISO       => MISO
+    );
+
+    -- FSM that dictates which channel is being read. The state of the component
+    -- should be thought as the pair (state, channel)
+    p_fsm : process(reset, clk)
+    begin
+        if reset = '1' then
+            state   <= READY;
+            channel <= (others => '0');
+        elsif rising_edge(clk) then
+            case state is
+                when READY =>
+                    if spi_busy = '0' then
+                        state <= INIT_READ_CHANNEL;
+                    end if;
+
+                when INIT_READ_CHANNEL =>
+                    state <= WAIT_FOR_DATA;
+
+                when WAIT_FOR_DATA =>
+                    if spi_datavalid = '1' then
+                        state   <= READY;
+                        channel <= channel + 1;
+                    end if;
+            end case;
+        end if;
+    end process p_fsm;
+
+    -- Updates the internal registers when a new data is available
+    p_data : process(reset, clk)
+    begin
+        if reset = '1' then
+            for i in 0 to NUM_CHANNELS - 1 loop
+                data_reg(i) <= (others => '0');
+            end loop;
+        elsif rising_edge(clk) then
+            if state = WAIT_FOR_DATA and spi_datavalid = '1' then
+                data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data;
+            end if;
+        end if;
+    end process p_data;
+
+    spi_start   <= '1' when state = INIT_READ_CHANNEL else '0';
+    spi_channel <= std_logic_vector(channel);
+
+    -- Interface with the Avalon Switch Fabric
+    p_avalon_read : process(reset, clk)
+    begin
+        if reset = '1' then
+            readdata <= (others => '0');
+        elsif rising_edge(clk) then
+            if read = '1' then
+                readdata <= data_reg(to_integer(unsigned(address)));
+            end if;
+        end if;
+    end process p_avalon_read;
+
+end architecture;

cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl

@@ -0,0 +1,137 @@
+# TCL File Generated by Component Editor 16.0
+# Sun Feb 05 18:14:06 CET 2017
+# DO NOT MODIFY
+
+
+#
+# mcp3204 "mcp3204" v1.0
+# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.18:14:06
+# 4-Channel 12-Bit A/D Converter with SPI Serial Interface
+#
+
+#
+# request TCL package from ACDS 16.0
+#
+package require -exact qsys 16.0
+
+
+#
+# module mcp3204
+#
+set_module_property DESCRIPTION "4-Channel 12-Bit A/D Converter with SPI Serial Interface"
+set_module_property NAME mcp3204
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP Joystick
+set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan"
+set_module_property DISPLAY_NAME mcp3204
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL mcp3204
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file mcp3204.vhd VHDL PATH mcp3204.vhd TOP_LEVEL_FILE
+add_fileset_file mcp3204_spi.vhd VHDL PATH mcp3204_spi.vhd
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point clock
+#
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+#
+# connection point reset
+#
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+#
+# connection point avalon_slave_0
+#
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+
+
+#
+# connection point conduit_end
+#
+add_interface conduit_end conduit end
+set_interface_property conduit_end associatedClock clock
+set_interface_property conduit_end associatedReset ""
+set_interface_property conduit_end ENABLED true
+set_interface_property conduit_end EXPORT_OF ""
+set_interface_property conduit_end PORT_NAME_MAP ""
+set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end CS_N cs_n Output 1
+add_interface_port conduit_end MOSI mosi Output 1
+add_interface_port conduit_end MISO miso Input 1
+add_interface_port conduit_end SCLK sclk Output 1
+

cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd

@@ -0,0 +1,87 @@
+-- #############################################################################
+-- mcp3204_spi.vhd
+-- ===============
+-- MCP3204 SPI interface.
+--
+-- Author        : Philémon Favrod [philemon.favrod@epfl.ch]
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Author        : <insert your name> (<insert your e-mail address>)
+-- Revision      : 1
+-- Last modified : <insert date>
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mcp3204_spi is
+    port(
+        -- 50 MHz
+        clk        : in  std_logic;
+        reset      : in  std_logic;
+        busy       : out std_logic;
+        start      : in  std_logic;
+        channel    : in  std_logic_vector(1 downto 0);
+        data_valid : out std_logic;
+        data       : out std_logic_vector(11 downto 0);
+
+        -- 1 MHz
+        SCLK : out std_logic;
+        CS_N : out std_logic;
+        MOSI : out std_logic;
+        MISO : in  std_logic
+    );
+end mcp3204_spi;
+
+architecture rtl of mcp3204_spi is
+    signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0');  -- need to be able to count until 24
+    signal reg_spi_en              : std_logic            := '0';  -- pulses every 0.5 MHz
+    signal reg_rising_edge_sclk    : std_logic            := '0';
+    signal reg_falling_edge_sclk   : std_logic            := '0';
+
+    signal reg_sclk : std_logic := '0';
+
+begin
+    clk_divider_generation : process(clk, reset)
+    begin
+        if reset = '1' then
+            reg_clk_divider_counter <= (others => '0');
+        elsif rising_edge(clk) then
+            reg_clk_divider_counter <= reg_clk_divider_counter + 1;
+            reg_spi_en              <= '0';
+            reg_rising_edge_sclk    <= '0';
+            reg_falling_edge_sclk   <= '0';
+
+            if reg_clk_divider_counter = 24 then
+                reg_clk_divider_counter <= (others => '0');
+                reg_spi_en              <= '1';
+
+                if reg_sclk = '0' then
+                    reg_rising_edge_sclk <= '1';
+                elsif reg_sclk = '1' then
+                    reg_falling_edge_sclk <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    SCLK_generation : process(clk, reset)
+    begin
+        if reset = '1' then
+            reg_sclk <= '0';
+        elsif rising_edge(clk) then
+            if reg_spi_en = '1' then
+                reg_sclk <= not reg_sclk;
+            end if;
+        end if;
+    end process;
+
+    STATE_LOGIC : process(clk, reset)
+    begin
+        -- TODO: complete this process
+        if reset = '1' then
+        elsif rising_edge(clk) then
+        end if;
+    end process;
+
+end architecture rtl;

cs309-psoc/lab_2_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd

@@ -0,0 +1,103 @@
+-- #############################################################################
+-- tb_mcp3204_spi.vhd
+-- ==================
+-- Testbench for MCP3204 SPI interface.
+--
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 1
+-- Last modified : 2018-03-06
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_mcp3204_spi is
+end entity;
+
+architecture rtl of tb_mcp3204_spi is
+    constant CLK_PERIOD : time      := 20 ns;
+    signal clk          : std_logic := '0';
+    signal reset        : std_logic := '0';
+    signal sim_finished : boolean   := false;
+
+    -- mcp3204_spi ------------------------------------------------------------
+    signal busy       : std_logic                     := '0';
+    signal start      : std_logic                     := '0';
+    signal channel    : std_logic_vector(1 downto 0)  := (others => '0');
+    signal data_valid : std_logic                     := '0';
+    signal data       : std_logic_vector(11 downto 0) := (others => '0');
+    signal SCLK       : std_logic                     := '0';
+    signal CS_N       : std_logic                     := '1';
+    signal MOSI       : std_logic                     := '0';
+    signal MISO       : std_logic                     := '0';
+
+begin
+    duv : entity work.mcp3204_spi
+    port map(
+        clk        => clk,
+        reset      => reset,
+        busy       => busy,
+        start      => start,
+        channel    => channel,
+        data_valid => data_valid,
+        data       => data,
+        SCLK       => SCLK,
+        CS_N       => CS_N,
+        MOSI       => MOSI,
+        MISO       => MISO
+    );
+
+    clk <= not clk after CLK_PERIOD / 2 when not sim_finished;
+
+    sim : process
+        procedure async_reset is
+        begin
+            wait until rising_edge(clk);
+            wait for CLK_PERIOD / 4;
+            reset <= '1';
+
+            wait for CLK_PERIOD / 2;
+            reset <= '0';
+        end procedure async_reset;
+
+        procedure spi_transfer(constant channel_number : natural range 0 to 3) is
+        begin
+            if busy = '1' then
+                wait until busy = '0';
+
+            else
+                wait until falling_edge(clk);
+                start   <= '1';
+                channel <= std_logic_vector(to_unsigned(channel_number, channel'length));
+
+                wait until falling_edge(clk);
+                start   <= '0';
+                channel <= (others => '0');
+
+                wait until rising_edge(data_valid);
+                wait until falling_edge(busy);
+            end if;
+        end procedure spi_transfer;
+
+    begin
+        async_reset;
+
+        MISO <= '1';
+        spi_transfer(0);
+
+        MISO <= '0';
+        spi_transfer(1);
+
+        MISO <= '1';
+        spi_transfer(2);
+
+        MISO <= '0';
+        spi_transfer(3);
+
+        sim_finished <= true;
+        wait;
+    end process sim;
+end architecture rtl;
+
+

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd

@@ -0,0 +1,139 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.utils.all;
+
+entity avalon_st_spi_master is
+    generic(
+        INPUT_CLK_FREQ : integer := 50000000;
+        SPI_SCLK_FREQ  : integer := 10000000;
+        CPOL           : integer := 1;
+        CPHA           : integer := 1
+    );
+    port(
+        -- Input clock
+        clk : in std_logic;
+
+        -- Reset
+        reset           : in  std_logic;
+        spi_cs_n        : in  std_logic;
+        -- Sink Avalon ST Interface
+        mosi_sink_data  : in  std_logic_vector(7 downto 0);
+        mosi_sink_valid : in  std_logic;
+        mosi_sink_ready : out std_logic;
+
+        -- Source Avalon ST Interface
+        miso_src_data  : out std_logic_vector(7 downto 0);
+        miso_src_valid : out std_logic;
+
+        -- SPI Master signals
+        SCLK : out std_logic;
+        MISO : in  std_logic;
+        MOSI : out std_logic;
+        CS_n : out std_logic
+    );
+end avalon_st_spi_master;
+
+architecture rtl of avalon_st_spi_master is
+    constant SCLK_PRESCALER_MAX : integer := INPUT_CLK_FREQ / SPI_SCLK_FREQ / 2;
+    signal sclk_prescaler       : unsigned(bitlength(SCLK_PRESCALER_MAX) downto 0);
+    signal sclk_toggle          : std_logic;
+
+    signal new_sink_buffer, cur_sink_buffer           : std_logic_vector(mosi_sink_data'range);
+    signal new_sink_buffer_busy, cur_sink_buffer_busy : std_logic;
+
+    signal miso_src_buffer : std_logic_vector(7 downto 0);
+
+    signal spi_done, i_sclk : std_logic;
+    signal spi_bit_index    : unsigned(2 downto 0);
+begin
+    CS_n <= spi_cs_n;
+
+    p_sclk_prescaler : process(clk, reset) is
+    begin
+        if reset = '1' then
+            sclk_prescaler <= to_unsigned(1, sclk_prescaler'length);
+        elsif rising_edge(clk) then
+            if sclk_prescaler = SCLK_PRESCALER_MAX then
+                sclk_prescaler <= to_unsigned(1, sclk_prescaler'length);
+            else
+                sclk_prescaler <= sclk_prescaler + 1;
+            end if;
+        end if;
+    end process p_sclk_prescaler;
+    sclk_toggle <= '1' when sclk_prescaler = SCLK_PRESCALER_MAX else '0';
+
+    p_avalon_st_sink : process(clk, reset) is
+    begin
+        if reset = '1' then
+            new_sink_buffer_busy <= '0';
+            new_sink_buffer      <= (others => '0');
+        elsif rising_edge(clk) then
+            if mosi_sink_valid = '1' then
+                if new_sink_buffer_busy = '0' and cur_sink_buffer_busy = '1' then
+                    new_sink_buffer      <= mosi_sink_data;
+                    new_sink_buffer_busy <= '1';
+                end if;
+            elsif new_sink_buffer_busy = '1' and cur_sink_buffer_busy = '0' then
+                new_sink_buffer_busy <= '0';
+            end if;
+        end if;
+    end process p_avalon_st_sink;
+    mosi_sink_ready <= not new_sink_buffer_busy;
+
+    p_cur_buffer : process(clk, reset) is
+    begin
+        if reset = '1' then
+            cur_sink_buffer      <= (others => '0');
+            cur_sink_buffer_busy <= '0';
+        elsif rising_edge(clk) then
+            if mosi_sink_valid = '1' and cur_sink_buffer_busy = '0' then
+                cur_sink_buffer      <= mosi_sink_data;
+                cur_sink_buffer_busy <= '1';
+            elsif cur_sink_buffer_busy = '0' and new_sink_buffer_busy = '1' then
+                cur_sink_buffer      <= new_sink_buffer;
+                cur_sink_buffer_busy <= '1';
+            elsif cur_sink_buffer_busy = '1' and spi_done = '1' then
+                cur_sink_buffer_busy <= '0';
+            end if;
+        end if;
+    end process p_cur_buffer;
+
+    p_spi : process(clk, reset) is
+    begin
+        if reset = '1' then
+            spi_done        <= '0';
+            i_sclk          <= to_unsigned(CPOL, 1)(0);
+            spi_bit_index   <= "000";
+            MOSI            <= '0';
+            miso_src_data   <= (others => '0');
+            miso_src_valid  <= '0';
+            miso_src_buffer <= (others => '0');
+
+        elsif rising_edge(clk) then
+            spi_done       <= '0';
+            miso_src_valid <= '0';
+            if cur_sink_buffer_busy = '1' and sclk_toggle = '1' then
+                if i_sclk /= to_unsigned(CPHA, 1)(0) then
+                    if spi_bit_index = "111" then
+                        spi_done       <= '1';
+                        spi_bit_index  <= "000";
+                        miso_src_valid <= '1';
+                        miso_src_data  <= miso_src_buffer(7 downto 1) & MISO;
+                    else
+                        MOSI                                           <= cur_sink_buffer(7 - to_integer(spi_bit_index));
+                        miso_src_buffer(7 - to_integer(spi_bit_index)) <= MISO;
+                        spi_bit_index                                  <= spi_bit_index + 1;
+
+                    end if;
+
+                end if;
+
+                i_sclk <= not i_sclk;
+
+            end if;
+        end if;
+    end process p_spi;
+    SCLK <= i_sclk;
+
+end rtl;

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/byte2pix.vhd

@@ -0,0 +1,87 @@
+-------------------------------------------------------------------------------
+-- Title      : Byte stream to pixel converter for the Lepton Camera
+-- Project    : PrSoC
+-------------------------------------------------------------------------------
+-- File       : byte2pix.vhd
+-- Author     : Philemon Orphee Favrod  <pofavrod@lappc5.epfl.ch>
+-- Company    :
+-- Created    : 2016-03-21
+-- Last update: 2017-03-19
+-- Platform   :
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Converts a byte stream to a 14-bit pixel stream.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2016
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2016-03-21  1.0      pofavrod        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity byte2pix is
+    port(
+        clk, reset : in  std_logic;
+        byte_data  : in  std_logic_vector(7 downto 0);
+        byte_valid : in  std_logic;
+        byte_sof   : in  std_logic;
+        byte_eof   : in  std_logic;
+        pix_data   : out std_logic_vector(13 downto 0);
+        pix_valid  : out std_logic;
+        pix_sof    : out std_logic;
+        pix_eof    : out std_logic);
+
+end byte2pix;
+
+architecture rtl of byte2pix is
+    signal last_sof : std_logic;
+    signal msb      : std_logic_vector(5 downto 0);
+    signal cnt      : std_logic;  -- used to skip msb sampling every other time
+begin
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            msb      <= (others => '0');
+            cnt      <= '0';
+            last_sof <= '0';
+        elsif rising_edge(clk) then
+            if byte_valid = '1' then
+                if cnt = '0' then
+                    msb      <= byte_data(5 downto 0);
+                    last_sof <= byte_sof;
+                end if;
+                cnt <= not cnt;
+            end if;
+        end if;
+    end process;
+
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            pix_data  <= (others => '0');
+            pix_valid <= '0';
+            pix_sof   <= '0';
+            pix_eof   <= '0';
+        elsif rising_edge(clk) then
+            pix_data  <= (others => '0');
+            pix_valid <= '0';
+            pix_sof   <= '0';
+            pix_eof   <= '0';
+
+            if byte_valid = '1' then
+                if cnt = '1' then
+                    pix_data  <= msb & byte_data;
+                    pix_valid <= '1';
+                    pix_sof   <= last_sof;
+                    pix_eof   <= byte_eof;
+                end if;
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd

@@ -0,0 +1,192 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: dual_ported_ram.vhd
+-- Megafunction Name(s):
+--                      altsyncram
+--
+-- Simulation Library Files(s):
+--                      altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus Prime License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library altera_mf;
+use altera_mf.altera_mf_components.all;
+
+entity dual_ported_ram is
+    port(
+        clock     : in  std_logic := '1';
+        data      : in  std_logic_vector(15 downto 0);
+        rdaddress : in  std_logic_vector(12 downto 0);
+        wraddress : in  std_logic_vector(12 downto 0);
+        wren      : in  std_logic := '0';
+        q         : out std_logic_vector(15 downto 0)
+    );
+end dual_ported_ram;
+
+architecture SYN of dual_ported_ram is
+    signal sub_wire0 : std_logic_vector(15 downto 0);
+
+begin
+    q <= sub_wire0(15 downto 0);
+
+    altsyncram_component : altsyncram
+    generic map(
+        address_aclr_b                     => "NONE",
+        address_reg_b                      => "CLOCK0",
+        clock_enable_input_a               => "BYPASS",
+        clock_enable_input_b               => "BYPASS",
+        clock_enable_output_b              => "BYPASS",
+        intended_device_family             => "Cyclone V",
+        lpm_type                           => "altsyncram",
+        numwords_a                         => 8192,
+        numwords_b                         => 8192,
+        operation_mode                     => "DUAL_PORT",
+        outdata_aclr_b                     => "NONE",
+        outdata_reg_b                      => "CLOCK0",
+        power_up_uninitialized             => "FALSE",
+        read_during_write_mode_mixed_ports => "DONT_CARE",
+        widthad_a                          => 13,
+        widthad_b                          => 13,
+        width_a                            => 16,
+        width_b                            => 16,
+        width_byteena_a                    => 1
+    )
+    port map(
+        address_a => wraddress,
+        address_b => rdaddress,
+        clock0    => clock,
+        data_a    => data,
+        wren_a    => wren,
+        q_b       => sub_wire0
+    );
+
+end SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]"
+-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
+-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton.vhd

@@ -0,0 +1,288 @@
+-- Lepton Avalon Memory-Mapped Slave Interface
+-- Author: Philémon Favrod (philemon.favrod@epfl.ch)
+-- Modified by: Sahand Kashani-Akhavan (sahand.kashani-akhavan@epfl.ch)
+-- Revision: 2
+
+-- Register map
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- | RegNo         | Name            | Access | Description                                       |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |             0 | COMMAND         | WO     | Command                                           |
+-- |               |                 |        | - Writing 1 starts capturing a frame & resets the |
+-- |               |                 |        |   ERROR bit (bit 1) in the STATUS register.       |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |             1 | STATUS          | RO     | Status                                            |
+-- |               |                 |        | - Bit 0: 0 --> no capture in progress.            |
+-- |               |                 |        |          1 --> capture in progress.               |
+-- |               |                 |        | - Bit 1: 0 --> previous capture successful.       |
+-- |               |                 |        |          1 --> error during previous capture.     |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |             2 | MIN             | RO     | Minimum pixel value in frame.                     |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |             3 | MAX             | RO     | Maximum pixel value in frame.                     |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |             4 | SUM_LSB         | RO     | Sum of all pixels in frame (low 16 bits).         |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |             5 | SUM_MSB         | RO     | Sum of all pixels in frame (high 16 bits).        |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |             6 | ROW_IDX         | RO     | Current line being captured (1 <= ROW_IDX <= 60). |
+-- |               |                 |        | Available for debugging purposes.                 |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |             7 | RESERVED        | -      | Reserved                                          |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |     8 -  4807 | RAW BUFFER      | RO     | View into RAW pixel buffer.                       |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |  4808 -  8191 | RESERVED        | -      | Reserved                                          |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- |  8192 - 12991 | ADJUSTED BUFFER | RO     | View into adjusted (scaled) pixel buffer.         |
+-- |               |                 |        | Values are scaled between MIN and MAX.            |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+-- | 12992 - 16383 | RESERVED        | -      | Reserved                                          |
+-- +---------------+-----------------+--------+---------------------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity lepton is
+    port(
+        clk       : in  std_logic;
+        reset     : in  std_logic;
+        address   : in  std_logic_vector(13 downto 0);
+        readdata  : out std_logic_vector(15 downto 0);
+        writedata : in  std_logic_vector(15 downto 0);
+        read      : in  std_logic;
+        write     : in  std_logic;
+
+        SCLK : out std_logic;
+        CSn  : out std_logic;
+        MOSI : out std_logic;
+        MISO : in  std_logic
+    );
+
+end lepton;
+
+architecture rtl of lepton is
+    signal spi_cs_n             : std_logic;
+    signal spi_mosi_data        : std_logic_vector(7 downto 0);
+    signal spi_mosi_valid       : std_logic;
+    signal spi_mosi_ready       : std_logic;
+    signal spi_miso_data        : std_logic_vector(7 downto 0);
+    signal spi_miso_valid       : std_logic;
+    signal lepton_manager_start : std_logic;
+    signal lepton_manager_error : std_logic;
+    signal byte_data            : std_logic_vector(7 downto 0);
+    signal byte_valid           : std_logic;
+    signal byte_sof             : std_logic;
+    signal byte_eof             : std_logic;
+    signal pix_data             : std_logic_vector(13 downto 0);
+    signal pix_valid            : std_logic;
+    signal pix_sof              : std_logic;
+    signal pix_eof              : std_logic;
+    signal stat_min             : std_logic_vector(13 downto 0);
+    signal stat_max             : std_logic_vector(13 downto 0);
+    signal stat_sum             : std_logic_vector(26 downto 0);
+    signal stat_valid           : std_logic;
+    signal ram_data             : std_logic_vector(15 downto 0);
+    signal ram_wren             : std_logic;
+    signal ram_wraddress        : std_logic_vector(12 downto 0);
+    signal ram_rdaddress        : std_logic_vector(12 downto 0);
+    signal ram_q                : std_logic_vector(15 downto 0);
+    signal row_idx              : std_logic_vector(5 downto 0);
+    signal raw_pixel            : std_logic_vector(13 downto 0);
+    signal raw_max              : std_logic_vector(13 downto 0);
+    signal raw_min              : std_logic_vector(13 downto 0);
+    signal raw_sum              : std_logic_vector(26 downto 0);
+    signal adjusted_pixel       : std_logic_vector(13 downto 0);
+
+    constant COMMAND_REG_OFFSET         : std_logic_vector(address'range) := "00000000000000";
+    constant STATUS_REG_OFFSET          : std_logic_vector(address'range) := "00000000000001";
+    constant MIN_REG_OFFSET             : std_logic_vector(address'range) := "00000000000010";
+    constant MAX_REG_OFFSET             : std_logic_vector(address'range) := "00000000000011";
+    constant SUM_LSB_REG_OFFSET         : std_logic_vector(address'range) := "00000000000100";
+    constant SUM_MSB_REG_OFFSET         : std_logic_vector(address'range) := "00000000000101";
+    constant ROW_IDX_REG_OFFSET         : std_logic_vector(address'range) := "00000000000110";
+    constant BUFFER_REG_OFFSET          : unsigned(address'range)         := "00000000001000";
+    constant ADJUSTED_BUFFER_REG_OFFSET : unsigned(address'range)         := "10000000000000";
+
+    constant IMAGE_SIZE       : integer                 := 80 * 60;
+    constant BUFFER_REG_LIMIT : unsigned(address'range) := unsigned(BUFFER_REG_OFFSET) + IMAGE_SIZE;
+
+    constant ADJUSTED_BUFFER_LIMIT : unsigned(address'range) := unsigned(ADJUSTED_BUFFER_REG_OFFSET) + IMAGE_SIZE;
+
+    signal max_reg   : std_logic_vector(stat_max'range);
+    signal min_reg   : std_logic_vector(stat_min'range);
+    signal sum_reg   : std_logic_vector(stat_sum'range);
+    signal error_reg : std_logic;
+
+begin
+    spi_controller0 : entity work.avalon_st_spi_master
+    port map(
+        clk             => clk,
+        reset           => reset,
+        spi_cs_n        => spi_cs_n,
+        mosi_sink_data  => spi_mosi_data,
+        mosi_sink_valid => spi_mosi_valid,
+        mosi_sink_ready => spi_mosi_ready,
+        miso_src_data   => spi_miso_data,
+        miso_src_valid  => spi_miso_valid,
+        SCLK            => SCLK,
+        MISO            => MISO,
+        MOSI            => MOSI,
+        CS_n            => CSn
+    );
+
+    lepton_manager0 : entity work.lepton_manager
+    port map(
+        clk                 => clk,
+        reset               => reset,
+        spi_miso_sink_data  => spi_miso_data,
+        spi_miso_sink_valid => spi_miso_valid,
+        spi_mosi_src_data   => spi_mosi_data,
+        spi_mosi_src_valid  => spi_mosi_valid,
+        spi_mosi_src_ready  => spi_mosi_ready,
+        lepton_out_data     => byte_data,
+        lepton_out_valid    => byte_valid,
+        lepton_out_sof      => byte_sof,
+        lepton_out_eof      => byte_eof,
+        row_idx             => row_idx,
+        error               => lepton_manager_error,
+        start               => lepton_manager_start,
+        spi_cs_n            => spi_cs_n
+    );
+
+    byte2pix0 : entity work.byte2pix
+    port map(
+        clk        => clk,
+        reset      => reset,
+        byte_data  => byte_data,
+        byte_valid => byte_valid,
+        byte_sof   => byte_sof,
+        byte_eof   => byte_eof,
+        pix_data   => pix_data,
+        pix_valid  => pix_valid,
+        pix_sof    => pix_sof,
+        pix_eof    => pix_eof
+    );
+
+    lepton_stats0 : entity work.lepton_stats
+    port map(
+        reset      => reset,
+        clk        => clk,
+        pix_data   => pix_data,
+        pix_valid  => pix_valid,
+        pix_sof    => pix_sof,
+        pix_eof    => pix_eof,
+        stat_min   => stat_min,
+        stat_max   => stat_max,
+        stat_sum   => stat_sum,
+        stat_valid => stat_valid
+    );
+
+    ram_writer0 : entity work.ram_writer
+    port map(
+        clk           => clk,
+        reset         => reset,
+        pix_data      => pix_data,
+        pix_valid     => pix_valid,
+        pix_sof       => pix_sof,
+        pix_eof       => pix_eof,
+        ram_data      => ram_data,
+        ram_wren      => ram_wren,
+        ram_wraddress => ram_wraddress
+    );
+
+    dual_ported_ram0 : entity work.dual_ported_ram
+    port map(
+        clock     => clk,
+        data      => ram_data,
+        rdaddress => ram_rdaddress,
+        wraddress => ram_wraddress,
+        wren      => ram_wren,
+        q         => ram_q
+    );
+
+    level_adjuster0 : entity work.level_adjuster
+    port map(
+        clk            => clk,
+        raw_pixel      => ram_q(13 downto 0),
+        raw_max        => max_reg,
+        raw_min        => min_reg,
+        raw_sum        => sum_reg,
+        adjusted_pixel => adjusted_pixel
+    );
+
+    p_lepton_start : process(clk, reset)
+    begin
+        if reset = '1' then
+            lepton_manager_start <= '0';
+            error_reg            <= '0';
+        elsif rising_edge(clk) then
+            if write = '1' and address = COMMAND_REG_OFFSET then
+                lepton_manager_start <= writedata(0);
+                error_reg            <= '0';
+            elsif pix_eof = '1' then
+                lepton_manager_start <= '0';
+            elsif lepton_manager_error = '1' then
+                error_reg <= '1';
+            end if;
+        end if;
+    end process p_lepton_start;
+
+    p_stat_reg : process(clk, reset)
+    begin
+        if reset = '1' then
+            min_reg <= (others => '0');
+            max_reg <= (others => '0');
+            sum_reg <= (others => '0');
+        elsif rising_edge(clk) then
+            if stat_valid = '1' then
+                min_reg <= stat_min;
+                max_reg <= stat_max;
+                sum_reg <= stat_sum;
+            end if;
+        end if;
+    end process p_stat_reg;
+
+    p_read : process(clk, reset)
+    begin
+        if reset = '1' then
+            readdata      <= (others => '0');
+            ram_rdaddress <= (others => '0');
+        elsif rising_edge(clk) then
+            readdata <= (others => '0');
+            if read = '1' then
+                case address is
+                    when STATUS_REG_OFFSET =>
+                        readdata(1) <= error_reg;
+                        readdata(0) <= lepton_manager_start;
+
+                    when MIN_REG_OFFSET =>
+                        readdata <= "00" & min_reg;
+
+                    when MAX_REG_OFFSET =>
+                        readdata <= "00" & max_reg;
+
+                    when SUM_MSB_REG_OFFSET =>
+                        readdata <= "00000" & sum_reg(26 downto 16);
+
+                    when SUM_LSB_REG_OFFSET =>
+                        readdata <= sum_reg(15 downto 0);
+
+                    when ROW_IDX_REG_OFFSET =>
+                        readdata(5 downto 0) <= row_idx;
+
+                    when others =>
+                        if unsigned(address) >= BUFFER_REG_OFFSET and unsigned(address) < BUFFER_REG_LIMIT then
+                            ram_rdaddress <= std_logic_vector(resize(unsigned(address) - BUFFER_REG_OFFSET, ram_rdaddress'length));
+                            readdata      <= ram_q;
+                        elsif unsigned(address) >= ADJUSTED_BUFFER_REG_OFFSET and unsigned(address) < ADJUSTED_BUFFER_LIMIT then
+                            ram_rdaddress <= std_logic_vector(resize(unsigned(address) - ADJUSTED_BUFFER_REG_OFFSET, ram_rdaddress'length));
+                            readdata      <= "00" & adjusted_pixel;
+                        end if;
+                end case;
+            end if;
+        end if;
+    end process p_read;
+
+end rtl;

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_hw.tcl

@@ -0,0 +1,148 @@
+# TCL File Generated by Component Editor 16.0
+# Sun Feb 05 19:05:24 CET 2017
+# DO NOT MODIFY
+
+
+#
+# lepton "lepton" v1.0
+# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.19:05:24
+# IR Camera 80x60
+#
+
+#
+# request TCL package from ACDS 16.0
+#
+package require -exact qsys 16.0
+
+
+#
+# module lepton
+#
+set_module_property DESCRIPTION "IR Camera 80x60"
+set_module_property NAME lepton
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP Camera
+set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan"
+set_module_property DISPLAY_NAME lepton
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL lepton
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file avalon_st_spi_master.vhd VHDL PATH avalon_st_spi_master.vhd
+add_fileset_file byte2pix.vhd VHDL PATH byte2pix.vhd
+add_fileset_file dual_ported_ram.vhd VHDL PATH dual_ported_ram.vhd
+add_fileset_file lepton.vhd VHDL PATH lepton.vhd TOP_LEVEL_FILE
+add_fileset_file lepton_manager.vhd VHDL PATH lepton_manager.vhd
+add_fileset_file lepton_stats.vhd VHDL PATH lepton_stats.vhd
+add_fileset_file ram_writer.vhd VHDL PATH ram_writer.vhd
+add_fileset_file utils.vhd VHDL PATH utils.vhd
+add_fileset_file level_adjuster.vhd VHDL PATH level_adjuster.vhd
+add_fileset_file lpm_divider.vhd VHDL PATH lpm_divider.vhd
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point clock
+#
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+#
+# connection point reset
+#
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+#
+# connection point avalon_slave_0
+#
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitStates 9
+set_interface_property avalon_slave_0 readWaitTime 9
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 14
+add_interface_port avalon_slave_0 readdata readdata Output 16
+add_interface_port avalon_slave_0 writedata writedata Input 16
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 write write Input 1
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+
+
+#
+# connection point spi
+#
+add_interface spi conduit end
+set_interface_property spi associatedClock clock
+set_interface_property spi associatedReset ""
+set_interface_property spi ENABLED true
+set_interface_property spi EXPORT_OF ""
+set_interface_property spi PORT_NAME_MAP ""
+set_interface_property spi CMSIS_SVD_VARIABLES ""
+set_interface_property spi SVD_ADDRESS_GROUP ""
+
+add_interface_port spi CSn cs_n Output 1
+add_interface_port spi MISO miso Input 1
+add_interface_port spi MOSI mosi Output 1
+add_interface_port spi SCLK sclk Output 1
+

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_manager.vhd

@@ -0,0 +1,235 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity lepton_manager is
+    generic(
+        INPUT_CLK_FREQ : integer := 50000000);
+    port(
+        clk   : in std_logic := '0';
+        reset : in std_logic := '0';
+
+        -- Avalon ST Sink to receive SPI data
+        spi_miso_sink_data  : in std_logic_vector(7 downto 0);
+        spi_miso_sink_valid : in std_logic;
+
+        -- Avalon ST Source to send SPI data
+        spi_mosi_src_data  : out std_logic_vector(7 downto 0);
+        spi_mosi_src_valid : out std_logic;
+        spi_mosi_src_ready : in  std_logic := '0';
+
+        -- Filtered output to retransmit cleaned data (without the discard packets, see Lepton Datasheet on page 31)
+        -- lepton_out_data is valid on rising edge when lepton_src_valid = '1'
+        lepton_out_data  : out std_logic_vector(7 downto 0);
+        lepton_out_valid : out std_logic;
+        lepton_out_sof   : out std_logic;
+        lepton_out_eof   : out std_logic;
+
+        -- Some status
+        row_idx : out std_logic_vector(5 downto 0);
+        error   : out std_logic;
+
+        -- Avalon MM Slave interface for configuration
+        start : in std_logic;
+
+        -- The SPI Chip Select (Active low !)
+        spi_cs_n : out std_logic := '0');
+end entity lepton_manager;
+
+architecture rtl of lepton_manager is
+    type state_t is (Idle, CSn, ReadHeader, ReadPayload, DiscardPayload, WaitBeforeIdle);
+    signal state, next_state : state_t;
+
+    signal header_3_last_nibbles : std_logic_vector(11 downto 0);
+
+    constant CLOCK_TICKS_PER_37_MS  : integer := 37 * (INPUT_CLK_FREQ / 1e3);  -- the timeout delay for a frame
+    constant CLOCK_TICKS_PER_200_MS : integer := 200 * (INPUT_CLK_FREQ / 1e3);
+    constant CLOCK_TICKS_PER_200_NS : integer := (200 * (INPUT_CLK_FREQ / 1e6)) / 1e3;
+    constant BYTES_PER_HEADER       : integer := 4;
+    constant BYTES_PER_PAYLOAD      : integer := 160;
+
+    constant NUMBER_OF_LINES_PER_FRAME : positive := 60;
+    signal counter, counter_max        : integer range 1 to CLOCK_TICKS_PER_200_MS;
+    signal line_counter                : integer range 1 to NUMBER_OF_LINES_PER_FRAME;
+    signal timeout_counter             : integer range 1 to CLOCK_TICKS_PER_37_MS;
+    signal counter_enabled             : boolean;
+    signal waited_long_enough          : boolean;
+    signal header_end, payload_end     : boolean;
+begin
+
+    -- purpose: register for state
+    p_fsm : process(clk, reset)
+    begin
+        if reset = '1' then
+            state <= Idle;
+        elsif rising_edge(clk) then
+            state <= next_state;
+        end if;
+    end process p_fsm;
+
+    -- purpose: compute the next state
+    p_nsl : process(header_3_last_nibbles, header_end, payload_end, start, spi_miso_sink_valid, state, waited_long_enough, line_counter)
+    begin
+        next_state <= state;
+
+        case state is
+            when Idle =>
+                if waited_long_enough and start = '1' then
+                    next_state <= CSn;
+                end if;
+
+            when CSn =>
+                if waited_long_enough then
+                    next_state <= ReadHeader;
+                end if;
+
+            when ReadHeader =>
+                if header_end then
+                    if header_3_last_nibbles(11 downto 8) = X"F" then
+                        next_state <= DiscardPayload;
+                    else
+                        next_state <= ReadPayload;
+                    end if;
+                end if;
+
+            when DiscardPayload | ReadPayload =>
+                if payload_end then
+                    next_state <= ReadHeader;
+
+                    if line_counter = NUMBER_OF_LINES_PER_FRAME then
+                        next_state <= WaitBeforeIdle;
+                    end if;
+                end if;
+
+            when WaitBeforeIdle =>
+                if spi_miso_sink_valid = '1' then
+                    next_state <= Idle;
+                end if;
+
+        end case;
+    end process p_nsl;
+
+    p_counter : process(clk, reset)
+    begin
+        if reset = '1' then
+            counter      <= 1;
+            line_counter <= 1;
+        elsif rising_edge(clk) then
+            if counter = counter_max and counter_enabled then
+                counter <= 1;
+
+                if state = ReadPayload then
+                    if line_counter = NUMBER_OF_LINES_PER_FRAME then
+                        line_counter <= 1;
+                    else
+                        line_counter <= line_counter + 1;
+                    end if;
+                end if;
+
+            elsif counter_enabled then
+                counter <= counter + 1;
+            end if;
+        end if;
+    end process p_counter;
+
+    p_error : process(clk, reset)
+    begin
+        if reset = '1' then
+            error           <= '0';
+            timeout_counter <= 1;
+        elsif rising_edge(clk) then
+            if state /= ReadHeader and state /= ReadPayload and state /= ReadHeader then
+                timeout_counter <= 1;
+                error           <= '0';
+            else
+                if timeout_counter = CLOCK_TICKS_PER_37_MS then
+                    error <= '1';
+                else
+                    timeout_counter <= timeout_counter + 1;
+                end if;
+            end if;
+            if state = ReadPayload and header_3_last_nibbles /= std_logic_vector(to_unsigned(line_counter - 1, header_3_last_nibbles'length)) then
+                error <= '1';
+            end if;
+        end if;
+    end process p_error;
+
+    -- purpose: wire the datapath
+    p_datapath : process(counter, counter_enabled, counter_max, line_counter, spi_miso_sink_data, spi_miso_sink_valid, spi_mosi_src_ready, state)
+        variable counter_ended : boolean;
+
+    begin
+        counter_max        <= 1;
+        counter_enabled    <= true;
+        waited_long_enough <= false;
+        lepton_out_data    <= (others => '0');
+        lepton_out_valid   <= '0';
+        lepton_out_sof     <= '0';
+        lepton_out_eof     <= '0';
+        spi_mosi_src_valid <= '0';
+        spi_mosi_src_data  <= (others => '0');
+        spi_cs_n           <= '0';
+        header_end         <= false;
+        payload_end        <= false;
+
+        counter_ended := (counter = counter_max and counter_enabled);
+
+        case state is
+            when Idle =>
+                counter_max        <= CLOCK_TICKS_PER_200_MS;
+                waited_long_enough <= counter_ended;
+                spi_cs_n           <= '1';
+
+            when CSn =>
+                counter_max        <= CLOCK_TICKS_PER_200_NS;
+                waited_long_enough <= counter_ended;
+
+            when ReadHeader =>
+                counter_max        <= BYTES_PER_HEADER;
+                counter_enabled    <= spi_miso_sink_valid = '1';
+                header_end         <= counter_ended;
+                spi_mosi_src_valid <= spi_mosi_src_ready;
+
+            when ReadPayload =>
+                counter_max        <= BYTES_PER_PAYLOAD;
+                counter_enabled    <= spi_miso_sink_valid = '1';
+                lepton_out_data    <= spi_miso_sink_data;
+                lepton_out_valid   <= spi_miso_sink_valid;
+                payload_end        <= counter_ended;
+                spi_mosi_src_valid <= spi_mosi_src_ready;
+                if spi_miso_sink_valid = '1' then
+                    if counter = 1 and counter_enabled and line_counter = 1 then
+                        lepton_out_sof <= '1';
+                    elsif counter_ended and line_counter = NUMBER_OF_LINES_PER_FRAME then
+                        lepton_out_eof <= '1';
+                    end if;
+                end if;
+
+            when DiscardPayload =>
+                counter_max        <= BYTES_PER_PAYLOAD;
+                counter_enabled    <= spi_miso_sink_valid = '1';
+                payload_end        <= counter_ended;
+                spi_mosi_src_valid <= spi_mosi_src_ready;
+
+            when others => null;
+        end case;
+    end process p_datapath;
+
+    p_capture_header : process(clk, reset)
+    begin
+        if reset = '1' then
+            header_3_last_nibbles <= X"000";
+        elsif rising_edge(clk) then
+            if state = ReadHeader and spi_miso_sink_valid = '1' then
+                if counter = 1 then
+                    header_3_last_nibbles(11 downto 8) <= spi_miso_sink_data(3 downto 0);
+                elsif counter = 2 then
+                    header_3_last_nibbles(7 downto 0) <= spi_miso_sink_data;
+                end if;
+            end if;
+        end if;
+    end process p_capture_header;
+
+    row_idx <= std_logic_vector(to_unsigned(line_counter, row_idx'length));
+
+end architecture rtl;

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_stats.vhd

@@ -0,0 +1,78 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity lepton_stats is
+    port(
+        clk        : in  std_logic;
+        reset      : in  std_logic;
+        pix_data   : in  std_logic_vector(13 downto 0);
+        pix_valid  : in  std_logic;
+        pix_sof    : in  std_logic;
+        pix_eof    : in  std_logic;
+        stat_min   : out std_logic_vector(13 downto 0);
+        stat_max   : out std_logic_vector(13 downto 0);
+        stat_sum   : out std_logic_vector(26 downto 0);
+        stat_valid : out std_logic);
+end lepton_stats;
+
+architecture rtl of lepton_stats is
+
+    -- The accumulated sum, min and max of the pixel values
+    signal curr_min : unsigned(13 downto 0);
+    signal curr_max : unsigned(13 downto 0);
+    signal curr_sum : unsigned(26 downto 0);
+
+    -- The next value of the registers
+    signal next_min : unsigned(13 downto 0);
+    signal next_max : unsigned(13 downto 0);
+    signal next_sum : unsigned(26 downto 0);
+
+begin
+
+    -- This is the synchronous transition logic
+    transition_logic : process(clk, reset)
+    begin
+        if reset = '1' then
+            curr_sum <= (others => '0');
+            curr_min <= (others => '0');
+            curr_max <= (others => '0');
+        elsif rising_edge(clk) then
+            curr_min <= next_min;
+            curr_max <= next_max;
+            curr_sum <= next_sum;
+        end if;
+    end process;
+
+    -- This is the combinatorial transition logic
+    next_min <=
+        curr_min when pix_valid = '0' else
+        unsigned(pix_data) when pix_sof = '1' else
+        curr_min when unsigned(pix_data) >= curr_min else
+        unsigned(pix_data);
+
+    next_max <=
+        curr_max when pix_valid = '0' else
+        unsigned(pix_data) when pix_sof = '1' else
+        curr_max when unsigned(pix_data) <= curr_max else
+        unsigned(pix_data);
+
+    next_sum <=
+        curr_sum when pix_valid = '0' else
+        unsigned((26 downto 14 => '0') & pix_data) when pix_sof = '1' else
+        curr_sum + unsigned((26 downto 14 => '0') & pix_data);
+
+    -- This is the synchronous output logic
+    output_logic : process(clk, reset)
+    begin
+        if rising_edge(clk) then
+            stat_valid <= pix_eof;
+        end if;
+    end process;
+
+    -- This is the combinatorial output logic
+    stat_min <= std_logic_vector(curr_min);
+    stat_max <= std_logic_vector(curr_max);
+    stat_sum <= std_logic_vector(curr_sum);
+
+end rtl;

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/level_adjuster.vhd

@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity level_adjuster is
+    port(
+        clk            : in  std_logic;
+        raw_pixel      : in  std_logic_vector(13 downto 0);
+        raw_max        : in  std_logic_vector(13 downto 0);
+        raw_min        : in  std_logic_vector(13 downto 0);
+        raw_sum        : in  std_logic_vector(26 downto 0);
+        adjusted_pixel : out std_logic_vector(13 downto 0));
+end level_adjuster;
+
+architecture rtl of level_adjuster is
+    component lpm_divider
+        port(
+            clock    : in  std_logic;
+            denom    : in  std_logic_vector(13 downto 0);
+            numer    : in  std_logic_vector(27 downto 0);
+            quotient : out std_logic_vector(27 downto 0);
+            remain   : out std_logic_vector(13 downto 0));
+    end component;
+
+    -- Intermediate signals needed by the divider
+    signal numer : std_logic_vector(27 downto 0);
+    signal denom : std_logic_vector(13 downto 0);
+    signal quot  : std_logic_vector(27 downto 0);
+
+begin
+
+    -- Computation of the intermediate signals
+    numer <= std_logic_vector((13 downto 0 => '1') * (unsigned(raw_pixel) - unsigned(raw_min)));
+    denom <= std_logic_vector(unsigned(raw_max) - unsigned(raw_min));
+    
+    -- We compute the remaineder of (x - min) / (max - min)
+    divider : lpm_divider port map(
+        clock => clk,
+        numer => numer,
+        denom => denom,
+        quotient => quot,
+        remain => open
+    );
+
+    -- And we only keep the LSB of the quotient (we know the MSB must be 0)
+    adjusted_pixel <=
+        (adjusted_pixel'range => '0') when denom = (denom'range => '0') else
+        quot(13 downto 0);
+
+end rtl;

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lpm_divider.vhd

@@ -0,0 +1,133 @@
+-- megafunction wizard: %LPM_DIVIDE%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_DIVIDE 
+
+-- ============================================================
+-- File Name: lpm_divider.vhd
+-- Megafunction Name(s):
+--                      LPM_DIVIDE
+--
+-- Simulation Library Files(s):
+--                      lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus Prime License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library lpm;
+use lpm.all;
+
+entity lpm_divider is
+    port(
+        clock    : in  std_logic;
+        denom    : in  std_logic_vector(13 downto 0);
+        numer    : in  std_logic_vector(27 downto 0);
+        quotient : out std_logic_vector(27 downto 0);
+        remain   : out std_logic_vector(13 downto 0)
+    );
+end lpm_divider;
+
+architecture SYN of lpm_divider is
+    signal sub_wire0 : std_logic_vector(27 downto 0);
+    signal sub_wire1 : std_logic_vector(13 downto 0);
+
+    component lpm_divide
+        generic(
+            lpm_drepresentation : string;
+            lpm_hint            : string;
+            lpm_nrepresentation : string;
+            lpm_pipeline        : natural;
+            lpm_type            : string;
+            lpm_widthd          : natural;
+            lpm_widthn          : natural
+        );
+        port(
+            clock    : in  std_logic;
+            denom    : in  std_logic_vector(13 downto 0);
+            numer    : in  std_logic_vector(27 downto 0);
+            quotient : out std_logic_vector(27 downto 0);
+            remain   : out std_logic_vector(13 downto 0)
+        );
+    end component;
+
+begin
+    quotient <= sub_wire0(27 downto 0);
+    remain   <= sub_wire1(13 downto 0);
+
+    LPM_DIVIDE_component : LPM_DIVIDE
+    generic map(
+        lpm_drepresentation => "UNSIGNED",
+        lpm_hint            => "LPM_REMAINDERPOSITIVE=TRUE",
+        lpm_nrepresentation => "UNSIGNED",
+        lpm_pipeline        => 5,
+        lpm_type            => "LPM_DIVIDE",
+        lpm_widthd          => 14,
+        lpm_widthn          => 28
+    )
+    port map(
+        clock    => clock,
+        denom    => denom,
+        numer    => numer,
+        quotient => sub_wire0,
+        remain   => sub_wire1
+    );
+
+end SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
+-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
+-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
+-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
+-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "14"
+-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "28"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: denom 0 0 14 0 INPUT NODEFVAL "denom[13..0]"
+-- Retrieval info: USED_PORT: numer 0 0 28 0 INPUT NODEFVAL "numer[27..0]"
+-- Retrieval info: USED_PORT: quotient 0 0 28 0 OUTPUT NODEFVAL "quotient[27..0]"
+-- Retrieval info: USED_PORT: remain 0 0 14 0 OUTPUT NODEFVAL "remain[13..0]"
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @denom 0 0 14 0 denom 0 0 14 0
+-- Retrieval info: CONNECT: @numer 0 0 28 0 numer 0 0 28 0
+-- Retrieval info: CONNECT: quotient 0 0 28 0 @quotient 0 0 28 0
+-- Retrieval info: CONNECT: remain 0 0 14 0 @remain 0 0 14 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/ram_writer.vhd

@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram_writer is
+    port(
+        clk, reset    : in  std_logic;
+        pix_data      : in  std_logic_vector(13 downto 0);
+        pix_valid     : in  std_logic;
+        pix_sof       : in  std_logic;
+        pix_eof       : in  std_logic;
+        ram_data      : out std_logic_vector(15 downto 0);
+        ram_wren      : out std_logic;
+        ram_wraddress : out std_logic_vector(12 downto 0));
+
+end ram_writer;
+
+architecture rtl of ram_writer is
+    signal wraddress_counter : unsigned(ram_wraddress'range);
+begin
+    p_address_gen : process(clk, reset)
+    begin
+        if reset = '1' then
+            wraddress_counter <= (others => '0');
+        elsif rising_edge(clk) then
+            if pix_eof = '1' then
+                wraddress_counter <= (others => '0');
+            elsif pix_valid = '1' then
+                wraddress_counter <= wraddress_counter + 1;
+            end if;
+        end if;
+    end process p_address_gen;
+
+    ram_data      <= "00" & pix_data;
+    ram_wren      <= pix_valid;
+    ram_wraddress <= std_logic_vector(wraddress_counter);
+
+end rtl;

cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/utils.vhd

@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package utils is
+    function bitlength(number : positive) return positive;
+
+end package utils;
+
+package body utils is
+
+    -- purpose: returns the minimum # of bits needed to represent the input number
+    function bitlength(number : positive) return positive is
+        variable acc : positive := 1;
+        variable i   : natural := 0;
+    begin
+        while True loop
+            if acc > number then
+                return i;
+            end if;
+
+            acc := acc * 2;
+            i   := i + 1;
+        end loop;
+    end function bitlength;
+
+end package body utils;

cs309-psoc/lab_2_0/hw/hdl/lepton/tb/lepton_tb.vhd

@@ -0,0 +1,77 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity lepton_tb is
+end lepton_tb;
+
+architecture tb of lepton_tb is
+    signal clk       : std_logic                     := '0';
+    signal reset     : std_logic                     := '0';
+    signal address   : std_logic_vector(13 downto 0) := (others => '0');
+    signal readdata  : std_logic_vector(15 downto 0) := (others => '0');
+    signal writedata : std_logic_vector(15 downto 0) := (others => '0');
+    signal read      : std_logic                     := '0';
+    signal write     : std_logic                     := '0';
+    signal SCLK      : std_logic                     := '0';
+    signal CSn       : std_logic                     := '0';
+    signal MOSI      : std_logic                     := '0';
+    signal MISO      : std_logic                     := '1';
+
+    constant CLK_PERIOD : time := 20 ns;
+
+    signal sim_ended : boolean := false;
+
+begin
+    dut : entity work.lepton
+    port map(
+        clk       => clk,
+        reset     => reset,
+        address   => address,
+        readdata  => readdata,
+        writedata => writedata,
+        read      => read,
+        write     => write,
+        SCLK      => SCLK,
+        CSn       => CSn,
+        MOSI      => MOSI,
+        MISO      => MISO
+    );
+
+    clk <= not clk after CLK_PERIOD / 2 when not sim_ended else '0';
+
+    miso_gen : process
+        variable seed1, seed2 : positive;
+        variable rand         : real;
+    begin
+        if sim_ended then
+            wait;
+        else
+            uniform(seed1, seed2, rand);
+            wait until rising_edge(SCLK);
+            MISO <= to_unsigned(integer(rand), 1)(0);
+
+        end if;
+    end process;
+
+    stimuli : process
+    begin
+        reset <= '1';
+        write <= '0';
+
+        wait for 2 * CLK_PERIOD;
+        reset <= '0';
+
+        wait for CLK_PERIOD;
+        write        <= '1';
+        writedata(0) <= '1';
+        wait for CLK_PERIOD;
+        write        <= '0';
+
+        wait for 17 ms;
+        sim_ended <= true;
+        wait;
+    end process;
+
+end tb;

cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm.vhd

@@ -0,0 +1,42 @@
+-- #############################################################################
+-- pwm.vhd
+-- =======
+-- PWM memory-mapped Avalon slave interface.
+--
+-- Author        : <insert your name> (<insert your e-mail address>)
+-- Author        : <insert your name> (<insert your e-mail address>)
+-- Revision      : <insert revision>
+-- Last modified : <insert date>
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pwm_constants.all;
+
+entity pwm is
+    port(
+        -- Avalon Clock interface
+        clk : in std_logic;
+
+        -- Avalon Reset interface
+        reset : in std_logic;
+
+        -- Avalon-MM Slave interface
+        address   : in  std_logic_vector(1 downto 0);
+        read      : in  std_logic;
+        write     : in  std_logic;
+        readdata  : out std_logic_vector(31 downto 0);
+        writedata : in  std_logic_vector(31 downto 0);
+
+        -- Avalon Conduit interface
+        pwm_out : out std_logic
+    );
+end pwm;
+
+architecture rtl of pwm is
+
+begin
+
+end architecture rtl;

cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm_constants.vhd

@@ -0,0 +1,61 @@
+-- #############################################################################
+-- pwm_constants.vhd
+-- =================
+-- This package contains constants used in the PWM design files.
+--
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 2
+-- Last modified : 2018-02-28
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package pwm_constants is
+    -- Register map
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | RegNo  | Name       | Access | Description                                                                  |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | 0      | PERIOD     | R/W    | Period in clock cycles [2 <= period <= (2**32) - 1].                         |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | This value can be read/written while the unit is in the middle of an ongoing |
+    -- |        |            |        | PWM pulse. To allow safe behaviour, one cannot modify the period of an       |
+    -- |        |            |        | ongoing pulse, so we adopt the following semantics for this register:        |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> WRITING a value in this register indicates the NEW period to apply to the |
+    -- |        |            |        |    next pulse.                                                               |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> READING a value from this register indicates the CURRENT period of the    |
+    -- |        |            |        |    ongoing pulse.                                                            |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | 1      | DUTY_CYCLE | R/W    | Duty cycle of the PWM [1 <= duty cycle <= period]                            |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | This value can be read/written while the unit is in the middle of an ongoing |
+    -- |        |            |        | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an   |
+    -- |        |            |        | ongoing pulse, so we adopt the following semantics for this register:        |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> WRITING a value in this register indicates the NEW duty cycle to apply to |
+    -- |        |            |        |    the next pulse.                                                           |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> READING a value from this register indicates the CURRENT duty cycle of    |
+    -- |        |            |        |    the ongoing pulse.                                                        |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    -- | 2      | CTRL       | WO     | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.|
+    -- |        |            |        |    Writing 1 to this register starts the PWM.                                |
+    -- |        |            |        |                                                                              |
+    -- |        |            |        | >> Reading this register always returns 0.                                   |
+    -- +--------+------------+--------+------------------------------------------------------------------------------+
+    constant REG_PERIOD_OFST     : std_logic_vector(1 downto 0) := "00";
+    constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01";
+    constant REG_CTRL_OFST       : std_logic_vector(1 downto 0) := "10";
+
+    -- Default values of registers after reset (BEFORE writing START to the CTRL
+    -- register with a new configuration)
+    constant DEFAULT_PERIOD     : natural := 4;
+    constant DEFAULT_DUTY_CYCLE : natural := 2;
+end package pwm_constants;
+
+package body pwm_constants is
+
+end package body pwm_constants;

cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm_hw.tcl

@@ -0,0 +1,135 @@
+# TCL File Generated by Component Editor 16.0
+# Tue Feb 28 12:18:00 CET 2017
+# DO NOT MODIFY
+
+
+#
+# pwm "pwm" v1.0
+#  2017.02.28.12:18:00
+# Pan-tilt
+#
+
+#
+# request TCL package from ACDS 16.0
+#
+package require -exact qsys 16.0
+
+
+#
+# module pwm
+#
+set_module_property DESCRIPTION Pan-tilt
+set_module_property NAME pwm
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP Pan-tilt
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME pwm
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE
+add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point clock
+#
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+#
+# connection point reset
+#
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+#
+# connection point avalon_slave_0
+#
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 writedata writedata Input 32
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+
+
+#
+# connection point conduit_end
+#
+add_interface conduit_end conduit end
+set_interface_property conduit_end associatedClock clock
+set_interface_property conduit_end associatedReset ""
+set_interface_property conduit_end ENABLED true
+set_interface_property conduit_end EXPORT_OF ""
+set_interface_property conduit_end PORT_NAME_MAP ""
+set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end pwm_out pwm Output 1

cs309-psoc/lab_2_0/hw/hdl/pantilt/tb/tb_pwm.vhd

@@ -0,0 +1,205 @@
+-- #############################################################################
+-- tb_pwm.vhd
+-- ==========
+-- Testbench for PWM memory-mapped Avalon slave interface.
+--
+-- Modified by   : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 2
+-- Last modified : 2018-02-28
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pwm_constants.all;
+
+entity tb_pwm is
+end entity;
+
+architecture rtl of tb_pwm is
+
+    -- 50 MHz clock
+    constant CLK_PERIOD : time := 20 ns;
+
+    -- Signal used to end simulator when we finished submitting our test cases
+    signal sim_finished : boolean := false;
+
+    -- PWM PORTS
+    signal clk       : std_logic;
+    signal reset     : std_logic;
+    signal address   : std_logic_vector(1 downto 0);
+    signal read      : std_logic;
+    signal write     : std_logic;
+    signal readdata  : std_logic_vector(31 downto 0);
+    signal writedata : std_logic_vector(31 downto 0);
+    signal pwm_out   : std_logic;
+
+    -- Values of registers we are going to use to configure the PWM unit
+    constant CONFIG_PERIOD     : natural := 100;
+    constant CONFIG_DUTY_CYCLE : natural := 20;
+    constant CONFIG_CTRL_START : natural := 1;
+    constant CONFIG_CTRL_STOP  : natural := 0;
+
+begin
+
+    -- Instantiate DUT
+    dut : entity work.pwm
+    port map(
+        clk       => clk,
+        reset     => reset,
+        address   => address,
+        read      => read,
+        write     => write,
+        readdata  => readdata,
+        writedata => writedata,
+        pwm_out   => pwm_out
+    );
+
+    -- Generate clk signal
+    clk_generation : process
+    begin
+        if not sim_finished then
+            clk <= '1';
+            wait for CLK_PERIOD / 2;
+            clk <= '0';
+            wait for CLK_PERIOD / 2;
+        else
+            wait;
+        end if;
+    end process clk_generation;
+
+    -- Test PWM
+    simulation : process
+
+        procedure async_reset is
+        begin
+            wait until rising_edge(clk);
+            wait for CLK_PERIOD / 4;
+
+            reset <= '1';
+            wait for CLK_PERIOD / 2;
+
+            reset <= '0';
+            wait for CLK_PERIOD / 4;
+        end procedure async_reset;
+
+        procedure write_register(constant ofst : in std_logic_vector(1 downto 0);
+                                 constant val  : in natural) is
+        begin
+            wait until rising_edge(clk);
+
+            address   <= ofst;
+            write     <= '1';
+            writedata <= std_logic_vector(to_unsigned(val, writedata'length));
+            wait until rising_edge(clk);
+
+            address   <= (others => '0');
+            write     <= '0';
+            writedata <= (others => '0');
+            wait until rising_edge(clk);
+        end procedure write_register;
+
+        procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is
+        begin
+            wait until rising_edge(clk);
+
+            address <= ofst;
+            read    <= '1';
+            -- The read has a 1 cycle wait-state, so we need to keep the read
+            -- signal high for 2 clock cycles.
+            wait until rising_edge(clk);
+            wait until rising_edge(clk);
+
+            address <= (others => '0');
+            read    <= '0';
+            wait until rising_edge(clk);
+        end procedure read_register;
+
+        procedure read_register_check(constant ofst         : in std_logic_vector(1 downto 0);
+                                      constant expected_val : in natural) is
+        begin
+            read_register(ofst);
+
+            case ofst is
+                when REG_PERIOD_OFST =>
+                    assert to_integer(unsigned(readdata)) = expected_val
+                    report "Unexpected PERIOD: " &
+                    "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " &
+                    "PERIOD_expected = " & integer'image(expected_val)
+                    severity error;
+
+                when REG_DUTY_CYCLE_OFST =>
+                    assert to_integer(unsigned(readdata)) = expected_val
+                    report "Unexpected DUTY_CYCLE: " &
+                    "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " &
+                    "DUTY_CYCLE_expected = " & integer'image(expected_val)
+                    severity error;
+
+                when REG_CTRL_OFST =>
+                    assert to_integer(unsigned(readdata)) = expected_val
+                    report "Unexpected CTRL: " &
+                    "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " &
+                    "CTRL_expected = " & integer'image(expected_val)
+                    severity error;
+
+                when others =>
+                    null;
+            end case;
+        end procedure read_register_check;
+
+    begin
+
+        -- Default values
+        reset     <= '0';
+        address   <= (others => '0');
+        read      <= '0';
+        write     <= '0';
+        writedata <= (others => '0');
+        wait until rising_edge(clk);
+
+        -- Reset the circuit
+        async_reset;
+
+        -- Write desired configuration to PWM Avalon-MM slave.
+        write_register(REG_PERIOD_OFST, CONFIG_PERIOD);
+        write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
+
+        -- Read back configuration from PWM Avalon-MM slave. Note that we have
+        -- not started the PWM unit yet, so the new configuration must not be
+        -- read back at this point (as per the register map).
+        read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD);
+        read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE);
+        read_register_check(REG_CTRL_OFST, 0);
+
+        -- Start PWM
+        write_register(REG_CTRL_OFST, CONFIG_CTRL_START);
+
+        -- Wait until PWM pulses for the first time after we sent START.
+        wait until rising_edge(pwm_out);
+
+        -- Read back configuration from PWM Avalon-MM slave. Now that we have
+        -- started the PWM unit, we should be able to read back the
+        -- configuration we wrote (as per the register map).
+        read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD);
+        read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
+        read_register_check(REG_CTRL_OFST, 0);
+
+        -- Wait for 2 PWM periods to finish
+        wait for 2 * CLK_PERIOD * CONFIG_PERIOD;
+
+        -- Stop PWM.
+        write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP);
+
+        -- Wait for PWM period to finish
+        wait for 1 * CLK_PERIOD * CONFIG_PERIOD;
+
+        -- Instruct "clk_generation" process to halt execution.
+        sim_finished <= true;
+
+        -- Make this process wait indefinitely (it will never re-execute from
+        -- its beginning again).
+        wait;
+    end process simulation;
+end architecture rtl;
+

cs309-psoc/lab_2_0/hw/quartus/ip/components.ipx

@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<library>
+ <!--  date: 2017.03.19.20:51:30 -->
+ <!--  generated by: ip-make-ipx -->
+ <!--   -->
+ <!--     3 in ../../hdl/ -->
+ <!--   -->
+ <component
+   name="lepton"
+   file="../../hdl/lepton/hdl/lepton_hw.tcl"
+   displayName="lepton"
+   version="1.0"
+   description="IR Camera 80x60"
+   tags="AUTHORSHIP=Philemon Favrod &amp; Sahand Kashani-Akhavan /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
+   categories="Camera"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+ <component
+   name="mcp3204"
+   file="../../hdl/joysticks/hdl/mcp3204_hw.tcl"
+   displayName="mcp3204"
+   version="1.0"
+   description="4-Channel 12-Bit A/D Converter with SPI Serial Interface"
+   tags="AUTHORSHIP=Philemon Favrod &amp; Sahand Kashani-Akhavan /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
+   categories="Joystick"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+ <component
+   name="pwm"
+   file="../../hdl/pantilt/hdl/pwm_hw.tcl"
+   displayName="pwm"
+   version="1.0"
+   description="Pan-tilt"
+   tags="AUTHORSHIP= /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
+   categories="Pan-tilt"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+</library>

cs309-psoc/lab_2_0/hw/quartus/lab_2_0.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors.  Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+# Date created = 11:03:02  February 05, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "15.1"
+DATE = "11:03:02  February 05, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "lab_2_0"

cs309-psoc/lab_2_0/hw/quartus/lab_2_0.qsf

@@ -0,0 +1,812 @@
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+
+set_global_assignment -name SMART_RECOMPILE OFF
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+
+set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level
+
+set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
+set_global_assignment -name QSYS_FILE soc_system.qsys
+set_global_assignment -name SDC_FILE lab_2_0.sdc
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA4U23C6
+set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+#============================================================
+# ADC
+#============================================================
+set_location_assignment PIN_U9 -to ADC_CONVST
+set_location_assignment PIN_V10 -to ADC_SCK
+set_location_assignment PIN_AC4 -to ADC_SDI
+set_location_assignment PIN_AD4 -to ADC_SDO
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+#============================================================
+# ARDUINO Extention OV7670 CAMERA
+#============================================================
+set_location_assignment PIN_AE15 -to CAM_D[0]
+set_location_assignment PIN_AE15 -to CAM_D_0
+set_location_assignment PIN_AF17 -to CAM_D[1]
+set_location_assignment PIN_AF17 -to CAM_D_1
+set_location_assignment PIN_AH8 -to CAM_D[2]
+set_location_assignment PIN_AH8 -to CAM_D_2
+set_location_assignment PIN_AG8 -to CAM_D[3]
+set_location_assignment PIN_AG8 -to CAM_D_3
+set_location_assignment PIN_U13 -to CAM_D[4]
+set_location_assignment PIN_U13 -to CAM_D_4
+set_location_assignment PIN_U14 -to CAM_D[5]
+set_location_assignment PIN_U14 -to CAM_D_5
+set_location_assignment PIN_AG9 -to CAM_D[6]
+set_location_assignment PIN_AG9 -to CAM_D_6
+set_location_assignment PIN_AG10 -to CAM_D[7]
+set_location_assignment PIN_AG10 -to CAM_D_7
+set_location_assignment PIN_AF13 -to CAM_D[8]
+set_location_assignment PIN_AF13 -to CAM_D_8
+set_location_assignment PIN_AG13 -to CAM_D[9]
+set_location_assignment PIN_AG13 -to CAM_D_9
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9
+
+#============================================================
+# Arduino Extension LEPTON CAMERA THERMAL CAM_TH
+#============================================================
+set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N
+set_location_assignment PIN_AG16 -to CAM_TH_MOSI
+set_location_assignment PIN_AH11 -to CAM_TH_MISO
+set_location_assignment PIN_AH12 -to CAM_TH_CLK
+set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA
+set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL
+
+set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_V11 -to FPGA_CLK1_50
+set_location_assignment PIN_Y13 -to FPGA_CLK2_50
+set_location_assignment PIN_E11 -to FPGA_CLK3_50
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
+
+#============================================================
+# HPS
+#============================================================
+set_location_assignment PIN_C6 -to HPS_CONV_USB_N
+set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0]
+set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0
+set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1]
+set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1
+set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2]
+set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2
+set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3]
+set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3
+set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4]
+set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4
+set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5]
+set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5
+set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6]
+set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6
+set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7]
+set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7
+set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8]
+set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8
+set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9]
+set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9
+set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10]
+set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10
+set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11]
+set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11
+set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12]
+set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12
+set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13]
+set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13
+set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14]
+set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14
+set_location_assignment PIN_A27 -to HPS_DDR3_BA[0]
+set_location_assignment PIN_A27 -to HPS_DDR3_BA_0
+set_location_assignment PIN_H25 -to HPS_DDR3_BA[1]
+set_location_assignment PIN_H25 -to HPS_DDR3_BA_1
+set_location_assignment PIN_G25 -to HPS_DDR3_BA[2]
+set_location_assignment PIN_G25 -to HPS_DDR3_BA_2
+set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N
+set_location_assignment PIN_L28 -to HPS_DDR3_CKE
+set_location_assignment PIN_N20 -to HPS_DDR3_CK_N
+set_location_assignment PIN_N21 -to HPS_DDR3_CK_P
+set_location_assignment PIN_L21 -to HPS_DDR3_CS_N
+set_location_assignment PIN_G28 -to HPS_DDR3_DM[0]
+set_location_assignment PIN_G28 -to HPS_DDR3_DM_0
+set_location_assignment PIN_P28 -to HPS_DDR3_DM[1]
+set_location_assignment PIN_P28 -to HPS_DDR3_DM_1
+set_location_assignment PIN_W28 -to HPS_DDR3_DM[2]
+set_location_assignment PIN_W28 -to HPS_DDR3_DM_2
+set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3]
+set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3
+set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0]
+set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0
+set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1]
+set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1
+set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2]
+set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2
+set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3]
+set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3
+set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4]
+set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4
+set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5]
+set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5
+set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6]
+set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6
+set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7]
+set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7
+set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8]
+set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8
+set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9]
+set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9
+set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10]
+set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10
+set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11]
+set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11
+set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12]
+set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12
+set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13]
+set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13
+set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14]
+set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14
+set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15]
+set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15
+set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16]
+set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16
+set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17]
+set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17
+set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18]
+set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18
+set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19]
+set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19
+set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20]
+set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20
+set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21]
+set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21
+set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22]
+set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22
+set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23]
+set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23
+set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24]
+set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24
+set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25]
+set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25
+set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26]
+set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26
+set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27]
+set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27
+set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28]
+set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28
+set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29]
+set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29
+set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30]
+set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30
+set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31]
+set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31
+set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0]
+set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0
+set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1]
+set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1
+set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2]
+set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2
+set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3]
+set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3
+set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0]
+set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0
+set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1]
+set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1
+set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2]
+set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2
+set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3]
+set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3
+set_location_assignment PIN_D28 -to HPS_DDR3_ODT
+set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N
+set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N
+set_location_assignment PIN_D25 -to HPS_DDR3_RZQ
+set_location_assignment PIN_E25 -to HPS_DDR3_WE_N
+set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK
+set_location_assignment PIN_B14 -to HPS_ENET_INT_N
+set_location_assignment PIN_A13 -to HPS_ENET_MDC
+set_location_assignment PIN_E16 -to HPS_ENET_MDIO
+set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK
+set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0]
+set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0
+set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1]
+set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1
+set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2]
+set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2
+set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3]
+set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3
+set_location_assignment PIN_J13 -to HPS_ENET_RX_DV
+set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0]
+set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0
+set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1]
+set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1
+set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2]
+set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2
+set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3]
+set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3
+set_location_assignment PIN_A12 -to HPS_ENET_TX_EN
+set_location_assignment PIN_A17 -to HPS_GSENSOR_INT
+set_location_assignment PIN_C18 -to HPS_I2C0_SCLK
+set_location_assignment PIN_A19 -to HPS_I2C0_SDAT
+set_location_assignment PIN_K18 -to HPS_I2C1_SCLK
+set_location_assignment PIN_A21 -to HPS_I2C1_SDAT
+set_location_assignment PIN_J18 -to HPS_KEY_N
+set_location_assignment PIN_A20 -to HPS_LED
+set_location_assignment PIN_H13 -to HPS_LTC_GPIO
+set_location_assignment PIN_B8 -to HPS_SD_CLK
+set_location_assignment PIN_D14 -to HPS_SD_CMD
+set_location_assignment PIN_C13 -to HPS_SD_DATA[0]
+set_location_assignment PIN_C13 -to HPS_SD_DATA_0
+set_location_assignment PIN_B6 -to HPS_SD_DATA[1]
+set_location_assignment PIN_B6 -to HPS_SD_DATA_1
+set_location_assignment PIN_B11 -to HPS_SD_DATA[2]
+set_location_assignment PIN_B11 -to HPS_SD_DATA_2
+set_location_assignment PIN_B9 -to HPS_SD_DATA[3]
+set_location_assignment PIN_B9 -to HPS_SD_DATA_3
+set_location_assignment PIN_C19 -to HPS_SPIM_CLK
+set_location_assignment PIN_B19 -to HPS_SPIM_MISO
+set_location_assignment PIN_B16 -to HPS_SPIM_MOSI
+set_location_assignment PIN_C16 -to HPS_SPIM_SS
+set_location_assignment PIN_A22 -to HPS_UART_RX
+set_location_assignment PIN_B21 -to HPS_UART_TX
+set_location_assignment PIN_G4 -to HPS_USB_CLKOUT
+set_location_assignment PIN_C10 -to HPS_USB_DATA[0]
+set_location_assignment PIN_C10 -to HPS_USB_DATA_0
+set_location_assignment PIN_F5 -to HPS_USB_DATA[1]
+set_location_assignment PIN_F5 -to HPS_USB_DATA_1
+set_location_assignment PIN_C9 -to HPS_USB_DATA[2]
+set_location_assignment PIN_C9 -to HPS_USB_DATA_2
+set_location_assignment PIN_C4 -to HPS_USB_DATA[3]
+set_location_assignment PIN_C4 -to HPS_USB_DATA_3
+set_location_assignment PIN_C8 -to HPS_USB_DATA[4]
+set_location_assignment PIN_C8 -to HPS_USB_DATA_4
+set_location_assignment PIN_D4 -to HPS_USB_DATA[5]
+set_location_assignment PIN_D4 -to HPS_USB_DATA_5
+set_location_assignment PIN_C7 -to HPS_USB_DATA[6]
+set_location_assignment PIN_C7 -to HPS_USB_DATA_6
+set_location_assignment PIN_F4 -to HPS_USB_DATA[7]
+set_location_assignment PIN_F4 -to HPS_USB_DATA_7
+set_location_assignment PIN_E5 -to HPS_USB_DIR
+set_location_assignment PIN_D5 -to HPS_USB_NXT
+set_location_assignment PIN_C5 -to HPS_USB_STP
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
+
+#============================================================
+# KEY_N
+#============================================================
+set_location_assignment PIN_AH17 -to KEY_N[0]
+set_location_assignment PIN_AH17 -to KEY_N_0
+set_location_assignment PIN_AH16 -to KEY_N[1]
+set_location_assignment PIN_AH16 -to KEY_N_1
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1
+
+#============================================================
+# LED
+#============================================================
+set_location_assignment PIN_W15 -to LED[0]
+set_location_assignment PIN_W15 -to LED_0
+set_location_assignment PIN_AA24 -to LED[1]
+set_location_assignment PIN_AA24 -to LED_1
+set_location_assignment PIN_V16 -to LED[2]
+set_location_assignment PIN_V16 -to LED_2
+set_location_assignment PIN_V15 -to LED[3]
+set_location_assignment PIN_V15 -to LED_3
+set_location_assignment PIN_AF26 -to LED[4]
+set_location_assignment PIN_AF26 -to LED_4
+set_location_assignment PIN_AE26 -to LED[5]
+set_location_assignment PIN_AE26 -to LED_5
+set_location_assignment PIN_Y16 -to LED[6]
+set_location_assignment PIN_Y16 -to LED_6
+set_location_assignment PIN_AA23 -to LED[7]
+set_location_assignment PIN_AA23 -to LED_7
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_L10 -to SW[0]
+set_location_assignment PIN_L10 -to SW_0
+set_location_assignment PIN_L9 -to SW[1]
+set_location_assignment PIN_L9 -to SW_1
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H6 -to SW_2
+set_location_assignment PIN_H5 -to SW[3]
+set_location_assignment PIN_H5 -to SW_3
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3
+
+#============================================================
+# GPIO_0, GPIO_0 connect to GPIO Default
+#============================================================
+set_location_assignment PIN_V12 -to PIO_INT_N
+set_location_assignment PIN_AE11 -to PIO_SCL
+set_location_assignment PIN_AE12 -to PIO_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA
+
+set_location_assignment PIN_AF7 -to PIR_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT
+
+set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA
+set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL
+set_location_assignment PIN_T11 -to CAM_SYS_CLK
+set_location_assignment PIN_AG6 -to CAM_LV
+set_location_assignment PIN_AH2 -to CAM_PIX_CLK
+set_location_assignment PIN_AE4 -to CAM_FV
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV
+
+set_location_assignment PIN_Y8 -to PAL_VD_HSO
+set_location_assignment PIN_AB4 -to PAL_VD_VSO
+set_location_assignment PIN_AG5 -to PAL_VD_VD[0]
+set_location_assignment PIN_AG5 -to PAL_VD_VD_0
+set_location_assignment PIN_AH5 -to PAL_VD_VD[1]
+set_location_assignment PIN_AH5 -to PAL_VD_VD_1
+set_location_assignment PIN_AH6 -to PAL_VD_VD[2]
+set_location_assignment PIN_AH6 -to PAL_VD_VD_2
+set_location_assignment PIN_T8 -to PAL_VD_VD[3]
+set_location_assignment PIN_T8 -to PAL_VD_VD_3
+set_location_assignment PIN_T12 -to PAL_VD_VD[4]
+set_location_assignment PIN_T12 -to PAL_VD_VD_4
+set_location_assignment PIN_Y5 -to PAL_VD_VD[5]
+set_location_assignment PIN_Y5 -to PAL_VD_VD_5
+set_location_assignment PIN_Y4 -to PAL_VD_VD[6]
+set_location_assignment PIN_Y4 -to PAL_VD_VD_6
+set_location_assignment PIN_W8 -to PAL_VD_VD[7]
+set_location_assignment PIN_W8 -to PAL_VD_VD_7
+set_location_assignment PIN_AH4 -to PAL_VD_CLKO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO
+
+set_location_assignment PIN_AH3 -to SERVO_0
+set_location_assignment PIN_AF4 -to SERVO_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1
+
+set_location_assignment PIN_AD12 -to J0_SPI_CLK
+set_location_assignment PIN_AD11 -to J0_SPI_MISO
+set_location_assignment PIN_AF9 -to J0_SPI_CS_N
+set_location_assignment PIN_AD10 -to J0_SPI_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI
+
+set_location_assignment PIN_AF5 -to FROM_ESP_TXD
+set_location_assignment PIN_T13 -to TO_ESP_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD
+
+set_location_assignment PIN_AE7 -to SPI_MISO
+set_location_assignment PIN_AF6 -to SPI_ENA_N
+set_location_assignment PIN_AE8 -to SPI_CLK
+set_location_assignment PIN_AE9 -to SPI_MOSI
+set_location_assignment PIN_AF10 -to SPI_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT
+
+set_location_assignment PIN_AF11 -to LED_BGR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR
+
+#============================================================
+# GPIO_1, GPIO_1 connect to GPIO Default
+#============================================================
+set_location_assignment PIN_AA15 -to RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N
+
+set_location_assignment PIN_AG28 -to TS_SCL
+set_location_assignment PIN_AH27 -to TS_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA
+
+set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N
+set_location_assignment PIN_AG26 -to LCD_DE
+set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN
+
+set_location_assignment PIN_AH24 -to BLT_TXD
+set_location_assignment PIN_AE22 -to BLT_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD
+
+set_location_assignment PIN_AG20 -to BOARD_ID
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID
+
+set_location_assignment PIN_AF21 -to VIDEO_HSYNC
+set_location_assignment PIN_AG19 -to VIDEO_VSYNC
+set_location_assignment PIN_AF20 -to VIDEO_CLK
+set_location_assignment PIN_AG23 -to VIDEO_B[0]
+set_location_assignment PIN_AG23 -to VIDEO_B_0
+set_location_assignment PIN_AH23 -to VIDEO_B[1]
+set_location_assignment PIN_AH23 -to VIDEO_B_1
+set_location_assignment PIN_AF25 -to VIDEO_B[2]
+set_location_assignment PIN_AF25 -to VIDEO_B_2
+set_location_assignment PIN_AG24 -to VIDEO_B[3]
+set_location_assignment PIN_AG24 -to VIDEO_B_3
+set_location_assignment PIN_AA19 -to VIDEO_B[4]
+set_location_assignment PIN_AA19 -to VIDEO_B_4
+set_location_assignment PIN_AH26 -to VIDEO_B[5]
+set_location_assignment PIN_AH26 -to VIDEO_B_5
+set_location_assignment PIN_AG18 -to VIDEO_B[6]
+set_location_assignment PIN_AG18 -to VIDEO_B_6
+set_location_assignment PIN_AC23 -to VIDEO_B[7]
+set_location_assignment PIN_AC23 -to VIDEO_B_7
+set_location_assignment PIN_AH22 -to VIDEO_G[0]
+set_location_assignment PIN_AH22 -to VIDEO_G_0
+set_location_assignment PIN_AF22 -to VIDEO_G[1]
+set_location_assignment PIN_AF22 -to VIDEO_G_1
+set_location_assignment PIN_AD20 -to VIDEO_G[2]
+set_location_assignment PIN_AD20 -to VIDEO_G_2
+set_location_assignment PIN_AE24 -to VIDEO_G[3]
+set_location_assignment PIN_AE24 -to VIDEO_G_3
+set_location_assignment PIN_AE20 -to VIDEO_G[4]
+set_location_assignment PIN_AE20 -to VIDEO_G_4
+set_location_assignment PIN_AD19 -to VIDEO_G[5]
+set_location_assignment PIN_AD19 -to VIDEO_G_5
+set_location_assignment PIN_AF18 -to VIDEO_G[6]
+set_location_assignment PIN_AF18 -to VIDEO_G_6
+set_location_assignment PIN_AE19 -to VIDEO_G[7]
+set_location_assignment PIN_AE19 -to VIDEO_G_7
+set_location_assignment PIN_AC22 -to VIDEO_R[0]
+set_location_assignment PIN_AC22 -to VIDEO_R_0
+set_location_assignment PIN_AA18 -to VIDEO_R[1]
+set_location_assignment PIN_AA18 -to VIDEO_R_1
+set_location_assignment PIN_AE23 -to VIDEO_R[2]
+set_location_assignment PIN_AE23 -to VIDEO_R_2
+set_location_assignment PIN_AD23 -to VIDEO_R[3]
+set_location_assignment PIN_AD23 -to VIDEO_R_3
+set_location_assignment PIN_AH18 -to VIDEO_R[4]
+set_location_assignment PIN_AH18 -to VIDEO_R_4
+set_location_assignment PIN_AG21 -to VIDEO_R[5]
+set_location_assignment PIN_AG21 -to VIDEO_R_5
+set_location_assignment PIN_AH21 -to VIDEO_R[6]
+set_location_assignment PIN_AH21 -to VIDEO_R_6
+set_location_assignment PIN_AH19 -to VIDEO_R[7]
+set_location_assignment PIN_AH19 -to VIDEO_R_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7

cs309-psoc/lab_2_0/hw/quartus/lab_2_0.sdc

@@ -0,0 +1,6 @@
+create_clock -period 20 [get_ports FPGA_CLK1_50]
+create_clock -period 20 [get_ports FPGA_CLK2_50]
+create_clock -period 20 [get_ports FPGA_CLK3_50]
+
+derive_pll_clocks
+derive_clock_uncertainty

cs309-psoc/lab_2_0/sw/nios/application/app.c

@@ -0,0 +1,33 @@
+#include <io.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "lepton/lepton.h"
+#include "system.h"
+
+int main(void) {
+    // Hardware control structures
+    lepton_dev lepton = lepton_inst((void *) LEPTON_0_BASE);
+
+    // Initialize hardware
+    lepton_init(&lepton);
+
+    // =========================================================================
+    // TODO : use the lepton library to capture an image.
+    //
+    // Fill me!
+
+    do{
+    	lepton_start_capture(&lepton);
+        lepton_wait_until_eof(&lepton);
+    }while(lepton_error_check(&lepton));
+
+    //
+    // =========================================================================
+
+    // Save the adjusted (rescaled) buffer to a file.
+    lepton_save_capture(&lepton, true, "/mnt/host/output.pgm");
+
+    return EXIT_SUCCESS;
+}

cs309-psoc/lab_2_0/sw/nios/application/joysticks/joysticks.c

@@ -0,0 +1,79 @@
+#include "joysticks.h"
+
+#define JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL (0)
+#define JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL (1)
+#define JOYSTICK_LEFT_VRY_MCP3204_CHANNEL  (2)
+#define JOYSTICK_LEFT_VRX_MCP3204_CHANNEL  (3)
+
+/**
+ * joysticks_inst
+ *
+ * Instantiate a joysticks device structure.
+ *
+ * @param base Base address of the MCP3204 component connected to the joysticks.
+ */
+joysticks_dev joysticks_inst(void *mcp3204_base) {
+    joysticks_dev dev;
+    dev.mcp3204 = mcp3204_inst((void *) mcp3204_base);
+
+    return dev;
+}
+
+/**
+ * joysticks_init
+ *
+ * Initializes the joysticks device.
+ *
+ * @param dev joysticks device structure.
+ */
+void joysticks_init(joysticks_dev *dev) {
+    mcp3204_init(&(dev->mcp3204));
+}
+
+/**
+ * joysticks_read_left_vertical
+ *
+ * Returns the vertical position of the left joystick. Return value ranges
+ * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
+ *
+ * @param dev joysticks device structure.
+ */
+uint32_t joysticks_read_left_vertical(joysticks_dev *dev) {
+	return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,LV_CHANNEL);
+}
+
+/**
+ * joysticks_read_left_horizontal
+ *
+ * Returns the horizontal position of the left joystick. Return value ranges
+ * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
+ *
+ * @param dev joysticks device structure.
+ */
+uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) {
+	return mcp3204_read(&dev->mcp3204,LH_CHANNEL);
+}
+
+/**
+ * joysticks_read_right_vertical
+ *
+ * Returns the vertical position of the right joystick. Return value ranges
+ * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
+ *
+ * @param dev joysticks device structure.
+ */
+uint32_t joysticks_read_right_vertical(joysticks_dev *dev) {
+	return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,RV_CHANNEL);
+}
+
+/**
+ * joysticks_read_right_horizontal
+ *
+ * Returns the horizontal position of the left joystick. Return value ranges
+ * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
+ *
+ * @param dev joysticks device structure.
+ */
+uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) {
+	return mcp3204_read(&dev->mcp3204,RH_CHANNEL);
+}

cs309-psoc/lab_2_0/sw/nios/application/joysticks/joysticks.h

@@ -0,0 +1,33 @@
+#ifndef __JOYSTICKS_H__
+#define __JOYSTICKS_H__
+
+#include "mcp3204/mcp3204.h"
+
+/* joysticks device structure */
+typedef struct joysticks_dev {
+    mcp3204_dev mcp3204; /* MCP3204 device handle */
+} joysticks_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+
+#define JOYSTICKS_MIN_VALUE (MCP3204_MIN_VALUE)
+#define JOYSTICKS_MAX_VALUE (MCP3204_MAX_VALUE)
+
+#define LV_CHANNEL 0
+#define LH_CHANNEL 1
+#define RV_CHANNEL 2
+#define RH_CHANNEL 3
+#define CC_CHANNEL "this is a joke"
+
+joysticks_dev joysticks_inst(void *mcp3204_base);
+
+void joysticks_init(joysticks_dev *dev);
+
+uint32_t joysticks_read_left_vertical(joysticks_dev *dev);
+uint32_t joysticks_read_left_horizontal(joysticks_dev *dev);
+uint32_t joysticks_read_right_vertical(joysticks_dev *dev);
+uint32_t joysticks_read_right_horizontal(joysticks_dev *dev);
+
+#endif /* __JOYSTICKS_H__ */

cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204.c

@@ -0,0 +1,50 @@
+#include <assert.h>
+#include <io.h>
+
+#include "mcp3204.h"
+#include "mcp3204_regs.h"
+
+#define MCP3204_NUM_CHANNELS (4)
+
+/**
+ * mcp3204_inst
+ *
+ * Instantiate a mcp3204 device structure.
+ *
+ * @param base Base address of the component.
+ */
+mcp3204_dev mcp3204_inst(void *base) {
+    mcp3204_dev dev;
+    dev.base = base;
+
+    return dev;
+}
+
+/**
+ * mcp3204_init
+ *
+ * Initializes the mcp3204 device.
+ *
+ * @param dev mcp3204 device structure.
+ */
+void mcp3204_init(mcp3204_dev *dev) {
+    return;
+}
+
+/**
+ * mcp3204_read
+ *
+ * Reads the register corresponding to the supplied channel parameter.
+ *
+ * @param dev mcp3204 device structure.
+ * @param channel channel to be read
+ */
+uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) {
+	switch(channel){
+		case 0: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_0_OFST);
+		case 1: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_1_OFST);
+		case 2: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_2_OFST);
+		case 3: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_3_OFST);
+		default: return 0;
+	}
+}

cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204.h

@@ -0,0 +1,23 @@
+#ifndef __MCP3204_H__
+#define __MCP3204_H__
+
+#include <stdint.h>
+
+/* mcp3204 device structure */
+typedef struct mcp3204_dev {
+    void *base; /* Base address of component */
+} mcp3204_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+
+#define MCP3204_MIN_VALUE (0)
+#define MCP3204_MAX_VALUE (4095)
+
+mcp3204_dev mcp3204_inst(void *base);
+
+void mcp3204_init(mcp3204_dev *dev);
+uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel);
+
+#endif /* __MCP3204_H__ */

cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h

@@ -0,0 +1,9 @@
+#ifndef __MCP3204_REGS_H__
+#define __MCP3204_REGS_H__
+
+#define MCP3204_CHANNEL_0_OFST (0 * 4) /* RO */
+#define MCP3204_CHANNEL_1_OFST (1 * 4) /* RO */
+#define MCP3204_CHANNEL_2_OFST (2 * 4) /* RO */
+#define MCP3204_CHANNEL_3_OFST (3 * 4) /* RO */
+
+#endif /* __MCP3204_REGS_H__ */

cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton.c

@@ -0,0 +1,118 @@
+#include <assert.h>
+#include <inttypes.h>
+#include <io.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include "lepton_regs.h"
+#include "lepton.h"
+
+/**
+ * lepton_inst
+ *
+ * Instantiate a lepton device structure.
+ *
+ * @param base Base address of the component.
+ */
+lepton_dev lepton_inst(void *base) {
+    lepton_dev dev;
+    dev.base = base;
+
+    return dev;
+}
+
+/**
+ * lepton_init
+ *
+ * Initializes the lepton device.
+ *
+ * @param dev lepton device structure.
+ */
+void lepton_init(lepton_dev *dev) {
+    return;
+}
+
+/**
+ * lepton_start_capture
+ *
+ * Instructs the device to start the frame capture process.
+ *
+ * @param dev lepton device structure.
+ */
+void lepton_start_capture(lepton_dev *dev) {
+	IOWR_16DIRECT(dev->base, LEPTON_REGS_COMMAND_OFST, 0x1);
+}
+
+/**
+ * lepton_error_check
+ *
+ * @abstract Check for errors at the device level.
+ * @param dev lepton device structure.
+ * @return true if there was an error, and false otherwise.
+ */
+bool lepton_error_check(lepton_dev *dev) {
+	return (IORD_16DIRECT(dev->base, LEPTON_REGS_STATUS_OFST) & 0x2) != 0;
+}
+
+/**
+ * lepton_wait_until_eof
+ *
+ * Waits until the frame being captured has been fully received and saved in the
+ * internal memory.
+ *
+ * @param dev lepton device structure.
+ */
+void lepton_wait_until_eof(lepton_dev *dev) {
+	while(IORD_16DIRECT(dev->base, LEPTON_REGS_STATUS_OFST) & 0x1);
+}
+
+/**
+ * lepton_save_capture
+ *
+ * Saves the captured frame on the host filesystem under the supplied filename.
+ * The frame will be saved in PGM format.
+ *
+ * @param dev lepton device structure.
+ * @param adjusted Setting this parameter to false will cause RAW sensor data to
+ *                 be written to the file.
+ *                 Setting this parameter to true will cause a preprocessed image
+ *                 (with a stretched dynamic range) to be saved to the file.
+ *
+ * @param fname the output file name.
+ */
+void lepton_save_capture(lepton_dev *dev, bool adjusted, const char *fname) {
+    FILE *fp = fopen(fname, "w");
+    assert(fp);
+
+    const uint8_t num_rows = 60;
+    const uint8_t num_cols = 80;
+
+    uint16_t offset = LEPTON_REGS_RAW_BUFFER_OFST;
+    uint16_t max_value = IORD_16DIRECT(dev->base, LEPTON_REGS_MAX_OFST);
+    if (adjusted) {
+        offset = LEPTON_REGS_ADJUSTED_BUFFER_OFST;
+        max_value = 0x3fff;
+    }
+
+    /* Write PGM header */
+    fprintf(fp, "P2\n%" PRIu8 " %" PRIu8 "\n%" PRIu16, num_cols, num_rows, max_value);
+
+    /* Write body */
+    uint8_t row = 0;
+    for (row = 0; row < num_rows; ++row) {
+        fprintf(fp, "\n");
+
+        uint8_t col = 0;
+        for (col = 0; col < num_cols; ++col) {
+            if (col > 0) {
+                fprintf(fp, " ");
+            }
+
+            uint16_t current_ofst = offset + (row * num_cols + col) * sizeof(uint16_t);
+            uint16_t pix_value = IORD_16DIRECT(dev->base, current_ofst);
+            fprintf(fp, "%" PRIu16, pix_value);
+        }
+    }
+
+    assert(!fclose(fp));
+}

cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton.h

@@ -0,0 +1,23 @@
+#ifndef __LEPTON_H__
+#define __LEPTON_H__
+
+#include <stdbool.h>
+
+/* lepton device structure */
+typedef struct {
+    void *base; /* Base address of the component */
+} lepton_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+
+lepton_dev lepton_inst(void *base);
+
+void lepton_init(lepton_dev *dev);
+void lepton_start_capture(lepton_dev *dev);
+void lepton_wait_until_eof(lepton_dev *dev);
+bool lepton_error_check(lepton_dev *dev);
+void lepton_save_capture(lepton_dev *dev, bool adjusted, const char *fname);
+
+#endif /* __LEPTON_H__ */

cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton_regs.h

@@ -0,0 +1,25 @@
+#ifndef __LEPTON_REGS_H__
+#define __LEPTON_REGS_H__
+
+/* Register offsets */
+#define LEPTON_REGS_COMMAND_OFST         (   0 * 2)  /* WO */
+#define LEPTON_REGS_STATUS_OFST          (   1 * 2)  /* RO */
+#define LEPTON_REGS_MIN_OFST             (   2 * 2)  /* RO */
+#define LEPTON_REGS_MAX_OFST             (   3 * 2)  /* RO */
+#define LEPTON_REGS_SUM_LSB_OFST         (   4 * 2)  /* RO */
+#define LEPTON_REGS_SUM_MSB_OFST         (   5 * 2)  /* RO */
+#define LEPTON_REGS_ROW_IDX_OFST         (   6 * 2)  /* RO */
+#define LEPTON_REGS_RAW_BUFFER_OFST      (   8 * 2)  /* RO */
+#define LEPTON_REGS_ADJUSTED_BUFFER_OFST (8192 * 2)  /* RO */
+
+/* Command register */
+#define LEPTON_COMMAND_START (0x0001)
+
+/* Status register */
+#define LEPTON_STATUS_CAPTURE_IN_PROGRESS_MASK (1 << 0)
+#define LEPTON_STATUS_ERROR_MASK               (1 << 1)
+
+#define LEPTON_REGS_BUFFER_NUM_PIXELS (80 * 60)
+#define LEPTON_REGS_BUFFER_BYTELENGTH (LEPTON_REGS_BUFFER_NUM_PIXELS * 2)
+
+#endif /* __LEPTON_REGS_H__ */

cs309-psoc/lab_2_0/sw/nios/application/pantilt/pantilt.c

@@ -0,0 +1,109 @@
+#include "pantilt.h"
+
+/**
+ * pantilt_inst
+ *
+ * Instantiate a pantilt device structure.
+ *
+ * @param pwm_v_base Base address of the vertical PWM component.
+ * @param pwm_h_base Base address of the horizontal PWM component.
+ */
+pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) {
+    pantilt_dev dev;
+    dev.pwm_v = pwm_inst(pwm_v_base);
+    dev.pwm_h = pwm_inst(pwm_h_base);
+
+    return dev;
+}
+
+/**
+ * pantilt_init
+ *
+ * Initializes the pantilt device.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_init(pantilt_dev *dev) {
+    pwm_init(&(dev->pwm_v));
+    pwm_init(&(dev->pwm_h));
+}
+
+/**
+ * pantilt_configure_vertical
+ *
+ * Configure the vertical PWM component.
+ *
+ * @param dev pantilt device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ */
+void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) {
+    // Need to compensate for inverted servo rotation.
+    duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US;
+
+    pwm_configure(&(dev->pwm_v),
+                  duty_cycle,
+                  PANTILT_PWM_PERIOD_US,
+                  PANTILT_PWM_CLOCK_FREQ_HZ);
+}
+
+/**
+ * pantilt_configure_horizontal
+ *
+ * Configure the horizontal PWM component.
+ *
+ * @param dev pantilt device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ */
+void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) {
+    // Need to compensate for inverted servo rotation.
+    duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US;
+
+    pwm_configure(&(dev->pwm_h),
+                  duty_cycle,
+                  PANTILT_PWM_PERIOD_US,
+                  PANTILT_PWM_CLOCK_FREQ_HZ);
+}
+
+/**
+ * pantilt_start_vertical
+ *
+ * Starts the vertical pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_start_vertical(pantilt_dev *dev) {
+    pwm_start(&(dev->pwm_v));
+}
+
+/**
+ * pantilt_start_horizontal
+ *
+ * Starts the horizontal pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_start_horizontal(pantilt_dev *dev) {
+    pwm_start(&(dev->pwm_h));
+}
+
+/**
+ * pantilt_stop_vertical
+ *
+ * Stops the vertical pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_stop_vertical(pantilt_dev *dev) {
+    pwm_stop(&(dev->pwm_v));
+}
+
+/**
+ * pantilt_stop_horizontal
+ *
+ * Stops the horizontal pwm controller.
+ *
+ * @param dev pantilt device structure.
+ */
+void pantilt_stop_horizontal(pantilt_dev *dev) {
+    pwm_stop(&(dev->pwm_h));
+}

cs309-psoc/lab_2_0/sw/nios/application/pantilt/pantilt.h

@@ -0,0 +1,39 @@
+#ifndef __PANTILT_H__
+#define __PANTILT_H__
+
+#include "pwm/pwm.h"
+
+/* joysticks device structure */
+typedef struct pantilt_dev {
+    pwm_dev pwm_v; /* Vertical PWM device handle */
+    pwm_dev pwm_h; /* Horizontal PWM device handle */
+} pantilt_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+
+#define PANTILT_PWM_CLOCK_FREQ_HZ       (50000000) // 50.00 MHz
+
+#define PANTILT_PWM_PERIOD_US           (25000)    // 25.00 ms
+
+/* Vertical servo */
+#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950)      //  0.95 ms
+#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150)     //  2.15 ms
+
+/* Horizontal servo */
+#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000)     //  1.00 ms
+#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000)     //  2.00 ms
+
+pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base);
+
+void pantilt_init(pantilt_dev *dev);
+
+void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle);
+void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle);
+void pantilt_start_vertical(pantilt_dev *dev);
+void pantilt_start_horizontal(pantilt_dev *dev);
+void pantilt_stop_vertical(pantilt_dev *dev);
+void pantilt_stop_horizontal(pantilt_dev *dev);
+
+#endif /* __PANTILT_H__ */

cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm.c

@@ -0,0 +1,71 @@
+#include <io.h>
+
+#include "pwm.h"
+#include "pwm_regs.h"
+
+#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000))
+
+
+/**
+ * pwm_inst
+ *
+ * Instantiate a pwm device structure.
+ *
+ * @param base Base address of the component.
+ */
+pwm_dev pwm_inst(void *base) {
+    pwm_dev dev;
+
+    dev.base = base;
+
+    return dev;
+}
+
+/**
+ * pwm_init
+ *
+ * Initializes the pwm device. This function stops the controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_init(pwm_dev *dev) {
+    pwm_stop(dev);
+}
+
+/**
+ * pwm_configure
+ *
+ * Configure pwm component.
+ *
+ * @param dev pwm device structure.
+ * @param duty_cycle pwm duty cycle in us.
+ * @param period pwm period in us.
+ * @param module_frequency frequency at which the component is clocked.
+ */
+void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) {
+
+	IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency));
+	IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency));
+}
+
+/**
+ * pwm_start
+ *
+ * Starts the pwm controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_start(pwm_dev *dev) {
+	IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK);
+}
+
+/**
+ * pwm_stop
+ *
+ * Stops the pwm controller.
+ *
+ * @param dev pwm device structure.
+ */
+void pwm_stop(pwm_dev *dev) {
+	IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK);
+}

cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm.h

@@ -0,0 +1,21 @@
+#ifndef __PWM_H__
+#define __PWM_H__
+
+#include <stdint.h>
+
+/* pwm device structure */
+typedef struct pwm_dev {
+    void *base; /* Base address of component */
+} pwm_dev;
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+pwm_dev pwm_inst(void *base);
+
+void pwm_init(pwm_dev *dev);
+void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency);
+void pwm_start(pwm_dev *dev);
+void pwm_stop(pwm_dev *dev);
+
+#endif /* __PWM_H__ */

cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm_regs.h

@@ -0,0 +1,11 @@
+#ifndef __PWM_REGS_H__
+#define __PWM_REGS_H__
+
+#define PWM_PERIOD_OFST     (0 * 4) /* RW */
+#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */
+#define PWM_CTRL_OFST       (2 * 4) /* WO */
+
+#define PWM_CTRL_STOP_MASK  (0)
+#define PWM_CTRL_START_MASK (1)
+
+#endif /* __PWM_REGS_H__ */

cs309-psoc/lab_2_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd

@@ -0,0 +1,203 @@
+-- #############################################################################
+-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
+--
+-- BOARD         : PrSoC extension board for DE0-Nano-SoC
+-- Author        : Florian Depraz based on Sahand Kashani-Akhavan work
+-- Revision      : 1.1
+-- Creation date : 06/02/2016
+--
+-- Syntax Rule : GROUP_NAME_N[bit]
+--
+-- GROUP : specify a particular interface (ex: SDR_)
+-- NAME  : signal name (ex: CONFIG, D, ...)
+-- bit   : signal index
+-- _N    : to specify an active-low signal
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity DE0_Nano_SoC_PrSoC_extn_board_top_level is
+    port(
+        -------------------------------
+        -- Comment ALL unused ports. --
+        -------------------------------
+
+        -- CLOCK
+        FPGA_CLK1_50 : in std_logic;
+     -- FPGA_CLK2_50 : in std_logic;
+     -- FPGA_CLK3_50 : in std_logic;
+
+        -- KEY on DE0 Nano SoC
+        KEY_N : in std_logic_vector(1 downto 0);
+
+        -- LEDs on DE0 Nano SoC
+     -- LED : out std_logic_vector(7 downto 0);
+
+        -- SWITCHES on DE0 Nano SoC
+     -- SW : in std_logic_vector(3 downto 0);
+
+        -- Servomotors pwm
+        SERVO_0 : out std_logic;
+        SERVO_1 : out std_logic;
+
+        -- ADC Joysticks
+        J0_SPI_CS_n : out std_logic;
+        J0_SPI_MOSI : out std_logic;
+        J0_SPI_MISO : in  std_logic;
+        J0_SPI_CLK  : out std_logic;
+
+        -- Lepton
+        CAM_TH_SPI_CS_N : out std_logic;
+        CAM_TH_MISO     : in  std_logic;
+        CAM_TH_MOSI     : out std_logic;
+        CAM_TH_CLK      : out std_logic
+
+        -- PCA9637
+     -- PIO_SCL   : inout std_logic;
+     -- PIO_SDA   : inout std_logic;
+     -- PIO_INT_N : in    std_logic;
+     -- RESET_N   : out   std_logic;
+
+        -- OV7670
+     -- CAM_D       : in  std_logic_vector(9 downto 0);
+     -- CAM_PIX_CLK : in  std_logic;
+     -- CAM_LV      : in  std_logic;
+     -- CAM_FV      : in  std_logic;
+     -- CAM_SYS_CLK : out std_logic;
+
+        -- VGA and LCD shared signals
+     -- VIDEO_CLK   : out std_logic;
+     -- VIDEO_VSYNC : out std_logic;
+     -- VIDEO_HSYNC : out std_logic;
+     -- VIDEO_B     : out std_logic_vector(7 downto 0);
+     -- VIDEO_G     : out std_logic_vector(7 downto 0);
+     -- VIDEO_R     : out std_logic_vector(7 downto 0);
+
+        -- LCD Specific signals
+     -- LCD_DE         : out   std_logic;
+     -- LCD_PIN_DAV_N  :       ? ?? std_logic;
+     -- LCD_DISPLAY_EN : out   std_logic;
+     -- SPI_MISO       : in    std_logic;
+     -- SPI_ENA_N      : out   std_logic;
+     -- SPI_CLK        : out   std_logic;
+     -- SPI_MOSI       : out   std_logic;
+     -- SPI_DAT        : inout std_logic;
+
+        -- I2C TOUCH SCREEN
+     -- TS_SCL : inout std_logic;
+     -- TS_SDA : inout std_logic;
+
+        -- BLUETOOTH (BLE)
+     -- BLT_TXD : in  std_logic;
+     -- BLT_RXD : out std_logic;
+
+        -- I2C For VGA, PAL and OV7670 cameras
+     -- CAM_PAL_VGA_SDA : inout std_logic;
+     -- CAM_PAL_VGA_SCL : inout std_logic;
+
+        -- ONE WIRE
+     -- BOARD_ID : inout std_logic;
+
+        -- PAL Camera
+     -- PAL_VD_VD   : in  std_logic_vector(7 downto 0);
+     -- PAL_VD_VSO  : in  std_logic;
+     -- PAL_VD_HSO  : in  std_logic;
+     -- PAL_VD_CLKO : in  std_logic;
+     -- PAL_PWDN    : out std_logic;
+
+        -- WIFI
+     -- FROM_ESP_TXD : in  std_logic;
+     -- TO_ESP_RXD   : out std_logic;
+
+        -- LED RGB
+     -- LED_BGR : out std_logic;
+
+        -- HPS
+     -- HPS_CONV_USB_N   : inout std_logic;
+     -- HPS_DDR3_ADDR    : out   std_logic_vector(14 downto 0);
+     -- HPS_DDR3_BA      : out   std_logic_vector(2 downto 0);
+     -- HPS_DDR3_CAS_N   : out   std_logic;
+     -- HPS_DDR3_CK_N    : out   std_logic;
+     -- HPS_DDR3_CK_P    : out   std_logic;
+     -- HPS_DDR3_CKE     : out   std_logic;
+
+     -- HPS_DDR3_CS_N    : out   std_logic;
+     -- HPS_DDR3_DM      : out   std_logic_vector(3 downto 0);
+     -- HPS_DDR3_DQ      : inout std_logic_vector(31 downto 0);
+     -- HPS_DDR3_DQS_N   : inout std_logic_vector(3 downto 0);
+     -- HPS_DDR3_DQS_P   : inout std_logic_vector(3 downto 0);
+     -- HPS_DDR3_ODT     : out   std_logic;
+     -- HPS_DDR3_RAS_N   : out   std_logic;
+     -- HPS_DDR3_RESET_N : out   std_logic;
+     -- HPS_DDR3_RZQ     : in    std_logic;
+     -- HPS_DDR3_WE_N    : out   std_logic;
+     -- HPS_ENET_GTX_CLK : out   std_logic;
+     -- HPS_ENET_INT_N   : inout std_logic;
+     -- HPS_ENET_MDC     : out   std_logic;
+     -- HPS_ENET_MDIO    : inout std_logic;
+     -- HPS_ENET_RX_CLK  : in    std_logic;
+     -- HPS_ENET_RX_DATA : in    std_logic_vector(3 downto 0);
+     -- HPS_ENET_RX_DV   : in    std_logic;
+     -- HPS_ENET_TX_DATA : out   std_logic_vector(3 downto 0);
+     -- HPS_ENET_TX_EN   : out   std_logic;
+     -- HPS_GSENSOR_INT  : inout std_logic;
+     -- HPS_I2C0_SCLK    : inout std_logic;
+     -- HPS_I2C0_SDAT    : inout std_logic;
+     -- HPS_I2C1_SCLK    : inout std_logic;
+     -- HPS_I2C1_SDAT    : inout std_logic;
+     -- HPS_KEY_N        : inout std_logic;
+     -- HPS_LED          : inout std_logic;
+     -- HPS_LTC_GPIO     : inout std_logic;
+     -- HPS_SD_CLK       : out   std_logic;
+     -- HPS_SD_CMD       : inout std_logic;
+     -- HPS_SD_DATA      : inout std_logic_vector(3 downto 0);
+     -- HPS_SPIM_CLK     : out   std_logic;
+     -- HPS_SPIM_MISO    : in    std_logic;
+     -- HPS_SPIM_MOSI    : out   std_logic;
+     -- HPS_SPIM_SS      : inout std_logic;
+     -- HPS_UART_RX      : in    std_logic;
+     -- HPS_UART_TX      : out   std_logic;
+     -- HPS_USB_CLKOUT   : in    std_logic;
+     -- HPS_USB_DATA     : inout std_logic_vector(7 downto 0);
+     -- HPS_USB_DIR      : in    std_logic;
+     -- HPS_USB_NXT      : in    std_logic;
+     -- HPS_USB_STP      : out   std_logic
+    );
+end entity DE0_Nano_SoC_PrSoC_extn_board_top_level;
+
+architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is
+	component soc_system is
+		port (
+			clk_clk                    : in  std_logic := 'X'; -- clk
+			lepton_0_conduit_end_mosi  : out std_logic;        -- mosi
+			lepton_0_conduit_end_miso  : in  std_logic := 'X'; -- miso
+			lepton_0_conduit_end_sclk  : out std_logic;        -- sclk
+			lepton_0_conduit_end_cs_n  : out  std_logic; -- cs_n
+			mcp3204_0_conduit_end_cs_n : out  std_logic; -- cs_n
+			mcp3204_0_conduit_end_miso : in  std_logic := 'X'; -- miso
+			mcp3204_0_conduit_end_mosi : out  std_logic; -- mosi
+			mcp3204_0_conduit_end_sclk : out  std_logic; -- sclk
+			pwm_0_conduit_end_pwm_out  : out std_logic;        -- pwm_out
+			pwm_1_conduit_end_pwm_out  : out std_logic;        -- pwm_out
+			reset_reset_n              : in  std_logic := 'X'  -- reset_n
+		);
+	end component soc_system;
+begin
+	u0 : component soc_system
+		port map (
+			clk_clk                    => FPGA_CLK1_50,                    --                   clk.clk
+			lepton_0_conduit_end_mosi  => CAM_TH_MOSI,  --  lepton_0_conduit_end.mosi
+			lepton_0_conduit_end_miso  => CAM_TH_MISO,  --                      .miso
+			lepton_0_conduit_end_sclk  => CAM_TH_CLK,  --                      .sclk
+			lepton_0_conduit_end_cs_n  => CAM_TH_SPI_CS_N,  --                      .cs_n
+			mcp3204_0_conduit_end_cs_n => J0_SPI_CS_n, -- mcp3204_0_conduit_end.cs_n
+			mcp3204_0_conduit_end_miso => J0_SPI_MISO, --                      .miso
+			mcp3204_0_conduit_end_mosi => J0_SPI_MOSI, --                      .mosi
+			mcp3204_0_conduit_end_sclk => J0_SPI_CLK, --                      .sclk
+			pwm_0_conduit_end_pwm_out  => SERVO_0,  --     pwm_0_conduit_end.pwm_out
+			pwm_1_conduit_end_pwm_out  => SERVO_1,  --     pwm_1_conduit_end.pwm_out
+			reset_reset_n              => KEY_N(0)               --                 reset.reset_n
+		);
+
+end;

cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204.vhd

@@ -0,0 +1,138 @@
+-- #############################################################################
+-- mcp3204.vhd
+-- ===========
+-- MCP3204 Avalon-MM slave interface.
+--
+-- Register map
+-- +-------+-----------+--------+------------------------------------+
+-- | RegNo | Name      | Access | Description                        |
+-- +-------+-----------+--------+------------------------------------+
+-- | 0     | CHANNEL_0 | RO     | 12-bit digital value of channel 0. |
+-- +-------+-----------+--------+------------------------------------+
+-- | 1     | CHANNEL_1 | RO     | 12-bit digital value of channel 1. |
+-- +-------+-----------+--------+------------------------------------+
+-- | 2     | CHANNEL_2 | RO     | 12-bit digital value of channel 2. |
+-- +-------+-----------+--------+------------------------------------+
+-- | 3     | CHANNEL_3 | RO     | 12-bit digital value of channel 3. |
+-- +-------+-----------+--------+------------------------------------+
+--
+-- Author        : Philémon Favrod [philemon.favrod@epfl.ch]
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 2
+-- Last modified : 2018-03-06
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity mcp3204 is
+    port(
+        -- Avalon Clock interface
+        clk : in std_logic;
+
+        -- Avalon Reset interface
+        reset : in std_logic;
+
+        -- Avalon-MM Slave interface
+        address  : in  std_logic_vector(1 downto 0);
+        read     : in  std_logic;
+        readdata : out std_logic_vector(31 downto 0);
+
+        -- Avalon Conduit interface
+        CS_N : out std_logic;
+        MOSI : out std_logic;
+        MISO : in  std_logic;
+        SCLK : out std_logic
+    );
+end entity;
+
+architecture arch of mcp3204 is
+    constant NUM_CHANNELS  : positive := 4;
+    constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS))));
+
+    type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range);
+    signal data_reg : data_array;
+
+    signal spi_busy, spi_start, spi_datavalid : std_logic;
+    signal spi_channel                        : std_logic_vector(1 downto 0);
+    signal spi_data                           : std_logic_vector(11 downto 0);
+
+    type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA);
+    signal state : state_t;
+
+    signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0);
+
+begin
+    SPI : entity work.mcp3204_spi
+    port map(
+        clk        => clk,
+        reset      => reset,
+        busy       => spi_busy,
+        start      => spi_start,
+        channel    => spi_channel,
+        data_valid => spi_datavalid,
+        data       => spi_data,
+        SCLK       => SCLK,
+        CS_N       => CS_N,
+        MOSI       => MOSI,
+        MISO       => MISO
+    );
+
+    -- FSM that dictates which channel is being read. The state of the component
+    -- should be thought as the pair (state, channel)
+    p_fsm : process(reset, clk)
+    begin
+        if reset = '1' then
+            state   <= READY;
+            channel <= (others => '0');
+        elsif rising_edge(clk) then
+            case state is
+                when READY =>
+                    if spi_busy = '0' then
+                        state <= INIT_READ_CHANNEL;
+                    end if;
+
+                when INIT_READ_CHANNEL =>
+                    state <= WAIT_FOR_DATA;
+
+                when WAIT_FOR_DATA =>
+                    if spi_datavalid = '1' then
+                        state   <= READY;
+                        channel <= channel + 1;
+                    end if;
+            end case;
+        end if;
+    end process p_fsm;
+
+    -- Updates the internal registers when a new data is available
+    p_data : process(reset, clk)
+    begin
+        if reset = '1' then
+            for i in 0 to NUM_CHANNELS - 1 loop
+                data_reg(i) <= (others => '0');
+            end loop;
+        elsif rising_edge(clk) then
+            if state = WAIT_FOR_DATA and spi_datavalid = '1' then
+                data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data;
+            end if;
+        end if;
+    end process p_data;
+
+    spi_start   <= '1' when state = INIT_READ_CHANNEL else '0';
+    spi_channel <= std_logic_vector(channel);
+
+    -- Interface with the Avalon Switch Fabric
+    p_avalon_read : process(reset, clk)
+    begin
+        if reset = '1' then
+            readdata <= (others => '0');
+        elsif rising_edge(clk) then
+            if read = '1' then
+                readdata <= data_reg(to_integer(unsigned(address)));
+            end if;
+        end if;
+    end process p_avalon_read;
+
+end architecture;

cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd

@@ -0,0 +1,87 @@
+-- #############################################################################
+-- mcp3204_spi.vhd
+-- ===============
+-- MCP3204 SPI interface.
+--
+-- Author        : Philémon Favrod [philemon.favrod@epfl.ch]
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Author        : <insert your name> (<insert your e-mail address>)
+-- Revision      : 1
+-- Last modified : <insert date>
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mcp3204_spi is
+    port(
+        -- 50 MHz
+        clk        : in  std_logic;
+        reset      : in  std_logic;
+        busy       : out std_logic;
+        start      : in  std_logic;
+        channel    : in  std_logic_vector(1 downto 0);
+        data_valid : out std_logic;
+        data       : out std_logic_vector(11 downto 0);
+
+        -- 1 MHz
+        SCLK : out std_logic;
+        CS_N : out std_logic;
+        MOSI : out std_logic;
+        MISO : in  std_logic
+    );
+end mcp3204_spi;
+
+architecture rtl of mcp3204_spi is
+    signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0');  -- need to be able to count until 24
+    signal reg_spi_en              : std_logic            := '0';  -- pulses every 0.5 MHz
+    signal reg_rising_edge_sclk    : std_logic            := '0';
+    signal reg_falling_edge_sclk   : std_logic            := '0';
+
+    signal reg_sclk : std_logic := '0';
+
+begin
+    clk_divider_generation : process(clk, reset)
+    begin
+        if reset = '1' then
+            reg_clk_divider_counter <= (others => '0');
+        elsif rising_edge(clk) then
+            reg_clk_divider_counter <= reg_clk_divider_counter + 1;
+            reg_spi_en              <= '0';
+            reg_rising_edge_sclk    <= '0';
+            reg_falling_edge_sclk   <= '0';
+
+            if reg_clk_divider_counter = 24 then
+                reg_clk_divider_counter <= (others => '0');
+                reg_spi_en              <= '1';
+
+                if reg_sclk = '0' then
+                    reg_rising_edge_sclk <= '1';
+                elsif reg_sclk = '1' then
+                    reg_falling_edge_sclk <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    SCLK_generation : process(clk, reset)
+    begin
+        if reset = '1' then
+            reg_sclk <= '0';
+        elsif rising_edge(clk) then
+            if reg_spi_en = '1' then
+                reg_sclk <= not reg_sclk;
+            end if;
+        end if;
+    end process;
+
+    STATE_LOGIC : process(clk, reset)
+    begin
+        -- TODO: complete this process
+        if reset = '1' then
+        elsif rising_edge(clk) then
+        end if;
+    end process;
+
+end architecture rtl;

cs309-psoc/lab_2_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd

@@ -0,0 +1,103 @@
+-- #############################################################################
+-- tb_mcp3204_spi.vhd
+-- ==================
+-- Testbench for MCP3204 SPI interface.
+--
+-- Author        : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
+-- Revision      : 1
+-- Last modified : 2018-03-06
+-- #############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_mcp3204_spi is
+end entity;
+
+architecture rtl of tb_mcp3204_spi is
+    constant CLK_PERIOD : time      := 20 ns;
+    signal clk          : std_logic := '0';
+    signal reset        : std_logic := '0';
+    signal sim_finished : boolean   := false;
+
+    -- mcp3204_spi ------------------------------------------------------------
+    signal busy       : std_logic                     := '0';
+    signal start      : std_logic                     := '0';
+    signal channel    : std_logic_vector(1 downto 0)  := (others => '0');
+    signal data_valid : std_logic                     := '0';
+    signal data       : std_logic_vector(11 downto 0) := (others => '0');
+    signal SCLK       : std_logic                     := '0';
+    signal CS_N       : std_logic                     := '1';
+    signal MOSI       : std_logic                     := '0';
+    signal MISO       : std_logic                     := '0';
+
+begin
+    duv : entity work.mcp3204_spi
+    port map(
+        clk        => clk,
+        reset      => reset,
+        busy       => busy,
+        start      => start,
+        channel    => channel,
+        data_valid => data_valid,
+        data       => data,
+        SCLK       => SCLK,
+        CS_N       => CS_N,
+        MOSI       => MOSI,
+        MISO       => MISO
+    );
+
+    clk <= not clk after CLK_PERIOD / 2 when not sim_finished;
+
+    sim : process
+        procedure async_reset is
+        begin
+            wait until rising_edge(clk);
+            wait for CLK_PERIOD / 4;
+            reset <= '1';
+
+            wait for CLK_PERIOD / 2;
+            reset <= '0';
+        end procedure async_reset;
+
+        procedure spi_transfer(constant channel_number : natural range 0 to 3) is
+        begin
+            if busy = '1' then
+                wait until busy = '0';
+
+            else
+                wait until falling_edge(clk);
+                start   <= '1';
+                channel <= std_logic_vector(to_unsigned(channel_number, channel'length));
+
+                wait until falling_edge(clk);
+                start   <= '0';
+                channel <= (others => '0');
+
+                wait until rising_edge(data_valid);
+                wait until falling_edge(busy);
+            end if;
+        end procedure spi_transfer;
+
+    begin
+        async_reset;
+
+        MISO <= '1';
+        spi_transfer(0);
+
+        MISO <= '0';
+        spi_transfer(1);
+
+        MISO <= '1';
+        spi_transfer(2);
+
+        MISO <= '0';
+        spi_transfer(3);
+
+        sim_finished <= true;
+        wait;
+    end process sim;
+end architecture rtl;
+
+

cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd

@@ -0,0 +1,139 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.utils.all;
+
+entity avalon_st_spi_master is
+    generic(
+        INPUT_CLK_FREQ : integer := 50000000;
+        SPI_SCLK_FREQ  : integer := 10000000;
+        CPOL           : integer := 1;
+        CPHA           : integer := 1
+    );
+    port(
+        -- Input clock
+        clk : in std_logic;
+
+        -- Reset
+        reset           : in  std_logic;
+        spi_cs_n        : in  std_logic;
+        -- Sink Avalon ST Interface
+        mosi_sink_data  : in  std_logic_vector(7 downto 0);
+        mosi_sink_valid : in  std_logic;
+        mosi_sink_ready : out std_logic;
+
+        -- Source Avalon ST Interface
+        miso_src_data  : out std_logic_vector(7 downto 0);
+        miso_src_valid : out std_logic;
+
+        -- SPI Master signals
+        SCLK : out std_logic;
+        MISO : in  std_logic;
+        MOSI : out std_logic;
+        CS_n : out std_logic
+    );
+end avalon_st_spi_master;
+
+architecture rtl of avalon_st_spi_master is
+    constant SCLK_PRESCALER_MAX : integer := INPUT_CLK_FREQ / SPI_SCLK_FREQ / 2;
+    signal sclk_prescaler       : unsigned(bitlength(SCLK_PRESCALER_MAX) downto 0);
+    signal sclk_toggle          : std_logic;
+
+    signal new_sink_buffer, cur_sink_buffer           : std_logic_vector(mosi_sink_data'range);
+    signal new_sink_buffer_busy, cur_sink_buffer_busy : std_logic;
+
+    signal miso_src_buffer : std_logic_vector(7 downto 0);
+
+    signal spi_done, i_sclk : std_logic;
+    signal spi_bit_index    : unsigned(2 downto 0);
+begin
+    CS_n <= spi_cs_n;
+
+    p_sclk_prescaler : process(clk, reset) is
+    begin
+        if reset = '1' then
+            sclk_prescaler <= to_unsigned(1, sclk_prescaler'length);
+        elsif rising_edge(clk) then
+            if sclk_prescaler = SCLK_PRESCALER_MAX then
+                sclk_prescaler <= to_unsigned(1, sclk_prescaler'length);
+            else
+                sclk_prescaler <= sclk_prescaler + 1;
+            end if;
+        end if;
+    end process p_sclk_prescaler;
+    sclk_toggle <= '1' when sclk_prescaler = SCLK_PRESCALER_MAX else '0';
+
+    p_avalon_st_sink : process(clk, reset) is
+    begin
+        if reset = '1' then
+            new_sink_buffer_busy <= '0';
+            new_sink_buffer      <= (others => '0');
+        elsif rising_edge(clk) then
+            if mosi_sink_valid = '1' then
+                if new_sink_buffer_busy = '0' and cur_sink_buffer_busy = '1' then
+                    new_sink_buffer      <= mosi_sink_data;
+                    new_sink_buffer_busy <= '1';
+                end if;
+            elsif new_sink_buffer_busy = '1' and cur_sink_buffer_busy = '0' then
+                new_sink_buffer_busy <= '0';
+            end if;
+        end if;
+    end process p_avalon_st_sink;
+    mosi_sink_ready <= not new_sink_buffer_busy;
+
+    p_cur_buffer : process(clk, reset) is
+    begin
+        if reset = '1' then
+            cur_sink_buffer      <= (others => '0');
+            cur_sink_buffer_busy <= '0';
+        elsif rising_edge(clk) then
+            if mosi_sink_valid = '1' and cur_sink_buffer_busy = '0' then
+                cur_sink_buffer      <= mosi_sink_data;
+                cur_sink_buffer_busy <= '1';
+            elsif cur_sink_buffer_busy = '0' and new_sink_buffer_busy = '1' then
+                cur_sink_buffer      <= new_sink_buffer;
+                cur_sink_buffer_busy <= '1';
+            elsif cur_sink_buffer_busy = '1' and spi_done = '1' then
+                cur_sink_buffer_busy <= '0';
+            end if;
+        end if;
+    end process p_cur_buffer;
+
+    p_spi : process(clk, reset) is
+    begin
+        if reset = '1' then
+            spi_done        <= '0';
+            i_sclk          <= to_unsigned(CPOL, 1)(0);
+            spi_bit_index   <= "000";
+            MOSI            <= '0';
+            miso_src_data   <= (others => '0');
+            miso_src_valid  <= '0';
+            miso_src_buffer <= (others => '0');
+
+        elsif rising_edge(clk) then
+            spi_done       <= '0';
+            miso_src_valid <= '0';
+            if cur_sink_buffer_busy = '1' and sclk_toggle = '1' then
+                if i_sclk /= to_unsigned(CPHA, 1)(0) then
+                    if spi_bit_index = "111" then
+                        spi_done       <= '1';
+                        spi_bit_index  <= "000";
+                        miso_src_valid <= '1';
+                        miso_src_data  <= miso_src_buffer(7 downto 1) & MISO;
+                    else
+                        MOSI                                           <= cur_sink_buffer(7 - to_integer(spi_bit_index));
+                        miso_src_buffer(7 - to_integer(spi_bit_index)) <= MISO;
+                        spi_bit_index                                  <= spi_bit_index + 1;
+
+                    end if;
+
+                end if;
+
+                i_sclk <= not i_sclk;
+
+            end if;
+        end if;
+    end process p_spi;
+    SCLK <= i_sclk;
+
+end rtl;

cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/byte2pix.vhd

@@ -0,0 +1,87 @@
+-------------------------------------------------------------------------------
+-- Title      : Byte stream to pixel converter for the Lepton Camera
+-- Project    : PrSoC
+-------------------------------------------------------------------------------
+-- File       : byte2pix.vhd
+-- Author     : Philemon Orphee Favrod  <pofavrod@lappc5.epfl.ch>
+-- Company    :
+-- Created    : 2016-03-21
+-- Last update: 2017-03-19
+-- Platform   :
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Converts a byte stream to a 14-bit pixel stream.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2016
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2016-03-21  1.0      pofavrod        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity byte2pix is
+    port(
+        clk, reset : in  std_logic;
+        byte_data  : in  std_logic_vector(7 downto 0);
+        byte_valid : in  std_logic;
+        byte_sof   : in  std_logic;
+        byte_eof   : in  std_logic;
+        pix_data   : out std_logic_vector(13 downto 0);
+        pix_valid  : out std_logic;
+        pix_sof    : out std_logic;
+        pix_eof    : out std_logic);
+
+end byte2pix;
+
+architecture rtl of byte2pix is
+    signal last_sof : std_logic;
+    signal msb      : std_logic_vector(5 downto 0);
+    signal cnt      : std_logic;  -- used to skip msb sampling every other time
+begin
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            msb      <= (others => '0');
+            cnt      <= '0';
+            last_sof <= '0';
+        elsif rising_edge(clk) then
+            if byte_valid = '1' then
+                if cnt = '0' then
+                    msb      <= byte_data(5 downto 0);
+                    last_sof <= byte_sof;
+                end if;
+                cnt <= not cnt;
+            end if;
+        end if;
+    end process;
+
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            pix_data  <= (others => '0');
+            pix_valid <= '0';
+            pix_sof   <= '0';
+            pix_eof   <= '0';
+        elsif rising_edge(clk) then
+            pix_data  <= (others => '0');
+            pix_valid <= '0';
+            pix_sof   <= '0';
+            pix_eof   <= '0';
+
+            if byte_valid = '1' then
+                if cnt = '1' then
+                    pix_data  <= msb & byte_data;
+                    pix_valid <= '1';
+                    pix_sof   <= last_sof;
+                    pix_eof   <= byte_eof;
+                end if;
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;