diff --git a/cs309-psoc/.gitignore b/cs309-psoc/.gitignore new file mode 100644 index 0000000..17b543b --- /dev/null +++ b/cs309-psoc/.gitignore @@ -0,0 +1,38 @@ +# Specify filepatterns you want git to ignore. + +*.o +*/**/quartus/output_files/ +*/**/quartus/db/ +*/**/incremental_db/ +*/**/simulation/ +*/**/timing/ +*/**/testbench/ +*/**/*_sim/ + +*/**/nios/*/HAL/ +*/**/nios/*/obj/HAL/ +*/**/synthesis +*/**/lab_*_bsp/ +*/**/obj + +*_generation_script* +*_inst.vhd +*.bak +*.cmp +*.done +*.eqn +*.hex +*.jdi +*.mif +*.pin +*.pof +*.ptf.* +*.qar +*.qarlog +*.qws +*.rpt +*.smsg +*.sopc_builder +*.summary +*~ +*sopc_* diff --git a/cs309-psoc/README.md b/cs309-psoc/README.md new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/cs309-psoc/README.md @@ -0,0 +1 @@ + diff --git a/cs309-psoc/lab_1_0/hw/quartus/soc_system.sopcinfo b/cs309-psoc/lab_1_0/hw/quartus/soc_system.sopcinfo new file mode 100644 index 0000000..38bb7fc --- /dev/null +++ b/cs309-psoc/lab_1_0/hw/quartus/soc_system.sopcinfo @@ -0,0 +1,7286 @@ + + + + + + + java.lang.Integer + 1488281335 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 5CSEMA4U23C6 + false + true + false + true + DEVICE + + + java.lang.String + 6 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + clk + + + java.lang.String + Cyclone V + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + CLOCK_RATE + clk_in + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + false + nios2_gen2_0 + clk + nios2_gen2_0.clk + + + false + jtag_uart_0 + clk + jtag_uart_0.clk + + + false + onchip_memory2_0 + clk1 + onchip_memory2_0.clk1 + + + false + pwm_0 + clock + pwm_0.clock + + + false + pwm_1 + clock + pwm_1.clock + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + embeddedsw.CMacro.READ_DEPTH + 64 + + + embeddedsw.CMacro.READ_THRESHOLD + 8 + + + embeddedsw.CMacro.WRITE_DEPTH + 64 + + + embeddedsw.CMacro.WRITE_THRESHOLD + 8 + + + embeddedsw.dts.compatible + altr,juart-1.0 + + + embeddedsw.dts.group + serial + + + embeddedsw.dts.name + juart + + + embeddedsw.dts.vendor + altr + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 64 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + + false + false + false + true + + + java.lang.String + NO_INTERACTIVE_WINDOWS + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 64 + false + true + true + true + + + int + 8 + false + true + true + true + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + 2.0 + false + true + false + true + AVALON_SPEC + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + rst_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 2 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + av_chipselect + Input + 1 + chipselect + + + av_address + Input + 1 + address + + + av_read_n + Input + 1 + read_n + + + av_readdata + Output + 32 + readdata + + + av_write_n + Input + 1 + write_n + + + av_writedata + Input + 32 + writedata + + + av_waitrequest + Output + 1 + waitrequest + + + + + + com.altera.entityinterfaces.IConnectionPoint + jtag_uart_0.avalon_jtag_slave + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + java.lang.Integer + + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + av_irq + Output + 1 + irq + + + + + + + debug.hostConnection + type jtag id 70:34|110:135 + + + embeddedsw.CMacro.BIG_ENDIAN + 0 + + + embeddedsw.CMacro.BREAK_ADDR + 0x00040820 + + + embeddedsw.CMacro.CPU_ARCH_NIOS2_R1 + + + + embeddedsw.CMacro.CPU_FREQ + 50000000u + + + embeddedsw.CMacro.CPU_ID_SIZE + 1 + + + embeddedsw.CMacro.CPU_ID_VALUE + 0x00000000 + + + embeddedsw.CMacro.CPU_IMPLEMENTATION + "fast" + + + embeddedsw.CMacro.DATA_ADDR_WIDTH + 19 + + + embeddedsw.CMacro.DCACHE_BYPASS_MASK + 0x80000000 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE + 32 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2 + 5 + + + embeddedsw.CMacro.DCACHE_SIZE + 2048 + + + embeddedsw.CMacro.EXCEPTION_ADDR + 0x00020020 + + + embeddedsw.CMacro.FLASH_ACCELERATOR_LINES + 0 + + + embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE + 0 + + + embeddedsw.CMacro.FLUSHDA_SUPPORTED + + + + embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT + 0 + + + embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT + 1 + + + embeddedsw.CMacro.HARDWARE_MULX_PRESENT + 0 + + + embeddedsw.CMacro.HAS_DEBUG_CORE + 1 + + + embeddedsw.CMacro.HAS_DEBUG_STUB + + + + embeddedsw.CMacro.HAS_EXTRA_EXCEPTION_INFO + + + + embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION + + + + embeddedsw.CMacro.HAS_JMPI_INSTRUCTION + + + + embeddedsw.CMacro.ICACHE_LINE_SIZE + 32 + + + embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2 + 5 + + + embeddedsw.CMacro.ICACHE_SIZE + 4096 + + + embeddedsw.CMacro.INITDA_SUPPORTED + + + + embeddedsw.CMacro.INST_ADDR_WIDTH + 19 + + + embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS + 0 + + + embeddedsw.CMacro.OCI_VERSION + 1 + + + embeddedsw.CMacro.RESET_ADDR + 0x00020000 + + + embeddedsw.configuration.DataCacheVictimBufImpl + ram + + + embeddedsw.configuration.HDLSimCachesCleared + 1 + + + embeddedsw.configuration.breakOffset + 32 + + + embeddedsw.configuration.breakSlave + nios2_gen2_0.debug_mem_slave + + + embeddedsw.configuration.cpuArchitecture + Nios II + + + embeddedsw.configuration.exceptionOffset + 32 + + + embeddedsw.configuration.exceptionSlave + onchip_memory2_0.s1 + + + embeddedsw.configuration.resetOffset + 0 + + + embeddedsw.configuration.resetSlave + onchip_memory2_0.s1 + + + embeddedsw.dts.compatible + altr,nios2-1.1 + + + embeddedsw.dts.group + cpu + + + embeddedsw.dts.name + nios2 + + + embeddedsw.dts.params.altr,exception-addr + 0x00020020 + + + embeddedsw.dts.params.altr,has-initda + 1 + + + embeddedsw.dts.params.altr,has-mul + 1 + + + embeddedsw.dts.params.altr,implementation + "fast" + + + embeddedsw.dts.params.altr,reset-addr + 0x00020000 + + + embeddedsw.dts.params.clock-frequency + 50000000u + + + embeddedsw.dts.params.dcache-line-size + 32 + + + embeddedsw.dts.params.dcache-size + 2048 + + + embeddedsw.dts.params.icache-line-size + 32 + + + embeddedsw.dts.params.icache-size + 4096 + + + embeddedsw.dts.vendor + altr + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 8 + false + false + true + true + + + int + 8 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 32 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + onchip_memory2_0.s1 + false + true + true + true + + + java.lang.String + None + false + false + true + true + + + java.lang.String + onchip_memory2_0.s1 + false + true + true + true + + + java.lang.String + None + false + true + false + true + + + java.lang.String + Internal + false + true + true + true + + + java.lang.String + Dynamic + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + fast_le_shift + true + true + false + true + + + java.lang.String + mul_fast32 + true + true + false + true + + + int + 0 + false + true + true + true + + + int + 2 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + false + true + true + + + java.lang.String + no_div + false + true + true + true + + + int + 12 + false + false + true + true + + + int + 12 + false + false + true + true + + + int + 4 + false + false + true + true + + + int + 6 + false + false + true + true + + + int + 7 + false + false + true + true + + + int + 16 + false + false + true + true + + + int + 8 + false + false + true + true + + + java.lang.String + Fast + false + true + true + true + + + int + 4096 + false + true + true + true + + + int + 2 + false + false + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + None + false + true + true + true + + + java.lang.String + false + false + true + true + true + + + java.lang.String + ram + false + true + true + true + + + int + 2048 + false + true + true + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + _128 + false + false + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + none + false + true + true + true + + + java.lang.String + onchip_trace + false + false + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + int + 131072 + true + true + true + true + + + int + 131104 + true + true + true + true + + + int + 264224 + true + true + false + true + + + int + 0 + true + true + true + true + + + java.lang.String + false + true + true + false + true + + + int + 2048 + true + true + false + true + + + java.lang.String + nios2_gen2_0.debug_mem_slave + true + true + false + true + + + int + 32 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + java.lang.String + "synthesis translate_on" + true + true + false + true + + + java.lang.String + "synthesis translate_off" + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 19 + false + true + false + true + ADDRESS_WIDTH + instruction_master + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + flash_instruction_master + + + int + 19 + false + true + false + true + ADDRESS_WIDTH + data_master + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_data_master_0 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_data_master_1 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_data_master_2 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_data_master_3 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_instruction_master_0 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_instruction_master_1 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_instruction_master_2 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + tightly_coupled_instruction_master_3 + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + data_master_high_performance + + + int + 1 + false + true + false + true + ADDRESS_WIDTH + instruction_master_high_performance + + + java.lang.String + ]]> + false + true + false + true + ADDRESS_MAP + instruction_master + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + flash_instruction_master + + + java.lang.String + ]]> + false + true + false + true + ADDRESS_MAP + data_master + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_data_master_0 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_data_master_1 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_data_master_2 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_data_master_3 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_instruction_master_0 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_instruction_master_1 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_instruction_master_2 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + tightly_coupled_instruction_master_3 + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + data_master_high_performance + + + java.lang.String + + false + true + false + true + ADDRESS_MAP + instruction_master_high_performance + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + long + 1 + false + true + false + true + INTERRUPTS_USED + irq + + + java.lang.String + ]]> + false + true + false + true + CUSTOM_INSTRUCTION_SLAVES + custom_instruction_master + + + java.lang.String + ]]> + false + true + false + true + CUSTOM_INSTRUCTION_SLAVES + custom_instruction_master_a + + + java.lang.String + ]]> + false + true + false + true + CUSTOM_INSTRUCTION_SLAVES + custom_instruction_master_b + + + java.lang.String + ]]> + false + true + false + true + CUSTOM_INSTRUCTION_SLAVES + custom_instruction_master_c + + + java.lang.String + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + false + true + false + true + DEVICE_FEATURES + + + java.lang.String + 5CSEMA4U23C6 + false + true + false + true + DEVICE + + + java.lang.String + 6 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.Integer + 1 + false + true + false + true + CLOCK_DOMAIN + clk + + + java.lang.Integer + 1 + false + true + false + true + RESET_DOMAIN + clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + reset_req + Input + 1 + reset_req + + + + + + debug.providesServices + master + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + 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1 + readdatavalid + + + debug_mem_slave_debugaccess_to_roms + Output + 1 + debugaccess + + + false + jtag_uart_0 + avalon_jtag_slave + jtag_uart_0.avalon_jtag_slave + 266272 + 8 + + + false + pwm_0 + avalon_slave_0 + pwm_0.avalon_slave_0 + 266256 + 16 + + + false + pwm_1 + avalon_slave_0 + pwm_1.avalon_slave_0 + 266240 + 16 + + + false + nios2_gen2_0 + debug_mem_slave + nios2_gen2_0.debug_mem_slave + 264192 + 2048 + + + false + onchip_memory2_0 + s1 + onchip_memory2_0.s1 + 131072 + 131072 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + 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true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + i_address + Output + 19 + address + + + i_read + Output + 1 + read + + + i_readdata + Input + 32 + readdata + + + i_waitrequest + Input + 1 + waitrequest + + + i_readdatavalid + Input + 1 + readdatavalid + + + false + nios2_gen2_0 + debug_mem_slave + nios2_gen2_0.debug_mem_slave + 264192 + 2048 + + + false + onchip_memory2_0 + s1 + onchip_memory2_0.s1 + 131072 + 131072 + + + + + + com.altera.entityinterfaces.IConnectionPoint + nios2_gen2_0.data_master + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + irq + Input + 32 + irq + + + false + jtag_uart_0 + irq + jtag_uart_0.irq + 0 + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + none + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + debug_reset_request + Output + 1 + reset + + + + + + embeddedsw.configuration.hideDevice + 1 + + + qsys.ui.connect + instruction_master,data_master + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 2048 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + debug_mem_slave_address + Input + 9 + address + + + debug_mem_slave_byteenable + Input + 4 + byteenable + + + debug_mem_slave_debugaccess + Input + 1 + debugaccess + + + debug_mem_slave_read + Input + 1 + read + + + debug_mem_slave_readdata + Output + 32 + readdata + + + debug_mem_slave_waitrequest + Output + 1 + waitrequest + + + debug_mem_slave_write + Input + 1 + write + + + debug_mem_slave_writedata + Input + 32 + writedata + + + + + + java.lang.String + + true + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + true + + dummy_ci_port + Output + 1 + readra + + + + + + + embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR + 0 + + + embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE + 0 + + + embeddedsw.CMacro.CONTENTS_INFO + "" + + + embeddedsw.CMacro.DUAL_PORT + 0 + + + embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE + AUTO + + + embeddedsw.CMacro.INIT_CONTENTS_FILE + soc_system_onchip_memory2_0 + + + embeddedsw.CMacro.INIT_MEM_CONTENT + 1 + + + embeddedsw.CMacro.INSTANCE_ID + NONE + + + embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED + 0 + + + embeddedsw.CMacro.RAM_BLOCK_TYPE + AUTO + + + embeddedsw.CMacro.READ_DURING_WRITE_MODE + DONT_CARE + + + embeddedsw.CMacro.SINGLE_CLOCK_OP + 0 + + + embeddedsw.CMacro.SIZE_MULTIPLE + 1 + + + embeddedsw.CMacro.SIZE_VALUE + 131072 + + + embeddedsw.CMacro.WRITABLE + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.HAS_BYTE_LANE + 0 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + QPF_DIR + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.MEM_INIT_FILENAME + soc_system_onchip_memory2_0 + + + postgeneration.simulation.init_file.param_name + INIT_FILE + + + postgeneration.simulation.init_file.type + MEM_INIT + + + boolean + false + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + onchip_mem.hex + false + false + true + true + + + java.lang.String + NONE + false + false + true + true + + + long + 131072 + false + true + true + true + + + java.lang.String + DONT_CARE + false + false + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + false + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + false + true + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + soc_system_onchip_memory2_0 + false + true + false + true + UNIQUE_ID + + + java.lang.String + CYCLONEV + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + false + true + false + true + DEVICE_FEATURES + + + int + 15 + true + true + false + true + + + int + 15 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 32 + true + true + false + true + + + java.lang.String + Automatic + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + soc_system_onchip_memory2_0.hex + true + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 131072 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk1 + false + true + true + true + + + java.lang.String + reset1 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 131072 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 15 + address + + + clken + Input + 1 + clken + + + chipselect + Input + 1 + chipselect + + + write + Input + 1 + write + + + readdata + Output + 32 + readdata + + + writedata + Input + 32 + writedata + + + byteenable + Input + 4 + byteenable + + + + + + java.lang.String + clk1 + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + reset_req + Input + 1 + reset_req + + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clock + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 16 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + read + Input + 1 + read + + + write + Input + 1 + write + + + readdata + Output + 32 + readdata + + + writedata + Input + 32 + writedata + + + + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + pwm_out + Output + 1 + pwm + + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clock + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 16 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + read + Input + 1 + read + + + write + Input + 1 + write + + + readdata + Output + 32 + readdata + + + writedata + Input + 32 + writedata + + + + + + java.lang.String + clock + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + pwm_out + Output + 1 + pwm + + + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041020 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + data_master + jtag_uart_0 + avalon_jtag_slave + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041010 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + data_master + pwm_0 + avalon_slave_0 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + data_master + pwm_1 + avalon_slave_0 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00040800 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + data_master + nios2_gen2_0 + debug_mem_slave + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00020000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + data_master + onchip_memory2_0 + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00040800 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + instruction_master + nios2_gen2_0 + debug_mem_slave + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00020000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + instruction_master + onchip_memory2_0 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + nios2_gen2_0 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + jtag_uart_0 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + onchip_memory2_0 + clk1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + pwm_0 + clock + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + pwm_1 + clock + + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + irq + jtag_uart_0 + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + nios2_gen2_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + jtag_uart_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + pwm_1 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + pwm_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + onchip_memory2_0 + reset1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + debug_reset_request + nios2_gen2_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + debug_reset_request + jtag_uart_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + debug_reset_request + pwm_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + debug_reset_request + pwm_1 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_gen2_0 + debug_reset_request + onchip_memory2_0 + reset1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 16.0 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 16.0 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 16.0 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 16.0 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 16.0 + + + 1 + altera_avalon_jtag_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + JTAG UART + 16.0 + + + 5 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 16.0 + + + 5 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 16.0 + + + 5 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 16.0 + + + 1 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 16.0 + + + 1 + altera_nios2_gen2 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Nios II Processor + 16.0 + + + 2 + avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Master + 16.0 + + + 1 + interrupt_receiver + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 16.0 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 16.0 + + + 1 + nios_custom_instruction_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Custom Instruction Master + 16.0 + + + 1 + altera_avalon_onchip_memory2 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + On-Chip Memory (RAM or ROM) + 16.0 + + + 2 + pwm + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + pwm + 1.0 + + + 2 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 16.0 + + + 7 + avalon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection + 16.0 + + + 5 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 16.0 + + + 1 + interrupt + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Interrupt Connection + 16.0 + + + 10 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection + 16.0 + + 16.0 211 + + diff --git a/cs309-psoc/lab_1_0/lab_1_0.pdf b/cs309-psoc/lab_1_0/lab_1_0.pdf new file mode 100644 index 0000000..a362052 Binary files /dev/null and b/cs309-psoc/lab_1_0/lab_1_0.pdf differ diff --git a/cs309-psoc/lab_1_0/sw/nios/application/app.c b/cs309-psoc/lab_1_0/sw/nios/application/app.c new file mode 100644 index 0000000..68bced9 --- /dev/null +++ b/cs309-psoc/lab_1_0/sw/nios/application/app.c @@ -0,0 +1,69 @@ +#include +#include +#include +#include +#include +#include + +#include "pantilt/pantilt.h" +#include "system.h" + +#define SLEEP_DURATION_US (25000) // 25 ms +#define PANTILT_STEP_US (25) // 25 us + +#define PANTILT_PWM_V_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_V_MIN_DUTY_CYCLE_US + PANTILT_PWM_V_MAX_DUTY_CYCLE_US) / 2) +#define PANTILT_PWM_H_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_H_MIN_DUTY_CYCLE_US + PANTILT_PWM_H_MAX_DUTY_CYCLE_US) / 2) + +int main(void) { + // Hardware control structures + pantilt_dev pantilt = pantilt_inst((void *) PWM_0_BASE, (void *) PWM_1_BASE); + + // Initialize hardware + pantilt_init(&pantilt); + + // Center servos. + pantilt_configure_vertical(&pantilt, PANTILT_PWM_V_MIN_DUTY_CYCLE_US); + pantilt_configure_horizontal(&pantilt, PANTILT_PWM_H_MIN_DUTY_CYCLE_US); + pantilt_start_vertical(&pantilt); + pantilt_start_horizontal(&pantilt); + + // Rotate servos in "square" motion + while (true) { + uint32_t v_duty_us = 0; + uint32_t h_duty_us = 0; + + // bottom to top + v_duty_us = PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + do { + pantilt_configure_vertical(&pantilt, v_duty_us); + v_duty_us += PANTILT_STEP_US; + usleep(SLEEP_DURATION_US); + } while (v_duty_us <= PANTILT_PWM_V_MAX_DUTY_CYCLE_US); + + // left to right + h_duty_us = PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + do { + pantilt_configure_horizontal(&pantilt, h_duty_us); + h_duty_us += PANTILT_STEP_US; + usleep(SLEEP_DURATION_US); + } while (h_duty_us <= PANTILT_PWM_H_MAX_DUTY_CYCLE_US); + + // top to bottom + v_duty_us = PANTILT_PWM_V_MAX_DUTY_CYCLE_US; + do { + pantilt_configure_vertical(&pantilt, v_duty_us); + v_duty_us -= PANTILT_STEP_US; + usleep(SLEEP_DURATION_US); + } while (PANTILT_PWM_V_MIN_DUTY_CYCLE_US <= v_duty_us); + + // left to right + h_duty_us = PANTILT_PWM_H_MAX_DUTY_CYCLE_US; + do { + pantilt_configure_horizontal(&pantilt, h_duty_us); + h_duty_us -= PANTILT_STEP_US; + usleep(SLEEP_DURATION_US); + } while (PANTILT_PWM_H_MIN_DUTY_CYCLE_US <= h_duty_us); + } + + return EXIT_SUCCESS; +} diff --git a/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pantilt.c b/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pantilt.c new file mode 100644 index 0000000..d9c4c72 --- /dev/null +++ b/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pantilt.c @@ -0,0 +1,109 @@ +#include "pantilt.h" + +/** + * pantilt_inst + * + * Instantiate a pantilt device structure. + * + * @param pwm_v_base Base address of the vertical PWM component. + * @param pwm_h_base Base address of the horizontal PWM component. + */ +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) { + pantilt_dev dev; + dev.pwm_v = pwm_inst(pwm_v_base); + dev.pwm_h = pwm_inst(pwm_h_base); + + return dev; +} + +/** + * pantilt_init + * + * Initializes the pantilt device. + * + * @param dev pantilt device structure. + */ +void pantilt_init(pantilt_dev *dev) { + pwm_init(&(dev->pwm_v)); + pwm_init(&(dev->pwm_h)); +} + +/** + * pantilt_configure_vertical + * + * Configure the vertical PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_v), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_configure_horizontal + * + * Configure the horizontal PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_h), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_start_vertical + * + * Starts the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_vertical(pantilt_dev *dev) { + pwm_start(&(dev->pwm_v)); +} + +/** + * pantilt_start_horizontal + * + * Starts the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_horizontal(pantilt_dev *dev) { + pwm_start(&(dev->pwm_h)); +} + +/** + * pantilt_stop_vertical + * + * Stops the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_vertical(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_v)); +} + +/** + * pantilt_stop_horizontal + * + * Stops the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_horizontal(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_h)); +} diff --git a/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pantilt.h b/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pantilt.h new file mode 100644 index 0000000..1f17500 --- /dev/null +++ b/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pantilt.h @@ -0,0 +1,39 @@ +#ifndef __PANTILT_H__ +#define __PANTILT_H__ + +#include "pwm/pwm.h" + +/* joysticks device structure */ +typedef struct pantilt_dev { + pwm_dev pwm_v; /* Vertical PWM device handle */ + pwm_dev pwm_h; /* Horizontal PWM device handle */ +} pantilt_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz + +#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms + +/* Vertical servo */ +#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms +#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms + +/* Horizontal servo */ +#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms +#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms + +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base); + +void pantilt_init(pantilt_dev *dev); + +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_start_vertical(pantilt_dev *dev); +void pantilt_start_horizontal(pantilt_dev *dev); +void pantilt_stop_vertical(pantilt_dev *dev); +void pantilt_stop_horizontal(pantilt_dev *dev); + +#endif /* __PANTILT_H__ */ diff --git a/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm.c b/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm.c new file mode 100644 index 0000000..293be53 --- /dev/null +++ b/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm.c @@ -0,0 +1,71 @@ +#include + +#include "pwm.h" +#include "pwm_regs.h" + +#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000)) + + +/** + * pwm_inst + * + * Instantiate a pwm device structure. + * + * @param base Base address of the component. + */ +pwm_dev pwm_inst(void *base) { + pwm_dev dev; + + dev.base = base; + + return dev; +} + +/** + * pwm_init + * + * Initializes the pwm device. This function stops the controller. + * + * @param dev pwm device structure. + */ +void pwm_init(pwm_dev *dev) { + pwm_stop(dev); +} + +/** + * pwm_configure + * + * Configure pwm component. + * + * @param dev pwm device structure. + * @param duty_cycle pwm duty cycle in us. + * @param period pwm period in us. + * @param module_frequency frequency at which the component is clocked. + */ +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) { + + IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency)); + IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency)); +} + +/** + * pwm_start + * + * Starts the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_start(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} + +/** + * pwm_stop + * + * Stops the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_stop(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK); +} diff --git a/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm.h b/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm.h new file mode 100644 index 0000000..e2987f4 --- /dev/null +++ b/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm.h @@ -0,0 +1,21 @@ +#ifndef __PWM_H__ +#define __PWM_H__ + +#include + +/* pwm device structure */ +typedef struct pwm_dev { + void *base; /* Base address of component */ +} pwm_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ +pwm_dev pwm_inst(void *base); + +void pwm_init(pwm_dev *dev); +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency); +void pwm_start(pwm_dev *dev); +void pwm_stop(pwm_dev *dev); + +#endif /* __PWM_H__ */ diff --git a/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm_regs.h b/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm_regs.h new file mode 100644 index 0000000..488583d --- /dev/null +++ b/cs309-psoc/lab_1_0/sw/nios/application/pantilt/pwm/pwm_regs.h @@ -0,0 +1,11 @@ +#ifndef __PWM_REGS_H__ +#define __PWM_REGS_H__ + +#define PWM_PERIOD_OFST (0 * 4) /* RW */ +#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */ +#define PWM_CTRL_OFST (2 * 4) /* WO */ + +#define PWM_CTRL_STOP_MASK (0) +#define PWM_CTRL_START_MASK (1) + +#endif /* __PWM_REGS_H__ */ diff --git a/cs309-psoc/lab_1_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd b/cs309-psoc/lab_1_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd new file mode 100644 index 0000000..bcb62be --- /dev/null +++ b/cs309-psoc/lab_1_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd @@ -0,0 +1,187 @@ +-- ############################################################################# +-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +-- +-- BOARD : PrSoC extension board for DE0-Nano-SoC +-- Author : Florian Depraz based on Sahand Kashani-Akhavan work +-- Revision : 1.1 +-- Creation date : 06/02/2016 +-- +-- Syntax Rule : GROUP_NAME_N[bit] +-- +-- GROUP : specify a particular interface (ex: SDR_) +-- NAME : signal name (ex: CONFIG, D, ...) +-- bit : signal index +-- _N : to specify an active-low signal +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; + +entity DE0_Nano_SoC_PrSoC_extn_board_top_level is + port( + ------------------------------- + -- Comment ALL unused ports. -- + ------------------------------- + + -- CLOCK + FPGA_CLK1_50 : in std_logic; + -- FPGA_CLK2_50 : in std_logic; + -- FPGA_CLK3_50 : in std_logic; + + -- KEY on DE0 Nano SoC + KEY_N : in std_logic_vector(1 downto 0); + + -- LEDs on DE0 Nano SoC + -- LED : out std_logic_vector(7 downto 0); + + -- SWITCHES on DE0 Nano SoC + -- SW : in std_logic_vector(3 downto 0); + + -- Servomotors pwm + SERVO_0 : out std_logic; + SERVO_1 : out std_logic + + -- ADC Joysticks + -- J0_SPI_CS_n : out std_logic; + -- J0_SPI_MOSI : out std_logic; + -- J0_SPI_MISO : in std_logic; + -- J0_SPI_CLK : out std_logic; + + -- Lepton + -- CAM_TH_SPI_CS_N : out std_logic; + -- CAM_TH_MISO : in std_logic; + -- CAM_TH_MOSI : out std_logic; + -- CAM_TH_CLK : out std_logic; + + -- PCA9637 + -- PIO_SCL : inout std_logic; + -- PIO_SDA : inout std_logic; + -- PIO_INT_N : in std_logic; + -- RESET_N : out std_logic; + + -- OV7670 + -- CAM_D : in std_logic_vector(9 downto 0); + -- CAM_PIX_CLK : in std_logic; + -- CAM_LV : in std_logic; + -- CAM_FV : in std_logic; + -- CAM_SYS_CLK : out std_logic; + + -- VGA and LCD shared signals + -- VIDEO_CLK : out std_logic; + -- VIDEO_VSYNC : out std_logic; + -- VIDEO_HSYNC : out std_logic; + -- VIDEO_B : out std_logic_vector(7 downto 0); + -- VIDEO_G : out std_logic_vector(7 downto 0); + -- VIDEO_R : out std_logic_vector(7 downto 0); + + -- LCD Specific signals + -- LCD_DE : out std_logic; + -- LCD_PIN_DAV_N : ? ?? std_logic; + -- LCD_DISPLAY_EN : out std_logic; + -- SPI_MISO : in std_logic; + -- SPI_ENA_N : out std_logic; + -- SPI_CLK : out std_logic; + -- SPI_MOSI : out std_logic; + -- SPI_DAT : inout std_logic; + + -- I2C TOUCH SCREEN + -- TS_SCL : inout std_logic; + -- TS_SDA : inout std_logic; + + -- BLUETOOTH (BLE) + -- BLT_TXD : in std_logic; + -- BLT_RXD : out std_logic; + + -- I2C For VGA, PAL and OV7670 cameras + -- CAM_PAL_VGA_SDA : inout std_logic; + -- CAM_PAL_VGA_SCL : inout std_logic; + + -- ONE WIRE + -- BOARD_ID : inout std_logic; + + -- PAL Camera + -- PAL_VD_VD : in std_logic_vector(7 downto 0); + -- PAL_VD_VSO : in std_logic; + -- PAL_VD_HSO : in std_logic; + -- PAL_VD_CLKO : in std_logic; + -- PAL_PWDN : out std_logic; + + -- WIFI + -- FROM_ESP_TXD : in std_logic; + -- TO_ESP_RXD : out std_logic; + + -- LED RGB + -- LED_BGR : out std_logic; + + -- HPS + -- HPS_CONV_USB_N : inout std_logic; + -- HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); + -- HPS_DDR3_BA : out std_logic_vector(2 downto 0); + -- HPS_DDR3_CAS_N : out std_logic; + -- HPS_DDR3_CK_N : out std_logic; + -- HPS_DDR3_CK_P : out std_logic; + -- HPS_DDR3_CKE : out std_logic; + -- HPS_DDR3_CS_N : out std_logic; + -- HPS_DDR3_DM : out std_logic_vector(3 downto 0); + -- HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); + -- HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); + -- HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); + -- HPS_DDR3_ODT : out std_logic; + -- HPS_DDR3_RAS_N : out std_logic; + -- HPS_DDR3_RESET_N : out std_logic; + -- HPS_DDR3_RZQ : in std_logic; + -- HPS_DDR3_WE_N : out std_logic; + -- HPS_ENET_GTX_CLK : out std_logic; + -- HPS_ENET_INT_N : inout std_logic; + -- HPS_ENET_MDC : out std_logic; + -- HPS_ENET_MDIO : inout std_logic; + -- HPS_ENET_RX_CLK : in std_logic; + -- HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); + -- HPS_ENET_RX_DV : in std_logic; + -- HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); + -- HPS_ENET_TX_EN : out std_logic; + -- HPS_GSENSOR_INT : inout std_logic; + -- HPS_I2C0_SCLK : inout std_logic; + -- HPS_I2C0_SDAT : inout std_logic; + -- HPS_I2C1_SCLK : inout std_logic; + -- HPS_I2C1_SDAT : inout std_logic; + -- HPS_KEY_N : inout std_logic; + -- HPS_LED : inout std_logic; + -- HPS_LTC_GPIO : inout std_logic; + -- HPS_SD_CLK : out std_logic; + -- HPS_SD_CMD : inout std_logic; + -- HPS_SD_DATA : inout std_logic_vector(3 downto 0); + -- HPS_SPIM_CLK : out std_logic; + -- HPS_SPIM_MISO : in std_logic; + -- HPS_SPIM_MOSI : out std_logic; + -- HPS_SPIM_SS : inout std_logic; + -- HPS_UART_RX : in std_logic; + -- HPS_UART_TX : out std_logic; + -- HPS_USB_CLKOUT : in std_logic; + -- HPS_USB_DATA : inout std_logic_vector(7 downto 0); + -- HPS_USB_DIR : in std_logic; + -- HPS_USB_NXT : in std_logic; + -- HPS_USB_STP : out std_logic + ); +end entity DE0_Nano_SoC_PrSoC_extn_board_top_level; + +architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is + component soc_system is + port ( + clk_clk : in std_logic := 'X'; + reset_reset_n : in std_logic := 'X'; + pwm_0_conduit_end_pwm : out std_logic; + pwm_1_conduit_end_pwm : out std_logic + ); + end component soc_system; + +begin + soc_system_inst : component soc_system + port map ( + clk_clk => FPGA_CLK1_50, + reset_reset_n => KEY_N(0), + pwm_0_conduit_end_pwm => SERVO_0, + pwm_1_conduit_end_pwm => SERVO_1 + ); + +end; diff --git a/cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm.vhd b/cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm.vhd new file mode 100644 index 0000000..03a6840 --- /dev/null +++ b/cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm.vhd @@ -0,0 +1,134 @@ +-- ############################################################################# +-- pwm.vhd +-- ======= +-- PWM memory-mapped Avalon slave interface. +-- +-- Author : Cedric Hoelzl (cedric.hoelzl@epfl.ch) +-- Author : Antoine Brunner (antoine.brunner@epfl.ch) +-- Revision : 0.0.1a_rc1 +-- Last modified : a few billion clock cycles in the past +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity pwm is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + write : in std_logic; + readdata : out std_logic_vector(31 downto 0); + writedata : in std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + pwm_out : out std_logic + ); +end pwm; + +architecture rtl of pwm is + + -- The period of the current and next PWM cycle + signal reg_next_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length); + signal reg_current_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length); + + -- The duty cycle of the current and next PWM cycle + signal reg_next_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length); + signal reg_current_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length); + + -- The status of the current and next PWM cycle + signal reg_prev_ctrl : std_logic := '0'; + signal reg_current_ctrl : std_logic := '0'; + + -- The internal counter of the PWN + signal reg_counter : unsigned(writedata'range) := to_unsigned(0, writedata'length); + +begin + +--Avalon-MM slave write +process(clk, reset) +begin + if reset = '1' then + reg_next_period <= to_unsigned(DEFAULT_PERIOD, writedata'length); + reg_next_dutycycle <= to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length); + reg_current_ctrl <= '0'; + elsif rising_edge(clk) then + if write = '1' then + case address is + when REG_PERIOD_OFST => + if unsigned(writedata) >= to_unsigned(2, writedata'length) then + reg_next_period <= unsigned(writedata); + end if; + when REG_DUTY_CYCLE_OFST => + if (unsigned(writedata) >= to_unsigned(1, writedata'length)) and + (unsigned(writedata) <= reg_next_period) then + reg_next_dutycycle <= unsigned(writedata); + end if; + when REG_CTRL_OFST => + reg_current_ctrl <= writedata(0); + when others => null; + end case; + end if; + end if; +end process; + + +--Avalon-MM slave read +process(clk, reset) +begin + if rising_edge(clk) then + if read = '1' then + case address is + when REG_PERIOD_OFST => + readdata <= std_logic_vector(reg_current_period); + when REG_DUTY_CYCLE_OFST => + readdata <= std_logic_vector(reg_current_dutycycle); + when others => + readdata <= (others => '0'); + end case; + end if; + end if; +end process; + +-- Internal synchronous logic +process(clk, reset) +begin + if reset = '1' then + reg_counter <= to_unsigned(0, writedata'length); + reg_prev_ctrl <= '0'; + elsif rising_edge(clk) then + if ((reg_prev_ctrl = '0') and (reg_current_ctrl = '1')) or + (reg_counter = reg_current_period - 1) then + reg_current_period <= reg_next_period; + reg_current_dutycycle <= reg_next_dutycycle; + reg_counter <= to_unsigned(0, writedata'length); + elsif (reg_current_ctrl = '1') then + reg_counter <= reg_counter + 1; + end if; + reg_prev_ctrl <= reg_current_ctrl; + end if; +end process; + +-- Avalon Conduit interface +process(clk, reset) +begin + if rising_edge(clk) then + if (reg_counter < reg_current_dutycycle) and (reg_current_ctrl = '1') then + pwm_out <= '1'; + else + pwm_out <= '0'; + end if; + end if; +end process; + + +end architecture rtl; diff --git a/cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm_constants.vhd b/cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm_constants.vhd new file mode 100644 index 0000000..bfff03b --- /dev/null +++ b/cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm_constants.vhd @@ -0,0 +1,61 @@ +-- ############################################################################# +-- pwm_constants.vhd +-- ================= +-- This package contains constants used in the PWM design files. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pwm_constants is + -- Register map + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | RegNo | Name | Access | Description | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW period to apply to the | + -- | | | | next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT period of the | + -- | | | | ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to | + -- | | | | the next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT duty cycle of | + -- | | | | the ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.| + -- | | | | Writing 1 to this register starts the PWM. | + -- | | | | | + -- | | | | >> Reading this register always returns 0. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00"; + constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01"; + constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10"; + + -- Default values of registers after reset (BEFORE writing START to the CTRL + -- register with a new configuration) + constant DEFAULT_PERIOD : natural := 4; + constant DEFAULT_DUTY_CYCLE : natural := 2; +end package pwm_constants; + +package body pwm_constants is + +end package body pwm_constants; diff --git a/cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm_hw.tcl b/cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm_hw.tcl new file mode 100644 index 0000000..df7d92a --- /dev/null +++ b/cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm_hw.tcl @@ -0,0 +1,135 @@ +# TCL File Generated by Component Editor 16.0 +# Tue Feb 28 12:18:00 CET 2017 +# DO NOT MODIFY + + +# +# pwm "pwm" v1.0 +# 2017.02.28.12:18:00 +# Pan-tilt +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module pwm +# +set_module_property DESCRIPTION Pan-tilt +set_module_property NAME pwm +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Pan-tilt +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME pwm +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE +add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +add_interface_port avalon_slave_0 writedata writedata Input 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end pwm_out pwm Output 1 diff --git a/cs309-psoc/lab_1_1/hw/hdl/pantilt/tb/tb_pwm.vhd b/cs309-psoc/lab_1_1/hw/hdl/pantilt/tb/tb_pwm.vhd new file mode 100644 index 0000000..ff2dee7 --- /dev/null +++ b/cs309-psoc/lab_1_1/hw/hdl/pantilt/tb/tb_pwm.vhd @@ -0,0 +1,205 @@ +-- ############################################################################# +-- tb_pwm.vhd +-- ========== +-- Testbench for PWM memory-mapped Avalon slave interface. +-- +-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity tb_pwm is +end entity; + +architecture rtl of tb_pwm is + + -- 50 MHz clock + constant CLK_PERIOD : time := 20 ns; + + -- Signal used to end simulator when we finished submitting our test cases + signal sim_finished : boolean := false; + + -- PWM PORTS + signal clk : std_logic; + signal reset : std_logic; + signal address : std_logic_vector(1 downto 0); + signal read : std_logic; + signal write : std_logic; + signal readdata : std_logic_vector(31 downto 0); + signal writedata : std_logic_vector(31 downto 0); + signal pwm_out : std_logic; + + -- Values of registers we are going to use to configure the PWM unit + constant CONFIG_PERIOD : natural := 100; + constant CONFIG_DUTY_CYCLE : natural := 20; + constant CONFIG_CTRL_START : natural := 1; + constant CONFIG_CTRL_STOP : natural := 0; + +begin + + -- Instantiate DUT + dut : entity work.pwm + port map( + clk => clk, + reset => reset, + address => address, + read => read, + write => write, + readdata => readdata, + writedata => writedata, + pwm_out => pwm_out + ); + + -- Generate clk signal + clk_generation : process + begin + if not sim_finished then + clk <= '1'; + wait for CLK_PERIOD / 2; + clk <= '0'; + wait for CLK_PERIOD / 2; + else + wait; + end if; + end process clk_generation; + + -- Test PWM + simulation : process + + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + + reset <= '1'; + wait for CLK_PERIOD / 2; + + reset <= '0'; + wait for CLK_PERIOD / 4; + end procedure async_reset; + + procedure write_register(constant ofst : in std_logic_vector(1 downto 0); + constant val : in natural) is + begin + wait until rising_edge(clk); + + address <= ofst; + write <= '1'; + writedata <= std_logic_vector(to_unsigned(val, writedata'length)); + wait until rising_edge(clk); + + address <= (others => '0'); + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + end procedure write_register; + + procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is + begin + wait until rising_edge(clk); + + address <= ofst; + read <= '1'; + -- The read has a 1 cycle wait-state, so we need to keep the read + -- signal high for 2 clock cycles. + wait until rising_edge(clk); + wait until rising_edge(clk); + + address <= (others => '0'); + read <= '0'; + wait until rising_edge(clk); + end procedure read_register; + + procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0); + constant expected_val : in natural) is + begin + read_register(ofst); + + case ofst is + when REG_PERIOD_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected PERIOD: " & + "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "PERIOD_expected = " & integer'image(expected_val) + severity error; + + when REG_DUTY_CYCLE_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected DUTY_CYCLE: " & + "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "DUTY_CYCLE_expected = " & integer'image(expected_val) + severity error; + + when REG_CTRL_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected CTRL: " & + "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "CTRL_expected = " & integer'image(expected_val) + severity error; + + when others => + null; + end case; + end procedure read_register_check; + + begin + + -- Default values + reset <= '0'; + address <= (others => '0'); + read <= '0'; + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + + -- Reset the circuit + async_reset; + + -- Write desired configuration to PWM Avalon-MM slave. + write_register(REG_PERIOD_OFST, CONFIG_PERIOD); + write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + + -- Read back configuration from PWM Avalon-MM slave. Note that we have + -- not started the PWM unit yet, so the new configuration must not be + -- read back at this point (as per the register map). + read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Start PWM + write_register(REG_CTRL_OFST, CONFIG_CTRL_START); + + -- Wait until PWM pulses for the first time after we sent START. + wait until rising_edge(pwm_out); + + -- Read back configuration from PWM Avalon-MM slave. Now that we have + -- started the PWM unit, we should be able to read back the + -- configuration we wrote (as per the register map). + read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Wait for 2 PWM periods to finish + wait for 2 * CLK_PERIOD * CONFIG_PERIOD; + + -- Stop PWM. + write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP); + + -- Wait for PWM period to finish + wait for 1 * CLK_PERIOD * CONFIG_PERIOD; + + -- Instruct "clk_generation" process to halt execution. + sim_finished <= true; + + -- Make this process wait indefinitely (it will never re-execute from + -- its beginning again). + wait; + end process simulation; +end architecture rtl; + diff --git a/cs309-psoc/lab_1_1/hw/quartus/ip/components.ipx b/cs309-psoc/lab_1_1/hw/quartus/ip/components.ipx new file mode 100644 index 0000000..c3872d0 --- /dev/null +++ b/cs309-psoc/lab_1_1/hw/quartus/ip/components.ipx @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_1_1/hw/quartus/lab_1_1.qpf b/cs309-psoc/lab_1_1/hw/quartus/lab_1_1.qpf new file mode 100644 index 0000000..88cceae --- /dev/null +++ b/cs309-psoc/lab_1_1/hw/quartus/lab_1_1.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition +# Date created = 11:03:02 February 05, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.1" +DATE = "11:03:02 February 05, 2016" + +# Revisions + +PROJECT_REVISION = "lab_1_1" diff --git a/cs309-psoc/lab_1_1/hw/quartus/lab_1_1.qsf b/cs309-psoc/lab_1_1/hw/quartus/lab_1_1.qsf new file mode 100644 index 0000000..2e27a21 --- /dev/null +++ b/cs309-psoc/lab_1_1/hw/quartus/lab_1_1.qsf @@ -0,0 +1,812 @@ +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 + +set_global_assignment -name SMART_RECOMPILE OFF +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level + +set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +set_global_assignment -name QSYS_FILE soc_system.qsys +set_global_assignment -name SDC_FILE lab_1_1.sdc + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA4U23C6 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO Extention OV7670 CAMERA +#============================================================ +set_location_assignment PIN_AE15 -to CAM_D[0] +set_location_assignment PIN_AE15 -to CAM_D_0 +set_location_assignment PIN_AF17 -to CAM_D[1] +set_location_assignment PIN_AF17 -to CAM_D_1 +set_location_assignment PIN_AH8 -to CAM_D[2] +set_location_assignment PIN_AH8 -to CAM_D_2 +set_location_assignment PIN_AG8 -to CAM_D[3] +set_location_assignment PIN_AG8 -to CAM_D_3 +set_location_assignment PIN_U13 -to CAM_D[4] +set_location_assignment PIN_U13 -to CAM_D_4 +set_location_assignment PIN_U14 -to CAM_D[5] +set_location_assignment PIN_U14 -to CAM_D_5 +set_location_assignment PIN_AG9 -to CAM_D[6] +set_location_assignment PIN_AG9 -to CAM_D_6 +set_location_assignment PIN_AG10 -to CAM_D[7] +set_location_assignment PIN_AG10 -to CAM_D_7 +set_location_assignment PIN_AF13 -to CAM_D[8] +set_location_assignment PIN_AF13 -to CAM_D_8 +set_location_assignment PIN_AG13 -to CAM_D[9] +set_location_assignment PIN_AG13 -to CAM_D_9 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9 + +#============================================================ +# Arduino Extension LEPTON CAMERA THERMAL CAM_TH +#============================================================ +set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N +set_location_assignment PIN_AG16 -to CAM_TH_MOSI +set_location_assignment PIN_AH11 -to CAM_TH_MISO +set_location_assignment PIN_AH12 -to CAM_TH_CLK +set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA +set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL + +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#============================================================ +# HPS +#============================================================ +set_location_assignment PIN_C6 -to HPS_CONV_USB_N +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0] +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0 +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1] +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1 +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2] +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2 +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3] +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3 +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4] +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4 +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5] +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5 +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6] +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6 +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7] +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7 +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8] +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8 +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9] +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9 +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10] +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10 +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11] +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11 +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12] +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12 +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13] +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13 +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14] +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14 +set_location_assignment PIN_A27 -to HPS_DDR3_BA[0] +set_location_assignment PIN_A27 -to HPS_DDR3_BA_0 +set_location_assignment PIN_H25 -to HPS_DDR3_BA[1] +set_location_assignment PIN_H25 -to HPS_DDR3_BA_1 +set_location_assignment PIN_G25 -to HPS_DDR3_BA[2] +set_location_assignment PIN_G25 -to HPS_DDR3_BA_2 +set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N +set_location_assignment PIN_L28 -to HPS_DDR3_CKE +set_location_assignment PIN_N20 -to HPS_DDR3_CK_N +set_location_assignment PIN_N21 -to HPS_DDR3_CK_P +set_location_assignment PIN_L21 -to HPS_DDR3_CS_N +set_location_assignment PIN_G28 -to HPS_DDR3_DM[0] +set_location_assignment PIN_G28 -to HPS_DDR3_DM_0 +set_location_assignment PIN_P28 -to HPS_DDR3_DM[1] +set_location_assignment PIN_P28 -to HPS_DDR3_DM_1 +set_location_assignment PIN_W28 -to HPS_DDR3_DM[2] +set_location_assignment PIN_W28 -to HPS_DDR3_DM_2 +set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3] +set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3 +set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0] +set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0 +set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1] +set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1 +set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2] +set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2 +set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3] +set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3 +set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4] +set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4 +set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5] +set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5 +set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6] +set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6 +set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7] +set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7 +set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8] +set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8 +set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9] +set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9 +set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10] +set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10 +set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11] +set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11 +set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12] +set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12 +set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13] +set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13 +set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14] +set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14 +set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15] +set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15 +set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16] +set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16 +set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17] +set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17 +set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18] +set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18 +set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19] +set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19 +set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20] +set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20 +set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21] +set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21 +set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22] +set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22 +set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23] +set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23 +set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24] +set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24 +set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25] +set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25 +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26] +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26 +set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27] +set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27 +set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28] +set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28 +set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29] +set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29 +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30] +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30 +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31] +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31 +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0] +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0 +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1] +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1 +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2] +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2 +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3] +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3 +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0] +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0 +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1] +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1 +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2] +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2 +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3] +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3 +set_location_assignment PIN_D28 -to HPS_DDR3_ODT +set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N +set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N +set_location_assignment PIN_D25 -to HPS_DDR3_RZQ +set_location_assignment PIN_E25 -to HPS_DDR3_WE_N +set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK +set_location_assignment PIN_B14 -to HPS_ENET_INT_N +set_location_assignment PIN_A13 -to HPS_ENET_MDC +set_location_assignment PIN_E16 -to HPS_ENET_MDIO +set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0] +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0 +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1] +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1 +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2] +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2 +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3] +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3 +set_location_assignment PIN_J13 -to HPS_ENET_RX_DV +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0] +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0 +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1] +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1 +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2] +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2 +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3] +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3 +set_location_assignment PIN_A12 -to HPS_ENET_TX_EN +set_location_assignment PIN_A17 -to HPS_GSENSOR_INT +set_location_assignment PIN_C18 -to HPS_I2C0_SCLK +set_location_assignment PIN_A19 -to HPS_I2C0_SDAT +set_location_assignment PIN_K18 -to HPS_I2C1_SCLK +set_location_assignment PIN_A21 -to HPS_I2C1_SDAT +set_location_assignment PIN_J18 -to HPS_KEY_N +set_location_assignment PIN_A20 -to HPS_LED +set_location_assignment PIN_H13 -to HPS_LTC_GPIO +set_location_assignment PIN_B8 -to HPS_SD_CLK +set_location_assignment PIN_D14 -to HPS_SD_CMD +set_location_assignment PIN_C13 -to HPS_SD_DATA[0] +set_location_assignment PIN_C13 -to HPS_SD_DATA_0 +set_location_assignment PIN_B6 -to HPS_SD_DATA[1] +set_location_assignment PIN_B6 -to HPS_SD_DATA_1 +set_location_assignment PIN_B11 -to HPS_SD_DATA[2] +set_location_assignment PIN_B11 -to HPS_SD_DATA_2 +set_location_assignment PIN_B9 -to HPS_SD_DATA[3] +set_location_assignment PIN_B9 -to HPS_SD_DATA_3 +set_location_assignment PIN_C19 -to HPS_SPIM_CLK +set_location_assignment PIN_B19 -to HPS_SPIM_MISO +set_location_assignment PIN_B16 -to HPS_SPIM_MOSI +set_location_assignment PIN_C16 -to HPS_SPIM_SS +set_location_assignment PIN_A22 -to HPS_UART_RX +set_location_assignment PIN_B21 -to HPS_UART_TX +set_location_assignment PIN_G4 -to HPS_USB_CLKOUT +set_location_assignment PIN_C10 -to HPS_USB_DATA[0] +set_location_assignment PIN_C10 -to HPS_USB_DATA_0 +set_location_assignment PIN_F5 -to HPS_USB_DATA[1] +set_location_assignment PIN_F5 -to HPS_USB_DATA_1 +set_location_assignment PIN_C9 -to HPS_USB_DATA[2] +set_location_assignment PIN_C9 -to HPS_USB_DATA_2 +set_location_assignment PIN_C4 -to HPS_USB_DATA[3] +set_location_assignment PIN_C4 -to HPS_USB_DATA_3 +set_location_assignment PIN_C8 -to HPS_USB_DATA[4] +set_location_assignment PIN_C8 -to HPS_USB_DATA_4 +set_location_assignment PIN_D4 -to HPS_USB_DATA[5] +set_location_assignment PIN_D4 -to HPS_USB_DATA_5 +set_location_assignment PIN_C7 -to HPS_USB_DATA[6] +set_location_assignment PIN_C7 -to HPS_USB_DATA_6 +set_location_assignment PIN_F4 -to HPS_USB_DATA[7] +set_location_assignment PIN_F4 -to HPS_USB_DATA_7 +set_location_assignment PIN_E5 -to HPS_USB_DIR +set_location_assignment PIN_D5 -to HPS_USB_NXT +set_location_assignment PIN_C5 -to HPS_USB_STP + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY_N +#============================================================ +set_location_assignment PIN_AH17 -to KEY_N[0] +set_location_assignment PIN_AH17 -to KEY_N_0 +set_location_assignment PIN_AH16 -to KEY_N[1] +set_location_assignment PIN_AH16 -to KEY_N_1 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_W15 -to LED_0 +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_AA24 -to LED_1 +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V16 -to LED_2 +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_V15 -to LED_3 +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AF26 -to LED_4 +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_AE26 -to LED_5 +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_Y16 -to LED_6 +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_AA23 -to LED_7 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7 + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_L10 -to SW[0] +set_location_assignment PIN_L10 -to SW_0 +set_location_assignment PIN_L9 -to SW[1] +set_location_assignment PIN_L9 -to SW_1 +set_location_assignment PIN_H6 -to SW[2] +set_location_assignment PIN_H6 -to SW_2 +set_location_assignment PIN_H5 -to SW[3] +set_location_assignment PIN_H5 -to SW_3 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3 + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_V12 -to PIO_INT_N +set_location_assignment PIN_AE11 -to PIO_SCL +set_location_assignment PIN_AE12 -to PIO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA + +set_location_assignment PIN_AF7 -to PIR_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT + +set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA +set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL +set_location_assignment PIN_T11 -to CAM_SYS_CLK +set_location_assignment PIN_AG6 -to CAM_LV +set_location_assignment PIN_AH2 -to CAM_PIX_CLK +set_location_assignment PIN_AE4 -to CAM_FV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV + +set_location_assignment PIN_Y8 -to PAL_VD_HSO +set_location_assignment PIN_AB4 -to PAL_VD_VSO +set_location_assignment PIN_AG5 -to PAL_VD_VD[0] +set_location_assignment PIN_AG5 -to PAL_VD_VD_0 +set_location_assignment PIN_AH5 -to PAL_VD_VD[1] +set_location_assignment PIN_AH5 -to PAL_VD_VD_1 +set_location_assignment PIN_AH6 -to PAL_VD_VD[2] +set_location_assignment PIN_AH6 -to PAL_VD_VD_2 +set_location_assignment PIN_T8 -to PAL_VD_VD[3] +set_location_assignment PIN_T8 -to PAL_VD_VD_3 +set_location_assignment PIN_T12 -to PAL_VD_VD[4] +set_location_assignment PIN_T12 -to PAL_VD_VD_4 +set_location_assignment PIN_Y5 -to PAL_VD_VD[5] +set_location_assignment PIN_Y5 -to PAL_VD_VD_5 +set_location_assignment PIN_Y4 -to PAL_VD_VD[6] +set_location_assignment PIN_Y4 -to PAL_VD_VD_6 +set_location_assignment PIN_W8 -to PAL_VD_VD[7] +set_location_assignment PIN_W8 -to PAL_VD_VD_7 +set_location_assignment PIN_AH4 -to PAL_VD_CLKO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO + +set_location_assignment PIN_AH3 -to SERVO_0 +set_location_assignment PIN_AF4 -to SERVO_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1 + +set_location_assignment PIN_AD12 -to J0_SPI_CLK +set_location_assignment PIN_AD11 -to J0_SPI_MISO +set_location_assignment PIN_AF9 -to J0_SPI_CS_N +set_location_assignment PIN_AD10 -to J0_SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI + +set_location_assignment PIN_AF5 -to FROM_ESP_TXD +set_location_assignment PIN_T13 -to TO_ESP_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD + +set_location_assignment PIN_AE7 -to SPI_MISO +set_location_assignment PIN_AF6 -to SPI_ENA_N +set_location_assignment PIN_AE8 -to SPI_CLK +set_location_assignment PIN_AE9 -to SPI_MOSI +set_location_assignment PIN_AF10 -to SPI_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT + +set_location_assignment PIN_AF11 -to LED_BGR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_AA15 -to RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N + +set_location_assignment PIN_AG28 -to TS_SCL +set_location_assignment PIN_AH27 -to TS_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA + +set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N +set_location_assignment PIN_AG26 -to LCD_DE +set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN + +set_location_assignment PIN_AH24 -to BLT_TXD +set_location_assignment PIN_AE22 -to BLT_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD + +set_location_assignment PIN_AG20 -to BOARD_ID +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID + +set_location_assignment PIN_AF21 -to VIDEO_HSYNC +set_location_assignment PIN_AG19 -to VIDEO_VSYNC +set_location_assignment PIN_AF20 -to VIDEO_CLK +set_location_assignment PIN_AG23 -to VIDEO_B[0] +set_location_assignment PIN_AG23 -to VIDEO_B_0 +set_location_assignment PIN_AH23 -to VIDEO_B[1] +set_location_assignment PIN_AH23 -to VIDEO_B_1 +set_location_assignment PIN_AF25 -to VIDEO_B[2] +set_location_assignment PIN_AF25 -to VIDEO_B_2 +set_location_assignment PIN_AG24 -to VIDEO_B[3] +set_location_assignment PIN_AG24 -to VIDEO_B_3 +set_location_assignment PIN_AA19 -to VIDEO_B[4] +set_location_assignment PIN_AA19 -to VIDEO_B_4 +set_location_assignment PIN_AH26 -to VIDEO_B[5] +set_location_assignment PIN_AH26 -to VIDEO_B_5 +set_location_assignment PIN_AG18 -to VIDEO_B[6] +set_location_assignment PIN_AG18 -to VIDEO_B_6 +set_location_assignment PIN_AC23 -to VIDEO_B[7] +set_location_assignment PIN_AC23 -to VIDEO_B_7 +set_location_assignment PIN_AH22 -to VIDEO_G[0] +set_location_assignment PIN_AH22 -to VIDEO_G_0 +set_location_assignment PIN_AF22 -to VIDEO_G[1] +set_location_assignment PIN_AF22 -to VIDEO_G_1 +set_location_assignment PIN_AD20 -to VIDEO_G[2] +set_location_assignment PIN_AD20 -to VIDEO_G_2 +set_location_assignment PIN_AE24 -to VIDEO_G[3] +set_location_assignment PIN_AE24 -to VIDEO_G_3 +set_location_assignment PIN_AE20 -to VIDEO_G[4] +set_location_assignment PIN_AE20 -to VIDEO_G_4 +set_location_assignment PIN_AD19 -to VIDEO_G[5] +set_location_assignment PIN_AD19 -to VIDEO_G_5 +set_location_assignment PIN_AF18 -to VIDEO_G[6] +set_location_assignment PIN_AF18 -to VIDEO_G_6 +set_location_assignment PIN_AE19 -to VIDEO_G[7] +set_location_assignment PIN_AE19 -to VIDEO_G_7 +set_location_assignment PIN_AC22 -to VIDEO_R[0] +set_location_assignment PIN_AC22 -to VIDEO_R_0 +set_location_assignment PIN_AA18 -to VIDEO_R[1] +set_location_assignment PIN_AA18 -to VIDEO_R_1 +set_location_assignment PIN_AE23 -to VIDEO_R[2] +set_location_assignment PIN_AE23 -to VIDEO_R_2 +set_location_assignment PIN_AD23 -to VIDEO_R[3] +set_location_assignment PIN_AD23 -to VIDEO_R_3 +set_location_assignment PIN_AH18 -to VIDEO_R[4] +set_location_assignment PIN_AH18 -to VIDEO_R_4 +set_location_assignment PIN_AG21 -to VIDEO_R[5] +set_location_assignment PIN_AG21 -to VIDEO_R_5 +set_location_assignment PIN_AH21 -to VIDEO_R[6] +set_location_assignment PIN_AH21 -to VIDEO_R_6 +set_location_assignment PIN_AH19 -to VIDEO_R[7] +set_location_assignment PIN_AH19 -to VIDEO_R_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7 diff --git a/cs309-psoc/lab_1_1/hw/quartus/lab_1_1.sdc b/cs309-psoc/lab_1_1/hw/quartus/lab_1_1.sdc new file mode 100644 index 0000000..16a41f3 --- /dev/null +++ b/cs309-psoc/lab_1_1/hw/quartus/lab_1_1.sdc @@ -0,0 +1,6 @@ +create_clock -period 20 [get_ports FPGA_CLK1_50] +create_clock -period 20 [get_ports FPGA_CLK2_50] +create_clock -period 20 [get_ports FPGA_CLK3_50] + +derive_pll_clocks +derive_clock_uncertainty diff --git a/cs309-psoc/lab_1_1/hw/quartus/soc_system.qsys b/cs309-psoc/lab_1_1/hw/quartus/soc_system.qsys new file mode 100644 index 0000000..3148405 --- /dev/null +++ b/cs309-psoc/lab_1_1/hw/quartus/soc_system.qsys @@ -0,0 +1,601 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + NO_INTERACTIVE_WINDOWS + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_onchip_memory2_0 + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_1_1/lab_1_1.pdf b/cs309-psoc/lab_1_1/lab_1_1.pdf new file mode 100644 index 0000000..43f8eff Binary files /dev/null and b/cs309-psoc/lab_1_1/lab_1_1.pdf differ diff --git a/cs309-psoc/lab_1_1/sw/nios/application/app.c b/cs309-psoc/lab_1_1/sw/nios/application/app.c new file mode 100644 index 0000000..68bced9 --- /dev/null +++ b/cs309-psoc/lab_1_1/sw/nios/application/app.c @@ -0,0 +1,69 @@ +#include +#include +#include +#include +#include +#include + +#include "pantilt/pantilt.h" +#include "system.h" + +#define SLEEP_DURATION_US (25000) // 25 ms +#define PANTILT_STEP_US (25) // 25 us + +#define PANTILT_PWM_V_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_V_MIN_DUTY_CYCLE_US + PANTILT_PWM_V_MAX_DUTY_CYCLE_US) / 2) +#define PANTILT_PWM_H_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_H_MIN_DUTY_CYCLE_US + PANTILT_PWM_H_MAX_DUTY_CYCLE_US) / 2) + +int main(void) { + // Hardware control structures + pantilt_dev pantilt = pantilt_inst((void *) PWM_0_BASE, (void *) PWM_1_BASE); + + // Initialize hardware + pantilt_init(&pantilt); + + // Center servos. + pantilt_configure_vertical(&pantilt, PANTILT_PWM_V_MIN_DUTY_CYCLE_US); + pantilt_configure_horizontal(&pantilt, PANTILT_PWM_H_MIN_DUTY_CYCLE_US); + pantilt_start_vertical(&pantilt); + pantilt_start_horizontal(&pantilt); + + // Rotate servos in "square" motion + while (true) { + uint32_t v_duty_us = 0; + uint32_t h_duty_us = 0; + + // bottom to top + v_duty_us = PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + do { + pantilt_configure_vertical(&pantilt, v_duty_us); + v_duty_us += PANTILT_STEP_US; + usleep(SLEEP_DURATION_US); + } while (v_duty_us <= PANTILT_PWM_V_MAX_DUTY_CYCLE_US); + + // left to right + h_duty_us = PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + do { + pantilt_configure_horizontal(&pantilt, h_duty_us); + h_duty_us += PANTILT_STEP_US; + usleep(SLEEP_DURATION_US); + } while (h_duty_us <= PANTILT_PWM_H_MAX_DUTY_CYCLE_US); + + // top to bottom + v_duty_us = PANTILT_PWM_V_MAX_DUTY_CYCLE_US; + do { + pantilt_configure_vertical(&pantilt, v_duty_us); + v_duty_us -= PANTILT_STEP_US; + usleep(SLEEP_DURATION_US); + } while (PANTILT_PWM_V_MIN_DUTY_CYCLE_US <= v_duty_us); + + // left to right + h_duty_us = PANTILT_PWM_H_MAX_DUTY_CYCLE_US; + do { + pantilt_configure_horizontal(&pantilt, h_duty_us); + h_duty_us -= PANTILT_STEP_US; + usleep(SLEEP_DURATION_US); + } while (PANTILT_PWM_H_MIN_DUTY_CYCLE_US <= h_duty_us); + } + + return EXIT_SUCCESS; +} diff --git a/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pantilt.c b/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pantilt.c new file mode 100644 index 0000000..d9c4c72 --- /dev/null +++ b/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pantilt.c @@ -0,0 +1,109 @@ +#include "pantilt.h" + +/** + * pantilt_inst + * + * Instantiate a pantilt device structure. + * + * @param pwm_v_base Base address of the vertical PWM component. + * @param pwm_h_base Base address of the horizontal PWM component. + */ +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) { + pantilt_dev dev; + dev.pwm_v = pwm_inst(pwm_v_base); + dev.pwm_h = pwm_inst(pwm_h_base); + + return dev; +} + +/** + * pantilt_init + * + * Initializes the pantilt device. + * + * @param dev pantilt device structure. + */ +void pantilt_init(pantilt_dev *dev) { + pwm_init(&(dev->pwm_v)); + pwm_init(&(dev->pwm_h)); +} + +/** + * pantilt_configure_vertical + * + * Configure the vertical PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_v), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_configure_horizontal + * + * Configure the horizontal PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_h), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_start_vertical + * + * Starts the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_vertical(pantilt_dev *dev) { + pwm_start(&(dev->pwm_v)); +} + +/** + * pantilt_start_horizontal + * + * Starts the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_horizontal(pantilt_dev *dev) { + pwm_start(&(dev->pwm_h)); +} + +/** + * pantilt_stop_vertical + * + * Stops the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_vertical(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_v)); +} + +/** + * pantilt_stop_horizontal + * + * Stops the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_horizontal(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_h)); +} diff --git a/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pantilt.h b/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pantilt.h new file mode 100644 index 0000000..1f17500 --- /dev/null +++ b/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pantilt.h @@ -0,0 +1,39 @@ +#ifndef __PANTILT_H__ +#define __PANTILT_H__ + +#include "pwm/pwm.h" + +/* joysticks device structure */ +typedef struct pantilt_dev { + pwm_dev pwm_v; /* Vertical PWM device handle */ + pwm_dev pwm_h; /* Horizontal PWM device handle */ +} pantilt_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz + +#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms + +/* Vertical servo */ +#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms +#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms + +/* Horizontal servo */ +#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms +#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms + +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base); + +void pantilt_init(pantilt_dev *dev); + +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_start_vertical(pantilt_dev *dev); +void pantilt_start_horizontal(pantilt_dev *dev); +void pantilt_stop_vertical(pantilt_dev *dev); +void pantilt_stop_horizontal(pantilt_dev *dev); + +#endif /* __PANTILT_H__ */ diff --git a/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm.c b/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm.c new file mode 100644 index 0000000..293be53 --- /dev/null +++ b/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm.c @@ -0,0 +1,71 @@ +#include + +#include "pwm.h" +#include "pwm_regs.h" + +#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000)) + + +/** + * pwm_inst + * + * Instantiate a pwm device structure. + * + * @param base Base address of the component. + */ +pwm_dev pwm_inst(void *base) { + pwm_dev dev; + + dev.base = base; + + return dev; +} + +/** + * pwm_init + * + * Initializes the pwm device. This function stops the controller. + * + * @param dev pwm device structure. + */ +void pwm_init(pwm_dev *dev) { + pwm_stop(dev); +} + +/** + * pwm_configure + * + * Configure pwm component. + * + * @param dev pwm device structure. + * @param duty_cycle pwm duty cycle in us. + * @param period pwm period in us. + * @param module_frequency frequency at which the component is clocked. + */ +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) { + + IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency)); + IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency)); +} + +/** + * pwm_start + * + * Starts the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_start(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} + +/** + * pwm_stop + * + * Stops the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_stop(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK); +} diff --git a/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm.h b/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm.h new file mode 100644 index 0000000..e2987f4 --- /dev/null +++ b/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm.h @@ -0,0 +1,21 @@ +#ifndef __PWM_H__ +#define __PWM_H__ + +#include + +/* pwm device structure */ +typedef struct pwm_dev { + void *base; /* Base address of component */ +} pwm_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ +pwm_dev pwm_inst(void *base); + +void pwm_init(pwm_dev *dev); +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency); +void pwm_start(pwm_dev *dev); +void pwm_stop(pwm_dev *dev); + +#endif /* __PWM_H__ */ diff --git a/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm_regs.h b/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm_regs.h new file mode 100644 index 0000000..488583d --- /dev/null +++ b/cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm_regs.h @@ -0,0 +1,11 @@ +#ifndef __PWM_REGS_H__ +#define __PWM_REGS_H__ + +#define PWM_PERIOD_OFST (0 * 4) /* RW */ +#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */ +#define PWM_CTRL_OFST (2 * 4) /* WO */ + +#define PWM_CTRL_STOP_MASK (0) +#define PWM_CTRL_START_MASK (1) + +#endif /* __PWM_REGS_H__ */ diff --git a/cs309-psoc/lab_1_2/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd b/cs309-psoc/lab_1_2/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd new file mode 100644 index 0000000..611292c --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd @@ -0,0 +1,195 @@ +-- ############################################################################# +-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +-- +-- BOARD : PrSoC extension board for DE0-Nano-SoC +-- Author : Florian Depraz based on Sahand Kashani-Akhavan work +-- Revision : 1.1 +-- Creation date : 06/02/2016 +-- +-- Syntax Rule : GROUP_NAME_N[bit] +-- +-- GROUP : specify a particular interface (ex: SDR_) +-- NAME : signal name (ex: CONFIG, D, ...) +-- bit : signal index +-- _N : to specify an active-low signal +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; + +entity DE0_Nano_SoC_PrSoC_extn_board_top_level is + port( + ------------------------------- + -- Comment ALL unused ports. -- + ------------------------------- + + -- CLOCK + FPGA_CLK1_50 : in std_logic; + -- FPGA_CLK2_50 : in std_logic; + -- FPGA_CLK3_50 : in std_logic; + + -- KEY on DE0 Nano SoC + KEY_N : in std_logic_vector(1 downto 0); + + -- LEDs on DE0 Nano SoC + -- LED : out std_logic_vector(7 downto 0); + + -- SWITCHES on DE0 Nano SoC + -- SW : in std_logic_vector(3 downto 0); + + -- Servomotors pwm + SERVO_0 : out std_logic; + SERVO_1 : out std_logic; + + -- ADC Joysticks + J0_SPI_CS_n : out std_logic; + J0_SPI_MOSI : out std_logic; + J0_SPI_MISO : in std_logic; + J0_SPI_CLK : out std_logic + + -- Lepton + -- CAM_TH_SPI_CS_N : out std_logic; + -- CAM_TH_MISO : in std_logic; + -- CAM_TH_MOSI : out std_logic; + -- CAM_TH_CLK : out std_logic; + + -- PCA9637 + -- PIO_SCL : inout std_logic; + -- PIO_SDA : inout std_logic; + -- PIO_INT_N : in std_logic; + -- RESET_N : out std_logic; + + -- OV7670 + -- CAM_D : in std_logic_vector(9 downto 0); + -- CAM_PIX_CLK : in std_logic; + -- CAM_LV : in std_logic; + -- CAM_FV : in std_logic; + -- CAM_SYS_CLK : out std_logic; + + -- VGA and LCD shared signals + -- VIDEO_CLK : out std_logic; + -- VIDEO_VSYNC : out std_logic; + -- VIDEO_HSYNC : out std_logic; + -- VIDEO_B : out std_logic_vector(7 downto 0); + -- VIDEO_G : out std_logic_vector(7 downto 0); + -- VIDEO_R : out std_logic_vector(7 downto 0); + + -- LCD Specific signals + -- LCD_DE : out std_logic; + -- LCD_PIN_DAV_N : ? ?? std_logic; + -- LCD_DISPLAY_EN : out std_logic; + -- SPI_MISO : in std_logic; + -- SPI_ENA_N : out std_logic; + -- SPI_CLK : out std_logic; + -- SPI_MOSI : out std_logic; + -- SPI_DAT : inout std_logic; + + -- I2C TOUCH SCREEN + -- TS_SCL : inout std_logic; + -- TS_SDA : inout std_logic; + + -- BLUETOOTH (BLE) + -- BLT_TXD : in std_logic; + -- BLT_RXD : out std_logic; + + -- I2C For VGA, PAL and OV7670 cameras + -- CAM_PAL_VGA_SDA : inout std_logic; + -- CAM_PAL_VGA_SCL : inout std_logic; + + -- ONE WIRE + -- BOARD_ID : inout std_logic; + + -- PAL Camera + -- PAL_VD_VD : in std_logic_vector(7 downto 0); + -- PAL_VD_VSO : in std_logic; + -- PAL_VD_HSO : in std_logic; + -- PAL_VD_CLKO : in std_logic; + -- PAL_PWDN : out std_logic; + + -- WIFI + -- FROM_ESP_TXD : in std_logic; + -- TO_ESP_RXD : out std_logic; + + -- LED RGB + -- LED_BGR : out std_logic; + + -- HPS + -- HPS_CONV_USB_N : inout std_logic; + -- HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); + -- HPS_DDR3_BA : out std_logic_vector(2 downto 0); + -- HPS_DDR3_CAS_N : out std_logic; + -- HPS_DDR3_CK_N : out std_logic; + -- HPS_DDR3_CK_P : out std_logic; + -- HPS_DDR3_CKE : out std_logic; + -- HPS_DDR3_CS_N : out std_logic; + -- HPS_DDR3_DM : out std_logic_vector(3 downto 0); + -- HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); + -- HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); + -- HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); + -- HPS_DDR3_ODT : out std_logic; + -- HPS_DDR3_RAS_N : out std_logic; + -- HPS_DDR3_RESET_N : out std_logic; + -- HPS_DDR3_RZQ : in std_logic; + -- HPS_DDR3_WE_N : out std_logic; + -- HPS_ENET_GTX_CLK : out std_logic; + -- HPS_ENET_INT_N : inout std_logic; + -- HPS_ENET_MDC : out std_logic; + -- HPS_ENET_MDIO : inout std_logic; + -- HPS_ENET_RX_CLK : in std_logic; + -- HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); + -- HPS_ENET_RX_DV : in std_logic; + -- HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); + -- HPS_ENET_TX_EN : out std_logic; + -- HPS_GSENSOR_INT : inout std_logic; + -- HPS_I2C0_SCLK : inout std_logic; + -- HPS_I2C0_SDAT : inout std_logic; + -- HPS_I2C1_SCLK : inout std_logic; + -- HPS_I2C1_SDAT : inout std_logic; + -- HPS_KEY_N : inout std_logic; + -- HPS_LED : inout std_logic; + -- HPS_LTC_GPIO : inout std_logic; + -- HPS_SD_CLK : out std_logic; + -- HPS_SD_CMD : inout std_logic; + -- HPS_SD_DATA : inout std_logic_vector(3 downto 0); + -- HPS_SPIM_CLK : out std_logic; + -- HPS_SPIM_MISO : in std_logic; + -- HPS_SPIM_MOSI : out std_logic; + -- HPS_SPIM_SS : inout std_logic; + -- HPS_UART_RX : in std_logic; + -- HPS_UART_TX : out std_logic; + -- HPS_USB_CLKOUT : in std_logic; + -- HPS_USB_DATA : inout std_logic_vector(7 downto 0); + -- HPS_USB_DIR : in std_logic; + -- HPS_USB_NXT : in std_logic; + -- HPS_USB_STP : out std_logic + ); +end entity DE0_Nano_SoC_PrSoC_extn_board_top_level; + +architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is + component soc_system is + port ( + clk_clk : in std_logic := 'X'; + reset_reset_n : in std_logic := 'X'; + pwm_0_conduit_end_pwm : out std_logic; + pwm_1_conduit_end_pwm : out std_logic; + mcp3204_0_conduit_end_cs_n : out std_logic; + mcp3204_0_conduit_end_mosi : out std_logic; + mcp3204_0_conduit_end_miso : in std_logic := 'X'; + mcp3204_0_conduit_end_sclk : out std_logic + ); + end component soc_system; + +begin + soc_system_inst : component soc_system + port map ( + clk_clk => FPGA_CLK1_50, + reset_reset_n => KEY_N(0), + pwm_0_conduit_end_pwm => SERVO_0, + pwm_1_conduit_end_pwm => SERVO_1, + mcp3204_0_conduit_end_cs_n => J0_SPI_CS_n, + mcp3204_0_conduit_end_mosi => J0_SPI_MOSI, + mcp3204_0_conduit_end_miso => J0_SPI_MISO, + mcp3204_0_conduit_end_sclk => J0_SPI_CLK + ); + +end; diff --git a/cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204.vhd b/cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204.vhd new file mode 100644 index 0000000..af0aafb --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204.vhd @@ -0,0 +1,138 @@ +-- ############################################################################# +-- mcp3204.vhd +-- =========== +-- MCP3204 Avalon-MM slave interface. +-- +-- Register map +-- +-------+-----------+--------+------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +-------+-----------+--------+------------------------------------+ +-- | 0 | CHANNEL_0 | RO | 12-bit digital value of channel 0. | +-- +-------+-----------+--------+------------------------------------+ +-- | 1 | CHANNEL_1 | RO | 12-bit digital value of channel 1. | +-- +-------+-----------+--------+------------------------------------+ +-- | 2 | CHANNEL_2 | RO | 12-bit digital value of channel 2. | +-- +-------+-----------+--------+------------------------------------+ +-- | 3 | CHANNEL_3 | RO | 12-bit digital value of channel 3. | +-- +-------+-----------+--------+------------------------------------+ +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity mcp3204 is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + readdata : out std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic; + SCLK : out std_logic + ); +end entity; + +architecture arch of mcp3204 is + constant NUM_CHANNELS : positive := 4; + constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS)))); + + type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range); + signal data_reg : data_array; + + signal spi_busy, spi_start, spi_datavalid : std_logic; + signal spi_channel : std_logic_vector(1 downto 0); + signal spi_data : std_logic_vector(11 downto 0); + + type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA); + signal state : state_t; + + signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0); + +begin + SPI : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => spi_busy, + start => spi_start, + channel => spi_channel, + data_valid => spi_datavalid, + data => spi_data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + -- FSM that dictates which channel is being read. The state of the component + -- should be thought as the pair (state, channel) + p_fsm : process(reset, clk) + begin + if reset = '1' then + state <= READY; + channel <= (others => '0'); + elsif rising_edge(clk) then + case state is + when READY => + if spi_busy = '0' then + state <= INIT_READ_CHANNEL; + end if; + + when INIT_READ_CHANNEL => + state <= WAIT_FOR_DATA; + + when WAIT_FOR_DATA => + if spi_datavalid = '1' then + state <= READY; + channel <= channel + 1; + end if; + end case; + end if; + end process p_fsm; + + -- Updates the internal registers when a new data is available + p_data : process(reset, clk) + begin + if reset = '1' then + for i in 0 to NUM_CHANNELS - 1 loop + data_reg(i) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + if state = WAIT_FOR_DATA and spi_datavalid = '1' then + data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data; + end if; + end if; + end process p_data; + + spi_start <= '1' when state = INIT_READ_CHANNEL else '0'; + spi_channel <= std_logic_vector(channel); + + -- Interface with the Avalon Switch Fabric + p_avalon_read : process(reset, clk) + begin + if reset = '1' then + readdata <= (others => '0'); + elsif rising_edge(clk) then + if read = '1' then + readdata <= data_reg(to_integer(unsigned(address))); + end if; + end if; + end process p_avalon_read; + +end architecture; diff --git a/cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204_hw.tcl b/cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204_hw.tcl new file mode 100644 index 0000000..757514d --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204_hw.tcl @@ -0,0 +1,137 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 18:14:06 CET 2017 +# DO NOT MODIFY + + +# +# mcp3204 "mcp3204" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.18:14:06 +# 4-Channel 12-Bit A/D Converter with SPI Serial Interface +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module mcp3204 +# +set_module_property DESCRIPTION "4-Channel 12-Bit A/D Converter with SPI Serial Interface" +set_module_property NAME mcp3204 +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Joystick +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME mcp3204 +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL mcp3204 +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file mcp3204.vhd VHDL PATH mcp3204.vhd TOP_LEVEL_FILE +add_fileset_file mcp3204_spi.vhd VHDL PATH mcp3204_spi.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end CS_N cs_n Output 1 +add_interface_port conduit_end MOSI mosi Output 1 +add_interface_port conduit_end MISO miso Input 1 +add_interface_port conduit_end SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204_spi.vhd b/cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204_spi.vhd new file mode 100644 index 0000000..ca6903b --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/hdl/joysticks/hdl/mcp3204_spi.vhd @@ -0,0 +1,161 @@ +-- ############################################################################# +-- mcp3204_spi.vhd +-- =============== +-- MCP3204 SPI interface. +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Author : () +-- Revision : 1 +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mcp3204_spi is + port( + -- 50 MHz + clk : in std_logic; + reset : in std_logic; + busy : out std_logic; + start : in std_logic; + channel : in std_logic_vector(1 downto 0); + data_valid : out std_logic; + data : out std_logic_vector(11 downto 0); + + -- 1 MHz + SCLK : out std_logic; + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); +end mcp3204_spi; + +architecture rtl of mcp3204_spi is + -- The signals that drive the clock divider + signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24 + signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz + signal reg_rising_edge_sclk : std_logic := '0'; + signal reg_falling_edge_sclk : std_logic := '0'; + signal reg_sclk : std_logic := '0'; + + -- The state related to the FSM + type state_type is (IDL, SYN, SND_S, SND_SGL, SND_D, WT, RCV_NB, RCV_D, WB); + signal reg_state, next_state : state_type := IDL; + signal reg_bit_idx : unsigned(3 downto 0) := (others => '0'); + signal reg_channel : unsigned(1 downto 0); + + -- The register that holds the transmitted data + signal reg_data : unsigned(11 downto 0) := (others => '0'); + +begin + clk_divider_generation : process(clk, reset) + begin + if reset = '1' then + reg_clk_divider_counter <= (others => '0'); + elsif rising_edge(clk) then + reg_clk_divider_counter <= reg_clk_divider_counter + 1; + reg_spi_en <= '0'; + reg_rising_edge_sclk <= '0'; + reg_falling_edge_sclk <= '0'; + + if reg_clk_divider_counter = 24 then + reg_clk_divider_counter <= (others => '0'); + reg_spi_en <= '1'; + + if reg_sclk = '0' then + reg_rising_edge_sclk <= '1'; + elsif reg_sclk = '1' then + reg_falling_edge_sclk <= '1'; + end if; + end if; + end if; + end process; + + SCLK_generation : process(clk, reset) + begin + if reset = '1' then + reg_sclk <= '0'; + elsif rising_edge(clk) then + if reg_spi_en = '1' then + reg_sclk <= not reg_sclk; + end if; + end if; + end process; + + STATE_LOGIC : process(clk, reset) + begin + if reset = '1' then + reg_state <= IDL; + reg_bit_idx <= (others => '0'); + elsif rising_edge(clk) then + reg_state <= next_state; + + case reg_state is + when IDL => + if next_state = SYN then + reg_channel <= unsigned(channel); + end if; + when SND_SGL => + if next_state = SND_D then + reg_bit_idx <= to_unsigned(2, reg_bit_idx'length); + end if; + when RCV_NB => + if next_state = RCV_D then + reg_bit_idx <= to_unsigned(11, reg_bit_idx'length); + end if; + when SND_D | RCV_D => + if reg_falling_edge_sclk = '1' then + reg_bit_idx <= reg_bit_idx - 1; + end if; + when others => + null; + end case; + end if; + end process; + + -- This is the combinatory logic to compute the next state + next_state <= + SYN when reg_state = IDL and start = '1' else + SND_S when reg_state = SYN and reg_falling_edge_sclk = '1' else + SND_SGL when reg_state = SND_S and reg_falling_edge_sclk = '1' else + SND_D when reg_state = SND_SGL and reg_falling_edge_sclk = '1' else + WT when reg_state = SND_D and reg_falling_edge_sclk = '1' and reg_bit_idx = 0 else + RCV_NB when reg_state = WT and reg_falling_edge_sclk = '1' else + RCV_D when reg_state = RCV_NB and reg_falling_edge_sclk = '1' else + WB when reg_state = RCV_D and reg_falling_edge_sclk = '1' and reg_bit_idx = 0 else + IDL when reg_state = WB else + reg_state; + + -- This process reads the bits sent from the ADC + ADC_READ : process(clk, reset) + begin + if reset = '1' then + reg_data <= (others => '0'); + elsif rising_edge(clk) then + if reg_state = RCV_D and reg_rising_edge_sclk = '1' then + reg_data(to_integer(reg_bit_idx)) <= MISO; + end if; + end if; + end process; + + -- This is the combinatory logic to the ADC converter + SCLK <= reg_sclk; + CS_N <= '1' when reg_state = IDL or reg_state = SYN or reg_state = WB else '0'; + MOSI <= + '1' when reg_state = SND_S or reg_state = SND_SGL else + '0' when reg_state = SND_D and reg_bit_idx = 2 else + reg_channel(to_integer(reg_bit_idx)) when reg_state = SND_D else + '0'; + + -- This is the combinatory logic to the SPI manager + busy <= '0' when reg_state = IDL else + '1'; + data_valid <= '1' when reg_state = WB else + '0'; + data <= std_logic_vector(reg_data) when reg_state = WB else + (others => '0'); + +end architecture rtl; diff --git a/cs309-psoc/lab_1_2/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd b/cs309-psoc/lab_1_2/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd new file mode 100644 index 0000000..1bb61d2 --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd @@ -0,0 +1,103 @@ +-- ############################################################################# +-- tb_mcp3204_spi.vhd +-- ================== +-- Testbench for MCP3204 SPI interface. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 1 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_mcp3204_spi is +end entity; + +architecture rtl of tb_mcp3204_spi is + constant CLK_PERIOD : time := 20 ns; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal sim_finished : boolean := false; + + -- mcp3204_spi ------------------------------------------------------------ + signal busy : std_logic := '0'; + signal start : std_logic := '0'; + signal channel : std_logic_vector(1 downto 0) := (others => '0'); + signal data_valid : std_logic := '0'; + signal data : std_logic_vector(11 downto 0) := (others => '0'); + signal SCLK : std_logic := '0'; + signal CS_N : std_logic := '1'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '0'; + +begin + duv : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => busy, + start => start, + channel => channel, + data_valid => data_valid, + data => data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_finished; + + sim : process + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + reset <= '1'; + + wait for CLK_PERIOD / 2; + reset <= '0'; + end procedure async_reset; + + procedure spi_transfer(constant channel_number : natural range 0 to 3) is + begin + if busy = '1' then + wait until busy = '0'; + + else + wait until falling_edge(clk); + start <= '1'; + channel <= std_logic_vector(to_unsigned(channel_number, channel'length)); + + wait until falling_edge(clk); + start <= '0'; + channel <= (others => '0'); + + wait until rising_edge(data_valid); + wait until falling_edge(busy); + end if; + end procedure spi_transfer; + + begin + async_reset; + + MISO <= '1'; + spi_transfer(0); + + MISO <= '0'; + spi_transfer(1); + + MISO <= '1'; + spi_transfer(2); + + MISO <= '0'; + spi_transfer(3); + + sim_finished <= true; + wait; + end process sim; +end architecture rtl; + + diff --git a/cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm.vhd b/cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm.vhd new file mode 100644 index 0000000..f639f39 --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm.vhd @@ -0,0 +1,134 @@ +-- ############################################################################# +-- pwm.vhd +-- ======= +-- PWM memory-mapped Avalon slave interface. +-- +-- Author : Cedric Hoelzl (cedric.hoelzl@epfl.ch) +-- Author : Antoine Brunner (antoine.brunner@epfl.ch) +-- Revision : 0.0.1a_rc1 +-- Last modified : a few billion clock cycles in the past +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity pwm is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + write : in std_logic; + readdata : out std_logic_vector(31 downto 0); + writedata : in std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + pwm_out : out std_logic + ); +end pwm; + +architecture rtl of pwm is + + -- The period of the current and next PWM cycle + signal reg_next_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length); + signal reg_current_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length); + + -- The duty cycle of the current and next PWM cycle + signal reg_next_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length); + signal reg_current_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length); + + -- The status of the current and next PWM cycle + signal reg_prev_ctrl : std_logic := '0'; + signal reg_current_ctrl : std_logic := '0'; + + -- The internal counter of the PWN + signal reg_counter : unsigned(writedata'range) := to_unsigned(0, writedata'length); + +begin + + --Avalon-MM slave write + process(clk, reset) + begin + if reset = '1' then + reg_next_period <= to_unsigned(DEFAULT_PERIOD, writedata'length); + reg_next_dutycycle <= to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length); + reg_current_ctrl <= '0'; + elsif rising_edge(clk) then + if write = '1' then + case address is + when REG_PERIOD_OFST => + if unsigned(writedata) >= to_unsigned(2, writedata'length) then + reg_next_period <= unsigned(writedata); + end if; + when REG_DUTY_CYCLE_OFST => + if (unsigned(writedata) >= to_unsigned(1, writedata'length)) and + (unsigned(writedata) <= reg_next_period) then + reg_next_dutycycle <= unsigned(writedata); + end if; + when REG_CTRL_OFST => + reg_current_ctrl <= writedata(0); + when others => null; + end case; + end if; + end if; + end process; + + + --Avalon-MM slave read + process(clk, reset) + begin + if rising_edge(clk) then + if read = '1' then + case address is + when REG_PERIOD_OFST => + readdata <= std_logic_vector(reg_current_period); + when REG_DUTY_CYCLE_OFST => + readdata <= std_logic_vector(reg_current_dutycycle); + when others => + readdata <= (others => '0'); + end case; + end if; + end if; + end process; + + -- Internal synchronous logic + process(clk, reset) + begin + if reset = '1' then + reg_counter <= to_unsigned(0, writedata'length); + reg_prev_ctrl <= '0'; + elsif rising_edge(clk) then + if ((reg_prev_ctrl = '0') and (reg_current_ctrl = '1')) or + (reg_counter = reg_current_period - 1) then + reg_current_period <= reg_next_period; + reg_current_dutycycle <= reg_next_dutycycle; + reg_counter <= to_unsigned(0, writedata'length); + elsif (reg_current_ctrl = '1') then + reg_counter <= reg_counter + 1; + end if; + reg_prev_ctrl <= reg_current_ctrl; + end if; + end process; + + -- Avalon Conduit interface + process(clk, reset) + begin + if rising_edge(clk) then + + if (reg_counter < reg_current_dutycycle) and (reg_current_ctrl = '1') then + pwm_out <= '1'; + else + pwm_out <= '0'; + end if; + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm_constants.vhd b/cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm_constants.vhd new file mode 100644 index 0000000..bfff03b --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm_constants.vhd @@ -0,0 +1,61 @@ +-- ############################################################################# +-- pwm_constants.vhd +-- ================= +-- This package contains constants used in the PWM design files. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pwm_constants is + -- Register map + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | RegNo | Name | Access | Description | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW period to apply to the | + -- | | | | next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT period of the | + -- | | | | ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to | + -- | | | | the next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT duty cycle of | + -- | | | | the ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.| + -- | | | | Writing 1 to this register starts the PWM. | + -- | | | | | + -- | | | | >> Reading this register always returns 0. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00"; + constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01"; + constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10"; + + -- Default values of registers after reset (BEFORE writing START to the CTRL + -- register with a new configuration) + constant DEFAULT_PERIOD : natural := 4; + constant DEFAULT_DUTY_CYCLE : natural := 2; +end package pwm_constants; + +package body pwm_constants is + +end package body pwm_constants; diff --git a/cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm_hw.tcl b/cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm_hw.tcl new file mode 100644 index 0000000..df7d92a --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/hdl/pantilt/hdl/pwm_hw.tcl @@ -0,0 +1,135 @@ +# TCL File Generated by Component Editor 16.0 +# Tue Feb 28 12:18:00 CET 2017 +# DO NOT MODIFY + + +# +# pwm "pwm" v1.0 +# 2017.02.28.12:18:00 +# Pan-tilt +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module pwm +# +set_module_property DESCRIPTION Pan-tilt +set_module_property NAME pwm +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Pan-tilt +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME pwm +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE +add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +add_interface_port avalon_slave_0 writedata writedata Input 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end pwm_out pwm Output 1 diff --git a/cs309-psoc/lab_1_2/hw/hdl/pantilt/tb/tb_pwm.vhd b/cs309-psoc/lab_1_2/hw/hdl/pantilt/tb/tb_pwm.vhd new file mode 100644 index 0000000..ff2dee7 --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/hdl/pantilt/tb/tb_pwm.vhd @@ -0,0 +1,205 @@ +-- ############################################################################# +-- tb_pwm.vhd +-- ========== +-- Testbench for PWM memory-mapped Avalon slave interface. +-- +-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity tb_pwm is +end entity; + +architecture rtl of tb_pwm is + + -- 50 MHz clock + constant CLK_PERIOD : time := 20 ns; + + -- Signal used to end simulator when we finished submitting our test cases + signal sim_finished : boolean := false; + + -- PWM PORTS + signal clk : std_logic; + signal reset : std_logic; + signal address : std_logic_vector(1 downto 0); + signal read : std_logic; + signal write : std_logic; + signal readdata : std_logic_vector(31 downto 0); + signal writedata : std_logic_vector(31 downto 0); + signal pwm_out : std_logic; + + -- Values of registers we are going to use to configure the PWM unit + constant CONFIG_PERIOD : natural := 100; + constant CONFIG_DUTY_CYCLE : natural := 20; + constant CONFIG_CTRL_START : natural := 1; + constant CONFIG_CTRL_STOP : natural := 0; + +begin + + -- Instantiate DUT + dut : entity work.pwm + port map( + clk => clk, + reset => reset, + address => address, + read => read, + write => write, + readdata => readdata, + writedata => writedata, + pwm_out => pwm_out + ); + + -- Generate clk signal + clk_generation : process + begin + if not sim_finished then + clk <= '1'; + wait for CLK_PERIOD / 2; + clk <= '0'; + wait for CLK_PERIOD / 2; + else + wait; + end if; + end process clk_generation; + + -- Test PWM + simulation : process + + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + + reset <= '1'; + wait for CLK_PERIOD / 2; + + reset <= '0'; + wait for CLK_PERIOD / 4; + end procedure async_reset; + + procedure write_register(constant ofst : in std_logic_vector(1 downto 0); + constant val : in natural) is + begin + wait until rising_edge(clk); + + address <= ofst; + write <= '1'; + writedata <= std_logic_vector(to_unsigned(val, writedata'length)); + wait until rising_edge(clk); + + address <= (others => '0'); + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + end procedure write_register; + + procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is + begin + wait until rising_edge(clk); + + address <= ofst; + read <= '1'; + -- The read has a 1 cycle wait-state, so we need to keep the read + -- signal high for 2 clock cycles. + wait until rising_edge(clk); + wait until rising_edge(clk); + + address <= (others => '0'); + read <= '0'; + wait until rising_edge(clk); + end procedure read_register; + + procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0); + constant expected_val : in natural) is + begin + read_register(ofst); + + case ofst is + when REG_PERIOD_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected PERIOD: " & + "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "PERIOD_expected = " & integer'image(expected_val) + severity error; + + when REG_DUTY_CYCLE_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected DUTY_CYCLE: " & + "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "DUTY_CYCLE_expected = " & integer'image(expected_val) + severity error; + + when REG_CTRL_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected CTRL: " & + "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "CTRL_expected = " & integer'image(expected_val) + severity error; + + when others => + null; + end case; + end procedure read_register_check; + + begin + + -- Default values + reset <= '0'; + address <= (others => '0'); + read <= '0'; + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + + -- Reset the circuit + async_reset; + + -- Write desired configuration to PWM Avalon-MM slave. + write_register(REG_PERIOD_OFST, CONFIG_PERIOD); + write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + + -- Read back configuration from PWM Avalon-MM slave. Note that we have + -- not started the PWM unit yet, so the new configuration must not be + -- read back at this point (as per the register map). + read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Start PWM + write_register(REG_CTRL_OFST, CONFIG_CTRL_START); + + -- Wait until PWM pulses for the first time after we sent START. + wait until rising_edge(pwm_out); + + -- Read back configuration from PWM Avalon-MM slave. Now that we have + -- started the PWM unit, we should be able to read back the + -- configuration we wrote (as per the register map). + read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Wait for 2 PWM periods to finish + wait for 2 * CLK_PERIOD * CONFIG_PERIOD; + + -- Stop PWM. + write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP); + + -- Wait for PWM period to finish + wait for 1 * CLK_PERIOD * CONFIG_PERIOD; + + -- Instruct "clk_generation" process to halt execution. + sim_finished <= true; + + -- Make this process wait indefinitely (it will never re-execute from + -- its beginning again). + wait; + end process simulation; +end architecture rtl; + diff --git a/cs309-psoc/lab_1_2/hw/quartus/ip/components.ipx b/cs309-psoc/lab_1_2/hw/quartus/ip/components.ipx new file mode 100644 index 0000000..8fe7fdc --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/quartus/ip/components.ipx @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_1_2/hw/quartus/lab_1_2.qpf b/cs309-psoc/lab_1_2/hw/quartus/lab_1_2.qpf new file mode 100644 index 0000000..5006be4 --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/quartus/lab_1_2.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition +# Date created = 11:03:02 February 05, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.1" +DATE = "11:03:02 February 05, 2016" + +# Revisions + +PROJECT_REVISION = "lab_1_2" diff --git a/cs309-psoc/lab_1_2/hw/quartus/lab_1_2.qsf b/cs309-psoc/lab_1_2/hw/quartus/lab_1_2.qsf new file mode 100644 index 0000000..773887f --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/quartus/lab_1_2.qsf @@ -0,0 +1,812 @@ +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 + +set_global_assignment -name SMART_RECOMPILE OFF +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level + +set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +set_global_assignment -name QSYS_FILE soc_system.qsys +set_global_assignment -name SDC_FILE lab_1_2.sdc + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA4U23C6 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO Extention OV7670 CAMERA +#============================================================ +set_location_assignment PIN_AE15 -to CAM_D[0] +set_location_assignment PIN_AE15 -to CAM_D_0 +set_location_assignment PIN_AF17 -to CAM_D[1] +set_location_assignment PIN_AF17 -to CAM_D_1 +set_location_assignment PIN_AH8 -to CAM_D[2] +set_location_assignment PIN_AH8 -to CAM_D_2 +set_location_assignment PIN_AG8 -to CAM_D[3] +set_location_assignment PIN_AG8 -to CAM_D_3 +set_location_assignment PIN_U13 -to CAM_D[4] +set_location_assignment PIN_U13 -to CAM_D_4 +set_location_assignment PIN_U14 -to CAM_D[5] +set_location_assignment PIN_U14 -to CAM_D_5 +set_location_assignment PIN_AG9 -to CAM_D[6] +set_location_assignment PIN_AG9 -to CAM_D_6 +set_location_assignment PIN_AG10 -to CAM_D[7] +set_location_assignment PIN_AG10 -to CAM_D_7 +set_location_assignment PIN_AF13 -to CAM_D[8] +set_location_assignment PIN_AF13 -to CAM_D_8 +set_location_assignment PIN_AG13 -to CAM_D[9] +set_location_assignment PIN_AG13 -to CAM_D_9 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9 + +#============================================================ +# Arduino Extension LEPTON CAMERA THERMAL CAM_TH +#============================================================ +set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N +set_location_assignment PIN_AG16 -to CAM_TH_MOSI +set_location_assignment PIN_AH11 -to CAM_TH_MISO +set_location_assignment PIN_AH12 -to CAM_TH_CLK +set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA +set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL + +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#============================================================ +# HPS +#============================================================ +set_location_assignment PIN_C6 -to HPS_CONV_USB_N +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0] +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0 +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1] +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1 +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2] +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2 +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3] +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3 +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4] +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4 +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5] +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5 +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6] +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6 +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7] +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7 +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8] +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8 +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9] +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9 +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10] +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10 +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11] +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11 +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12] +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12 +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13] +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13 +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14] +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14 +set_location_assignment PIN_A27 -to HPS_DDR3_BA[0] +set_location_assignment PIN_A27 -to HPS_DDR3_BA_0 +set_location_assignment PIN_H25 -to HPS_DDR3_BA[1] +set_location_assignment PIN_H25 -to HPS_DDR3_BA_1 +set_location_assignment PIN_G25 -to HPS_DDR3_BA[2] +set_location_assignment PIN_G25 -to HPS_DDR3_BA_2 +set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N +set_location_assignment PIN_L28 -to HPS_DDR3_CKE +set_location_assignment PIN_N20 -to HPS_DDR3_CK_N +set_location_assignment PIN_N21 -to HPS_DDR3_CK_P +set_location_assignment PIN_L21 -to HPS_DDR3_CS_N +set_location_assignment PIN_G28 -to HPS_DDR3_DM[0] +set_location_assignment PIN_G28 -to HPS_DDR3_DM_0 +set_location_assignment PIN_P28 -to HPS_DDR3_DM[1] +set_location_assignment PIN_P28 -to HPS_DDR3_DM_1 +set_location_assignment PIN_W28 -to HPS_DDR3_DM[2] +set_location_assignment PIN_W28 -to HPS_DDR3_DM_2 +set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3] +set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3 +set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0] +set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0 +set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1] +set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1 +set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2] +set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2 +set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3] +set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3 +set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4] +set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4 +set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5] +set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5 +set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6] +set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6 +set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7] +set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7 +set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8] +set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8 +set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9] +set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9 +set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10] +set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10 +set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11] +set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11 +set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12] +set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12 +set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13] +set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13 +set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14] +set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14 +set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15] +set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15 +set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16] +set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16 +set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17] +set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17 +set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18] +set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18 +set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19] +set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19 +set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20] +set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20 +set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21] +set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21 +set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22] +set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22 +set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23] +set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23 +set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24] +set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24 +set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25] +set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25 +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26] +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26 +set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27] +set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27 +set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28] +set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28 +set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29] +set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29 +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30] +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30 +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31] +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31 +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0] +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0 +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1] +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1 +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2] +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2 +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3] +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3 +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0] +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0 +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1] +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1 +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2] +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2 +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3] +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3 +set_location_assignment PIN_D28 -to HPS_DDR3_ODT +set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N +set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N +set_location_assignment PIN_D25 -to HPS_DDR3_RZQ +set_location_assignment PIN_E25 -to HPS_DDR3_WE_N +set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK +set_location_assignment PIN_B14 -to HPS_ENET_INT_N +set_location_assignment PIN_A13 -to HPS_ENET_MDC +set_location_assignment PIN_E16 -to HPS_ENET_MDIO +set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0] +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0 +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1] +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1 +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2] +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2 +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3] +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3 +set_location_assignment PIN_J13 -to HPS_ENET_RX_DV +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0] +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0 +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1] +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1 +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2] +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2 +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3] +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3 +set_location_assignment PIN_A12 -to HPS_ENET_TX_EN +set_location_assignment PIN_A17 -to HPS_GSENSOR_INT +set_location_assignment PIN_C18 -to HPS_I2C0_SCLK +set_location_assignment PIN_A19 -to HPS_I2C0_SDAT +set_location_assignment PIN_K18 -to HPS_I2C1_SCLK +set_location_assignment PIN_A21 -to HPS_I2C1_SDAT +set_location_assignment PIN_J18 -to HPS_KEY_N +set_location_assignment PIN_A20 -to HPS_LED +set_location_assignment PIN_H13 -to HPS_LTC_GPIO +set_location_assignment PIN_B8 -to HPS_SD_CLK +set_location_assignment PIN_D14 -to HPS_SD_CMD +set_location_assignment PIN_C13 -to HPS_SD_DATA[0] +set_location_assignment PIN_C13 -to HPS_SD_DATA_0 +set_location_assignment PIN_B6 -to HPS_SD_DATA[1] +set_location_assignment PIN_B6 -to HPS_SD_DATA_1 +set_location_assignment PIN_B11 -to HPS_SD_DATA[2] +set_location_assignment PIN_B11 -to HPS_SD_DATA_2 +set_location_assignment PIN_B9 -to HPS_SD_DATA[3] +set_location_assignment PIN_B9 -to HPS_SD_DATA_3 +set_location_assignment PIN_C19 -to HPS_SPIM_CLK +set_location_assignment PIN_B19 -to HPS_SPIM_MISO +set_location_assignment PIN_B16 -to HPS_SPIM_MOSI +set_location_assignment PIN_C16 -to HPS_SPIM_SS +set_location_assignment PIN_A22 -to HPS_UART_RX +set_location_assignment PIN_B21 -to HPS_UART_TX +set_location_assignment PIN_G4 -to HPS_USB_CLKOUT +set_location_assignment PIN_C10 -to HPS_USB_DATA[0] +set_location_assignment PIN_C10 -to HPS_USB_DATA_0 +set_location_assignment PIN_F5 -to HPS_USB_DATA[1] +set_location_assignment PIN_F5 -to HPS_USB_DATA_1 +set_location_assignment PIN_C9 -to HPS_USB_DATA[2] +set_location_assignment PIN_C9 -to HPS_USB_DATA_2 +set_location_assignment PIN_C4 -to HPS_USB_DATA[3] +set_location_assignment PIN_C4 -to HPS_USB_DATA_3 +set_location_assignment PIN_C8 -to HPS_USB_DATA[4] +set_location_assignment PIN_C8 -to HPS_USB_DATA_4 +set_location_assignment PIN_D4 -to HPS_USB_DATA[5] +set_location_assignment PIN_D4 -to HPS_USB_DATA_5 +set_location_assignment PIN_C7 -to HPS_USB_DATA[6] +set_location_assignment PIN_C7 -to HPS_USB_DATA_6 +set_location_assignment PIN_F4 -to HPS_USB_DATA[7] +set_location_assignment PIN_F4 -to HPS_USB_DATA_7 +set_location_assignment PIN_E5 -to HPS_USB_DIR +set_location_assignment PIN_D5 -to HPS_USB_NXT +set_location_assignment PIN_C5 -to HPS_USB_STP + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY_N +#============================================================ +set_location_assignment PIN_AH17 -to KEY_N[0] +set_location_assignment PIN_AH17 -to KEY_N_0 +set_location_assignment PIN_AH16 -to KEY_N[1] +set_location_assignment PIN_AH16 -to KEY_N_1 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_W15 -to LED_0 +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_AA24 -to LED_1 +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V16 -to LED_2 +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_V15 -to LED_3 +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AF26 -to LED_4 +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_AE26 -to LED_5 +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_Y16 -to LED_6 +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_AA23 -to LED_7 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7 + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_L10 -to SW[0] +set_location_assignment PIN_L10 -to SW_0 +set_location_assignment PIN_L9 -to SW[1] +set_location_assignment PIN_L9 -to SW_1 +set_location_assignment PIN_H6 -to SW[2] +set_location_assignment PIN_H6 -to SW_2 +set_location_assignment PIN_H5 -to SW[3] +set_location_assignment PIN_H5 -to SW_3 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3 + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_V12 -to PIO_INT_N +set_location_assignment PIN_AE11 -to PIO_SCL +set_location_assignment PIN_AE12 -to PIO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA + +set_location_assignment PIN_AF7 -to PIR_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT + +set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA +set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL +set_location_assignment PIN_T11 -to CAM_SYS_CLK +set_location_assignment PIN_AG6 -to CAM_LV +set_location_assignment PIN_AH2 -to CAM_PIX_CLK +set_location_assignment PIN_AE4 -to CAM_FV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV + +set_location_assignment PIN_Y8 -to PAL_VD_HSO +set_location_assignment PIN_AB4 -to PAL_VD_VSO +set_location_assignment PIN_AG5 -to PAL_VD_VD[0] +set_location_assignment PIN_AG5 -to PAL_VD_VD_0 +set_location_assignment PIN_AH5 -to PAL_VD_VD[1] +set_location_assignment PIN_AH5 -to PAL_VD_VD_1 +set_location_assignment PIN_AH6 -to PAL_VD_VD[2] +set_location_assignment PIN_AH6 -to PAL_VD_VD_2 +set_location_assignment PIN_T8 -to PAL_VD_VD[3] +set_location_assignment PIN_T8 -to PAL_VD_VD_3 +set_location_assignment PIN_T12 -to PAL_VD_VD[4] +set_location_assignment PIN_T12 -to PAL_VD_VD_4 +set_location_assignment PIN_Y5 -to PAL_VD_VD[5] +set_location_assignment PIN_Y5 -to PAL_VD_VD_5 +set_location_assignment PIN_Y4 -to PAL_VD_VD[6] +set_location_assignment PIN_Y4 -to PAL_VD_VD_6 +set_location_assignment PIN_W8 -to PAL_VD_VD[7] +set_location_assignment PIN_W8 -to PAL_VD_VD_7 +set_location_assignment PIN_AH4 -to PAL_VD_CLKO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO + +set_location_assignment PIN_AH3 -to SERVO_0 +set_location_assignment PIN_AF4 -to SERVO_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1 + +set_location_assignment PIN_AD12 -to J0_SPI_CLK +set_location_assignment PIN_AD11 -to J0_SPI_MISO +set_location_assignment PIN_AF9 -to J0_SPI_CS_N +set_location_assignment PIN_AD10 -to J0_SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI + +set_location_assignment PIN_AF5 -to FROM_ESP_TXD +set_location_assignment PIN_T13 -to TO_ESP_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD + +set_location_assignment PIN_AE7 -to SPI_MISO +set_location_assignment PIN_AF6 -to SPI_ENA_N +set_location_assignment PIN_AE8 -to SPI_CLK +set_location_assignment PIN_AE9 -to SPI_MOSI +set_location_assignment PIN_AF10 -to SPI_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT + +set_location_assignment PIN_AF11 -to LED_BGR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_AA15 -to RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N + +set_location_assignment PIN_AG28 -to TS_SCL +set_location_assignment PIN_AH27 -to TS_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA + +set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N +set_location_assignment PIN_AG26 -to LCD_DE +set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN + +set_location_assignment PIN_AH24 -to BLT_TXD +set_location_assignment PIN_AE22 -to BLT_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD + +set_location_assignment PIN_AG20 -to BOARD_ID +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID + +set_location_assignment PIN_AF21 -to VIDEO_HSYNC +set_location_assignment PIN_AG19 -to VIDEO_VSYNC +set_location_assignment PIN_AF20 -to VIDEO_CLK +set_location_assignment PIN_AG23 -to VIDEO_B[0] +set_location_assignment PIN_AG23 -to VIDEO_B_0 +set_location_assignment PIN_AH23 -to VIDEO_B[1] +set_location_assignment PIN_AH23 -to VIDEO_B_1 +set_location_assignment PIN_AF25 -to VIDEO_B[2] +set_location_assignment PIN_AF25 -to VIDEO_B_2 +set_location_assignment PIN_AG24 -to VIDEO_B[3] +set_location_assignment PIN_AG24 -to VIDEO_B_3 +set_location_assignment PIN_AA19 -to VIDEO_B[4] +set_location_assignment PIN_AA19 -to VIDEO_B_4 +set_location_assignment PIN_AH26 -to VIDEO_B[5] +set_location_assignment PIN_AH26 -to VIDEO_B_5 +set_location_assignment PIN_AG18 -to VIDEO_B[6] +set_location_assignment PIN_AG18 -to VIDEO_B_6 +set_location_assignment PIN_AC23 -to VIDEO_B[7] +set_location_assignment PIN_AC23 -to VIDEO_B_7 +set_location_assignment PIN_AH22 -to VIDEO_G[0] +set_location_assignment PIN_AH22 -to VIDEO_G_0 +set_location_assignment PIN_AF22 -to VIDEO_G[1] +set_location_assignment PIN_AF22 -to VIDEO_G_1 +set_location_assignment PIN_AD20 -to VIDEO_G[2] +set_location_assignment PIN_AD20 -to VIDEO_G_2 +set_location_assignment PIN_AE24 -to VIDEO_G[3] +set_location_assignment PIN_AE24 -to VIDEO_G_3 +set_location_assignment PIN_AE20 -to VIDEO_G[4] +set_location_assignment PIN_AE20 -to VIDEO_G_4 +set_location_assignment PIN_AD19 -to VIDEO_G[5] +set_location_assignment PIN_AD19 -to VIDEO_G_5 +set_location_assignment PIN_AF18 -to VIDEO_G[6] +set_location_assignment PIN_AF18 -to VIDEO_G_6 +set_location_assignment PIN_AE19 -to VIDEO_G[7] +set_location_assignment PIN_AE19 -to VIDEO_G_7 +set_location_assignment PIN_AC22 -to VIDEO_R[0] +set_location_assignment PIN_AC22 -to VIDEO_R_0 +set_location_assignment PIN_AA18 -to VIDEO_R[1] +set_location_assignment PIN_AA18 -to VIDEO_R_1 +set_location_assignment PIN_AE23 -to VIDEO_R[2] +set_location_assignment PIN_AE23 -to VIDEO_R_2 +set_location_assignment PIN_AD23 -to VIDEO_R[3] +set_location_assignment PIN_AD23 -to VIDEO_R_3 +set_location_assignment PIN_AH18 -to VIDEO_R[4] +set_location_assignment PIN_AH18 -to VIDEO_R_4 +set_location_assignment PIN_AG21 -to VIDEO_R[5] +set_location_assignment PIN_AG21 -to VIDEO_R_5 +set_location_assignment PIN_AH21 -to VIDEO_R[6] +set_location_assignment PIN_AH21 -to VIDEO_R_6 +set_location_assignment PIN_AH19 -to VIDEO_R[7] +set_location_assignment PIN_AH19 -to VIDEO_R_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7 diff --git a/cs309-psoc/lab_1_2/hw/quartus/lab_1_2.sdc b/cs309-psoc/lab_1_2/hw/quartus/lab_1_2.sdc new file mode 100644 index 0000000..16a41f3 --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/quartus/lab_1_2.sdc @@ -0,0 +1,6 @@ +create_clock -period 20 [get_ports FPGA_CLK1_50] +create_clock -period 20 [get_ports FPGA_CLK2_50] +create_clock -period 20 [get_ports FPGA_CLK3_50] + +derive_pll_clocks +derive_clock_uncertainty diff --git a/cs309-psoc/lab_1_2/hw/quartus/soc_system.qsys b/cs309-psoc/lab_1_2/hw/quartus/soc_system.qsys new file mode 100644 index 0000000..e9d7689 --- /dev/null +++ b/cs309-psoc/lab_1_2/hw/quartus/soc_system.qsys @@ -0,0 +1,643 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + NO_INTERACTIVE_WINDOWS + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_onchip_memory2_0 + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_1_2/lab_1_2.pdf b/cs309-psoc/lab_1_2/lab_1_2.pdf new file mode 100644 index 0000000..21f6e6e Binary files /dev/null and b/cs309-psoc/lab_1_2/lab_1_2.pdf differ diff --git a/cs309-psoc/lab_1_2/sw/nios/application/app.c b/cs309-psoc/lab_1_2/sw/nios/application/app.c new file mode 100644 index 0000000..a8af02a --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/app.c @@ -0,0 +1,69 @@ +#include +#include +#include +#include +#include +#include + +#include "pantilt/pantilt.h" +#include "joysticks/joysticks.h" +#include "system.h" + +#define SLEEP_DURATION_US (100000) // 100 ms + +// Servos +#define PANTILT_PWM_V_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_V_MIN_DUTY_CYCLE_US + PANTILT_PWM_V_MAX_DUTY_CYCLE_US) / 2) +#define PANTILT_PWM_H_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_H_MIN_DUTY_CYCLE_US + PANTILT_PWM_H_MAX_DUTY_CYCLE_US) / 2) + +uint32_t interpolate(uint32_t input, + uint32_t input_lower_bound, + uint32_t input_upper_bound, + uint32_t output_lower_bound, + uint32_t output_upper_bound) { + return (input - input_lower_bound) * (output_upper_bound - output_lower_bound) / (input_upper_bound - input_lower_bound) + output_lower_bound; +} + +int main(void) { + // Hardware control structures + pantilt_dev pantilt = pantilt_inst((void *) PWM_0_BASE, (void *) PWM_1_BASE); + joysticks_dev joysticks = joysticks_inst((void *) MCP3204_0_BASE); + + // Initialize hardware + pantilt_init(&pantilt); + joysticks_init(&joysticks); + + // Center servos. + pantilt_configure_vertical(&pantilt, PANTILT_PWM_V_CENTER_DUTY_CYCLE_US); + pantilt_configure_horizontal(&pantilt, PANTILT_PWM_H_CENTER_DUTY_CYCLE_US); + pantilt_start_vertical(&pantilt); + pantilt_start_horizontal(&pantilt); + + // Control servos with joystick. + while (true) { + // Read LEFT joystick position + uint32_t left_joystick_v = joysticks_read_left_vertical(&joysticks); + uint32_t left_joystick_h = joysticks_read_left_horizontal(&joysticks); + + // Interpolate LEFT joystick position between SERVO_x_MIN_DUTY_CYCLE_US + // and SERVO_x_MAX_DUTY_CYCLE_US + uint32_t pantilt_v_duty_us = interpolate(left_joystick_v, + JOYSTICKS_MIN_VALUE, + JOYSTICKS_MAX_VALUE, + PANTILT_PWM_V_MIN_DUTY_CYCLE_US, + PANTILT_PWM_V_MAX_DUTY_CYCLE_US); + uint32_t pantilt_h_duty_us = interpolate(left_joystick_h, + JOYSTICKS_MIN_VALUE, + JOYSTICKS_MAX_VALUE, + PANTILT_PWM_H_MIN_DUTY_CYCLE_US, + PANTILT_PWM_H_MAX_DUTY_CYCLE_US); + + // Configure servos with interpolated joystick values + pantilt_configure_vertical(&pantilt, pantilt_v_duty_us); + pantilt_configure_horizontal(&pantilt, pantilt_h_duty_us); + + // Sleep for a while to avoid excessive sensitivity + usleep(SLEEP_DURATION_US); + } + + return EXIT_SUCCESS; +} diff --git a/cs309-psoc/lab_1_2/sw/nios/application/joysticks/joysticks.c b/cs309-psoc/lab_1_2/sw/nios/application/joysticks/joysticks.c new file mode 100644 index 0000000..d4742e3 --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/joysticks/joysticks.c @@ -0,0 +1,79 @@ +#include "joysticks.h" + +#define JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL (0) +#define JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL (1) +#define JOYSTICK_LEFT_VRY_MCP3204_CHANNEL (2) +#define JOYSTICK_LEFT_VRX_MCP3204_CHANNEL (3) + +/** + * joysticks_inst + * + * Instantiate a joysticks device structure. + * + * @param base Base address of the MCP3204 component connected to the joysticks. + */ +joysticks_dev joysticks_inst(void *mcp3204_base) { + joysticks_dev dev; + dev.mcp3204 = mcp3204_inst((void *) mcp3204_base); + + return dev; +} + +/** + * joysticks_init + * + * Initializes the joysticks device. + * + * @param dev joysticks device structure. + */ +void joysticks_init(joysticks_dev *dev) { + mcp3204_init(&(dev->mcp3204)); +} + +/** + * joysticks_read_left_vertical + * + * Returns the vertical position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,LV_CHANNEL); +} + +/** + * joysticks_read_left_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204,LH_CHANNEL); +} + +/** + * joysticks_read_right_vertical + * + * Returns the vertical position of the right joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,RV_CHANNEL); +} + +/** + * joysticks_read_right_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204,RH_CHANNEL); +} diff --git a/cs309-psoc/lab_1_2/sw/nios/application/joysticks/joysticks.h b/cs309-psoc/lab_1_2/sw/nios/application/joysticks/joysticks.h new file mode 100644 index 0000000..b43c174 --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/joysticks/joysticks.h @@ -0,0 +1,33 @@ +#ifndef __JOYSTICKS_H__ +#define __JOYSTICKS_H__ + +#include "mcp3204/mcp3204.h" + +/* joysticks device structure */ +typedef struct joysticks_dev { + mcp3204_dev mcp3204; /* MCP3204 device handle */ +} joysticks_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define JOYSTICKS_MIN_VALUE (MCP3204_MIN_VALUE) +#define JOYSTICKS_MAX_VALUE (MCP3204_MAX_VALUE) + +#define LV_CHANNEL 0 +#define LH_CHANNEL 1 +#define RV_CHANNEL 2 +#define RH_CHANNEL 3 +#define CC_CHANNEL "this is a joke" + +joysticks_dev joysticks_inst(void *mcp3204_base); + +void joysticks_init(joysticks_dev *dev); + +uint32_t joysticks_read_left_vertical(joysticks_dev *dev); +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev); +uint32_t joysticks_read_right_vertical(joysticks_dev *dev); +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev); + +#endif /* __JOYSTICKS_H__ */ diff --git a/cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204.c b/cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204.c new file mode 100644 index 0000000..140f053 --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204.c @@ -0,0 +1,44 @@ +#include +#include + +#include "mcp3204.h" +#include "mcp3204_regs.h" + +#define MCP3204_NUM_CHANNELS (4) + +/** + * mcp3204_inst + * + * Instantiate a mcp3204 device structure. + * + * @param base Base address of the component. + */ +mcp3204_dev mcp3204_inst(void *base) { + mcp3204_dev dev; + dev.base = base; + + return dev; +} + +/** + * mcp3204_init + * + * Initializes the mcp3204 device. + * + * @param dev mcp3204 device structure. + */ +void mcp3204_init(mcp3204_dev *dev) { + return; +} + +/** + * mcp3204_read + * + * Reads the register corresponding to the supplied channel parameter. + * + * @param dev mcp3204 device structure. + * @param channel channel to be read + */ +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) { + return channel < 4 ? IORD_32DIRECT(dev->base, channel * 4) : 0; +} diff --git a/cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204.h b/cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204.h new file mode 100644 index 0000000..3b2b2e6 --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204.h @@ -0,0 +1,23 @@ +#ifndef __MCP3204_H__ +#define __MCP3204_H__ + +#include + +/* mcp3204 device structure */ +typedef struct mcp3204_dev { + void *base; /* Base address of component */ +} mcp3204_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define MCP3204_MIN_VALUE (0) +#define MCP3204_MAX_VALUE (4095) + +mcp3204_dev mcp3204_inst(void *base); + +void mcp3204_init(mcp3204_dev *dev); +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel); + +#endif /* __MCP3204_H__ */ diff --git a/cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h b/cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h new file mode 100644 index 0000000..b1c78cd --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h @@ -0,0 +1,9 @@ +#ifndef __MCP3204_REGS_H__ +#define __MCP3204_REGS_H__ + +#define MCP3204_CHANNEL_0_OFST (0 * 4) /* RO */ +#define MCP3204_CHANNEL_1_OFST (1 * 4) /* RO */ +#define MCP3204_CHANNEL_2_OFST (2 * 4) /* RO */ +#define MCP3204_CHANNEL_3_OFST (3 * 4) /* RO */ + +#endif /* __MCP3204_REGS_H__ */ diff --git a/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pantilt.c b/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pantilt.c new file mode 100644 index 0000000..d9c4c72 --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pantilt.c @@ -0,0 +1,109 @@ +#include "pantilt.h" + +/** + * pantilt_inst + * + * Instantiate a pantilt device structure. + * + * @param pwm_v_base Base address of the vertical PWM component. + * @param pwm_h_base Base address of the horizontal PWM component. + */ +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) { + pantilt_dev dev; + dev.pwm_v = pwm_inst(pwm_v_base); + dev.pwm_h = pwm_inst(pwm_h_base); + + return dev; +} + +/** + * pantilt_init + * + * Initializes the pantilt device. + * + * @param dev pantilt device structure. + */ +void pantilt_init(pantilt_dev *dev) { + pwm_init(&(dev->pwm_v)); + pwm_init(&(dev->pwm_h)); +} + +/** + * pantilt_configure_vertical + * + * Configure the vertical PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_v), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_configure_horizontal + * + * Configure the horizontal PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_h), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_start_vertical + * + * Starts the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_vertical(pantilt_dev *dev) { + pwm_start(&(dev->pwm_v)); +} + +/** + * pantilt_start_horizontal + * + * Starts the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_horizontal(pantilt_dev *dev) { + pwm_start(&(dev->pwm_h)); +} + +/** + * pantilt_stop_vertical + * + * Stops the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_vertical(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_v)); +} + +/** + * pantilt_stop_horizontal + * + * Stops the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_horizontal(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_h)); +} diff --git a/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pantilt.h b/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pantilt.h new file mode 100644 index 0000000..1f17500 --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pantilt.h @@ -0,0 +1,39 @@ +#ifndef __PANTILT_H__ +#define __PANTILT_H__ + +#include "pwm/pwm.h" + +/* joysticks device structure */ +typedef struct pantilt_dev { + pwm_dev pwm_v; /* Vertical PWM device handle */ + pwm_dev pwm_h; /* Horizontal PWM device handle */ +} pantilt_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz + +#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms + +/* Vertical servo */ +#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms +#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms + +/* Horizontal servo */ +#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms +#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms + +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base); + +void pantilt_init(pantilt_dev *dev); + +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_start_vertical(pantilt_dev *dev); +void pantilt_start_horizontal(pantilt_dev *dev); +void pantilt_stop_vertical(pantilt_dev *dev); +void pantilt_stop_horizontal(pantilt_dev *dev); + +#endif /* __PANTILT_H__ */ diff --git a/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm.c b/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm.c new file mode 100644 index 0000000..47f0de6 --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm.c @@ -0,0 +1,70 @@ +#include + +#include "pwm.h" +#include "pwm_regs.h" + +#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000)) + + +/** + * pwm_inst + * + * Instantiate a pwm device structure. + * + * @param base Base address of the component. + */ +pwm_dev pwm_inst(void *base) { + pwm_dev dev; + + dev.base = base; + + return dev; +} + +/** + * pwm_init + * + * Initializes the pwm device. This function stops the controller. + * + * @param dev pwm device structure. + */ +void pwm_init(pwm_dev *dev) { + pwm_stop(dev); +} + +/** + * pwm_configure + * + * Configure pwm component. + * + * @param dev pwm device structure. + * @param duty_cycle pwm duty cycle in us. + * @param period pwm period in us. + * @param module_frequency frequency at which the component is clocked. + */ +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) { + IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency)); + IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency)); +} + +/** + * pwm_start + * + * Starts the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_start(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} + +/** + * pwm_stop + * + * Stops the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_stop(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK); +} diff --git a/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm.h b/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm.h new file mode 100644 index 0000000..e2987f4 --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm.h @@ -0,0 +1,21 @@ +#ifndef __PWM_H__ +#define __PWM_H__ + +#include + +/* pwm device structure */ +typedef struct pwm_dev { + void *base; /* Base address of component */ +} pwm_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ +pwm_dev pwm_inst(void *base); + +void pwm_init(pwm_dev *dev); +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency); +void pwm_start(pwm_dev *dev); +void pwm_stop(pwm_dev *dev); + +#endif /* __PWM_H__ */ diff --git a/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm_regs.h b/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm_regs.h new file mode 100644 index 0000000..488583d --- /dev/null +++ b/cs309-psoc/lab_1_2/sw/nios/application/pantilt/pwm/pwm_regs.h @@ -0,0 +1,11 @@ +#ifndef __PWM_REGS_H__ +#define __PWM_REGS_H__ + +#define PWM_PERIOD_OFST (0 * 4) /* RW */ +#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */ +#define PWM_CTRL_OFST (2 * 4) /* WO */ + +#define PWM_CTRL_STOP_MASK (0) +#define PWM_CTRL_START_MASK (1) + +#endif /* __PWM_REGS_H__ */ diff --git a/cs309-psoc/lab_2_0/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd b/cs309-psoc/lab_2_0/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd new file mode 100644 index 0000000..738904a --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd @@ -0,0 +1,203 @@ +-- ############################################################################# +-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +-- +-- BOARD : PrSoC extension board for DE0-Nano-SoC +-- Author : Florian Depraz based on Sahand Kashani-Akhavan work +-- Revision : 1.1 +-- Creation date : 06/02/2016 +-- +-- Syntax Rule : GROUP_NAME_N[bit] +-- +-- GROUP : specify a particular interface (ex: SDR_) +-- NAME : signal name (ex: CONFIG, D, ...) +-- bit : signal index +-- _N : to specify an active-low signal +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; + +entity DE0_Nano_SoC_PrSoC_extn_board_top_level is + port( + ------------------------------- + -- Comment ALL unused ports. -- + ------------------------------- + + -- CLOCK + FPGA_CLK1_50 : in std_logic; + -- FPGA_CLK2_50 : in std_logic; + -- FPGA_CLK3_50 : in std_logic; + + -- KEY on DE0 Nano SoC + KEY_N : in std_logic_vector(1 downto 0); + + -- LEDs on DE0 Nano SoC + -- LED : out std_logic_vector(7 downto 0); + + -- SWITCHES on DE0 Nano SoC + -- SW : in std_logic_vector(3 downto 0); + + -- Servomotors pwm + SERVO_0 : out std_logic; + SERVO_1 : out std_logic; + + -- ADC Joysticks + J0_SPI_CS_n : out std_logic; + J0_SPI_MOSI : out std_logic; + J0_SPI_MISO : in std_logic; + J0_SPI_CLK : out std_logic; + + -- Lepton + CAM_TH_SPI_CS_N : out std_logic; + CAM_TH_MISO : in std_logic; + CAM_TH_MOSI : out std_logic; + CAM_TH_CLK : out std_logic + + -- PCA9637 + -- PIO_SCL : inout std_logic; + -- PIO_SDA : inout std_logic; + -- PIO_INT_N : in std_logic; + -- RESET_N : out std_logic; + + -- OV7670 + -- CAM_D : in std_logic_vector(9 downto 0); + -- CAM_PIX_CLK : in std_logic; + -- CAM_LV : in std_logic; + -- CAM_FV : in std_logic; + -- CAM_SYS_CLK : out std_logic; + + -- VGA and LCD shared signals + -- VIDEO_CLK : out std_logic; + -- VIDEO_VSYNC : out std_logic; + -- VIDEO_HSYNC : out std_logic; + -- VIDEO_B : out std_logic_vector(7 downto 0); + -- VIDEO_G : out std_logic_vector(7 downto 0); + -- VIDEO_R : out std_logic_vector(7 downto 0); + + -- LCD Specific signals + -- LCD_DE : out std_logic; + -- LCD_PIN_DAV_N : ? ?? std_logic; + -- LCD_DISPLAY_EN : out std_logic; + -- SPI_MISO : in std_logic; + -- SPI_ENA_N : out std_logic; + -- SPI_CLK : out std_logic; + -- SPI_MOSI : out std_logic; + -- SPI_DAT : inout std_logic; + + -- I2C TOUCH SCREEN + -- TS_SCL : inout std_logic; + -- TS_SDA : inout std_logic; + + -- BLUETOOTH (BLE) + -- BLT_TXD : in std_logic; + -- BLT_RXD : out std_logic; + + -- I2C For VGA, PAL and OV7670 cameras + -- CAM_PAL_VGA_SDA : inout std_logic; + -- CAM_PAL_VGA_SCL : inout std_logic; + + -- ONE WIRE + -- BOARD_ID : inout std_logic; + + -- PAL Camera + -- PAL_VD_VD : in std_logic_vector(7 downto 0); + -- PAL_VD_VSO : in std_logic; + -- PAL_VD_HSO : in std_logic; + -- PAL_VD_CLKO : in std_logic; + -- PAL_PWDN : out std_logic; + + -- WIFI + -- FROM_ESP_TXD : in std_logic; + -- TO_ESP_RXD : out std_logic; + + -- LED RGB + -- LED_BGR : out std_logic; + + -- HPS + -- HPS_CONV_USB_N : inout std_logic; + -- HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); + -- HPS_DDR3_BA : out std_logic_vector(2 downto 0); + -- HPS_DDR3_CAS_N : out std_logic; + -- HPS_DDR3_CK_N : out std_logic; + -- HPS_DDR3_CK_P : out std_logic; + -- HPS_DDR3_CKE : out std_logic; + -- HPS_DDR3_CS_N : out std_logic; + -- HPS_DDR3_DM : out std_logic_vector(3 downto 0); + -- HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); + -- HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); + -- HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); + -- HPS_DDR3_ODT : out std_logic; + -- HPS_DDR3_RAS_N : out std_logic; + -- HPS_DDR3_RESET_N : out std_logic; + -- HPS_DDR3_RZQ : in std_logic; + -- HPS_DDR3_WE_N : out std_logic; + -- HPS_ENET_GTX_CLK : out std_logic; + -- HPS_ENET_INT_N : inout std_logic; + -- HPS_ENET_MDC : out std_logic; + -- HPS_ENET_MDIO : inout std_logic; + -- HPS_ENET_RX_CLK : in std_logic; + -- HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); + -- HPS_ENET_RX_DV : in std_logic; + -- HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); + -- HPS_ENET_TX_EN : out std_logic; + -- HPS_GSENSOR_INT : inout std_logic; + -- HPS_I2C0_SCLK : inout std_logic; + -- HPS_I2C0_SDAT : inout std_logic; + -- HPS_I2C1_SCLK : inout std_logic; + -- HPS_I2C1_SDAT : inout std_logic; + -- HPS_KEY_N : inout std_logic; + -- HPS_LED : inout std_logic; + -- HPS_LTC_GPIO : inout std_logic; + -- HPS_SD_CLK : out std_logic; + -- HPS_SD_CMD : inout std_logic; + -- HPS_SD_DATA : inout std_logic_vector(3 downto 0); + -- HPS_SPIM_CLK : out std_logic; + -- HPS_SPIM_MISO : in std_logic; + -- HPS_SPIM_MOSI : out std_logic; + -- HPS_SPIM_SS : inout std_logic; + -- HPS_UART_RX : in std_logic; + -- HPS_UART_TX : out std_logic; + -- HPS_USB_CLKOUT : in std_logic; + -- HPS_USB_DATA : inout std_logic_vector(7 downto 0); + -- HPS_USB_DIR : in std_logic; + -- HPS_USB_NXT : in std_logic; + -- HPS_USB_STP : out std_logic + ); +end entity DE0_Nano_SoC_PrSoC_extn_board_top_level; + +architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is + component soc_system is + port ( + clk_clk : in std_logic := 'X'; + reset_reset_n : in std_logic := 'X'; + pwm_0_conduit_end_pwm : out std_logic; + pwm_1_conduit_end_pwm : out std_logic; + mcp3204_0_conduit_end_cs_n : out std_logic; + mcp3204_0_conduit_end_mosi : out std_logic; + mcp3204_0_conduit_end_miso : in std_logic := 'X'; + mcp3204_0_conduit_end_sclk : out std_logic; + lepton_0_spi_cs_n : out std_logic; + lepton_0_spi_mosi : out std_logic; + lepton_0_spi_miso : in std_logic := 'X'; + lepton_0_spi_sclk : out std_logic + ); + end component soc_system; + +begin + soc_system_inst : component soc_system + port map ( + clk_clk => FPGA_CLK1_50, + reset_reset_n => KEY_N(0), + pwm_0_conduit_end_pwm => SERVO_0, + pwm_1_conduit_end_pwm => SERVO_1, + mcp3204_0_conduit_end_cs_n => J0_SPI_CS_n, + mcp3204_0_conduit_end_mosi => J0_SPI_MOSI, + mcp3204_0_conduit_end_miso => J0_SPI_MISO, + mcp3204_0_conduit_end_sclk => J0_SPI_CLK, + lepton_0_spi_cs_n => CAM_TH_SPI_CS_N, + lepton_0_spi_mosi => CAM_TH_MOSI, + lepton_0_spi_miso => CAM_TH_MISO, + lepton_0_spi_sclk => CAM_TH_CLK + ); + +end; diff --git a/cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204.vhd b/cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204.vhd new file mode 100644 index 0000000..af0aafb --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204.vhd @@ -0,0 +1,138 @@ +-- ############################################################################# +-- mcp3204.vhd +-- =========== +-- MCP3204 Avalon-MM slave interface. +-- +-- Register map +-- +-------+-----------+--------+------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +-------+-----------+--------+------------------------------------+ +-- | 0 | CHANNEL_0 | RO | 12-bit digital value of channel 0. | +-- +-------+-----------+--------+------------------------------------+ +-- | 1 | CHANNEL_1 | RO | 12-bit digital value of channel 1. | +-- +-------+-----------+--------+------------------------------------+ +-- | 2 | CHANNEL_2 | RO | 12-bit digital value of channel 2. | +-- +-------+-----------+--------+------------------------------------+ +-- | 3 | CHANNEL_3 | RO | 12-bit digital value of channel 3. | +-- +-------+-----------+--------+------------------------------------+ +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity mcp3204 is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + readdata : out std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic; + SCLK : out std_logic + ); +end entity; + +architecture arch of mcp3204 is + constant NUM_CHANNELS : positive := 4; + constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS)))); + + type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range); + signal data_reg : data_array; + + signal spi_busy, spi_start, spi_datavalid : std_logic; + signal spi_channel : std_logic_vector(1 downto 0); + signal spi_data : std_logic_vector(11 downto 0); + + type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA); + signal state : state_t; + + signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0); + +begin + SPI : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => spi_busy, + start => spi_start, + channel => spi_channel, + data_valid => spi_datavalid, + data => spi_data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + -- FSM that dictates which channel is being read. The state of the component + -- should be thought as the pair (state, channel) + p_fsm : process(reset, clk) + begin + if reset = '1' then + state <= READY; + channel <= (others => '0'); + elsif rising_edge(clk) then + case state is + when READY => + if spi_busy = '0' then + state <= INIT_READ_CHANNEL; + end if; + + when INIT_READ_CHANNEL => + state <= WAIT_FOR_DATA; + + when WAIT_FOR_DATA => + if spi_datavalid = '1' then + state <= READY; + channel <= channel + 1; + end if; + end case; + end if; + end process p_fsm; + + -- Updates the internal registers when a new data is available + p_data : process(reset, clk) + begin + if reset = '1' then + for i in 0 to NUM_CHANNELS - 1 loop + data_reg(i) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + if state = WAIT_FOR_DATA and spi_datavalid = '1' then + data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data; + end if; + end if; + end process p_data; + + spi_start <= '1' when state = INIT_READ_CHANNEL else '0'; + spi_channel <= std_logic_vector(channel); + + -- Interface with the Avalon Switch Fabric + p_avalon_read : process(reset, clk) + begin + if reset = '1' then + readdata <= (others => '0'); + elsif rising_edge(clk) then + if read = '1' then + readdata <= data_reg(to_integer(unsigned(address))); + end if; + end if; + end process p_avalon_read; + +end architecture; diff --git a/cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl b/cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl new file mode 100644 index 0000000..757514d --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl @@ -0,0 +1,137 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 18:14:06 CET 2017 +# DO NOT MODIFY + + +# +# mcp3204 "mcp3204" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.18:14:06 +# 4-Channel 12-Bit A/D Converter with SPI Serial Interface +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module mcp3204 +# +set_module_property DESCRIPTION "4-Channel 12-Bit A/D Converter with SPI Serial Interface" +set_module_property NAME mcp3204 +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Joystick +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME mcp3204 +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL mcp3204 +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file mcp3204.vhd VHDL PATH mcp3204.vhd TOP_LEVEL_FILE +add_fileset_file mcp3204_spi.vhd VHDL PATH mcp3204_spi.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end CS_N cs_n Output 1 +add_interface_port conduit_end MOSI mosi Output 1 +add_interface_port conduit_end MISO miso Input 1 +add_interface_port conduit_end SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd b/cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd new file mode 100644 index 0000000..f5e072e --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd @@ -0,0 +1,87 @@ +-- ############################################################################# +-- mcp3204_spi.vhd +-- =============== +-- MCP3204 SPI interface. +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Author : () +-- Revision : 1 +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mcp3204_spi is + port( + -- 50 MHz + clk : in std_logic; + reset : in std_logic; + busy : out std_logic; + start : in std_logic; + channel : in std_logic_vector(1 downto 0); + data_valid : out std_logic; + data : out std_logic_vector(11 downto 0); + + -- 1 MHz + SCLK : out std_logic; + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); +end mcp3204_spi; + +architecture rtl of mcp3204_spi is + signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24 + signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz + signal reg_rising_edge_sclk : std_logic := '0'; + signal reg_falling_edge_sclk : std_logic := '0'; + + signal reg_sclk : std_logic := '0'; + +begin + clk_divider_generation : process(clk, reset) + begin + if reset = '1' then + reg_clk_divider_counter <= (others => '0'); + elsif rising_edge(clk) then + reg_clk_divider_counter <= reg_clk_divider_counter + 1; + reg_spi_en <= '0'; + reg_rising_edge_sclk <= '0'; + reg_falling_edge_sclk <= '0'; + + if reg_clk_divider_counter = 24 then + reg_clk_divider_counter <= (others => '0'); + reg_spi_en <= '1'; + + if reg_sclk = '0' then + reg_rising_edge_sclk <= '1'; + elsif reg_sclk = '1' then + reg_falling_edge_sclk <= '1'; + end if; + end if; + end if; + end process; + + SCLK_generation : process(clk, reset) + begin + if reset = '1' then + reg_sclk <= '0'; + elsif rising_edge(clk) then + if reg_spi_en = '1' then + reg_sclk <= not reg_sclk; + end if; + end if; + end process; + + STATE_LOGIC : process(clk, reset) + begin + -- TODO: complete this process + if reset = '1' then + elsif rising_edge(clk) then + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_2_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd b/cs309-psoc/lab_2_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd new file mode 100644 index 0000000..1bb61d2 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd @@ -0,0 +1,103 @@ +-- ############################################################################# +-- tb_mcp3204_spi.vhd +-- ================== +-- Testbench for MCP3204 SPI interface. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 1 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_mcp3204_spi is +end entity; + +architecture rtl of tb_mcp3204_spi is + constant CLK_PERIOD : time := 20 ns; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal sim_finished : boolean := false; + + -- mcp3204_spi ------------------------------------------------------------ + signal busy : std_logic := '0'; + signal start : std_logic := '0'; + signal channel : std_logic_vector(1 downto 0) := (others => '0'); + signal data_valid : std_logic := '0'; + signal data : std_logic_vector(11 downto 0) := (others => '0'); + signal SCLK : std_logic := '0'; + signal CS_N : std_logic := '1'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '0'; + +begin + duv : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => busy, + start => start, + channel => channel, + data_valid => data_valid, + data => data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_finished; + + sim : process + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + reset <= '1'; + + wait for CLK_PERIOD / 2; + reset <= '0'; + end procedure async_reset; + + procedure spi_transfer(constant channel_number : natural range 0 to 3) is + begin + if busy = '1' then + wait until busy = '0'; + + else + wait until falling_edge(clk); + start <= '1'; + channel <= std_logic_vector(to_unsigned(channel_number, channel'length)); + + wait until falling_edge(clk); + start <= '0'; + channel <= (others => '0'); + + wait until rising_edge(data_valid); + wait until falling_edge(busy); + end if; + end procedure spi_transfer; + + begin + async_reset; + + MISO <= '1'; + spi_transfer(0); + + MISO <= '0'; + spi_transfer(1); + + MISO <= '1'; + spi_transfer(2); + + MISO <= '0'; + spi_transfer(3); + + sim_finished <= true; + wait; + end process sim; +end architecture rtl; + + diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd new file mode 100644 index 0000000..9769bb8 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd @@ -0,0 +1,139 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.utils.all; + +entity avalon_st_spi_master is + generic( + INPUT_CLK_FREQ : integer := 50000000; + SPI_SCLK_FREQ : integer := 10000000; + CPOL : integer := 1; + CPHA : integer := 1 + ); + port( + -- Input clock + clk : in std_logic; + + -- Reset + reset : in std_logic; + spi_cs_n : in std_logic; + -- Sink Avalon ST Interface + mosi_sink_data : in std_logic_vector(7 downto 0); + mosi_sink_valid : in std_logic; + mosi_sink_ready : out std_logic; + + -- Source Avalon ST Interface + miso_src_data : out std_logic_vector(7 downto 0); + miso_src_valid : out std_logic; + + -- SPI Master signals + SCLK : out std_logic; + MISO : in std_logic; + MOSI : out std_logic; + CS_n : out std_logic + ); +end avalon_st_spi_master; + +architecture rtl of avalon_st_spi_master is + constant SCLK_PRESCALER_MAX : integer := INPUT_CLK_FREQ / SPI_SCLK_FREQ / 2; + signal sclk_prescaler : unsigned(bitlength(SCLK_PRESCALER_MAX) downto 0); + signal sclk_toggle : std_logic; + + signal new_sink_buffer, cur_sink_buffer : std_logic_vector(mosi_sink_data'range); + signal new_sink_buffer_busy, cur_sink_buffer_busy : std_logic; + + signal miso_src_buffer : std_logic_vector(7 downto 0); + + signal spi_done, i_sclk : std_logic; + signal spi_bit_index : unsigned(2 downto 0); +begin + CS_n <= spi_cs_n; + + p_sclk_prescaler : process(clk, reset) is + begin + if reset = '1' then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + elsif rising_edge(clk) then + if sclk_prescaler = SCLK_PRESCALER_MAX then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + else + sclk_prescaler <= sclk_prescaler + 1; + end if; + end if; + end process p_sclk_prescaler; + sclk_toggle <= '1' when sclk_prescaler = SCLK_PRESCALER_MAX else '0'; + + p_avalon_st_sink : process(clk, reset) is + begin + if reset = '1' then + new_sink_buffer_busy <= '0'; + new_sink_buffer <= (others => '0'); + elsif rising_edge(clk) then + if mosi_sink_valid = '1' then + if new_sink_buffer_busy = '0' and cur_sink_buffer_busy = '1' then + new_sink_buffer <= mosi_sink_data; + new_sink_buffer_busy <= '1'; + end if; + elsif new_sink_buffer_busy = '1' and cur_sink_buffer_busy = '0' then + new_sink_buffer_busy <= '0'; + end if; + end if; + end process p_avalon_st_sink; + mosi_sink_ready <= not new_sink_buffer_busy; + + p_cur_buffer : process(clk, reset) is + begin + if reset = '1' then + cur_sink_buffer <= (others => '0'); + cur_sink_buffer_busy <= '0'; + elsif rising_edge(clk) then + if mosi_sink_valid = '1' and cur_sink_buffer_busy = '0' then + cur_sink_buffer <= mosi_sink_data; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '0' and new_sink_buffer_busy = '1' then + cur_sink_buffer <= new_sink_buffer; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '1' and spi_done = '1' then + cur_sink_buffer_busy <= '0'; + end if; + end if; + end process p_cur_buffer; + + p_spi : process(clk, reset) is + begin + if reset = '1' then + spi_done <= '0'; + i_sclk <= to_unsigned(CPOL, 1)(0); + spi_bit_index <= "000"; + MOSI <= '0'; + miso_src_data <= (others => '0'); + miso_src_valid <= '0'; + miso_src_buffer <= (others => '0'); + + elsif rising_edge(clk) then + spi_done <= '0'; + miso_src_valid <= '0'; + if cur_sink_buffer_busy = '1' and sclk_toggle = '1' then + if i_sclk /= to_unsigned(CPHA, 1)(0) then + if spi_bit_index = "111" then + spi_done <= '1'; + spi_bit_index <= "000"; + miso_src_valid <= '1'; + miso_src_data <= miso_src_buffer(7 downto 1) & MISO; + else + MOSI <= cur_sink_buffer(7 - to_integer(spi_bit_index)); + miso_src_buffer(7 - to_integer(spi_bit_index)) <= MISO; + spi_bit_index <= spi_bit_index + 1; + + end if; + + end if; + + i_sclk <= not i_sclk; + + end if; + end if; + end process p_spi; + SCLK <= i_sclk; + +end rtl; diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/byte2pix.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/byte2pix.vhd new file mode 100644 index 0000000..b888ba9 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/byte2pix.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------- +-- Title : Byte stream to pixel converter for the Lepton Camera +-- Project : PrSoC +------------------------------------------------------------------------------- +-- File : byte2pix.vhd +-- Author : Philemon Orphee Favrod +-- Company : +-- Created : 2016-03-21 +-- Last update: 2017-03-19 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: Converts a byte stream to a 14-bit pixel stream. +------------------------------------------------------------------------------- +-- Copyright (c) 2016 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2016-03-21 1.0 pofavrod Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity byte2pix is + port( + clk, reset : in std_logic; + byte_data : in std_logic_vector(7 downto 0); + byte_valid : in std_logic; + byte_sof : in std_logic; + byte_eof : in std_logic; + pix_data : out std_logic_vector(13 downto 0); + pix_valid : out std_logic; + pix_sof : out std_logic; + pix_eof : out std_logic); + +end byte2pix; + +architecture rtl of byte2pix is + signal last_sof : std_logic; + signal msb : std_logic_vector(5 downto 0); + signal cnt : std_logic; -- used to skip msb sampling every other time +begin + process(clk, reset) + begin + if reset = '1' then + msb <= (others => '0'); + cnt <= '0'; + last_sof <= '0'; + elsif rising_edge(clk) then + if byte_valid = '1' then + if cnt = '0' then + msb <= byte_data(5 downto 0); + last_sof <= byte_sof; + end if; + cnt <= not cnt; + end if; + end if; + end process; + + process(clk, reset) + begin + if reset = '1' then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + elsif rising_edge(clk) then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + + if byte_valid = '1' then + if cnt = '1' then + pix_data <= msb & byte_data; + pix_valid <= '1'; + pix_sof <= last_sof; + pix_eof <= byte_eof; + end if; + end if; + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd new file mode 100644 index 0000000..d4b4812 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd @@ -0,0 +1,192 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: dual_ported_ram.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +entity dual_ported_ram is + port( + clock : in std_logic := '1'; + data : in std_logic_vector(15 downto 0); + rdaddress : in std_logic_vector(12 downto 0); + wraddress : in std_logic_vector(12 downto 0); + wren : in std_logic := '0'; + q : out std_logic_vector(15 downto 0) + ); +end dual_ported_ram; + +architecture SYN of dual_ported_ram is + signal sub_wire0 : std_logic_vector(15 downto 0); + +begin + q <= sub_wire0(15 downto 0); + + altsyncram_component : altsyncram + generic map( + address_aclr_b => "NONE", + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 8192, + numwords_b => 8192, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "CLOCK0", + power_up_uninitialized => "FALSE", + read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => 13, + widthad_b => 13, + width_a => 16, + width_b => 16, + width_byteena_a => 1 + ) + port map( + address_a => wraddress, + address_b => rdaddress, + clock0 => clock, + data_a => data, + wren_a => wren, + q_b => sub_wire0 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]" +-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 +-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton.vhd new file mode 100644 index 0000000..82678ba --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton.vhd @@ -0,0 +1,288 @@ +-- Lepton Avalon Memory-Mapped Slave Interface +-- Author: Philémon Favrod (philemon.favrod@epfl.ch) +-- Modified by: Sahand Kashani-Akhavan (sahand.kashani-akhavan@epfl.ch) +-- Revision: 2 + +-- Register map +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 0 | COMMAND | WO | Command | +-- | | | | - Writing 1 starts capturing a frame & resets the | +-- | | | | ERROR bit (bit 1) in the STATUS register. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 1 | STATUS | RO | Status | +-- | | | | - Bit 0: 0 --> no capture in progress. | +-- | | | | 1 --> capture in progress. | +-- | | | | - Bit 1: 0 --> previous capture successful. | +-- | | | | 1 --> error during previous capture. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 2 | MIN | RO | Minimum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 3 | MAX | RO | Maximum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4 | SUM_LSB | RO | Sum of all pixels in frame (low 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 5 | SUM_MSB | RO | Sum of all pixels in frame (high 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 6 | ROW_IDX | RO | Current line being captured (1 <= ROW_IDX <= 60). | +-- | | | | Available for debugging purposes. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 7 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8 - 4807 | RAW BUFFER | RO | View into RAW pixel buffer. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4808 - 8191 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8192 - 12991 | ADJUSTED BUFFER | RO | View into adjusted (scaled) pixel buffer. | +-- | | | | Values are scaled between MIN and MAX. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 12992 - 16383 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton is + port( + clk : in std_logic; + reset : in std_logic; + address : in std_logic_vector(13 downto 0); + readdata : out std_logic_vector(15 downto 0); + writedata : in std_logic_vector(15 downto 0); + read : in std_logic; + write : in std_logic; + + SCLK : out std_logic; + CSn : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); + +end lepton; + +architecture rtl of lepton is + signal spi_cs_n : std_logic; + signal spi_mosi_data : std_logic_vector(7 downto 0); + signal spi_mosi_valid : std_logic; + signal spi_mosi_ready : std_logic; + signal spi_miso_data : std_logic_vector(7 downto 0); + signal spi_miso_valid : std_logic; + signal lepton_manager_start : std_logic; + signal lepton_manager_error : std_logic; + signal byte_data : std_logic_vector(7 downto 0); + signal byte_valid : std_logic; + signal byte_sof : std_logic; + signal byte_eof : std_logic; + signal pix_data : std_logic_vector(13 downto 0); + signal pix_valid : std_logic; + signal pix_sof : std_logic; + signal pix_eof : std_logic; + signal stat_min : std_logic_vector(13 downto 0); + signal stat_max : std_logic_vector(13 downto 0); + signal stat_sum : std_logic_vector(26 downto 0); + signal stat_valid : std_logic; + signal ram_data : std_logic_vector(15 downto 0); + signal ram_wren : std_logic; + signal ram_wraddress : std_logic_vector(12 downto 0); + signal ram_rdaddress : std_logic_vector(12 downto 0); + signal ram_q : std_logic_vector(15 downto 0); + signal row_idx : std_logic_vector(5 downto 0); + signal raw_pixel : std_logic_vector(13 downto 0); + signal raw_max : std_logic_vector(13 downto 0); + signal raw_min : std_logic_vector(13 downto 0); + signal raw_sum : std_logic_vector(26 downto 0); + signal adjusted_pixel : std_logic_vector(13 downto 0); + + constant COMMAND_REG_OFFSET : std_logic_vector(address'range) := "00000000000000"; + constant STATUS_REG_OFFSET : std_logic_vector(address'range) := "00000000000001"; + constant MIN_REG_OFFSET : std_logic_vector(address'range) := "00000000000010"; + constant MAX_REG_OFFSET : std_logic_vector(address'range) := "00000000000011"; + constant SUM_LSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000100"; + constant SUM_MSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000101"; + constant ROW_IDX_REG_OFFSET : std_logic_vector(address'range) := "00000000000110"; + constant BUFFER_REG_OFFSET : unsigned(address'range) := "00000000001000"; + constant ADJUSTED_BUFFER_REG_OFFSET : unsigned(address'range) := "10000000000000"; + + constant IMAGE_SIZE : integer := 80 * 60; + constant BUFFER_REG_LIMIT : unsigned(address'range) := unsigned(BUFFER_REG_OFFSET) + IMAGE_SIZE; + + constant ADJUSTED_BUFFER_LIMIT : unsigned(address'range) := unsigned(ADJUSTED_BUFFER_REG_OFFSET) + IMAGE_SIZE; + + signal max_reg : std_logic_vector(stat_max'range); + signal min_reg : std_logic_vector(stat_min'range); + signal sum_reg : std_logic_vector(stat_sum'range); + signal error_reg : std_logic; + +begin + spi_controller0 : entity work.avalon_st_spi_master + port map( + clk => clk, + reset => reset, + spi_cs_n => spi_cs_n, + mosi_sink_data => spi_mosi_data, + mosi_sink_valid => spi_mosi_valid, + mosi_sink_ready => spi_mosi_ready, + miso_src_data => spi_miso_data, + miso_src_valid => spi_miso_valid, + SCLK => SCLK, + MISO => MISO, + MOSI => MOSI, + CS_n => CSn + ); + + lepton_manager0 : entity work.lepton_manager + port map( + clk => clk, + reset => reset, + spi_miso_sink_data => spi_miso_data, + spi_miso_sink_valid => spi_miso_valid, + spi_mosi_src_data => spi_mosi_data, + spi_mosi_src_valid => spi_mosi_valid, + spi_mosi_src_ready => spi_mosi_ready, + lepton_out_data => byte_data, + lepton_out_valid => byte_valid, + lepton_out_sof => byte_sof, + lepton_out_eof => byte_eof, + row_idx => row_idx, + error => lepton_manager_error, + start => lepton_manager_start, + spi_cs_n => spi_cs_n + ); + + byte2pix0 : entity work.byte2pix + port map( + clk => clk, + reset => reset, + byte_data => byte_data, + byte_valid => byte_valid, + byte_sof => byte_sof, + byte_eof => byte_eof, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof + ); + + lepton_stats0 : entity work.lepton_stats + port map( + reset => reset, + clk => clk, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + stat_min => stat_min, + stat_max => stat_max, + stat_sum => stat_sum, + stat_valid => stat_valid + ); + + ram_writer0 : entity work.ram_writer + port map( + clk => clk, + reset => reset, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + ram_data => ram_data, + ram_wren => ram_wren, + ram_wraddress => ram_wraddress + ); + + dual_ported_ram0 : entity work.dual_ported_ram + port map( + clock => clk, + data => ram_data, + rdaddress => ram_rdaddress, + wraddress => ram_wraddress, + wren => ram_wren, + q => ram_q + ); + + level_adjuster0 : entity work.level_adjuster + port map( + clk => clk, + raw_pixel => ram_q(13 downto 0), + raw_max => max_reg, + raw_min => min_reg, + raw_sum => sum_reg, + adjusted_pixel => adjusted_pixel + ); + + p_lepton_start : process(clk, reset) + begin + if reset = '1' then + lepton_manager_start <= '0'; + error_reg <= '0'; + elsif rising_edge(clk) then + if write = '1' and address = COMMAND_REG_OFFSET then + lepton_manager_start <= writedata(0); + error_reg <= '0'; + elsif pix_eof = '1' then + lepton_manager_start <= '0'; + elsif lepton_manager_error = '1' then + error_reg <= '1'; + end if; + end if; + end process p_lepton_start; + + p_stat_reg : process(clk, reset) + begin + if reset = '1' then + min_reg <= (others => '0'); + max_reg <= (others => '0'); + sum_reg <= (others => '0'); + elsif rising_edge(clk) then + if stat_valid = '1' then + min_reg <= stat_min; + max_reg <= stat_max; + sum_reg <= stat_sum; + end if; + end if; + end process p_stat_reg; + + p_read : process(clk, reset) + begin + if reset = '1' then + readdata <= (others => '0'); + ram_rdaddress <= (others => '0'); + elsif rising_edge(clk) then + readdata <= (others => '0'); + if read = '1' then + case address is + when STATUS_REG_OFFSET => + readdata(1) <= error_reg; + readdata(0) <= lepton_manager_start; + + when MIN_REG_OFFSET => + readdata <= "00" & min_reg; + + when MAX_REG_OFFSET => + readdata <= "00" & max_reg; + + when SUM_MSB_REG_OFFSET => + readdata <= "00000" & sum_reg(26 downto 16); + + when SUM_LSB_REG_OFFSET => + readdata <= sum_reg(15 downto 0); + + when ROW_IDX_REG_OFFSET => + readdata(5 downto 0) <= row_idx; + + when others => + if unsigned(address) >= BUFFER_REG_OFFSET and unsigned(address) < BUFFER_REG_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= ram_q; + elsif unsigned(address) >= ADJUSTED_BUFFER_REG_OFFSET and unsigned(address) < ADJUSTED_BUFFER_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - ADJUSTED_BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= "00" & adjusted_pixel; + end if; + end case; + end if; + end if; + end process p_read; + +end rtl; diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_hw.tcl b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_hw.tcl new file mode 100644 index 0000000..d62e01b --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_hw.tcl @@ -0,0 +1,148 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 19:05:24 CET 2017 +# DO NOT MODIFY + + +# +# lepton "lepton" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.19:05:24 +# IR Camera 80x60 +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module lepton +# +set_module_property DESCRIPTION "IR Camera 80x60" +set_module_property NAME lepton +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Camera +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME lepton +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL lepton +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file avalon_st_spi_master.vhd VHDL PATH avalon_st_spi_master.vhd +add_fileset_file byte2pix.vhd VHDL PATH byte2pix.vhd +add_fileset_file dual_ported_ram.vhd VHDL PATH dual_ported_ram.vhd +add_fileset_file lepton.vhd VHDL PATH lepton.vhd TOP_LEVEL_FILE +add_fileset_file lepton_manager.vhd VHDL PATH lepton_manager.vhd +add_fileset_file lepton_stats.vhd VHDL PATH lepton_stats.vhd +add_fileset_file ram_writer.vhd VHDL PATH ram_writer.vhd +add_fileset_file utils.vhd VHDL PATH utils.vhd +add_fileset_file level_adjuster.vhd VHDL PATH level_adjuster.vhd +add_fileset_file lpm_divider.vhd VHDL PATH lpm_divider.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitStates 9 +set_interface_property avalon_slave_0 readWaitTime 9 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 14 +add_interface_port avalon_slave_0 readdata readdata Output 16 +add_interface_port avalon_slave_0 writedata writedata Input 16 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point spi +# +add_interface spi conduit end +set_interface_property spi associatedClock clock +set_interface_property spi associatedReset "" +set_interface_property spi ENABLED true +set_interface_property spi EXPORT_OF "" +set_interface_property spi PORT_NAME_MAP "" +set_interface_property spi CMSIS_SVD_VARIABLES "" +set_interface_property spi SVD_ADDRESS_GROUP "" + +add_interface_port spi CSn cs_n Output 1 +add_interface_port spi MISO miso Input 1 +add_interface_port spi MOSI mosi Output 1 +add_interface_port spi SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_manager.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_manager.vhd new file mode 100644 index 0000000..1580be1 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_manager.vhd @@ -0,0 +1,235 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_manager is + generic( + INPUT_CLK_FREQ : integer := 50000000); + port( + clk : in std_logic := '0'; + reset : in std_logic := '0'; + + -- Avalon ST Sink to receive SPI data + spi_miso_sink_data : in std_logic_vector(7 downto 0); + spi_miso_sink_valid : in std_logic; + + -- Avalon ST Source to send SPI data + spi_mosi_src_data : out std_logic_vector(7 downto 0); + spi_mosi_src_valid : out std_logic; + spi_mosi_src_ready : in std_logic := '0'; + + -- Filtered output to retransmit cleaned data (without the discard packets, see Lepton Datasheet on page 31) + -- lepton_out_data is valid on rising edge when lepton_src_valid = '1' + lepton_out_data : out std_logic_vector(7 downto 0); + lepton_out_valid : out std_logic; + lepton_out_sof : out std_logic; + lepton_out_eof : out std_logic; + + -- Some status + row_idx : out std_logic_vector(5 downto 0); + error : out std_logic; + + -- Avalon MM Slave interface for configuration + start : in std_logic; + + -- The SPI Chip Select (Active low !) + spi_cs_n : out std_logic := '0'); +end entity lepton_manager; + +architecture rtl of lepton_manager is + type state_t is (Idle, CSn, ReadHeader, ReadPayload, DiscardPayload, WaitBeforeIdle); + signal state, next_state : state_t; + + signal header_3_last_nibbles : std_logic_vector(11 downto 0); + + constant CLOCK_TICKS_PER_37_MS : integer := 37 * (INPUT_CLK_FREQ / 1e3); -- the timeout delay for a frame + constant CLOCK_TICKS_PER_200_MS : integer := 200 * (INPUT_CLK_FREQ / 1e3); + constant CLOCK_TICKS_PER_200_NS : integer := (200 * (INPUT_CLK_FREQ / 1e6)) / 1e3; + constant BYTES_PER_HEADER : integer := 4; + constant BYTES_PER_PAYLOAD : integer := 160; + + constant NUMBER_OF_LINES_PER_FRAME : positive := 60; + signal counter, counter_max : integer range 1 to CLOCK_TICKS_PER_200_MS; + signal line_counter : integer range 1 to NUMBER_OF_LINES_PER_FRAME; + signal timeout_counter : integer range 1 to CLOCK_TICKS_PER_37_MS; + signal counter_enabled : boolean; + signal waited_long_enough : boolean; + signal header_end, payload_end : boolean; +begin + + -- purpose: register for state + p_fsm : process(clk, reset) + begin + if reset = '1' then + state <= Idle; + elsif rising_edge(clk) then + state <= next_state; + end if; + end process p_fsm; + + -- purpose: compute the next state + p_nsl : process(header_3_last_nibbles, header_end, payload_end, start, spi_miso_sink_valid, state, waited_long_enough, line_counter) + begin + next_state <= state; + + case state is + when Idle => + if waited_long_enough and start = '1' then + next_state <= CSn; + end if; + + when CSn => + if waited_long_enough then + next_state <= ReadHeader; + end if; + + when ReadHeader => + if header_end then + if header_3_last_nibbles(11 downto 8) = X"F" then + next_state <= DiscardPayload; + else + next_state <= ReadPayload; + end if; + end if; + + when DiscardPayload | ReadPayload => + if payload_end then + next_state <= ReadHeader; + + if line_counter = NUMBER_OF_LINES_PER_FRAME then + next_state <= WaitBeforeIdle; + end if; + end if; + + when WaitBeforeIdle => + if spi_miso_sink_valid = '1' then + next_state <= Idle; + end if; + + end case; + end process p_nsl; + + p_counter : process(clk, reset) + begin + if reset = '1' then + counter <= 1; + line_counter <= 1; + elsif rising_edge(clk) then + if counter = counter_max and counter_enabled then + counter <= 1; + + if state = ReadPayload then + if line_counter = NUMBER_OF_LINES_PER_FRAME then + line_counter <= 1; + else + line_counter <= line_counter + 1; + end if; + end if; + + elsif counter_enabled then + counter <= counter + 1; + end if; + end if; + end process p_counter; + + p_error : process(clk, reset) + begin + if reset = '1' then + error <= '0'; + timeout_counter <= 1; + elsif rising_edge(clk) then + if state /= ReadHeader and state /= ReadPayload and state /= ReadHeader then + timeout_counter <= 1; + error <= '0'; + else + if timeout_counter = CLOCK_TICKS_PER_37_MS then + error <= '1'; + else + timeout_counter <= timeout_counter + 1; + end if; + end if; + if state = ReadPayload and header_3_last_nibbles /= std_logic_vector(to_unsigned(line_counter - 1, header_3_last_nibbles'length)) then + error <= '1'; + end if; + end if; + end process p_error; + + -- purpose: wire the datapath + p_datapath : process(counter, counter_enabled, counter_max, line_counter, spi_miso_sink_data, spi_miso_sink_valid, spi_mosi_src_ready, state) + variable counter_ended : boolean; + + begin + counter_max <= 1; + counter_enabled <= true; + waited_long_enough <= false; + lepton_out_data <= (others => '0'); + lepton_out_valid <= '0'; + lepton_out_sof <= '0'; + lepton_out_eof <= '0'; + spi_mosi_src_valid <= '0'; + spi_mosi_src_data <= (others => '0'); + spi_cs_n <= '0'; + header_end <= false; + payload_end <= false; + + counter_ended := (counter = counter_max and counter_enabled); + + case state is + when Idle => + counter_max <= CLOCK_TICKS_PER_200_MS; + waited_long_enough <= counter_ended; + spi_cs_n <= '1'; + + when CSn => + counter_max <= CLOCK_TICKS_PER_200_NS; + waited_long_enough <= counter_ended; + + when ReadHeader => + counter_max <= BYTES_PER_HEADER; + counter_enabled <= spi_miso_sink_valid = '1'; + header_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when ReadPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + lepton_out_data <= spi_miso_sink_data; + lepton_out_valid <= spi_miso_sink_valid; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + if spi_miso_sink_valid = '1' then + if counter = 1 and counter_enabled and line_counter = 1 then + lepton_out_sof <= '1'; + elsif counter_ended and line_counter = NUMBER_OF_LINES_PER_FRAME then + lepton_out_eof <= '1'; + end if; + end if; + + when DiscardPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when others => null; + end case; + end process p_datapath; + + p_capture_header : process(clk, reset) + begin + if reset = '1' then + header_3_last_nibbles <= X"000"; + elsif rising_edge(clk) then + if state = ReadHeader and spi_miso_sink_valid = '1' then + if counter = 1 then + header_3_last_nibbles(11 downto 8) <= spi_miso_sink_data(3 downto 0); + elsif counter = 2 then + header_3_last_nibbles(7 downto 0) <= spi_miso_sink_data; + end if; + end if; + end if; + end process p_capture_header; + + row_idx <= std_logic_vector(to_unsigned(line_counter, row_idx'length)); + +end architecture rtl; diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_stats.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_stats.vhd new file mode 100644 index 0000000..4b5cc91 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lepton_stats.vhd @@ -0,0 +1,78 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_stats is + port( + clk : in std_logic; + reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + stat_min : out std_logic_vector(13 downto 0); + stat_max : out std_logic_vector(13 downto 0); + stat_sum : out std_logic_vector(26 downto 0); + stat_valid : out std_logic); +end lepton_stats; + +architecture rtl of lepton_stats is + + -- The accumulated sum, min and max of the pixel values + signal curr_min : unsigned(13 downto 0); + signal curr_max : unsigned(13 downto 0); + signal curr_sum : unsigned(26 downto 0); + + -- The next value of the registers + signal next_min : unsigned(13 downto 0); + signal next_max : unsigned(13 downto 0); + signal next_sum : unsigned(26 downto 0); + +begin + + -- This is the synchronous transition logic + transition_logic : process(clk, reset) + begin + if reset = '1' then + curr_sum <= (others => '0'); + curr_min <= (others => '0'); + curr_max <= (others => '0'); + elsif rising_edge(clk) then + curr_min <= next_min; + curr_max <= next_max; + curr_sum <= next_sum; + end if; + end process; + + -- This is the combinatorial transition logic + next_min <= + curr_min when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_min when unsigned(pix_data) >= curr_min else + unsigned(pix_data); + + next_max <= + curr_max when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_max when unsigned(pix_data) <= curr_max else + unsigned(pix_data); + + next_sum <= + curr_sum when pix_valid = '0' else + unsigned((26 downto 14 => '0') & pix_data) when pix_sof = '1' else + curr_sum + unsigned((26 downto 14 => '0') & pix_data); + + -- This is the synchronous output logic + output_logic : process(clk, reset) + begin + if rising_edge(clk) then + stat_valid <= pix_eof; + end if; + end process; + + -- This is the combinatorial output logic + stat_min <= std_logic_vector(curr_min); + stat_max <= std_logic_vector(curr_max); + stat_sum <= std_logic_vector(curr_sum); + +end rtl; diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/level_adjuster.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/level_adjuster.vhd new file mode 100644 index 0000000..6b3053d --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/level_adjuster.vhd @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity level_adjuster is + port( + clk : in std_logic; + raw_pixel : in std_logic_vector(13 downto 0); + raw_max : in std_logic_vector(13 downto 0); + raw_min : in std_logic_vector(13 downto 0); + raw_sum : in std_logic_vector(26 downto 0); + adjusted_pixel : out std_logic_vector(13 downto 0)); +end level_adjuster; + +architecture rtl of level_adjuster is + component lpm_divider + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0)); + end component; + + -- Intermediate signals needed by the divider + signal numer : std_logic_vector(27 downto 0); + signal denom : std_logic_vector(13 downto 0); + signal quot : std_logic_vector(27 downto 0); + +begin + + -- Computation of the intermediate signals + numer <= std_logic_vector((13 downto 0 => '1') * (unsigned(raw_pixel) - unsigned(raw_min))); + denom <= std_logic_vector(unsigned(raw_max) - unsigned(raw_min)); + + -- We compute the remaineder of (x - min) / (max - min) + divider : lpm_divider port map( + clock => clk, + numer => numer, + denom => denom, + quotient => quot, + remain => open + ); + + -- And we only keep the LSB of the quotient (we know the MSB must be 0) + adjusted_pixel <= + (adjusted_pixel'range => '0') when denom = (denom'range => '0') else + quot(13 downto 0); + +end rtl; diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lpm_divider.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lpm_divider.vhd new file mode 100644 index 0000000..f8de4a6 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/lpm_divider.vhd @@ -0,0 +1,133 @@ +-- megafunction wizard: %LPM_DIVIDE% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_DIVIDE + +-- ============================================================ +-- File Name: lpm_divider.vhd +-- Megafunction Name(s): +-- LPM_DIVIDE +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library lpm; +use lpm.all; + +entity lpm_divider is + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); +end lpm_divider; + +architecture SYN of lpm_divider is + signal sub_wire0 : std_logic_vector(27 downto 0); + signal sub_wire1 : std_logic_vector(13 downto 0); + + component lpm_divide + generic( + lpm_drepresentation : string; + lpm_hint : string; + lpm_nrepresentation : string; + lpm_pipeline : natural; + lpm_type : string; + lpm_widthd : natural; + lpm_widthn : natural + ); + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); + end component; + +begin + quotient <= sub_wire0(27 downto 0); + remain <= sub_wire1(13 downto 0); + + LPM_DIVIDE_component : LPM_DIVIDE + generic map( + lpm_drepresentation => "UNSIGNED", + lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE", + lpm_nrepresentation => "UNSIGNED", + lpm_pipeline => 5, + lpm_type => "LPM_DIVIDE", + lpm_widthd => 14, + lpm_widthn => 28 + ) + port map( + clock => clock, + denom => denom, + numer => numer, + quotient => sub_wire0, + remain => sub_wire1 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" +-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1" +-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" +-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" +-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "14" +-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "28" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: denom 0 0 14 0 INPUT NODEFVAL "denom[13..0]" +-- Retrieval info: USED_PORT: numer 0 0 28 0 INPUT NODEFVAL "numer[27..0]" +-- Retrieval info: USED_PORT: quotient 0 0 28 0 OUTPUT NODEFVAL "quotient[27..0]" +-- Retrieval info: USED_PORT: remain 0 0 14 0 OUTPUT NODEFVAL "remain[13..0]" +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @denom 0 0 14 0 denom 0 0 14 0 +-- Retrieval info: CONNECT: @numer 0 0 28 0 numer 0 0 28 0 +-- Retrieval info: CONNECT: quotient 0 0 28 0 @quotient 0 0 28 0 +-- Retrieval info: CONNECT: remain 0 0 14 0 @remain 0 0 14 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/ram_writer.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/ram_writer.vhd new file mode 100644 index 0000000..8912cdb --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/ram_writer.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram_writer is + port( + clk, reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + ram_data : out std_logic_vector(15 downto 0); + ram_wren : out std_logic; + ram_wraddress : out std_logic_vector(12 downto 0)); + +end ram_writer; + +architecture rtl of ram_writer is + signal wraddress_counter : unsigned(ram_wraddress'range); +begin + p_address_gen : process(clk, reset) + begin + if reset = '1' then + wraddress_counter <= (others => '0'); + elsif rising_edge(clk) then + if pix_eof = '1' then + wraddress_counter <= (others => '0'); + elsif pix_valid = '1' then + wraddress_counter <= wraddress_counter + 1; + end if; + end if; + end process p_address_gen; + + ram_data <= "00" & pix_data; + ram_wren <= pix_valid; + ram_wraddress <= std_logic_vector(wraddress_counter); + +end rtl; diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/utils.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/utils.vhd new file mode 100644 index 0000000..83105ad --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/hdl/utils.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package utils is + function bitlength(number : positive) return positive; + +end package utils; + +package body utils is + + -- purpose: returns the minimum # of bits needed to represent the input number + function bitlength(number : positive) return positive is + variable acc : positive := 1; + variable i : natural := 0; + begin + while True loop + if acc > number then + return i; + end if; + + acc := acc * 2; + i := i + 1; + end loop; + end function bitlength; + +end package body utils; diff --git a/cs309-psoc/lab_2_0/hw/hdl/lepton/tb/lepton_tb.vhd b/cs309-psoc/lab_2_0/hw/hdl/lepton/tb/lepton_tb.vhd new file mode 100644 index 0000000..f134613 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/lepton/tb/lepton_tb.vhd @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity lepton_tb is +end lepton_tb; + +architecture tb of lepton_tb is + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal address : std_logic_vector(13 downto 0) := (others => '0'); + signal readdata : std_logic_vector(15 downto 0) := (others => '0'); + signal writedata : std_logic_vector(15 downto 0) := (others => '0'); + signal read : std_logic := '0'; + signal write : std_logic := '0'; + signal SCLK : std_logic := '0'; + signal CSn : std_logic := '0'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '1'; + + constant CLK_PERIOD : time := 20 ns; + + signal sim_ended : boolean := false; + +begin + dut : entity work.lepton + port map( + clk => clk, + reset => reset, + address => address, + readdata => readdata, + writedata => writedata, + read => read, + write => write, + SCLK => SCLK, + CSn => CSn, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_ended else '0'; + + miso_gen : process + variable seed1, seed2 : positive; + variable rand : real; + begin + if sim_ended then + wait; + else + uniform(seed1, seed2, rand); + wait until rising_edge(SCLK); + MISO <= to_unsigned(integer(rand), 1)(0); + + end if; + end process; + + stimuli : process + begin + reset <= '1'; + write <= '0'; + + wait for 2 * CLK_PERIOD; + reset <= '0'; + + wait for CLK_PERIOD; + write <= '1'; + writedata(0) <= '1'; + wait for CLK_PERIOD; + write <= '0'; + + wait for 17 ms; + sim_ended <= true; + wait; + end process; + +end tb; diff --git a/cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm.vhd b/cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm.vhd new file mode 100644 index 0000000..1b5cdc3 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm.vhd @@ -0,0 +1,42 @@ +-- ############################################################################# +-- pwm.vhd +-- ======= +-- PWM memory-mapped Avalon slave interface. +-- +-- Author : () +-- Author : () +-- Revision : +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity pwm is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + write : in std_logic; + readdata : out std_logic_vector(31 downto 0); + writedata : in std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + pwm_out : out std_logic + ); +end pwm; + +architecture rtl of pwm is + +begin + +end architecture rtl; diff --git a/cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm_constants.vhd b/cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm_constants.vhd new file mode 100644 index 0000000..bfff03b --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm_constants.vhd @@ -0,0 +1,61 @@ +-- ############################################################################# +-- pwm_constants.vhd +-- ================= +-- This package contains constants used in the PWM design files. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pwm_constants is + -- Register map + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | RegNo | Name | Access | Description | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW period to apply to the | + -- | | | | next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT period of the | + -- | | | | ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to | + -- | | | | the next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT duty cycle of | + -- | | | | the ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.| + -- | | | | Writing 1 to this register starts the PWM. | + -- | | | | | + -- | | | | >> Reading this register always returns 0. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00"; + constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01"; + constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10"; + + -- Default values of registers after reset (BEFORE writing START to the CTRL + -- register with a new configuration) + constant DEFAULT_PERIOD : natural := 4; + constant DEFAULT_DUTY_CYCLE : natural := 2; +end package pwm_constants; + +package body pwm_constants is + +end package body pwm_constants; diff --git a/cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm_hw.tcl b/cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm_hw.tcl new file mode 100644 index 0000000..df7d92a --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/pantilt/hdl/pwm_hw.tcl @@ -0,0 +1,135 @@ +# TCL File Generated by Component Editor 16.0 +# Tue Feb 28 12:18:00 CET 2017 +# DO NOT MODIFY + + +# +# pwm "pwm" v1.0 +# 2017.02.28.12:18:00 +# Pan-tilt +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module pwm +# +set_module_property DESCRIPTION Pan-tilt +set_module_property NAME pwm +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Pan-tilt +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME pwm +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE +add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +add_interface_port avalon_slave_0 writedata writedata Input 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end pwm_out pwm Output 1 diff --git a/cs309-psoc/lab_2_0/hw/hdl/pantilt/tb/tb_pwm.vhd b/cs309-psoc/lab_2_0/hw/hdl/pantilt/tb/tb_pwm.vhd new file mode 100644 index 0000000..ff2dee7 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/hdl/pantilt/tb/tb_pwm.vhd @@ -0,0 +1,205 @@ +-- ############################################################################# +-- tb_pwm.vhd +-- ========== +-- Testbench for PWM memory-mapped Avalon slave interface. +-- +-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity tb_pwm is +end entity; + +architecture rtl of tb_pwm is + + -- 50 MHz clock + constant CLK_PERIOD : time := 20 ns; + + -- Signal used to end simulator when we finished submitting our test cases + signal sim_finished : boolean := false; + + -- PWM PORTS + signal clk : std_logic; + signal reset : std_logic; + signal address : std_logic_vector(1 downto 0); + signal read : std_logic; + signal write : std_logic; + signal readdata : std_logic_vector(31 downto 0); + signal writedata : std_logic_vector(31 downto 0); + signal pwm_out : std_logic; + + -- Values of registers we are going to use to configure the PWM unit + constant CONFIG_PERIOD : natural := 100; + constant CONFIG_DUTY_CYCLE : natural := 20; + constant CONFIG_CTRL_START : natural := 1; + constant CONFIG_CTRL_STOP : natural := 0; + +begin + + -- Instantiate DUT + dut : entity work.pwm + port map( + clk => clk, + reset => reset, + address => address, + read => read, + write => write, + readdata => readdata, + writedata => writedata, + pwm_out => pwm_out + ); + + -- Generate clk signal + clk_generation : process + begin + if not sim_finished then + clk <= '1'; + wait for CLK_PERIOD / 2; + clk <= '0'; + wait for CLK_PERIOD / 2; + else + wait; + end if; + end process clk_generation; + + -- Test PWM + simulation : process + + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + + reset <= '1'; + wait for CLK_PERIOD / 2; + + reset <= '0'; + wait for CLK_PERIOD / 4; + end procedure async_reset; + + procedure write_register(constant ofst : in std_logic_vector(1 downto 0); + constant val : in natural) is + begin + wait until rising_edge(clk); + + address <= ofst; + write <= '1'; + writedata <= std_logic_vector(to_unsigned(val, writedata'length)); + wait until rising_edge(clk); + + address <= (others => '0'); + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + end procedure write_register; + + procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is + begin + wait until rising_edge(clk); + + address <= ofst; + read <= '1'; + -- The read has a 1 cycle wait-state, so we need to keep the read + -- signal high for 2 clock cycles. + wait until rising_edge(clk); + wait until rising_edge(clk); + + address <= (others => '0'); + read <= '0'; + wait until rising_edge(clk); + end procedure read_register; + + procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0); + constant expected_val : in natural) is + begin + read_register(ofst); + + case ofst is + when REG_PERIOD_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected PERIOD: " & + "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "PERIOD_expected = " & integer'image(expected_val) + severity error; + + when REG_DUTY_CYCLE_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected DUTY_CYCLE: " & + "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "DUTY_CYCLE_expected = " & integer'image(expected_val) + severity error; + + when REG_CTRL_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected CTRL: " & + "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "CTRL_expected = " & integer'image(expected_val) + severity error; + + when others => + null; + end case; + end procedure read_register_check; + + begin + + -- Default values + reset <= '0'; + address <= (others => '0'); + read <= '0'; + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + + -- Reset the circuit + async_reset; + + -- Write desired configuration to PWM Avalon-MM slave. + write_register(REG_PERIOD_OFST, CONFIG_PERIOD); + write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + + -- Read back configuration from PWM Avalon-MM slave. Note that we have + -- not started the PWM unit yet, so the new configuration must not be + -- read back at this point (as per the register map). + read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Start PWM + write_register(REG_CTRL_OFST, CONFIG_CTRL_START); + + -- Wait until PWM pulses for the first time after we sent START. + wait until rising_edge(pwm_out); + + -- Read back configuration from PWM Avalon-MM slave. Now that we have + -- started the PWM unit, we should be able to read back the + -- configuration we wrote (as per the register map). + read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Wait for 2 PWM periods to finish + wait for 2 * CLK_PERIOD * CONFIG_PERIOD; + + -- Stop PWM. + write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP); + + -- Wait for PWM period to finish + wait for 1 * CLK_PERIOD * CONFIG_PERIOD; + + -- Instruct "clk_generation" process to halt execution. + sim_finished <= true; + + -- Make this process wait indefinitely (it will never re-execute from + -- its beginning again). + wait; + end process simulation; +end architecture rtl; + diff --git a/cs309-psoc/lab_2_0/hw/quartus/ip/components.ipx b/cs309-psoc/lab_2_0/hw/quartus/ip/components.ipx new file mode 100644 index 0000000..7536257 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/quartus/ip/components.ipx @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_2_0/hw/quartus/lab_2_0.qpf b/cs309-psoc/lab_2_0/hw/quartus/lab_2_0.qpf new file mode 100644 index 0000000..e649e8e --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/quartus/lab_2_0.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition +# Date created = 11:03:02 February 05, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.1" +DATE = "11:03:02 February 05, 2016" + +# Revisions + +PROJECT_REVISION = "lab_2_0" diff --git a/cs309-psoc/lab_2_0/hw/quartus/lab_2_0.qsf b/cs309-psoc/lab_2_0/hw/quartus/lab_2_0.qsf new file mode 100644 index 0000000..c8c28b4 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/quartus/lab_2_0.qsf @@ -0,0 +1,812 @@ +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 + +set_global_assignment -name SMART_RECOMPILE OFF +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level + +set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +set_global_assignment -name QSYS_FILE soc_system.qsys +set_global_assignment -name SDC_FILE lab_2_0.sdc + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA4U23C6 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO Extention OV7670 CAMERA +#============================================================ +set_location_assignment PIN_AE15 -to CAM_D[0] +set_location_assignment PIN_AE15 -to CAM_D_0 +set_location_assignment PIN_AF17 -to CAM_D[1] +set_location_assignment PIN_AF17 -to CAM_D_1 +set_location_assignment PIN_AH8 -to CAM_D[2] +set_location_assignment PIN_AH8 -to CAM_D_2 +set_location_assignment PIN_AG8 -to CAM_D[3] +set_location_assignment PIN_AG8 -to CAM_D_3 +set_location_assignment PIN_U13 -to CAM_D[4] +set_location_assignment PIN_U13 -to CAM_D_4 +set_location_assignment PIN_U14 -to CAM_D[5] +set_location_assignment PIN_U14 -to CAM_D_5 +set_location_assignment PIN_AG9 -to CAM_D[6] +set_location_assignment PIN_AG9 -to CAM_D_6 +set_location_assignment PIN_AG10 -to CAM_D[7] +set_location_assignment PIN_AG10 -to CAM_D_7 +set_location_assignment PIN_AF13 -to CAM_D[8] +set_location_assignment PIN_AF13 -to CAM_D_8 +set_location_assignment PIN_AG13 -to CAM_D[9] +set_location_assignment PIN_AG13 -to CAM_D_9 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9 + +#============================================================ +# Arduino Extension LEPTON CAMERA THERMAL CAM_TH +#============================================================ +set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N +set_location_assignment PIN_AG16 -to CAM_TH_MOSI +set_location_assignment PIN_AH11 -to CAM_TH_MISO +set_location_assignment PIN_AH12 -to CAM_TH_CLK +set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA +set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL + +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#============================================================ +# HPS +#============================================================ +set_location_assignment PIN_C6 -to HPS_CONV_USB_N +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0] +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0 +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1] +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1 +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2] +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2 +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3] +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3 +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4] +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4 +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5] +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5 +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6] +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6 +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7] +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7 +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8] +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8 +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9] +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9 +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10] +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10 +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11] +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11 +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12] +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12 +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13] +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13 +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14] +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14 +set_location_assignment PIN_A27 -to HPS_DDR3_BA[0] +set_location_assignment PIN_A27 -to HPS_DDR3_BA_0 +set_location_assignment PIN_H25 -to HPS_DDR3_BA[1] +set_location_assignment PIN_H25 -to HPS_DDR3_BA_1 +set_location_assignment PIN_G25 -to HPS_DDR3_BA[2] +set_location_assignment PIN_G25 -to HPS_DDR3_BA_2 +set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N +set_location_assignment PIN_L28 -to HPS_DDR3_CKE +set_location_assignment PIN_N20 -to HPS_DDR3_CK_N +set_location_assignment PIN_N21 -to HPS_DDR3_CK_P +set_location_assignment PIN_L21 -to HPS_DDR3_CS_N +set_location_assignment PIN_G28 -to HPS_DDR3_DM[0] +set_location_assignment PIN_G28 -to HPS_DDR3_DM_0 +set_location_assignment PIN_P28 -to HPS_DDR3_DM[1] +set_location_assignment PIN_P28 -to HPS_DDR3_DM_1 +set_location_assignment PIN_W28 -to HPS_DDR3_DM[2] +set_location_assignment PIN_W28 -to HPS_DDR3_DM_2 +set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3] +set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3 +set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0] +set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0 +set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1] +set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1 +set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2] +set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2 +set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3] +set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3 +set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4] +set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4 +set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5] +set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5 +set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6] +set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6 +set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7] +set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7 +set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8] +set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8 +set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9] +set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9 +set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10] +set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10 +set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11] +set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11 +set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12] +set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12 +set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13] +set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13 +set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14] +set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14 +set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15] +set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15 +set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16] +set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16 +set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17] +set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17 +set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18] +set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18 +set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19] +set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19 +set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20] +set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20 +set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21] +set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21 +set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22] +set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22 +set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23] +set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23 +set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24] +set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24 +set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25] +set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25 +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26] +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26 +set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27] +set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27 +set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28] +set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28 +set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29] +set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29 +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30] +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30 +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31] +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31 +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0] +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0 +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1] +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1 +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2] +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2 +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3] +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3 +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0] +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0 +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1] +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1 +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2] +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2 +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3] +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3 +set_location_assignment PIN_D28 -to HPS_DDR3_ODT +set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N +set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N +set_location_assignment PIN_D25 -to HPS_DDR3_RZQ +set_location_assignment PIN_E25 -to HPS_DDR3_WE_N +set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK +set_location_assignment PIN_B14 -to HPS_ENET_INT_N +set_location_assignment PIN_A13 -to HPS_ENET_MDC +set_location_assignment PIN_E16 -to HPS_ENET_MDIO +set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0] +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0 +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1] +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1 +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2] +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2 +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3] +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3 +set_location_assignment PIN_J13 -to HPS_ENET_RX_DV +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0] +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0 +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1] +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1 +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2] +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2 +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3] +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3 +set_location_assignment PIN_A12 -to HPS_ENET_TX_EN +set_location_assignment PIN_A17 -to HPS_GSENSOR_INT +set_location_assignment PIN_C18 -to HPS_I2C0_SCLK +set_location_assignment PIN_A19 -to HPS_I2C0_SDAT +set_location_assignment PIN_K18 -to HPS_I2C1_SCLK +set_location_assignment PIN_A21 -to HPS_I2C1_SDAT +set_location_assignment PIN_J18 -to HPS_KEY_N +set_location_assignment PIN_A20 -to HPS_LED +set_location_assignment PIN_H13 -to HPS_LTC_GPIO +set_location_assignment PIN_B8 -to HPS_SD_CLK +set_location_assignment PIN_D14 -to HPS_SD_CMD +set_location_assignment PIN_C13 -to HPS_SD_DATA[0] +set_location_assignment PIN_C13 -to HPS_SD_DATA_0 +set_location_assignment PIN_B6 -to HPS_SD_DATA[1] +set_location_assignment PIN_B6 -to HPS_SD_DATA_1 +set_location_assignment PIN_B11 -to HPS_SD_DATA[2] +set_location_assignment PIN_B11 -to HPS_SD_DATA_2 +set_location_assignment PIN_B9 -to HPS_SD_DATA[3] +set_location_assignment PIN_B9 -to HPS_SD_DATA_3 +set_location_assignment PIN_C19 -to HPS_SPIM_CLK +set_location_assignment PIN_B19 -to HPS_SPIM_MISO +set_location_assignment PIN_B16 -to HPS_SPIM_MOSI +set_location_assignment PIN_C16 -to HPS_SPIM_SS +set_location_assignment PIN_A22 -to HPS_UART_RX +set_location_assignment PIN_B21 -to HPS_UART_TX +set_location_assignment PIN_G4 -to HPS_USB_CLKOUT +set_location_assignment PIN_C10 -to HPS_USB_DATA[0] +set_location_assignment PIN_C10 -to HPS_USB_DATA_0 +set_location_assignment PIN_F5 -to HPS_USB_DATA[1] +set_location_assignment PIN_F5 -to HPS_USB_DATA_1 +set_location_assignment PIN_C9 -to HPS_USB_DATA[2] +set_location_assignment PIN_C9 -to HPS_USB_DATA_2 +set_location_assignment PIN_C4 -to HPS_USB_DATA[3] +set_location_assignment PIN_C4 -to HPS_USB_DATA_3 +set_location_assignment PIN_C8 -to HPS_USB_DATA[4] +set_location_assignment PIN_C8 -to HPS_USB_DATA_4 +set_location_assignment PIN_D4 -to HPS_USB_DATA[5] +set_location_assignment PIN_D4 -to HPS_USB_DATA_5 +set_location_assignment PIN_C7 -to HPS_USB_DATA[6] +set_location_assignment PIN_C7 -to HPS_USB_DATA_6 +set_location_assignment PIN_F4 -to HPS_USB_DATA[7] +set_location_assignment PIN_F4 -to HPS_USB_DATA_7 +set_location_assignment PIN_E5 -to HPS_USB_DIR +set_location_assignment PIN_D5 -to HPS_USB_NXT +set_location_assignment PIN_C5 -to HPS_USB_STP + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY_N +#============================================================ +set_location_assignment PIN_AH17 -to KEY_N[0] +set_location_assignment PIN_AH17 -to KEY_N_0 +set_location_assignment PIN_AH16 -to KEY_N[1] +set_location_assignment PIN_AH16 -to KEY_N_1 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_W15 -to LED_0 +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_AA24 -to LED_1 +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V16 -to LED_2 +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_V15 -to LED_3 +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AF26 -to LED_4 +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_AE26 -to LED_5 +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_Y16 -to LED_6 +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_AA23 -to LED_7 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7 + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_L10 -to SW[0] +set_location_assignment PIN_L10 -to SW_0 +set_location_assignment PIN_L9 -to SW[1] +set_location_assignment PIN_L9 -to SW_1 +set_location_assignment PIN_H6 -to SW[2] +set_location_assignment PIN_H6 -to SW_2 +set_location_assignment PIN_H5 -to SW[3] +set_location_assignment PIN_H5 -to SW_3 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3 + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_V12 -to PIO_INT_N +set_location_assignment PIN_AE11 -to PIO_SCL +set_location_assignment PIN_AE12 -to PIO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA + +set_location_assignment PIN_AF7 -to PIR_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT + +set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA +set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL +set_location_assignment PIN_T11 -to CAM_SYS_CLK +set_location_assignment PIN_AG6 -to CAM_LV +set_location_assignment PIN_AH2 -to CAM_PIX_CLK +set_location_assignment PIN_AE4 -to CAM_FV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV + +set_location_assignment PIN_Y8 -to PAL_VD_HSO +set_location_assignment PIN_AB4 -to PAL_VD_VSO +set_location_assignment PIN_AG5 -to PAL_VD_VD[0] +set_location_assignment PIN_AG5 -to PAL_VD_VD_0 +set_location_assignment PIN_AH5 -to PAL_VD_VD[1] +set_location_assignment PIN_AH5 -to PAL_VD_VD_1 +set_location_assignment PIN_AH6 -to PAL_VD_VD[2] +set_location_assignment PIN_AH6 -to PAL_VD_VD_2 +set_location_assignment PIN_T8 -to PAL_VD_VD[3] +set_location_assignment PIN_T8 -to PAL_VD_VD_3 +set_location_assignment PIN_T12 -to PAL_VD_VD[4] +set_location_assignment PIN_T12 -to PAL_VD_VD_4 +set_location_assignment PIN_Y5 -to PAL_VD_VD[5] +set_location_assignment PIN_Y5 -to PAL_VD_VD_5 +set_location_assignment PIN_Y4 -to PAL_VD_VD[6] +set_location_assignment PIN_Y4 -to PAL_VD_VD_6 +set_location_assignment PIN_W8 -to PAL_VD_VD[7] +set_location_assignment PIN_W8 -to PAL_VD_VD_7 +set_location_assignment PIN_AH4 -to PAL_VD_CLKO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO + +set_location_assignment PIN_AH3 -to SERVO_0 +set_location_assignment PIN_AF4 -to SERVO_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1 + +set_location_assignment PIN_AD12 -to J0_SPI_CLK +set_location_assignment PIN_AD11 -to J0_SPI_MISO +set_location_assignment PIN_AF9 -to J0_SPI_CS_N +set_location_assignment PIN_AD10 -to J0_SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI + +set_location_assignment PIN_AF5 -to FROM_ESP_TXD +set_location_assignment PIN_T13 -to TO_ESP_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD + +set_location_assignment PIN_AE7 -to SPI_MISO +set_location_assignment PIN_AF6 -to SPI_ENA_N +set_location_assignment PIN_AE8 -to SPI_CLK +set_location_assignment PIN_AE9 -to SPI_MOSI +set_location_assignment PIN_AF10 -to SPI_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT + +set_location_assignment PIN_AF11 -to LED_BGR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_AA15 -to RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N + +set_location_assignment PIN_AG28 -to TS_SCL +set_location_assignment PIN_AH27 -to TS_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA + +set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N +set_location_assignment PIN_AG26 -to LCD_DE +set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN + +set_location_assignment PIN_AH24 -to BLT_TXD +set_location_assignment PIN_AE22 -to BLT_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD + +set_location_assignment PIN_AG20 -to BOARD_ID +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID + +set_location_assignment PIN_AF21 -to VIDEO_HSYNC +set_location_assignment PIN_AG19 -to VIDEO_VSYNC +set_location_assignment PIN_AF20 -to VIDEO_CLK +set_location_assignment PIN_AG23 -to VIDEO_B[0] +set_location_assignment PIN_AG23 -to VIDEO_B_0 +set_location_assignment PIN_AH23 -to VIDEO_B[1] +set_location_assignment PIN_AH23 -to VIDEO_B_1 +set_location_assignment PIN_AF25 -to VIDEO_B[2] +set_location_assignment PIN_AF25 -to VIDEO_B_2 +set_location_assignment PIN_AG24 -to VIDEO_B[3] +set_location_assignment PIN_AG24 -to VIDEO_B_3 +set_location_assignment PIN_AA19 -to VIDEO_B[4] +set_location_assignment PIN_AA19 -to VIDEO_B_4 +set_location_assignment PIN_AH26 -to VIDEO_B[5] +set_location_assignment PIN_AH26 -to VIDEO_B_5 +set_location_assignment PIN_AG18 -to VIDEO_B[6] +set_location_assignment PIN_AG18 -to VIDEO_B_6 +set_location_assignment PIN_AC23 -to VIDEO_B[7] +set_location_assignment PIN_AC23 -to VIDEO_B_7 +set_location_assignment PIN_AH22 -to VIDEO_G[0] +set_location_assignment PIN_AH22 -to VIDEO_G_0 +set_location_assignment PIN_AF22 -to VIDEO_G[1] +set_location_assignment PIN_AF22 -to VIDEO_G_1 +set_location_assignment PIN_AD20 -to VIDEO_G[2] +set_location_assignment PIN_AD20 -to VIDEO_G_2 +set_location_assignment PIN_AE24 -to VIDEO_G[3] +set_location_assignment PIN_AE24 -to VIDEO_G_3 +set_location_assignment PIN_AE20 -to VIDEO_G[4] +set_location_assignment PIN_AE20 -to VIDEO_G_4 +set_location_assignment PIN_AD19 -to VIDEO_G[5] +set_location_assignment PIN_AD19 -to VIDEO_G_5 +set_location_assignment PIN_AF18 -to VIDEO_G[6] +set_location_assignment PIN_AF18 -to VIDEO_G_6 +set_location_assignment PIN_AE19 -to VIDEO_G[7] +set_location_assignment PIN_AE19 -to VIDEO_G_7 +set_location_assignment PIN_AC22 -to VIDEO_R[0] +set_location_assignment PIN_AC22 -to VIDEO_R_0 +set_location_assignment PIN_AA18 -to VIDEO_R[1] +set_location_assignment PIN_AA18 -to VIDEO_R_1 +set_location_assignment PIN_AE23 -to VIDEO_R[2] +set_location_assignment PIN_AE23 -to VIDEO_R_2 +set_location_assignment PIN_AD23 -to VIDEO_R[3] +set_location_assignment PIN_AD23 -to VIDEO_R_3 +set_location_assignment PIN_AH18 -to VIDEO_R[4] +set_location_assignment PIN_AH18 -to VIDEO_R_4 +set_location_assignment PIN_AG21 -to VIDEO_R[5] +set_location_assignment PIN_AG21 -to VIDEO_R_5 +set_location_assignment PIN_AH21 -to VIDEO_R[6] +set_location_assignment PIN_AH21 -to VIDEO_R_6 +set_location_assignment PIN_AH19 -to VIDEO_R[7] +set_location_assignment PIN_AH19 -to VIDEO_R_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7 diff --git a/cs309-psoc/lab_2_0/hw/quartus/lab_2_0.sdc b/cs309-psoc/lab_2_0/hw/quartus/lab_2_0.sdc new file mode 100644 index 0000000..16a41f3 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/quartus/lab_2_0.sdc @@ -0,0 +1,6 @@ +create_clock -period 20 [get_ports FPGA_CLK1_50] +create_clock -period 20 [get_ports FPGA_CLK2_50] +create_clock -period 20 [get_ports FPGA_CLK3_50] + +derive_pll_clocks +derive_clock_uncertainty diff --git a/cs309-psoc/lab_2_0/hw/quartus/soc_system.qsys b/cs309-psoc/lab_2_0/hw/quartus/soc_system.qsys new file mode 100644 index 0000000..a9780c8 --- /dev/null +++ b/cs309-psoc/lab_2_0/hw/quartus/soc_system.qsys @@ -0,0 +1,681 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + NO_INTERACTIVE_WINDOWS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_onchip_memory2_0 + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_2_0/lab_2_0.pdf b/cs309-psoc/lab_2_0/lab_2_0.pdf new file mode 100644 index 0000000..4290ed2 Binary files /dev/null and b/cs309-psoc/lab_2_0/lab_2_0.pdf differ diff --git a/cs309-psoc/lab_2_0/sw/nios/application/app.c b/cs309-psoc/lab_2_0/sw/nios/application/app.c new file mode 100644 index 0000000..d405f7f --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/app.c @@ -0,0 +1,33 @@ +#include +#include +#include +#include + +#include "lepton/lepton.h" +#include "system.h" + +int main(void) { + // Hardware control structures + lepton_dev lepton = lepton_inst((void *) LEPTON_0_BASE); + + // Initialize hardware + lepton_init(&lepton); + + // ========================================================================= + // TODO : use the lepton library to capture an image. + // + // Fill me! + + do{ + lepton_start_capture(&lepton); + lepton_wait_until_eof(&lepton); + }while(lepton_error_check(&lepton)); + + // + // ========================================================================= + + // Save the adjusted (rescaled) buffer to a file. + lepton_save_capture(&lepton, true, "/mnt/host/output.pgm"); + + return EXIT_SUCCESS; +} diff --git a/cs309-psoc/lab_2_0/sw/nios/application/joysticks/joysticks.c b/cs309-psoc/lab_2_0/sw/nios/application/joysticks/joysticks.c new file mode 100644 index 0000000..d4742e3 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/joysticks/joysticks.c @@ -0,0 +1,79 @@ +#include "joysticks.h" + +#define JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL (0) +#define JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL (1) +#define JOYSTICK_LEFT_VRY_MCP3204_CHANNEL (2) +#define JOYSTICK_LEFT_VRX_MCP3204_CHANNEL (3) + +/** + * joysticks_inst + * + * Instantiate a joysticks device structure. + * + * @param base Base address of the MCP3204 component connected to the joysticks. + */ +joysticks_dev joysticks_inst(void *mcp3204_base) { + joysticks_dev dev; + dev.mcp3204 = mcp3204_inst((void *) mcp3204_base); + + return dev; +} + +/** + * joysticks_init + * + * Initializes the joysticks device. + * + * @param dev joysticks device structure. + */ +void joysticks_init(joysticks_dev *dev) { + mcp3204_init(&(dev->mcp3204)); +} + +/** + * joysticks_read_left_vertical + * + * Returns the vertical position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,LV_CHANNEL); +} + +/** + * joysticks_read_left_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204,LH_CHANNEL); +} + +/** + * joysticks_read_right_vertical + * + * Returns the vertical position of the right joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,RV_CHANNEL); +} + +/** + * joysticks_read_right_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204,RH_CHANNEL); +} diff --git a/cs309-psoc/lab_2_0/sw/nios/application/joysticks/joysticks.h b/cs309-psoc/lab_2_0/sw/nios/application/joysticks/joysticks.h new file mode 100644 index 0000000..b43c174 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/joysticks/joysticks.h @@ -0,0 +1,33 @@ +#ifndef __JOYSTICKS_H__ +#define __JOYSTICKS_H__ + +#include "mcp3204/mcp3204.h" + +/* joysticks device structure */ +typedef struct joysticks_dev { + mcp3204_dev mcp3204; /* MCP3204 device handle */ +} joysticks_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define JOYSTICKS_MIN_VALUE (MCP3204_MIN_VALUE) +#define JOYSTICKS_MAX_VALUE (MCP3204_MAX_VALUE) + +#define LV_CHANNEL 0 +#define LH_CHANNEL 1 +#define RV_CHANNEL 2 +#define RH_CHANNEL 3 +#define CC_CHANNEL "this is a joke" + +joysticks_dev joysticks_inst(void *mcp3204_base); + +void joysticks_init(joysticks_dev *dev); + +uint32_t joysticks_read_left_vertical(joysticks_dev *dev); +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev); +uint32_t joysticks_read_right_vertical(joysticks_dev *dev); +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev); + +#endif /* __JOYSTICKS_H__ */ diff --git a/cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204.c b/cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204.c new file mode 100644 index 0000000..a827962 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204.c @@ -0,0 +1,50 @@ +#include +#include + +#include "mcp3204.h" +#include "mcp3204_regs.h" + +#define MCP3204_NUM_CHANNELS (4) + +/** + * mcp3204_inst + * + * Instantiate a mcp3204 device structure. + * + * @param base Base address of the component. + */ +mcp3204_dev mcp3204_inst(void *base) { + mcp3204_dev dev; + dev.base = base; + + return dev; +} + +/** + * mcp3204_init + * + * Initializes the mcp3204 device. + * + * @param dev mcp3204 device structure. + */ +void mcp3204_init(mcp3204_dev *dev) { + return; +} + +/** + * mcp3204_read + * + * Reads the register corresponding to the supplied channel parameter. + * + * @param dev mcp3204 device structure. + * @param channel channel to be read + */ +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) { + switch(channel){ + case 0: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_0_OFST); + case 1: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_1_OFST); + case 2: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_2_OFST); + case 3: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_3_OFST); + default: return 0; + } +} diff --git a/cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204.h b/cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204.h new file mode 100644 index 0000000..3b2b2e6 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204.h @@ -0,0 +1,23 @@ +#ifndef __MCP3204_H__ +#define __MCP3204_H__ + +#include + +/* mcp3204 device structure */ +typedef struct mcp3204_dev { + void *base; /* Base address of component */ +} mcp3204_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define MCP3204_MIN_VALUE (0) +#define MCP3204_MAX_VALUE (4095) + +mcp3204_dev mcp3204_inst(void *base); + +void mcp3204_init(mcp3204_dev *dev); +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel); + +#endif /* __MCP3204_H__ */ diff --git a/cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h b/cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h new file mode 100644 index 0000000..b1c78cd --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h @@ -0,0 +1,9 @@ +#ifndef __MCP3204_REGS_H__ +#define __MCP3204_REGS_H__ + +#define MCP3204_CHANNEL_0_OFST (0 * 4) /* RO */ +#define MCP3204_CHANNEL_1_OFST (1 * 4) /* RO */ +#define MCP3204_CHANNEL_2_OFST (2 * 4) /* RO */ +#define MCP3204_CHANNEL_3_OFST (3 * 4) /* RO */ + +#endif /* __MCP3204_REGS_H__ */ diff --git a/cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton.c b/cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton.c new file mode 100644 index 0000000..af49d25 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton.c @@ -0,0 +1,118 @@ +#include +#include +#include +#include +#include + +#include "lepton_regs.h" +#include "lepton.h" + +/** + * lepton_inst + * + * Instantiate a lepton device structure. + * + * @param base Base address of the component. + */ +lepton_dev lepton_inst(void *base) { + lepton_dev dev; + dev.base = base; + + return dev; +} + +/** + * lepton_init + * + * Initializes the lepton device. + * + * @param dev lepton device structure. + */ +void lepton_init(lepton_dev *dev) { + return; +} + +/** + * lepton_start_capture + * + * Instructs the device to start the frame capture process. + * + * @param dev lepton device structure. + */ +void lepton_start_capture(lepton_dev *dev) { + IOWR_16DIRECT(dev->base, LEPTON_REGS_COMMAND_OFST, 0x1); +} + +/** + * lepton_error_check + * + * @abstract Check for errors at the device level. + * @param dev lepton device structure. + * @return true if there was an error, and false otherwise. + */ +bool lepton_error_check(lepton_dev *dev) { + return (IORD_16DIRECT(dev->base, LEPTON_REGS_STATUS_OFST) & 0x2) != 0; +} + +/** + * lepton_wait_until_eof + * + * Waits until the frame being captured has been fully received and saved in the + * internal memory. + * + * @param dev lepton device structure. + */ +void lepton_wait_until_eof(lepton_dev *dev) { + while(IORD_16DIRECT(dev->base, LEPTON_REGS_STATUS_OFST) & 0x1); +} + +/** + * lepton_save_capture + * + * Saves the captured frame on the host filesystem under the supplied filename. + * The frame will be saved in PGM format. + * + * @param dev lepton device structure. + * @param adjusted Setting this parameter to false will cause RAW sensor data to + * be written to the file. + * Setting this parameter to true will cause a preprocessed image + * (with a stretched dynamic range) to be saved to the file. + * + * @param fname the output file name. + */ +void lepton_save_capture(lepton_dev *dev, bool adjusted, const char *fname) { + FILE *fp = fopen(fname, "w"); + assert(fp); + + const uint8_t num_rows = 60; + const uint8_t num_cols = 80; + + uint16_t offset = LEPTON_REGS_RAW_BUFFER_OFST; + uint16_t max_value = IORD_16DIRECT(dev->base, LEPTON_REGS_MAX_OFST); + if (adjusted) { + offset = LEPTON_REGS_ADJUSTED_BUFFER_OFST; + max_value = 0x3fff; + } + + /* Write PGM header */ + fprintf(fp, "P2\n%" PRIu8 " %" PRIu8 "\n%" PRIu16, num_cols, num_rows, max_value); + + /* Write body */ + uint8_t row = 0; + for (row = 0; row < num_rows; ++row) { + fprintf(fp, "\n"); + + uint8_t col = 0; + for (col = 0; col < num_cols; ++col) { + if (col > 0) { + fprintf(fp, " "); + } + + uint16_t current_ofst = offset + (row * num_cols + col) * sizeof(uint16_t); + uint16_t pix_value = IORD_16DIRECT(dev->base, current_ofst); + fprintf(fp, "%" PRIu16, pix_value); + } + } + + assert(!fclose(fp)); +} diff --git a/cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton.h b/cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton.h new file mode 100644 index 0000000..cf197d2 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton.h @@ -0,0 +1,23 @@ +#ifndef __LEPTON_H__ +#define __LEPTON_H__ + +#include + +/* lepton device structure */ +typedef struct { + void *base; /* Base address of the component */ +} lepton_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +lepton_dev lepton_inst(void *base); + +void lepton_init(lepton_dev *dev); +void lepton_start_capture(lepton_dev *dev); +void lepton_wait_until_eof(lepton_dev *dev); +bool lepton_error_check(lepton_dev *dev); +void lepton_save_capture(lepton_dev *dev, bool adjusted, const char *fname); + +#endif /* __LEPTON_H__ */ diff --git a/cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton_regs.h b/cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton_regs.h new file mode 100644 index 0000000..db24244 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/lepton/lepton_regs.h @@ -0,0 +1,25 @@ +#ifndef __LEPTON_REGS_H__ +#define __LEPTON_REGS_H__ + +/* Register offsets */ +#define LEPTON_REGS_COMMAND_OFST ( 0 * 2) /* WO */ +#define LEPTON_REGS_STATUS_OFST ( 1 * 2) /* RO */ +#define LEPTON_REGS_MIN_OFST ( 2 * 2) /* RO */ +#define LEPTON_REGS_MAX_OFST ( 3 * 2) /* RO */ +#define LEPTON_REGS_SUM_LSB_OFST ( 4 * 2) /* RO */ +#define LEPTON_REGS_SUM_MSB_OFST ( 5 * 2) /* RO */ +#define LEPTON_REGS_ROW_IDX_OFST ( 6 * 2) /* RO */ +#define LEPTON_REGS_RAW_BUFFER_OFST ( 8 * 2) /* RO */ +#define LEPTON_REGS_ADJUSTED_BUFFER_OFST (8192 * 2) /* RO */ + +/* Command register */ +#define LEPTON_COMMAND_START (0x0001) + +/* Status register */ +#define LEPTON_STATUS_CAPTURE_IN_PROGRESS_MASK (1 << 0) +#define LEPTON_STATUS_ERROR_MASK (1 << 1) + +#define LEPTON_REGS_BUFFER_NUM_PIXELS (80 * 60) +#define LEPTON_REGS_BUFFER_BYTELENGTH (LEPTON_REGS_BUFFER_NUM_PIXELS * 2) + +#endif /* __LEPTON_REGS_H__ */ diff --git a/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pantilt.c b/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pantilt.c new file mode 100644 index 0000000..d9c4c72 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pantilt.c @@ -0,0 +1,109 @@ +#include "pantilt.h" + +/** + * pantilt_inst + * + * Instantiate a pantilt device structure. + * + * @param pwm_v_base Base address of the vertical PWM component. + * @param pwm_h_base Base address of the horizontal PWM component. + */ +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) { + pantilt_dev dev; + dev.pwm_v = pwm_inst(pwm_v_base); + dev.pwm_h = pwm_inst(pwm_h_base); + + return dev; +} + +/** + * pantilt_init + * + * Initializes the pantilt device. + * + * @param dev pantilt device structure. + */ +void pantilt_init(pantilt_dev *dev) { + pwm_init(&(dev->pwm_v)); + pwm_init(&(dev->pwm_h)); +} + +/** + * pantilt_configure_vertical + * + * Configure the vertical PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_v), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_configure_horizontal + * + * Configure the horizontal PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_h), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_start_vertical + * + * Starts the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_vertical(pantilt_dev *dev) { + pwm_start(&(dev->pwm_v)); +} + +/** + * pantilt_start_horizontal + * + * Starts the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_horizontal(pantilt_dev *dev) { + pwm_start(&(dev->pwm_h)); +} + +/** + * pantilt_stop_vertical + * + * Stops the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_vertical(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_v)); +} + +/** + * pantilt_stop_horizontal + * + * Stops the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_horizontal(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_h)); +} diff --git a/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pantilt.h b/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pantilt.h new file mode 100644 index 0000000..1f17500 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pantilt.h @@ -0,0 +1,39 @@ +#ifndef __PANTILT_H__ +#define __PANTILT_H__ + +#include "pwm/pwm.h" + +/* joysticks device structure */ +typedef struct pantilt_dev { + pwm_dev pwm_v; /* Vertical PWM device handle */ + pwm_dev pwm_h; /* Horizontal PWM device handle */ +} pantilt_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz + +#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms + +/* Vertical servo */ +#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms +#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms + +/* Horizontal servo */ +#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms +#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms + +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base); + +void pantilt_init(pantilt_dev *dev); + +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_start_vertical(pantilt_dev *dev); +void pantilt_start_horizontal(pantilt_dev *dev); +void pantilt_stop_vertical(pantilt_dev *dev); +void pantilt_stop_horizontal(pantilt_dev *dev); + +#endif /* __PANTILT_H__ */ diff --git a/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm.c b/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm.c new file mode 100644 index 0000000..293be53 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm.c @@ -0,0 +1,71 @@ +#include + +#include "pwm.h" +#include "pwm_regs.h" + +#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000)) + + +/** + * pwm_inst + * + * Instantiate a pwm device structure. + * + * @param base Base address of the component. + */ +pwm_dev pwm_inst(void *base) { + pwm_dev dev; + + dev.base = base; + + return dev; +} + +/** + * pwm_init + * + * Initializes the pwm device. This function stops the controller. + * + * @param dev pwm device structure. + */ +void pwm_init(pwm_dev *dev) { + pwm_stop(dev); +} + +/** + * pwm_configure + * + * Configure pwm component. + * + * @param dev pwm device structure. + * @param duty_cycle pwm duty cycle in us. + * @param period pwm period in us. + * @param module_frequency frequency at which the component is clocked. + */ +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) { + + IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency)); + IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency)); +} + +/** + * pwm_start + * + * Starts the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_start(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} + +/** + * pwm_stop + * + * Stops the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_stop(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK); +} diff --git a/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm.h b/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm.h new file mode 100644 index 0000000..e2987f4 --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm.h @@ -0,0 +1,21 @@ +#ifndef __PWM_H__ +#define __PWM_H__ + +#include + +/* pwm device structure */ +typedef struct pwm_dev { + void *base; /* Base address of component */ +} pwm_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ +pwm_dev pwm_inst(void *base); + +void pwm_init(pwm_dev *dev); +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency); +void pwm_start(pwm_dev *dev); +void pwm_stop(pwm_dev *dev); + +#endif /* __PWM_H__ */ diff --git a/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm_regs.h b/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm_regs.h new file mode 100644 index 0000000..488583d --- /dev/null +++ b/cs309-psoc/lab_2_0/sw/nios/application/pantilt/pwm/pwm_regs.h @@ -0,0 +1,11 @@ +#ifndef __PWM_REGS_H__ +#define __PWM_REGS_H__ + +#define PWM_PERIOD_OFST (0 * 4) /* RW */ +#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */ +#define PWM_CTRL_OFST (2 * 4) /* WO */ + +#define PWM_CTRL_STOP_MASK (0) +#define PWM_CTRL_START_MASK (1) + +#endif /* __PWM_REGS_H__ */ diff --git a/cs309-psoc/lab_2_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd b/cs309-psoc/lab_2_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd new file mode 100644 index 0000000..be1001d --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd @@ -0,0 +1,203 @@ +-- ############################################################################# +-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +-- +-- BOARD : PrSoC extension board for DE0-Nano-SoC +-- Author : Florian Depraz based on Sahand Kashani-Akhavan work +-- Revision : 1.1 +-- Creation date : 06/02/2016 +-- +-- Syntax Rule : GROUP_NAME_N[bit] +-- +-- GROUP : specify a particular interface (ex: SDR_) +-- NAME : signal name (ex: CONFIG, D, ...) +-- bit : signal index +-- _N : to specify an active-low signal +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; + +entity DE0_Nano_SoC_PrSoC_extn_board_top_level is + port( + ------------------------------- + -- Comment ALL unused ports. -- + ------------------------------- + + -- CLOCK + FPGA_CLK1_50 : in std_logic; + -- FPGA_CLK2_50 : in std_logic; + -- FPGA_CLK3_50 : in std_logic; + + -- KEY on DE0 Nano SoC + KEY_N : in std_logic_vector(1 downto 0); + + -- LEDs on DE0 Nano SoC + -- LED : out std_logic_vector(7 downto 0); + + -- SWITCHES on DE0 Nano SoC + -- SW : in std_logic_vector(3 downto 0); + + -- Servomotors pwm + SERVO_0 : out std_logic; + SERVO_1 : out std_logic; + + -- ADC Joysticks + J0_SPI_CS_n : out std_logic; + J0_SPI_MOSI : out std_logic; + J0_SPI_MISO : in std_logic; + J0_SPI_CLK : out std_logic; + + -- Lepton + CAM_TH_SPI_CS_N : out std_logic; + CAM_TH_MISO : in std_logic; + CAM_TH_MOSI : out std_logic; + CAM_TH_CLK : out std_logic + + -- PCA9637 + -- PIO_SCL : inout std_logic; + -- PIO_SDA : inout std_logic; + -- PIO_INT_N : in std_logic; + -- RESET_N : out std_logic; + + -- OV7670 + -- CAM_D : in std_logic_vector(9 downto 0); + -- CAM_PIX_CLK : in std_logic; + -- CAM_LV : in std_logic; + -- CAM_FV : in std_logic; + -- CAM_SYS_CLK : out std_logic; + + -- VGA and LCD shared signals + -- VIDEO_CLK : out std_logic; + -- VIDEO_VSYNC : out std_logic; + -- VIDEO_HSYNC : out std_logic; + -- VIDEO_B : out std_logic_vector(7 downto 0); + -- VIDEO_G : out std_logic_vector(7 downto 0); + -- VIDEO_R : out std_logic_vector(7 downto 0); + + -- LCD Specific signals + -- LCD_DE : out std_logic; + -- LCD_PIN_DAV_N : ? ?? std_logic; + -- LCD_DISPLAY_EN : out std_logic; + -- SPI_MISO : in std_logic; + -- SPI_ENA_N : out std_logic; + -- SPI_CLK : out std_logic; + -- SPI_MOSI : out std_logic; + -- SPI_DAT : inout std_logic; + + -- I2C TOUCH SCREEN + -- TS_SCL : inout std_logic; + -- TS_SDA : inout std_logic; + + -- BLUETOOTH (BLE) + -- BLT_TXD : in std_logic; + -- BLT_RXD : out std_logic; + + -- I2C For VGA, PAL and OV7670 cameras + -- CAM_PAL_VGA_SDA : inout std_logic; + -- CAM_PAL_VGA_SCL : inout std_logic; + + -- ONE WIRE + -- BOARD_ID : inout std_logic; + + -- PAL Camera + -- PAL_VD_VD : in std_logic_vector(7 downto 0); + -- PAL_VD_VSO : in std_logic; + -- PAL_VD_HSO : in std_logic; + -- PAL_VD_CLKO : in std_logic; + -- PAL_PWDN : out std_logic; + + -- WIFI + -- FROM_ESP_TXD : in std_logic; + -- TO_ESP_RXD : out std_logic; + + -- LED RGB + -- LED_BGR : out std_logic; + + -- HPS + -- HPS_CONV_USB_N : inout std_logic; + -- HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); + -- HPS_DDR3_BA : out std_logic_vector(2 downto 0); + -- HPS_DDR3_CAS_N : out std_logic; + -- HPS_DDR3_CK_N : out std_logic; + -- HPS_DDR3_CK_P : out std_logic; + -- HPS_DDR3_CKE : out std_logic; + + -- HPS_DDR3_CS_N : out std_logic; + -- HPS_DDR3_DM : out std_logic_vector(3 downto 0); + -- HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); + -- HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); + -- HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); + -- HPS_DDR3_ODT : out std_logic; + -- HPS_DDR3_RAS_N : out std_logic; + -- HPS_DDR3_RESET_N : out std_logic; + -- HPS_DDR3_RZQ : in std_logic; + -- HPS_DDR3_WE_N : out std_logic; + -- HPS_ENET_GTX_CLK : out std_logic; + -- HPS_ENET_INT_N : inout std_logic; + -- HPS_ENET_MDC : out std_logic; + -- HPS_ENET_MDIO : inout std_logic; + -- HPS_ENET_RX_CLK : in std_logic; + -- HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); + -- HPS_ENET_RX_DV : in std_logic; + -- HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); + -- HPS_ENET_TX_EN : out std_logic; + -- HPS_GSENSOR_INT : inout std_logic; + -- HPS_I2C0_SCLK : inout std_logic; + -- HPS_I2C0_SDAT : inout std_logic; + -- HPS_I2C1_SCLK : inout std_logic; + -- HPS_I2C1_SDAT : inout std_logic; + -- HPS_KEY_N : inout std_logic; + -- HPS_LED : inout std_logic; + -- HPS_LTC_GPIO : inout std_logic; + -- HPS_SD_CLK : out std_logic; + -- HPS_SD_CMD : inout std_logic; + -- HPS_SD_DATA : inout std_logic_vector(3 downto 0); + -- HPS_SPIM_CLK : out std_logic; + -- HPS_SPIM_MISO : in std_logic; + -- HPS_SPIM_MOSI : out std_logic; + -- HPS_SPIM_SS : inout std_logic; + -- HPS_UART_RX : in std_logic; + -- HPS_UART_TX : out std_logic; + -- HPS_USB_CLKOUT : in std_logic; + -- HPS_USB_DATA : inout std_logic_vector(7 downto 0); + -- HPS_USB_DIR : in std_logic; + -- HPS_USB_NXT : in std_logic; + -- HPS_USB_STP : out std_logic + ); +end entity DE0_Nano_SoC_PrSoC_extn_board_top_level; + +architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is + component soc_system is + port ( + clk_clk : in std_logic := 'X'; -- clk + lepton_0_conduit_end_mosi : out std_logic; -- mosi + lepton_0_conduit_end_miso : in std_logic := 'X'; -- miso + lepton_0_conduit_end_sclk : out std_logic; -- sclk + lepton_0_conduit_end_cs_n : out std_logic; -- cs_n + mcp3204_0_conduit_end_cs_n : out std_logic; -- cs_n + mcp3204_0_conduit_end_miso : in std_logic := 'X'; -- miso + mcp3204_0_conduit_end_mosi : out std_logic; -- mosi + mcp3204_0_conduit_end_sclk : out std_logic; -- sclk + pwm_0_conduit_end_pwm_out : out std_logic; -- pwm_out + pwm_1_conduit_end_pwm_out : out std_logic; -- pwm_out + reset_reset_n : in std_logic := 'X' -- reset_n + ); + end component soc_system; +begin + u0 : component soc_system + port map ( + clk_clk => FPGA_CLK1_50, -- clk.clk + lepton_0_conduit_end_mosi => CAM_TH_MOSI, -- lepton_0_conduit_end.mosi + lepton_0_conduit_end_miso => CAM_TH_MISO, -- .miso + lepton_0_conduit_end_sclk => CAM_TH_CLK, -- .sclk + lepton_0_conduit_end_cs_n => CAM_TH_SPI_CS_N, -- .cs_n + mcp3204_0_conduit_end_cs_n => J0_SPI_CS_n, -- mcp3204_0_conduit_end.cs_n + mcp3204_0_conduit_end_miso => J0_SPI_MISO, -- .miso + mcp3204_0_conduit_end_mosi => J0_SPI_MOSI, -- .mosi + mcp3204_0_conduit_end_sclk => J0_SPI_CLK, -- .sclk + pwm_0_conduit_end_pwm_out => SERVO_0, -- pwm_0_conduit_end.pwm_out + pwm_1_conduit_end_pwm_out => SERVO_1, -- pwm_1_conduit_end.pwm_out + reset_reset_n => KEY_N(0) -- reset.reset_n + ); + +end; diff --git a/cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204.vhd b/cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204.vhd new file mode 100644 index 0000000..af0aafb --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204.vhd @@ -0,0 +1,138 @@ +-- ############################################################################# +-- mcp3204.vhd +-- =========== +-- MCP3204 Avalon-MM slave interface. +-- +-- Register map +-- +-------+-----------+--------+------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +-------+-----------+--------+------------------------------------+ +-- | 0 | CHANNEL_0 | RO | 12-bit digital value of channel 0. | +-- +-------+-----------+--------+------------------------------------+ +-- | 1 | CHANNEL_1 | RO | 12-bit digital value of channel 1. | +-- +-------+-----------+--------+------------------------------------+ +-- | 2 | CHANNEL_2 | RO | 12-bit digital value of channel 2. | +-- +-------+-----------+--------+------------------------------------+ +-- | 3 | CHANNEL_3 | RO | 12-bit digital value of channel 3. | +-- +-------+-----------+--------+------------------------------------+ +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity mcp3204 is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + readdata : out std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic; + SCLK : out std_logic + ); +end entity; + +architecture arch of mcp3204 is + constant NUM_CHANNELS : positive := 4; + constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS)))); + + type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range); + signal data_reg : data_array; + + signal spi_busy, spi_start, spi_datavalid : std_logic; + signal spi_channel : std_logic_vector(1 downto 0); + signal spi_data : std_logic_vector(11 downto 0); + + type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA); + signal state : state_t; + + signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0); + +begin + SPI : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => spi_busy, + start => spi_start, + channel => spi_channel, + data_valid => spi_datavalid, + data => spi_data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + -- FSM that dictates which channel is being read. The state of the component + -- should be thought as the pair (state, channel) + p_fsm : process(reset, clk) + begin + if reset = '1' then + state <= READY; + channel <= (others => '0'); + elsif rising_edge(clk) then + case state is + when READY => + if spi_busy = '0' then + state <= INIT_READ_CHANNEL; + end if; + + when INIT_READ_CHANNEL => + state <= WAIT_FOR_DATA; + + when WAIT_FOR_DATA => + if spi_datavalid = '1' then + state <= READY; + channel <= channel + 1; + end if; + end case; + end if; + end process p_fsm; + + -- Updates the internal registers when a new data is available + p_data : process(reset, clk) + begin + if reset = '1' then + for i in 0 to NUM_CHANNELS - 1 loop + data_reg(i) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + if state = WAIT_FOR_DATA and spi_datavalid = '1' then + data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data; + end if; + end if; + end process p_data; + + spi_start <= '1' when state = INIT_READ_CHANNEL else '0'; + spi_channel <= std_logic_vector(channel); + + -- Interface with the Avalon Switch Fabric + p_avalon_read : process(reset, clk) + begin + if reset = '1' then + readdata <= (others => '0'); + elsif rising_edge(clk) then + if read = '1' then + readdata <= data_reg(to_integer(unsigned(address))); + end if; + end if; + end process p_avalon_read; + +end architecture; diff --git a/cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd b/cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd new file mode 100644 index 0000000..f5e072e --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd @@ -0,0 +1,87 @@ +-- ############################################################################# +-- mcp3204_spi.vhd +-- =============== +-- MCP3204 SPI interface. +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Author : () +-- Revision : 1 +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mcp3204_spi is + port( + -- 50 MHz + clk : in std_logic; + reset : in std_logic; + busy : out std_logic; + start : in std_logic; + channel : in std_logic_vector(1 downto 0); + data_valid : out std_logic; + data : out std_logic_vector(11 downto 0); + + -- 1 MHz + SCLK : out std_logic; + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); +end mcp3204_spi; + +architecture rtl of mcp3204_spi is + signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24 + signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz + signal reg_rising_edge_sclk : std_logic := '0'; + signal reg_falling_edge_sclk : std_logic := '0'; + + signal reg_sclk : std_logic := '0'; + +begin + clk_divider_generation : process(clk, reset) + begin + if reset = '1' then + reg_clk_divider_counter <= (others => '0'); + elsif rising_edge(clk) then + reg_clk_divider_counter <= reg_clk_divider_counter + 1; + reg_spi_en <= '0'; + reg_rising_edge_sclk <= '0'; + reg_falling_edge_sclk <= '0'; + + if reg_clk_divider_counter = 24 then + reg_clk_divider_counter <= (others => '0'); + reg_spi_en <= '1'; + + if reg_sclk = '0' then + reg_rising_edge_sclk <= '1'; + elsif reg_sclk = '1' then + reg_falling_edge_sclk <= '1'; + end if; + end if; + end if; + end process; + + SCLK_generation : process(clk, reset) + begin + if reset = '1' then + reg_sclk <= '0'; + elsif rising_edge(clk) then + if reg_spi_en = '1' then + reg_sclk <= not reg_sclk; + end if; + end if; + end process; + + STATE_LOGIC : process(clk, reset) + begin + -- TODO: complete this process + if reset = '1' then + elsif rising_edge(clk) then + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_2_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd b/cs309-psoc/lab_2_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd new file mode 100644 index 0000000..1bb61d2 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd @@ -0,0 +1,103 @@ +-- ############################################################################# +-- tb_mcp3204_spi.vhd +-- ================== +-- Testbench for MCP3204 SPI interface. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 1 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_mcp3204_spi is +end entity; + +architecture rtl of tb_mcp3204_spi is + constant CLK_PERIOD : time := 20 ns; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal sim_finished : boolean := false; + + -- mcp3204_spi ------------------------------------------------------------ + signal busy : std_logic := '0'; + signal start : std_logic := '0'; + signal channel : std_logic_vector(1 downto 0) := (others => '0'); + signal data_valid : std_logic := '0'; + signal data : std_logic_vector(11 downto 0) := (others => '0'); + signal SCLK : std_logic := '0'; + signal CS_N : std_logic := '1'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '0'; + +begin + duv : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => busy, + start => start, + channel => channel, + data_valid => data_valid, + data => data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_finished; + + sim : process + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + reset <= '1'; + + wait for CLK_PERIOD / 2; + reset <= '0'; + end procedure async_reset; + + procedure spi_transfer(constant channel_number : natural range 0 to 3) is + begin + if busy = '1' then + wait until busy = '0'; + + else + wait until falling_edge(clk); + start <= '1'; + channel <= std_logic_vector(to_unsigned(channel_number, channel'length)); + + wait until falling_edge(clk); + start <= '0'; + channel <= (others => '0'); + + wait until rising_edge(data_valid); + wait until falling_edge(busy); + end if; + end procedure spi_transfer; + + begin + async_reset; + + MISO <= '1'; + spi_transfer(0); + + MISO <= '0'; + spi_transfer(1); + + MISO <= '1'; + spi_transfer(2); + + MISO <= '0'; + spi_transfer(3); + + sim_finished <= true; + wait; + end process sim; +end architecture rtl; + + diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd new file mode 100644 index 0000000..9769bb8 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd @@ -0,0 +1,139 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.utils.all; + +entity avalon_st_spi_master is + generic( + INPUT_CLK_FREQ : integer := 50000000; + SPI_SCLK_FREQ : integer := 10000000; + CPOL : integer := 1; + CPHA : integer := 1 + ); + port( + -- Input clock + clk : in std_logic; + + -- Reset + reset : in std_logic; + spi_cs_n : in std_logic; + -- Sink Avalon ST Interface + mosi_sink_data : in std_logic_vector(7 downto 0); + mosi_sink_valid : in std_logic; + mosi_sink_ready : out std_logic; + + -- Source Avalon ST Interface + miso_src_data : out std_logic_vector(7 downto 0); + miso_src_valid : out std_logic; + + -- SPI Master signals + SCLK : out std_logic; + MISO : in std_logic; + MOSI : out std_logic; + CS_n : out std_logic + ); +end avalon_st_spi_master; + +architecture rtl of avalon_st_spi_master is + constant SCLK_PRESCALER_MAX : integer := INPUT_CLK_FREQ / SPI_SCLK_FREQ / 2; + signal sclk_prescaler : unsigned(bitlength(SCLK_PRESCALER_MAX) downto 0); + signal sclk_toggle : std_logic; + + signal new_sink_buffer, cur_sink_buffer : std_logic_vector(mosi_sink_data'range); + signal new_sink_buffer_busy, cur_sink_buffer_busy : std_logic; + + signal miso_src_buffer : std_logic_vector(7 downto 0); + + signal spi_done, i_sclk : std_logic; + signal spi_bit_index : unsigned(2 downto 0); +begin + CS_n <= spi_cs_n; + + p_sclk_prescaler : process(clk, reset) is + begin + if reset = '1' then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + elsif rising_edge(clk) then + if sclk_prescaler = SCLK_PRESCALER_MAX then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + else + sclk_prescaler <= sclk_prescaler + 1; + end if; + end if; + end process p_sclk_prescaler; + sclk_toggle <= '1' when sclk_prescaler = SCLK_PRESCALER_MAX else '0'; + + p_avalon_st_sink : process(clk, reset) is + begin + if reset = '1' then + new_sink_buffer_busy <= '0'; + new_sink_buffer <= (others => '0'); + elsif rising_edge(clk) then + if mosi_sink_valid = '1' then + if new_sink_buffer_busy = '0' and cur_sink_buffer_busy = '1' then + new_sink_buffer <= mosi_sink_data; + new_sink_buffer_busy <= '1'; + end if; + elsif new_sink_buffer_busy = '1' and cur_sink_buffer_busy = '0' then + new_sink_buffer_busy <= '0'; + end if; + end if; + end process p_avalon_st_sink; + mosi_sink_ready <= not new_sink_buffer_busy; + + p_cur_buffer : process(clk, reset) is + begin + if reset = '1' then + cur_sink_buffer <= (others => '0'); + cur_sink_buffer_busy <= '0'; + elsif rising_edge(clk) then + if mosi_sink_valid = '1' and cur_sink_buffer_busy = '0' then + cur_sink_buffer <= mosi_sink_data; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '0' and new_sink_buffer_busy = '1' then + cur_sink_buffer <= new_sink_buffer; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '1' and spi_done = '1' then + cur_sink_buffer_busy <= '0'; + end if; + end if; + end process p_cur_buffer; + + p_spi : process(clk, reset) is + begin + if reset = '1' then + spi_done <= '0'; + i_sclk <= to_unsigned(CPOL, 1)(0); + spi_bit_index <= "000"; + MOSI <= '0'; + miso_src_data <= (others => '0'); + miso_src_valid <= '0'; + miso_src_buffer <= (others => '0'); + + elsif rising_edge(clk) then + spi_done <= '0'; + miso_src_valid <= '0'; + if cur_sink_buffer_busy = '1' and sclk_toggle = '1' then + if i_sclk /= to_unsigned(CPHA, 1)(0) then + if spi_bit_index = "111" then + spi_done <= '1'; + spi_bit_index <= "000"; + miso_src_valid <= '1'; + miso_src_data <= miso_src_buffer(7 downto 1) & MISO; + else + MOSI <= cur_sink_buffer(7 - to_integer(spi_bit_index)); + miso_src_buffer(7 - to_integer(spi_bit_index)) <= MISO; + spi_bit_index <= spi_bit_index + 1; + + end if; + + end if; + + i_sclk <= not i_sclk; + + end if; + end if; + end process p_spi; + SCLK <= i_sclk; + +end rtl; diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/byte2pix.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/byte2pix.vhd new file mode 100644 index 0000000..b888ba9 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/byte2pix.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------- +-- Title : Byte stream to pixel converter for the Lepton Camera +-- Project : PrSoC +------------------------------------------------------------------------------- +-- File : byte2pix.vhd +-- Author : Philemon Orphee Favrod +-- Company : +-- Created : 2016-03-21 +-- Last update: 2017-03-19 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: Converts a byte stream to a 14-bit pixel stream. +------------------------------------------------------------------------------- +-- Copyright (c) 2016 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2016-03-21 1.0 pofavrod Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity byte2pix is + port( + clk, reset : in std_logic; + byte_data : in std_logic_vector(7 downto 0); + byte_valid : in std_logic; + byte_sof : in std_logic; + byte_eof : in std_logic; + pix_data : out std_logic_vector(13 downto 0); + pix_valid : out std_logic; + pix_sof : out std_logic; + pix_eof : out std_logic); + +end byte2pix; + +architecture rtl of byte2pix is + signal last_sof : std_logic; + signal msb : std_logic_vector(5 downto 0); + signal cnt : std_logic; -- used to skip msb sampling every other time +begin + process(clk, reset) + begin + if reset = '1' then + msb <= (others => '0'); + cnt <= '0'; + last_sof <= '0'; + elsif rising_edge(clk) then + if byte_valid = '1' then + if cnt = '0' then + msb <= byte_data(5 downto 0); + last_sof <= byte_sof; + end if; + cnt <= not cnt; + end if; + end if; + end process; + + process(clk, reset) + begin + if reset = '1' then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + elsif rising_edge(clk) then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + + if byte_valid = '1' then + if cnt = '1' then + pix_data <= msb & byte_data; + pix_valid <= '1'; + pix_sof <= last_sof; + pix_eof <= byte_eof; + end if; + end if; + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd new file mode 100644 index 0000000..d4b4812 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd @@ -0,0 +1,192 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: dual_ported_ram.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +entity dual_ported_ram is + port( + clock : in std_logic := '1'; + data : in std_logic_vector(15 downto 0); + rdaddress : in std_logic_vector(12 downto 0); + wraddress : in std_logic_vector(12 downto 0); + wren : in std_logic := '0'; + q : out std_logic_vector(15 downto 0) + ); +end dual_ported_ram; + +architecture SYN of dual_ported_ram is + signal sub_wire0 : std_logic_vector(15 downto 0); + +begin + q <= sub_wire0(15 downto 0); + + altsyncram_component : altsyncram + generic map( + address_aclr_b => "NONE", + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 8192, + numwords_b => 8192, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "CLOCK0", + power_up_uninitialized => "FALSE", + read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => 13, + widthad_b => 13, + width_a => 16, + width_b => 16, + width_byteena_a => 1 + ) + port map( + address_a => wraddress, + address_b => rdaddress, + clock0 => clock, + data_a => data, + wren_a => wren, + q_b => sub_wire0 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]" +-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 +-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton.vhd new file mode 100644 index 0000000..82678ba --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton.vhd @@ -0,0 +1,288 @@ +-- Lepton Avalon Memory-Mapped Slave Interface +-- Author: Philémon Favrod (philemon.favrod@epfl.ch) +-- Modified by: Sahand Kashani-Akhavan (sahand.kashani-akhavan@epfl.ch) +-- Revision: 2 + +-- Register map +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 0 | COMMAND | WO | Command | +-- | | | | - Writing 1 starts capturing a frame & resets the | +-- | | | | ERROR bit (bit 1) in the STATUS register. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 1 | STATUS | RO | Status | +-- | | | | - Bit 0: 0 --> no capture in progress. | +-- | | | | 1 --> capture in progress. | +-- | | | | - Bit 1: 0 --> previous capture successful. | +-- | | | | 1 --> error during previous capture. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 2 | MIN | RO | Minimum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 3 | MAX | RO | Maximum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4 | SUM_LSB | RO | Sum of all pixels in frame (low 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 5 | SUM_MSB | RO | Sum of all pixels in frame (high 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 6 | ROW_IDX | RO | Current line being captured (1 <= ROW_IDX <= 60). | +-- | | | | Available for debugging purposes. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 7 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8 - 4807 | RAW BUFFER | RO | View into RAW pixel buffer. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4808 - 8191 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8192 - 12991 | ADJUSTED BUFFER | RO | View into adjusted (scaled) pixel buffer. | +-- | | | | Values are scaled between MIN and MAX. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 12992 - 16383 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton is + port( + clk : in std_logic; + reset : in std_logic; + address : in std_logic_vector(13 downto 0); + readdata : out std_logic_vector(15 downto 0); + writedata : in std_logic_vector(15 downto 0); + read : in std_logic; + write : in std_logic; + + SCLK : out std_logic; + CSn : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); + +end lepton; + +architecture rtl of lepton is + signal spi_cs_n : std_logic; + signal spi_mosi_data : std_logic_vector(7 downto 0); + signal spi_mosi_valid : std_logic; + signal spi_mosi_ready : std_logic; + signal spi_miso_data : std_logic_vector(7 downto 0); + signal spi_miso_valid : std_logic; + signal lepton_manager_start : std_logic; + signal lepton_manager_error : std_logic; + signal byte_data : std_logic_vector(7 downto 0); + signal byte_valid : std_logic; + signal byte_sof : std_logic; + signal byte_eof : std_logic; + signal pix_data : std_logic_vector(13 downto 0); + signal pix_valid : std_logic; + signal pix_sof : std_logic; + signal pix_eof : std_logic; + signal stat_min : std_logic_vector(13 downto 0); + signal stat_max : std_logic_vector(13 downto 0); + signal stat_sum : std_logic_vector(26 downto 0); + signal stat_valid : std_logic; + signal ram_data : std_logic_vector(15 downto 0); + signal ram_wren : std_logic; + signal ram_wraddress : std_logic_vector(12 downto 0); + signal ram_rdaddress : std_logic_vector(12 downto 0); + signal ram_q : std_logic_vector(15 downto 0); + signal row_idx : std_logic_vector(5 downto 0); + signal raw_pixel : std_logic_vector(13 downto 0); + signal raw_max : std_logic_vector(13 downto 0); + signal raw_min : std_logic_vector(13 downto 0); + signal raw_sum : std_logic_vector(26 downto 0); + signal adjusted_pixel : std_logic_vector(13 downto 0); + + constant COMMAND_REG_OFFSET : std_logic_vector(address'range) := "00000000000000"; + constant STATUS_REG_OFFSET : std_logic_vector(address'range) := "00000000000001"; + constant MIN_REG_OFFSET : std_logic_vector(address'range) := "00000000000010"; + constant MAX_REG_OFFSET : std_logic_vector(address'range) := "00000000000011"; + constant SUM_LSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000100"; + constant SUM_MSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000101"; + constant ROW_IDX_REG_OFFSET : std_logic_vector(address'range) := "00000000000110"; + constant BUFFER_REG_OFFSET : unsigned(address'range) := "00000000001000"; + constant ADJUSTED_BUFFER_REG_OFFSET : unsigned(address'range) := "10000000000000"; + + constant IMAGE_SIZE : integer := 80 * 60; + constant BUFFER_REG_LIMIT : unsigned(address'range) := unsigned(BUFFER_REG_OFFSET) + IMAGE_SIZE; + + constant ADJUSTED_BUFFER_LIMIT : unsigned(address'range) := unsigned(ADJUSTED_BUFFER_REG_OFFSET) + IMAGE_SIZE; + + signal max_reg : std_logic_vector(stat_max'range); + signal min_reg : std_logic_vector(stat_min'range); + signal sum_reg : std_logic_vector(stat_sum'range); + signal error_reg : std_logic; + +begin + spi_controller0 : entity work.avalon_st_spi_master + port map( + clk => clk, + reset => reset, + spi_cs_n => spi_cs_n, + mosi_sink_data => spi_mosi_data, + mosi_sink_valid => spi_mosi_valid, + mosi_sink_ready => spi_mosi_ready, + miso_src_data => spi_miso_data, + miso_src_valid => spi_miso_valid, + SCLK => SCLK, + MISO => MISO, + MOSI => MOSI, + CS_n => CSn + ); + + lepton_manager0 : entity work.lepton_manager + port map( + clk => clk, + reset => reset, + spi_miso_sink_data => spi_miso_data, + spi_miso_sink_valid => spi_miso_valid, + spi_mosi_src_data => spi_mosi_data, + spi_mosi_src_valid => spi_mosi_valid, + spi_mosi_src_ready => spi_mosi_ready, + lepton_out_data => byte_data, + lepton_out_valid => byte_valid, + lepton_out_sof => byte_sof, + lepton_out_eof => byte_eof, + row_idx => row_idx, + error => lepton_manager_error, + start => lepton_manager_start, + spi_cs_n => spi_cs_n + ); + + byte2pix0 : entity work.byte2pix + port map( + clk => clk, + reset => reset, + byte_data => byte_data, + byte_valid => byte_valid, + byte_sof => byte_sof, + byte_eof => byte_eof, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof + ); + + lepton_stats0 : entity work.lepton_stats + port map( + reset => reset, + clk => clk, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + stat_min => stat_min, + stat_max => stat_max, + stat_sum => stat_sum, + stat_valid => stat_valid + ); + + ram_writer0 : entity work.ram_writer + port map( + clk => clk, + reset => reset, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + ram_data => ram_data, + ram_wren => ram_wren, + ram_wraddress => ram_wraddress + ); + + dual_ported_ram0 : entity work.dual_ported_ram + port map( + clock => clk, + data => ram_data, + rdaddress => ram_rdaddress, + wraddress => ram_wraddress, + wren => ram_wren, + q => ram_q + ); + + level_adjuster0 : entity work.level_adjuster + port map( + clk => clk, + raw_pixel => ram_q(13 downto 0), + raw_max => max_reg, + raw_min => min_reg, + raw_sum => sum_reg, + adjusted_pixel => adjusted_pixel + ); + + p_lepton_start : process(clk, reset) + begin + if reset = '1' then + lepton_manager_start <= '0'; + error_reg <= '0'; + elsif rising_edge(clk) then + if write = '1' and address = COMMAND_REG_OFFSET then + lepton_manager_start <= writedata(0); + error_reg <= '0'; + elsif pix_eof = '1' then + lepton_manager_start <= '0'; + elsif lepton_manager_error = '1' then + error_reg <= '1'; + end if; + end if; + end process p_lepton_start; + + p_stat_reg : process(clk, reset) + begin + if reset = '1' then + min_reg <= (others => '0'); + max_reg <= (others => '0'); + sum_reg <= (others => '0'); + elsif rising_edge(clk) then + if stat_valid = '1' then + min_reg <= stat_min; + max_reg <= stat_max; + sum_reg <= stat_sum; + end if; + end if; + end process p_stat_reg; + + p_read : process(clk, reset) + begin + if reset = '1' then + readdata <= (others => '0'); + ram_rdaddress <= (others => '0'); + elsif rising_edge(clk) then + readdata <= (others => '0'); + if read = '1' then + case address is + when STATUS_REG_OFFSET => + readdata(1) <= error_reg; + readdata(0) <= lepton_manager_start; + + when MIN_REG_OFFSET => + readdata <= "00" & min_reg; + + when MAX_REG_OFFSET => + readdata <= "00" & max_reg; + + when SUM_MSB_REG_OFFSET => + readdata <= "00000" & sum_reg(26 downto 16); + + when SUM_LSB_REG_OFFSET => + readdata <= sum_reg(15 downto 0); + + when ROW_IDX_REG_OFFSET => + readdata(5 downto 0) <= row_idx; + + when others => + if unsigned(address) >= BUFFER_REG_OFFSET and unsigned(address) < BUFFER_REG_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= ram_q; + elsif unsigned(address) >= ADJUSTED_BUFFER_REG_OFFSET and unsigned(address) < ADJUSTED_BUFFER_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - ADJUSTED_BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= "00" & adjusted_pixel; + end if; + end case; + end if; + end if; + end process p_read; + +end rtl; diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton_manager.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton_manager.vhd new file mode 100644 index 0000000..1580be1 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton_manager.vhd @@ -0,0 +1,235 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_manager is + generic( + INPUT_CLK_FREQ : integer := 50000000); + port( + clk : in std_logic := '0'; + reset : in std_logic := '0'; + + -- Avalon ST Sink to receive SPI data + spi_miso_sink_data : in std_logic_vector(7 downto 0); + spi_miso_sink_valid : in std_logic; + + -- Avalon ST Source to send SPI data + spi_mosi_src_data : out std_logic_vector(7 downto 0); + spi_mosi_src_valid : out std_logic; + spi_mosi_src_ready : in std_logic := '0'; + + -- Filtered output to retransmit cleaned data (without the discard packets, see Lepton Datasheet on page 31) + -- lepton_out_data is valid on rising edge when lepton_src_valid = '1' + lepton_out_data : out std_logic_vector(7 downto 0); + lepton_out_valid : out std_logic; + lepton_out_sof : out std_logic; + lepton_out_eof : out std_logic; + + -- Some status + row_idx : out std_logic_vector(5 downto 0); + error : out std_logic; + + -- Avalon MM Slave interface for configuration + start : in std_logic; + + -- The SPI Chip Select (Active low !) + spi_cs_n : out std_logic := '0'); +end entity lepton_manager; + +architecture rtl of lepton_manager is + type state_t is (Idle, CSn, ReadHeader, ReadPayload, DiscardPayload, WaitBeforeIdle); + signal state, next_state : state_t; + + signal header_3_last_nibbles : std_logic_vector(11 downto 0); + + constant CLOCK_TICKS_PER_37_MS : integer := 37 * (INPUT_CLK_FREQ / 1e3); -- the timeout delay for a frame + constant CLOCK_TICKS_PER_200_MS : integer := 200 * (INPUT_CLK_FREQ / 1e3); + constant CLOCK_TICKS_PER_200_NS : integer := (200 * (INPUT_CLK_FREQ / 1e6)) / 1e3; + constant BYTES_PER_HEADER : integer := 4; + constant BYTES_PER_PAYLOAD : integer := 160; + + constant NUMBER_OF_LINES_PER_FRAME : positive := 60; + signal counter, counter_max : integer range 1 to CLOCK_TICKS_PER_200_MS; + signal line_counter : integer range 1 to NUMBER_OF_LINES_PER_FRAME; + signal timeout_counter : integer range 1 to CLOCK_TICKS_PER_37_MS; + signal counter_enabled : boolean; + signal waited_long_enough : boolean; + signal header_end, payload_end : boolean; +begin + + -- purpose: register for state + p_fsm : process(clk, reset) + begin + if reset = '1' then + state <= Idle; + elsif rising_edge(clk) then + state <= next_state; + end if; + end process p_fsm; + + -- purpose: compute the next state + p_nsl : process(header_3_last_nibbles, header_end, payload_end, start, spi_miso_sink_valid, state, waited_long_enough, line_counter) + begin + next_state <= state; + + case state is + when Idle => + if waited_long_enough and start = '1' then + next_state <= CSn; + end if; + + when CSn => + if waited_long_enough then + next_state <= ReadHeader; + end if; + + when ReadHeader => + if header_end then + if header_3_last_nibbles(11 downto 8) = X"F" then + next_state <= DiscardPayload; + else + next_state <= ReadPayload; + end if; + end if; + + when DiscardPayload | ReadPayload => + if payload_end then + next_state <= ReadHeader; + + if line_counter = NUMBER_OF_LINES_PER_FRAME then + next_state <= WaitBeforeIdle; + end if; + end if; + + when WaitBeforeIdle => + if spi_miso_sink_valid = '1' then + next_state <= Idle; + end if; + + end case; + end process p_nsl; + + p_counter : process(clk, reset) + begin + if reset = '1' then + counter <= 1; + line_counter <= 1; + elsif rising_edge(clk) then + if counter = counter_max and counter_enabled then + counter <= 1; + + if state = ReadPayload then + if line_counter = NUMBER_OF_LINES_PER_FRAME then + line_counter <= 1; + else + line_counter <= line_counter + 1; + end if; + end if; + + elsif counter_enabled then + counter <= counter + 1; + end if; + end if; + end process p_counter; + + p_error : process(clk, reset) + begin + if reset = '1' then + error <= '0'; + timeout_counter <= 1; + elsif rising_edge(clk) then + if state /= ReadHeader and state /= ReadPayload and state /= ReadHeader then + timeout_counter <= 1; + error <= '0'; + else + if timeout_counter = CLOCK_TICKS_PER_37_MS then + error <= '1'; + else + timeout_counter <= timeout_counter + 1; + end if; + end if; + if state = ReadPayload and header_3_last_nibbles /= std_logic_vector(to_unsigned(line_counter - 1, header_3_last_nibbles'length)) then + error <= '1'; + end if; + end if; + end process p_error; + + -- purpose: wire the datapath + p_datapath : process(counter, counter_enabled, counter_max, line_counter, spi_miso_sink_data, spi_miso_sink_valid, spi_mosi_src_ready, state) + variable counter_ended : boolean; + + begin + counter_max <= 1; + counter_enabled <= true; + waited_long_enough <= false; + lepton_out_data <= (others => '0'); + lepton_out_valid <= '0'; + lepton_out_sof <= '0'; + lepton_out_eof <= '0'; + spi_mosi_src_valid <= '0'; + spi_mosi_src_data <= (others => '0'); + spi_cs_n <= '0'; + header_end <= false; + payload_end <= false; + + counter_ended := (counter = counter_max and counter_enabled); + + case state is + when Idle => + counter_max <= CLOCK_TICKS_PER_200_MS; + waited_long_enough <= counter_ended; + spi_cs_n <= '1'; + + when CSn => + counter_max <= CLOCK_TICKS_PER_200_NS; + waited_long_enough <= counter_ended; + + when ReadHeader => + counter_max <= BYTES_PER_HEADER; + counter_enabled <= spi_miso_sink_valid = '1'; + header_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when ReadPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + lepton_out_data <= spi_miso_sink_data; + lepton_out_valid <= spi_miso_sink_valid; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + if spi_miso_sink_valid = '1' then + if counter = 1 and counter_enabled and line_counter = 1 then + lepton_out_sof <= '1'; + elsif counter_ended and line_counter = NUMBER_OF_LINES_PER_FRAME then + lepton_out_eof <= '1'; + end if; + end if; + + when DiscardPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when others => null; + end case; + end process p_datapath; + + p_capture_header : process(clk, reset) + begin + if reset = '1' then + header_3_last_nibbles <= X"000"; + elsif rising_edge(clk) then + if state = ReadHeader and spi_miso_sink_valid = '1' then + if counter = 1 then + header_3_last_nibbles(11 downto 8) <= spi_miso_sink_data(3 downto 0); + elsif counter = 2 then + header_3_last_nibbles(7 downto 0) <= spi_miso_sink_data; + end if; + end if; + end if; + end process p_capture_header; + + row_idx <= std_logic_vector(to_unsigned(line_counter, row_idx'length)); + +end architecture rtl; diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton_stats.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton_stats.vhd new file mode 100644 index 0000000..4b5cc91 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton_stats.vhd @@ -0,0 +1,78 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_stats is + port( + clk : in std_logic; + reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + stat_min : out std_logic_vector(13 downto 0); + stat_max : out std_logic_vector(13 downto 0); + stat_sum : out std_logic_vector(26 downto 0); + stat_valid : out std_logic); +end lepton_stats; + +architecture rtl of lepton_stats is + + -- The accumulated sum, min and max of the pixel values + signal curr_min : unsigned(13 downto 0); + signal curr_max : unsigned(13 downto 0); + signal curr_sum : unsigned(26 downto 0); + + -- The next value of the registers + signal next_min : unsigned(13 downto 0); + signal next_max : unsigned(13 downto 0); + signal next_sum : unsigned(26 downto 0); + +begin + + -- This is the synchronous transition logic + transition_logic : process(clk, reset) + begin + if reset = '1' then + curr_sum <= (others => '0'); + curr_min <= (others => '0'); + curr_max <= (others => '0'); + elsif rising_edge(clk) then + curr_min <= next_min; + curr_max <= next_max; + curr_sum <= next_sum; + end if; + end process; + + -- This is the combinatorial transition logic + next_min <= + curr_min when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_min when unsigned(pix_data) >= curr_min else + unsigned(pix_data); + + next_max <= + curr_max when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_max when unsigned(pix_data) <= curr_max else + unsigned(pix_data); + + next_sum <= + curr_sum when pix_valid = '0' else + unsigned((26 downto 14 => '0') & pix_data) when pix_sof = '1' else + curr_sum + unsigned((26 downto 14 => '0') & pix_data); + + -- This is the synchronous output logic + output_logic : process(clk, reset) + begin + if rising_edge(clk) then + stat_valid <= pix_eof; + end if; + end process; + + -- This is the combinatorial output logic + stat_min <= std_logic_vector(curr_min); + stat_max <= std_logic_vector(curr_max); + stat_sum <= std_logic_vector(curr_sum); + +end rtl; diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/level_adjuster.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/level_adjuster.vhd new file mode 100644 index 0000000..6b3053d --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/level_adjuster.vhd @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity level_adjuster is + port( + clk : in std_logic; + raw_pixel : in std_logic_vector(13 downto 0); + raw_max : in std_logic_vector(13 downto 0); + raw_min : in std_logic_vector(13 downto 0); + raw_sum : in std_logic_vector(26 downto 0); + adjusted_pixel : out std_logic_vector(13 downto 0)); +end level_adjuster; + +architecture rtl of level_adjuster is + component lpm_divider + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0)); + end component; + + -- Intermediate signals needed by the divider + signal numer : std_logic_vector(27 downto 0); + signal denom : std_logic_vector(13 downto 0); + signal quot : std_logic_vector(27 downto 0); + +begin + + -- Computation of the intermediate signals + numer <= std_logic_vector((13 downto 0 => '1') * (unsigned(raw_pixel) - unsigned(raw_min))); + denom <= std_logic_vector(unsigned(raw_max) - unsigned(raw_min)); + + -- We compute the remaineder of (x - min) / (max - min) + divider : lpm_divider port map( + clock => clk, + numer => numer, + denom => denom, + quotient => quot, + remain => open + ); + + -- And we only keep the LSB of the quotient (we know the MSB must be 0) + adjusted_pixel <= + (adjusted_pixel'range => '0') when denom = (denom'range => '0') else + quot(13 downto 0); + +end rtl; diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lpm_divider.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lpm_divider.vhd new file mode 100644 index 0000000..f8de4a6 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lpm_divider.vhd @@ -0,0 +1,133 @@ +-- megafunction wizard: %LPM_DIVIDE% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_DIVIDE + +-- ============================================================ +-- File Name: lpm_divider.vhd +-- Megafunction Name(s): +-- LPM_DIVIDE +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library lpm; +use lpm.all; + +entity lpm_divider is + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); +end lpm_divider; + +architecture SYN of lpm_divider is + signal sub_wire0 : std_logic_vector(27 downto 0); + signal sub_wire1 : std_logic_vector(13 downto 0); + + component lpm_divide + generic( + lpm_drepresentation : string; + lpm_hint : string; + lpm_nrepresentation : string; + lpm_pipeline : natural; + lpm_type : string; + lpm_widthd : natural; + lpm_widthn : natural + ); + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); + end component; + +begin + quotient <= sub_wire0(27 downto 0); + remain <= sub_wire1(13 downto 0); + + LPM_DIVIDE_component : LPM_DIVIDE + generic map( + lpm_drepresentation => "UNSIGNED", + lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE", + lpm_nrepresentation => "UNSIGNED", + lpm_pipeline => 5, + lpm_type => "LPM_DIVIDE", + lpm_widthd => 14, + lpm_widthn => 28 + ) + port map( + clock => clock, + denom => denom, + numer => numer, + quotient => sub_wire0, + remain => sub_wire1 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" +-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1" +-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" +-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" +-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "14" +-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "28" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: denom 0 0 14 0 INPUT NODEFVAL "denom[13..0]" +-- Retrieval info: USED_PORT: numer 0 0 28 0 INPUT NODEFVAL "numer[27..0]" +-- Retrieval info: USED_PORT: quotient 0 0 28 0 OUTPUT NODEFVAL "quotient[27..0]" +-- Retrieval info: USED_PORT: remain 0 0 14 0 OUTPUT NODEFVAL "remain[13..0]" +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @denom 0 0 14 0 denom 0 0 14 0 +-- Retrieval info: CONNECT: @numer 0 0 28 0 numer 0 0 28 0 +-- Retrieval info: CONNECT: quotient 0 0 28 0 @quotient 0 0 28 0 +-- Retrieval info: CONNECT: remain 0 0 14 0 @remain 0 0 14 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/ram_writer.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/ram_writer.vhd new file mode 100644 index 0000000..8912cdb --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/ram_writer.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram_writer is + port( + clk, reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + ram_data : out std_logic_vector(15 downto 0); + ram_wren : out std_logic; + ram_wraddress : out std_logic_vector(12 downto 0)); + +end ram_writer; + +architecture rtl of ram_writer is + signal wraddress_counter : unsigned(ram_wraddress'range); +begin + p_address_gen : process(clk, reset) + begin + if reset = '1' then + wraddress_counter <= (others => '0'); + elsif rising_edge(clk) then + if pix_eof = '1' then + wraddress_counter <= (others => '0'); + elsif pix_valid = '1' then + wraddress_counter <= wraddress_counter + 1; + end if; + end if; + end process p_address_gen; + + ram_data <= "00" & pix_data; + ram_wren <= pix_valid; + ram_wraddress <= std_logic_vector(wraddress_counter); + +end rtl; diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/utils.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/utils.vhd new file mode 100644 index 0000000..83105ad --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/utils.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package utils is + function bitlength(number : positive) return positive; + +end package utils; + +package body utils is + + -- purpose: returns the minimum # of bits needed to represent the input number + function bitlength(number : positive) return positive is + variable acc : positive := 1; + variable i : natural := 0; + begin + while True loop + if acc > number then + return i; + end if; + + acc := acc * 2; + i := i + 1; + end loop; + end function bitlength; + +end package body utils; diff --git a/cs309-psoc/lab_2_1/hw/hdl/lepton/tb/lepton_tb.vhd b/cs309-psoc/lab_2_1/hw/hdl/lepton/tb/lepton_tb.vhd new file mode 100644 index 0000000..f134613 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/lepton/tb/lepton_tb.vhd @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity lepton_tb is +end lepton_tb; + +architecture tb of lepton_tb is + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal address : std_logic_vector(13 downto 0) := (others => '0'); + signal readdata : std_logic_vector(15 downto 0) := (others => '0'); + signal writedata : std_logic_vector(15 downto 0) := (others => '0'); + signal read : std_logic := '0'; + signal write : std_logic := '0'; + signal SCLK : std_logic := '0'; + signal CSn : std_logic := '0'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '1'; + + constant CLK_PERIOD : time := 20 ns; + + signal sim_ended : boolean := false; + +begin + dut : entity work.lepton + port map( + clk => clk, + reset => reset, + address => address, + readdata => readdata, + writedata => writedata, + read => read, + write => write, + SCLK => SCLK, + CSn => CSn, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_ended else '0'; + + miso_gen : process + variable seed1, seed2 : positive; + variable rand : real; + begin + if sim_ended then + wait; + else + uniform(seed1, seed2, rand); + wait until rising_edge(SCLK); + MISO <= to_unsigned(integer(rand), 1)(0); + + end if; + end process; + + stimuli : process + begin + reset <= '1'; + write <= '0'; + + wait for 2 * CLK_PERIOD; + reset <= '0'; + + wait for CLK_PERIOD; + write <= '1'; + writedata(0) <= '1'; + wait for CLK_PERIOD; + write <= '0'; + + wait for 17 ms; + sim_ended <= true; + wait; + end process; + +end tb; diff --git a/cs309-psoc/lab_2_1/hw/hdl/pantilt/hdl/pwm.vhd b/cs309-psoc/lab_2_1/hw/hdl/pantilt/hdl/pwm.vhd new file mode 100644 index 0000000..1b5cdc3 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/pantilt/hdl/pwm.vhd @@ -0,0 +1,42 @@ +-- ############################################################################# +-- pwm.vhd +-- ======= +-- PWM memory-mapped Avalon slave interface. +-- +-- Author : () +-- Author : () +-- Revision : +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity pwm is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + write : in std_logic; + readdata : out std_logic_vector(31 downto 0); + writedata : in std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + pwm_out : out std_logic + ); +end pwm; + +architecture rtl of pwm is + +begin + +end architecture rtl; diff --git a/cs309-psoc/lab_2_1/hw/hdl/pantilt/hdl/pwm_constants.vhd b/cs309-psoc/lab_2_1/hw/hdl/pantilt/hdl/pwm_constants.vhd new file mode 100644 index 0000000..bfff03b --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/pantilt/hdl/pwm_constants.vhd @@ -0,0 +1,61 @@ +-- ############################################################################# +-- pwm_constants.vhd +-- ================= +-- This package contains constants used in the PWM design files. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pwm_constants is + -- Register map + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | RegNo | Name | Access | Description | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW period to apply to the | + -- | | | | next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT period of the | + -- | | | | ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to | + -- | | | | the next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT duty cycle of | + -- | | | | the ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.| + -- | | | | Writing 1 to this register starts the PWM. | + -- | | | | | + -- | | | | >> Reading this register always returns 0. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00"; + constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01"; + constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10"; + + -- Default values of registers after reset (BEFORE writing START to the CTRL + -- register with a new configuration) + constant DEFAULT_PERIOD : natural := 4; + constant DEFAULT_DUTY_CYCLE : natural := 2; +end package pwm_constants; + +package body pwm_constants is + +end package body pwm_constants; diff --git a/cs309-psoc/lab_2_1/hw/hdl/pantilt/tb/tb_pwm.vhd b/cs309-psoc/lab_2_1/hw/hdl/pantilt/tb/tb_pwm.vhd new file mode 100644 index 0000000..ff2dee7 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/hdl/pantilt/tb/tb_pwm.vhd @@ -0,0 +1,205 @@ +-- ############################################################################# +-- tb_pwm.vhd +-- ========== +-- Testbench for PWM memory-mapped Avalon slave interface. +-- +-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity tb_pwm is +end entity; + +architecture rtl of tb_pwm is + + -- 50 MHz clock + constant CLK_PERIOD : time := 20 ns; + + -- Signal used to end simulator when we finished submitting our test cases + signal sim_finished : boolean := false; + + -- PWM PORTS + signal clk : std_logic; + signal reset : std_logic; + signal address : std_logic_vector(1 downto 0); + signal read : std_logic; + signal write : std_logic; + signal readdata : std_logic_vector(31 downto 0); + signal writedata : std_logic_vector(31 downto 0); + signal pwm_out : std_logic; + + -- Values of registers we are going to use to configure the PWM unit + constant CONFIG_PERIOD : natural := 100; + constant CONFIG_DUTY_CYCLE : natural := 20; + constant CONFIG_CTRL_START : natural := 1; + constant CONFIG_CTRL_STOP : natural := 0; + +begin + + -- Instantiate DUT + dut : entity work.pwm + port map( + clk => clk, + reset => reset, + address => address, + read => read, + write => write, + readdata => readdata, + writedata => writedata, + pwm_out => pwm_out + ); + + -- Generate clk signal + clk_generation : process + begin + if not sim_finished then + clk <= '1'; + wait for CLK_PERIOD / 2; + clk <= '0'; + wait for CLK_PERIOD / 2; + else + wait; + end if; + end process clk_generation; + + -- Test PWM + simulation : process + + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + + reset <= '1'; + wait for CLK_PERIOD / 2; + + reset <= '0'; + wait for CLK_PERIOD / 4; + end procedure async_reset; + + procedure write_register(constant ofst : in std_logic_vector(1 downto 0); + constant val : in natural) is + begin + wait until rising_edge(clk); + + address <= ofst; + write <= '1'; + writedata <= std_logic_vector(to_unsigned(val, writedata'length)); + wait until rising_edge(clk); + + address <= (others => '0'); + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + end procedure write_register; + + procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is + begin + wait until rising_edge(clk); + + address <= ofst; + read <= '1'; + -- The read has a 1 cycle wait-state, so we need to keep the read + -- signal high for 2 clock cycles. + wait until rising_edge(clk); + wait until rising_edge(clk); + + address <= (others => '0'); + read <= '0'; + wait until rising_edge(clk); + end procedure read_register; + + procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0); + constant expected_val : in natural) is + begin + read_register(ofst); + + case ofst is + when REG_PERIOD_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected PERIOD: " & + "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "PERIOD_expected = " & integer'image(expected_val) + severity error; + + when REG_DUTY_CYCLE_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected DUTY_CYCLE: " & + "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "DUTY_CYCLE_expected = " & integer'image(expected_val) + severity error; + + when REG_CTRL_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected CTRL: " & + "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "CTRL_expected = " & integer'image(expected_val) + severity error; + + when others => + null; + end case; + end procedure read_register_check; + + begin + + -- Default values + reset <= '0'; + address <= (others => '0'); + read <= '0'; + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + + -- Reset the circuit + async_reset; + + -- Write desired configuration to PWM Avalon-MM slave. + write_register(REG_PERIOD_OFST, CONFIG_PERIOD); + write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + + -- Read back configuration from PWM Avalon-MM slave. Note that we have + -- not started the PWM unit yet, so the new configuration must not be + -- read back at this point (as per the register map). + read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Start PWM + write_register(REG_CTRL_OFST, CONFIG_CTRL_START); + + -- Wait until PWM pulses for the first time after we sent START. + wait until rising_edge(pwm_out); + + -- Read back configuration from PWM Avalon-MM slave. Now that we have + -- started the PWM unit, we should be able to read back the + -- configuration we wrote (as per the register map). + read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Wait for 2 PWM periods to finish + wait for 2 * CLK_PERIOD * CONFIG_PERIOD; + + -- Stop PWM. + write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP); + + -- Wait for PWM period to finish + wait for 1 * CLK_PERIOD * CONFIG_PERIOD; + + -- Instruct "clk_generation" process to halt execution. + sim_finished <= true; + + -- Make this process wait indefinitely (it will never re-execute from + -- its beginning again). + wait; + end process simulation; +end architecture rtl; + diff --git a/cs309-psoc/lab_2_1/hw/quartus/lab_2_1.qpf b/cs309-psoc/lab_2_1/hw/quartus/lab_2_1.qpf new file mode 100644 index 0000000..fbba3c4 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/quartus/lab_2_1.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition +# Date created = 11:03:02 February 05, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.1" +DATE = "11:03:02 February 05, 2016" + +# Revisions + +PROJECT_REVISION = "lab_2_1" diff --git a/cs309-psoc/lab_2_1/hw/quartus/lab_2_1.qsf b/cs309-psoc/lab_2_1/hw/quartus/lab_2_1.qsf new file mode 100644 index 0000000..1157fd2 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/quartus/lab_2_1.qsf @@ -0,0 +1,811 @@ +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 + +set_global_assignment -name SMART_RECOMPILE OFF +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level + +set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +set_global_assignment -name SDC_FILE lab_2_1.sdc + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA4U23C6 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO Extention OV7670 CAMERA +#============================================================ +set_location_assignment PIN_AE15 -to CAM_D[0] +set_location_assignment PIN_AE15 -to CAM_D_0 +set_location_assignment PIN_AF17 -to CAM_D[1] +set_location_assignment PIN_AF17 -to CAM_D_1 +set_location_assignment PIN_AH8 -to CAM_D[2] +set_location_assignment PIN_AH8 -to CAM_D_2 +set_location_assignment PIN_AG8 -to CAM_D[3] +set_location_assignment PIN_AG8 -to CAM_D_3 +set_location_assignment PIN_U13 -to CAM_D[4] +set_location_assignment PIN_U13 -to CAM_D_4 +set_location_assignment PIN_U14 -to CAM_D[5] +set_location_assignment PIN_U14 -to CAM_D_5 +set_location_assignment PIN_AG9 -to CAM_D[6] +set_location_assignment PIN_AG9 -to CAM_D_6 +set_location_assignment PIN_AG10 -to CAM_D[7] +set_location_assignment PIN_AG10 -to CAM_D_7 +set_location_assignment PIN_AF13 -to CAM_D[8] +set_location_assignment PIN_AF13 -to CAM_D_8 +set_location_assignment PIN_AG13 -to CAM_D[9] +set_location_assignment PIN_AG13 -to CAM_D_9 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9 + +#============================================================ +# Arduino Extension LEPTON CAMERA THERMAL CAM_TH +#============================================================ +set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N +set_location_assignment PIN_AG16 -to CAM_TH_MOSI +set_location_assignment PIN_AH11 -to CAM_TH_MISO +set_location_assignment PIN_AH12 -to CAM_TH_CLK +set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA +set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL + +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#============================================================ +# HPS +#============================================================ +set_location_assignment PIN_C6 -to HPS_CONV_USB_N +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0] +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0 +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1] +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1 +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2] +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2 +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3] +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3 +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4] +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4 +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5] +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5 +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6] +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6 +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7] +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7 +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8] +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8 +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9] +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9 +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10] +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10 +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11] +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11 +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12] +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12 +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13] +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13 +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14] +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14 +set_location_assignment PIN_A27 -to HPS_DDR3_BA[0] +set_location_assignment PIN_A27 -to HPS_DDR3_BA_0 +set_location_assignment PIN_H25 -to HPS_DDR3_BA[1] +set_location_assignment PIN_H25 -to HPS_DDR3_BA_1 +set_location_assignment PIN_G25 -to HPS_DDR3_BA[2] +set_location_assignment PIN_G25 -to HPS_DDR3_BA_2 +set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N +set_location_assignment PIN_L28 -to HPS_DDR3_CKE +set_location_assignment PIN_N20 -to HPS_DDR3_CK_N +set_location_assignment PIN_N21 -to HPS_DDR3_CK_P +set_location_assignment PIN_L21 -to HPS_DDR3_CS_N +set_location_assignment PIN_G28 -to HPS_DDR3_DM[0] +set_location_assignment PIN_G28 -to HPS_DDR3_DM_0 +set_location_assignment PIN_P28 -to HPS_DDR3_DM[1] +set_location_assignment PIN_P28 -to HPS_DDR3_DM_1 +set_location_assignment PIN_W28 -to HPS_DDR3_DM[2] +set_location_assignment PIN_W28 -to HPS_DDR3_DM_2 +set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3] +set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3 +set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0] +set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0 +set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1] +set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1 +set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2] +set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2 +set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3] +set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3 +set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4] +set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4 +set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5] +set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5 +set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6] +set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6 +set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7] +set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7 +set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8] +set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8 +set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9] +set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9 +set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10] +set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10 +set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11] +set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11 +set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12] +set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12 +set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13] +set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13 +set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14] +set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14 +set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15] +set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15 +set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16] +set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16 +set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17] +set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17 +set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18] +set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18 +set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19] +set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19 +set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20] +set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20 +set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21] +set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21 +set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22] +set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22 +set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23] +set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23 +set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24] +set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24 +set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25] +set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25 +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26] +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26 +set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27] +set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27 +set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28] +set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28 +set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29] +set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29 +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30] +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30 +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31] +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31 +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0] +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0 +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1] +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1 +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2] +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2 +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3] +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3 +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0] +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0 +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1] +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1 +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2] +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2 +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3] +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3 +set_location_assignment PIN_D28 -to HPS_DDR3_ODT +set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N +set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N +set_location_assignment PIN_D25 -to HPS_DDR3_RZQ +set_location_assignment PIN_E25 -to HPS_DDR3_WE_N +set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK +set_location_assignment PIN_B14 -to HPS_ENET_INT_N +set_location_assignment PIN_A13 -to HPS_ENET_MDC +set_location_assignment PIN_E16 -to HPS_ENET_MDIO +set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0] +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0 +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1] +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1 +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2] +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2 +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3] +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3 +set_location_assignment PIN_J13 -to HPS_ENET_RX_DV +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0] +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0 +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1] +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1 +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2] +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2 +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3] +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3 +set_location_assignment PIN_A12 -to HPS_ENET_TX_EN +set_location_assignment PIN_A17 -to HPS_GSENSOR_INT +set_location_assignment PIN_C18 -to HPS_I2C0_SCLK +set_location_assignment PIN_A19 -to HPS_I2C0_SDAT +set_location_assignment PIN_K18 -to HPS_I2C1_SCLK +set_location_assignment PIN_A21 -to HPS_I2C1_SDAT +set_location_assignment PIN_J18 -to HPS_KEY_N +set_location_assignment PIN_A20 -to HPS_LED +set_location_assignment PIN_H13 -to HPS_LTC_GPIO +set_location_assignment PIN_B8 -to HPS_SD_CLK +set_location_assignment PIN_D14 -to HPS_SD_CMD +set_location_assignment PIN_C13 -to HPS_SD_DATA[0] +set_location_assignment PIN_C13 -to HPS_SD_DATA_0 +set_location_assignment PIN_B6 -to HPS_SD_DATA[1] +set_location_assignment PIN_B6 -to HPS_SD_DATA_1 +set_location_assignment PIN_B11 -to HPS_SD_DATA[2] +set_location_assignment PIN_B11 -to HPS_SD_DATA_2 +set_location_assignment PIN_B9 -to HPS_SD_DATA[3] +set_location_assignment PIN_B9 -to HPS_SD_DATA_3 +set_location_assignment PIN_C19 -to HPS_SPIM_CLK +set_location_assignment PIN_B19 -to HPS_SPIM_MISO +set_location_assignment PIN_B16 -to HPS_SPIM_MOSI +set_location_assignment PIN_C16 -to HPS_SPIM_SS +set_location_assignment PIN_A22 -to HPS_UART_RX +set_location_assignment PIN_B21 -to HPS_UART_TX +set_location_assignment PIN_G4 -to HPS_USB_CLKOUT +set_location_assignment PIN_C10 -to HPS_USB_DATA[0] +set_location_assignment PIN_C10 -to HPS_USB_DATA_0 +set_location_assignment PIN_F5 -to HPS_USB_DATA[1] +set_location_assignment PIN_F5 -to HPS_USB_DATA_1 +set_location_assignment PIN_C9 -to HPS_USB_DATA[2] +set_location_assignment PIN_C9 -to HPS_USB_DATA_2 +set_location_assignment PIN_C4 -to HPS_USB_DATA[3] +set_location_assignment PIN_C4 -to HPS_USB_DATA_3 +set_location_assignment PIN_C8 -to HPS_USB_DATA[4] +set_location_assignment PIN_C8 -to HPS_USB_DATA_4 +set_location_assignment PIN_D4 -to HPS_USB_DATA[5] +set_location_assignment PIN_D4 -to HPS_USB_DATA_5 +set_location_assignment PIN_C7 -to HPS_USB_DATA[6] +set_location_assignment PIN_C7 -to HPS_USB_DATA_6 +set_location_assignment PIN_F4 -to HPS_USB_DATA[7] +set_location_assignment PIN_F4 -to HPS_USB_DATA_7 +set_location_assignment PIN_E5 -to HPS_USB_DIR +set_location_assignment PIN_D5 -to HPS_USB_NXT +set_location_assignment PIN_C5 -to HPS_USB_STP + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY_N +#============================================================ +set_location_assignment PIN_AH17 -to KEY_N[0] +set_location_assignment PIN_AH17 -to KEY_N_0 +set_location_assignment PIN_AH16 -to KEY_N[1] +set_location_assignment PIN_AH16 -to KEY_N_1 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_W15 -to LED_0 +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_AA24 -to LED_1 +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V16 -to LED_2 +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_V15 -to LED_3 +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AF26 -to LED_4 +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_AE26 -to LED_5 +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_Y16 -to LED_6 +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_AA23 -to LED_7 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7 + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_L10 -to SW[0] +set_location_assignment PIN_L10 -to SW_0 +set_location_assignment PIN_L9 -to SW[1] +set_location_assignment PIN_L9 -to SW_1 +set_location_assignment PIN_H6 -to SW[2] +set_location_assignment PIN_H6 -to SW_2 +set_location_assignment PIN_H5 -to SW[3] +set_location_assignment PIN_H5 -to SW_3 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3 + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_V12 -to PIO_INT_N +set_location_assignment PIN_AE11 -to PIO_SCL +set_location_assignment PIN_AE12 -to PIO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA + +set_location_assignment PIN_AF7 -to PIR_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT + +set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA +set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL +set_location_assignment PIN_T11 -to CAM_SYS_CLK +set_location_assignment PIN_AG6 -to CAM_LV +set_location_assignment PIN_AH2 -to CAM_PIX_CLK +set_location_assignment PIN_AE4 -to CAM_FV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV + +set_location_assignment PIN_Y8 -to PAL_VD_HSO +set_location_assignment PIN_AB4 -to PAL_VD_VSO +set_location_assignment PIN_AG5 -to PAL_VD_VD[0] +set_location_assignment PIN_AG5 -to PAL_VD_VD_0 +set_location_assignment PIN_AH5 -to PAL_VD_VD[1] +set_location_assignment PIN_AH5 -to PAL_VD_VD_1 +set_location_assignment PIN_AH6 -to PAL_VD_VD[2] +set_location_assignment PIN_AH6 -to PAL_VD_VD_2 +set_location_assignment PIN_T8 -to PAL_VD_VD[3] +set_location_assignment PIN_T8 -to PAL_VD_VD_3 +set_location_assignment PIN_T12 -to PAL_VD_VD[4] +set_location_assignment PIN_T12 -to PAL_VD_VD_4 +set_location_assignment PIN_Y5 -to PAL_VD_VD[5] +set_location_assignment PIN_Y5 -to PAL_VD_VD_5 +set_location_assignment PIN_Y4 -to PAL_VD_VD[6] +set_location_assignment PIN_Y4 -to PAL_VD_VD_6 +set_location_assignment PIN_W8 -to PAL_VD_VD[7] +set_location_assignment PIN_W8 -to PAL_VD_VD_7 +set_location_assignment PIN_AH4 -to PAL_VD_CLKO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO + +set_location_assignment PIN_AH3 -to SERVO_0 +set_location_assignment PIN_AF4 -to SERVO_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1 + +set_location_assignment PIN_AD12 -to J0_SPI_CLK +set_location_assignment PIN_AD11 -to J0_SPI_MISO +set_location_assignment PIN_AF9 -to J0_SPI_CS_N +set_location_assignment PIN_AD10 -to J0_SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI + +set_location_assignment PIN_AF5 -to FROM_ESP_TXD +set_location_assignment PIN_T13 -to TO_ESP_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD + +set_location_assignment PIN_AE7 -to SPI_MISO +set_location_assignment PIN_AF6 -to SPI_ENA_N +set_location_assignment PIN_AE8 -to SPI_CLK +set_location_assignment PIN_AE9 -to SPI_MOSI +set_location_assignment PIN_AF10 -to SPI_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT + +set_location_assignment PIN_AF11 -to LED_BGR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_AA15 -to RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N + +set_location_assignment PIN_AG28 -to TS_SCL +set_location_assignment PIN_AH27 -to TS_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA + +set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N +set_location_assignment PIN_AG26 -to LCD_DE +set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN + +set_location_assignment PIN_AH24 -to BLT_TXD +set_location_assignment PIN_AE22 -to BLT_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD + +set_location_assignment PIN_AG20 -to BOARD_ID +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID + +set_location_assignment PIN_AF21 -to VIDEO_HSYNC +set_location_assignment PIN_AG19 -to VIDEO_VSYNC +set_location_assignment PIN_AF20 -to VIDEO_CLK +set_location_assignment PIN_AG23 -to VIDEO_B[0] +set_location_assignment PIN_AG23 -to VIDEO_B_0 +set_location_assignment PIN_AH23 -to VIDEO_B[1] +set_location_assignment PIN_AH23 -to VIDEO_B_1 +set_location_assignment PIN_AF25 -to VIDEO_B[2] +set_location_assignment PIN_AF25 -to VIDEO_B_2 +set_location_assignment PIN_AG24 -to VIDEO_B[3] +set_location_assignment PIN_AG24 -to VIDEO_B_3 +set_location_assignment PIN_AA19 -to VIDEO_B[4] +set_location_assignment PIN_AA19 -to VIDEO_B_4 +set_location_assignment PIN_AH26 -to VIDEO_B[5] +set_location_assignment PIN_AH26 -to VIDEO_B_5 +set_location_assignment PIN_AG18 -to VIDEO_B[6] +set_location_assignment PIN_AG18 -to VIDEO_B_6 +set_location_assignment PIN_AC23 -to VIDEO_B[7] +set_location_assignment PIN_AC23 -to VIDEO_B_7 +set_location_assignment PIN_AH22 -to VIDEO_G[0] +set_location_assignment PIN_AH22 -to VIDEO_G_0 +set_location_assignment PIN_AF22 -to VIDEO_G[1] +set_location_assignment PIN_AF22 -to VIDEO_G_1 +set_location_assignment PIN_AD20 -to VIDEO_G[2] +set_location_assignment PIN_AD20 -to VIDEO_G_2 +set_location_assignment PIN_AE24 -to VIDEO_G[3] +set_location_assignment PIN_AE24 -to VIDEO_G_3 +set_location_assignment PIN_AE20 -to VIDEO_G[4] +set_location_assignment PIN_AE20 -to VIDEO_G_4 +set_location_assignment PIN_AD19 -to VIDEO_G[5] +set_location_assignment PIN_AD19 -to VIDEO_G_5 +set_location_assignment PIN_AF18 -to VIDEO_G[6] +set_location_assignment PIN_AF18 -to VIDEO_G_6 +set_location_assignment PIN_AE19 -to VIDEO_G[7] +set_location_assignment PIN_AE19 -to VIDEO_G_7 +set_location_assignment PIN_AC22 -to VIDEO_R[0] +set_location_assignment PIN_AC22 -to VIDEO_R_0 +set_location_assignment PIN_AA18 -to VIDEO_R[1] +set_location_assignment PIN_AA18 -to VIDEO_R_1 +set_location_assignment PIN_AE23 -to VIDEO_R[2] +set_location_assignment PIN_AE23 -to VIDEO_R_2 +set_location_assignment PIN_AD23 -to VIDEO_R[3] +set_location_assignment PIN_AD23 -to VIDEO_R_3 +set_location_assignment PIN_AH18 -to VIDEO_R[4] +set_location_assignment PIN_AH18 -to VIDEO_R_4 +set_location_assignment PIN_AG21 -to VIDEO_R[5] +set_location_assignment PIN_AG21 -to VIDEO_R_5 +set_location_assignment PIN_AH21 -to VIDEO_R[6] +set_location_assignment PIN_AH21 -to VIDEO_R_6 +set_location_assignment PIN_AH19 -to VIDEO_R[7] +set_location_assignment PIN_AH19 -to VIDEO_R_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7 diff --git a/cs309-psoc/lab_2_1/hw/quartus/lab_2_1.sdc b/cs309-psoc/lab_2_1/hw/quartus/lab_2_1.sdc new file mode 100644 index 0000000..16a41f3 --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/quartus/lab_2_1.sdc @@ -0,0 +1,6 @@ +create_clock -period 20 [get_ports FPGA_CLK1_50] +create_clock -period 20 [get_ports FPGA_CLK2_50] +create_clock -period 20 [get_ports FPGA_CLK3_50] + +derive_pll_clocks +derive_clock_uncertainty diff --git a/cs309-psoc/lab_2_1/hw/quartus/soc_system.qsys b/cs309-psoc/lab_2_1/hw/quartus/soc_system.qsys new file mode 100644 index 0000000..810f01e --- /dev/null +++ b/cs309-psoc/lab_2_1/hw/quartus/soc_system.qsys @@ -0,0 +1,731 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + NO_INTERACTIVE_WINDOWS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + soc_system_onchip_memory2_0 + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_2_1/lab_2_1.pdf b/cs309-psoc/lab_2_1/lab_2_1.pdf new file mode 100644 index 0000000..84dfa07 Binary files /dev/null and b/cs309-psoc/lab_2_1/lab_2_1.pdf differ diff --git a/cs309-psoc/lab_2_1/sw/nios/application/app.c b/cs309-psoc/lab_2_1/sw/nios/application/app.c new file mode 100644 index 0000000..717f62b --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/app.c @@ -0,0 +1,31 @@ +#include +#include +#include +#include + +#include "lepton/lepton.h" +#include "system.h" + +int main(void) { + // Hardware control structures + lepton_dev lepton = lepton_inst((void *) LEPTON_0_BASE); + + // Initialize hardware + lepton_init(&lepton); + + // ========================================================================= + + + do { + lepton_start_capture(&lepton); + lepton_wait_until_eof(&lepton); + } while(lepton_error_check(&lepton)); + + // + // ========================================================================= + + // Save the adjusted (rescaled) buffer to a file. + lepton_save_capture(&lepton, true, "/mnt/host/output.pgm"); + + return EXIT_SUCCESS; +} diff --git a/cs309-psoc/lab_2_1/sw/nios/application/joysticks/joysticks.c b/cs309-psoc/lab_2_1/sw/nios/application/joysticks/joysticks.c new file mode 100644 index 0000000..d4742e3 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/joysticks/joysticks.c @@ -0,0 +1,79 @@ +#include "joysticks.h" + +#define JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL (0) +#define JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL (1) +#define JOYSTICK_LEFT_VRY_MCP3204_CHANNEL (2) +#define JOYSTICK_LEFT_VRX_MCP3204_CHANNEL (3) + +/** + * joysticks_inst + * + * Instantiate a joysticks device structure. + * + * @param base Base address of the MCP3204 component connected to the joysticks. + */ +joysticks_dev joysticks_inst(void *mcp3204_base) { + joysticks_dev dev; + dev.mcp3204 = mcp3204_inst((void *) mcp3204_base); + + return dev; +} + +/** + * joysticks_init + * + * Initializes the joysticks device. + * + * @param dev joysticks device structure. + */ +void joysticks_init(joysticks_dev *dev) { + mcp3204_init(&(dev->mcp3204)); +} + +/** + * joysticks_read_left_vertical + * + * Returns the vertical position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,LV_CHANNEL); +} + +/** + * joysticks_read_left_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204,LH_CHANNEL); +} + +/** + * joysticks_read_right_vertical + * + * Returns the vertical position of the right joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,RV_CHANNEL); +} + +/** + * joysticks_read_right_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204,RH_CHANNEL); +} diff --git a/cs309-psoc/lab_2_1/sw/nios/application/joysticks/joysticks.h b/cs309-psoc/lab_2_1/sw/nios/application/joysticks/joysticks.h new file mode 100644 index 0000000..b43c174 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/joysticks/joysticks.h @@ -0,0 +1,33 @@ +#ifndef __JOYSTICKS_H__ +#define __JOYSTICKS_H__ + +#include "mcp3204/mcp3204.h" + +/* joysticks device structure */ +typedef struct joysticks_dev { + mcp3204_dev mcp3204; /* MCP3204 device handle */ +} joysticks_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define JOYSTICKS_MIN_VALUE (MCP3204_MIN_VALUE) +#define JOYSTICKS_MAX_VALUE (MCP3204_MAX_VALUE) + +#define LV_CHANNEL 0 +#define LH_CHANNEL 1 +#define RV_CHANNEL 2 +#define RH_CHANNEL 3 +#define CC_CHANNEL "this is a joke" + +joysticks_dev joysticks_inst(void *mcp3204_base); + +void joysticks_init(joysticks_dev *dev); + +uint32_t joysticks_read_left_vertical(joysticks_dev *dev); +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev); +uint32_t joysticks_read_right_vertical(joysticks_dev *dev); +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev); + +#endif /* __JOYSTICKS_H__ */ diff --git a/cs309-psoc/lab_2_1/sw/nios/application/joysticks/mcp3204/mcp3204.c b/cs309-psoc/lab_2_1/sw/nios/application/joysticks/mcp3204/mcp3204.c new file mode 100644 index 0000000..a827962 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/joysticks/mcp3204/mcp3204.c @@ -0,0 +1,50 @@ +#include +#include + +#include "mcp3204.h" +#include "mcp3204_regs.h" + +#define MCP3204_NUM_CHANNELS (4) + +/** + * mcp3204_inst + * + * Instantiate a mcp3204 device structure. + * + * @param base Base address of the component. + */ +mcp3204_dev mcp3204_inst(void *base) { + mcp3204_dev dev; + dev.base = base; + + return dev; +} + +/** + * mcp3204_init + * + * Initializes the mcp3204 device. + * + * @param dev mcp3204 device structure. + */ +void mcp3204_init(mcp3204_dev *dev) { + return; +} + +/** + * mcp3204_read + * + * Reads the register corresponding to the supplied channel parameter. + * + * @param dev mcp3204 device structure. + * @param channel channel to be read + */ +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) { + switch(channel){ + case 0: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_0_OFST); + case 1: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_1_OFST); + case 2: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_2_OFST); + case 3: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_3_OFST); + default: return 0; + } +} diff --git a/cs309-psoc/lab_2_1/sw/nios/application/joysticks/mcp3204/mcp3204.h b/cs309-psoc/lab_2_1/sw/nios/application/joysticks/mcp3204/mcp3204.h new file mode 100644 index 0000000..3b2b2e6 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/joysticks/mcp3204/mcp3204.h @@ -0,0 +1,23 @@ +#ifndef __MCP3204_H__ +#define __MCP3204_H__ + +#include + +/* mcp3204 device structure */ +typedef struct mcp3204_dev { + void *base; /* Base address of component */ +} mcp3204_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define MCP3204_MIN_VALUE (0) +#define MCP3204_MAX_VALUE (4095) + +mcp3204_dev mcp3204_inst(void *base); + +void mcp3204_init(mcp3204_dev *dev); +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel); + +#endif /* __MCP3204_H__ */ diff --git a/cs309-psoc/lab_2_1/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h b/cs309-psoc/lab_2_1/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h new file mode 100644 index 0000000..b1c78cd --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/joysticks/mcp3204/mcp3204_regs.h @@ -0,0 +1,9 @@ +#ifndef __MCP3204_REGS_H__ +#define __MCP3204_REGS_H__ + +#define MCP3204_CHANNEL_0_OFST (0 * 4) /* RO */ +#define MCP3204_CHANNEL_1_OFST (1 * 4) /* RO */ +#define MCP3204_CHANNEL_2_OFST (2 * 4) /* RO */ +#define MCP3204_CHANNEL_3_OFST (3 * 4) /* RO */ + +#endif /* __MCP3204_REGS_H__ */ diff --git a/cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton.c b/cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton.c new file mode 100644 index 0000000..75d706d --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton.c @@ -0,0 +1,118 @@ +#include +#include +#include +#include +#include + +#include "lepton_regs.h" +#include "lepton.h" + +/** + * lepton_inst + * + * Instantiate a lepton device structure. + * + * @param base Base address of the component. + */ +lepton_dev lepton_inst(void *base) { + lepton_dev dev; + dev.base = base; + + return dev; +} + +/** + * lepton_init + * + * Initializes the lepton device. + * + * @param dev lepton device structure. + */ +void lepton_init(lepton_dev *dev) { + return; +} + +/** + * lepton_start_capture + * + * Instructs the device to start the frame capture process. + * + * @param dev lepton device structure. + */ +void lepton_start_capture(lepton_dev *dev) { + IOWR_16DIRECT(dev->base, LEPTON_REGS_COMMAND_OFST, 0x1); +} + +/** + * lepton_error_check + * + * @abstract Check for errors at the device level. + * @param dev lepton device structure. + * @return true if there was an error, and false otherwise. + */ +bool lepton_error_check(lepton_dev *dev) { + return (IORD_16DIRECT(dev->base, LEPTON_REGS_STATUS_OFST) & 0x2) != 0; +} + +/** + * lepton_wait_until_eof + * + * Waits until the frame being captured has been fully received and saved in the + * internal memory. + * + * @param dev lepton device structure. + */ +void lepton_wait_until_eof(lepton_dev *dev) { + while (IORD_16DIRECT(dev->base, LEPTON_REGS_STATUS_OFST) & 0x1); +} + +/** + * lepton_save_capture + * + * Saves the captured frame on the host filesystem under the supplied filename. + * The frame will be saved in PGM format. + * + * @param dev lepton device structure. + * @param adjusted Setting this parameter to false will cause RAW sensor data to + * be written to the file. + * Setting this parameter to true will cause a preprocessed image + * (with a stretched dynamic range) to be saved to the file. + * + * @param fname the output file name. + */ +void lepton_save_capture(lepton_dev *dev, bool adjusted, const char *fname) { + FILE *fp = fopen(fname, "w"); + assert(fp); + + const uint8_t num_rows = 60; + const uint8_t num_cols = 80; + + uint16_t offset = LEPTON_REGS_RAW_BUFFER_OFST; + uint16_t max_value = IORD_16DIRECT(dev->base, LEPTON_REGS_MAX_OFST); + if (adjusted) { + offset = LEPTON_REGS_ADJUSTED_BUFFER_OFST; + max_value = 0x3fff; + } + + /* Write PGM header */ + fprintf(fp, "P2\n%" PRIu8 " %" PRIu8 "\n%" PRIu16, num_cols, num_rows, max_value); + + /* Write body */ + uint8_t row = 0; + for (row = 0; row < num_rows; ++row) { + fprintf(fp, "\n"); + + uint8_t col = 0; + for (col = 0; col < num_cols; ++col) { + if (col > 0) { + fprintf(fp, " "); + } + + uint16_t current_ofst = offset + (row * num_cols + col) * sizeof(uint16_t); + uint16_t pix_value = IORD_16DIRECT(dev->base, current_ofst); + fprintf(fp, "%" PRIu16, pix_value); + } + } + + assert(!fclose(fp)); +} diff --git a/cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton.h b/cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton.h new file mode 100644 index 0000000..cf197d2 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton.h @@ -0,0 +1,23 @@ +#ifndef __LEPTON_H__ +#define __LEPTON_H__ + +#include + +/* lepton device structure */ +typedef struct { + void *base; /* Base address of the component */ +} lepton_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +lepton_dev lepton_inst(void *base); + +void lepton_init(lepton_dev *dev); +void lepton_start_capture(lepton_dev *dev); +void lepton_wait_until_eof(lepton_dev *dev); +bool lepton_error_check(lepton_dev *dev); +void lepton_save_capture(lepton_dev *dev, bool adjusted, const char *fname); + +#endif /* __LEPTON_H__ */ diff --git a/cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton_regs.h b/cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton_regs.h new file mode 100644 index 0000000..db24244 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton_regs.h @@ -0,0 +1,25 @@ +#ifndef __LEPTON_REGS_H__ +#define __LEPTON_REGS_H__ + +/* Register offsets */ +#define LEPTON_REGS_COMMAND_OFST ( 0 * 2) /* WO */ +#define LEPTON_REGS_STATUS_OFST ( 1 * 2) /* RO */ +#define LEPTON_REGS_MIN_OFST ( 2 * 2) /* RO */ +#define LEPTON_REGS_MAX_OFST ( 3 * 2) /* RO */ +#define LEPTON_REGS_SUM_LSB_OFST ( 4 * 2) /* RO */ +#define LEPTON_REGS_SUM_MSB_OFST ( 5 * 2) /* RO */ +#define LEPTON_REGS_ROW_IDX_OFST ( 6 * 2) /* RO */ +#define LEPTON_REGS_RAW_BUFFER_OFST ( 8 * 2) /* RO */ +#define LEPTON_REGS_ADJUSTED_BUFFER_OFST (8192 * 2) /* RO */ + +/* Command register */ +#define LEPTON_COMMAND_START (0x0001) + +/* Status register */ +#define LEPTON_STATUS_CAPTURE_IN_PROGRESS_MASK (1 << 0) +#define LEPTON_STATUS_ERROR_MASK (1 << 1) + +#define LEPTON_REGS_BUFFER_NUM_PIXELS (80 * 60) +#define LEPTON_REGS_BUFFER_BYTELENGTH (LEPTON_REGS_BUFFER_NUM_PIXELS * 2) + +#endif /* __LEPTON_REGS_H__ */ diff --git a/cs309-psoc/lab_2_1/sw/nios/application/output_bottle.pgm b/cs309-psoc/lab_2_1/sw/nios/application/output_bottle.pgm new file mode 100644 index 0000000..5669932 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/output_bottle.pgm @@ -0,0 +1,63 @@ +P2 +80 60 +16383 +11667 11607 11546 11335 11063 11093 11032 10730 10458 10549 10398 10367 10186 10126 10035 9944 10156 10518 11728 13904 16383 15143 13934 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4861 4312 3993 4185 4338 3955 3725 3725 4146 4963 4899 4516 4312 3866 3687 3610 3572 3508 2334 2156 3508 3534 3725 3381 3496 4555 4720 4759 4733 4082 1148 816 740 \ No newline at end of file diff --git a/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pantilt.c b/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pantilt.c new file mode 100644 index 0000000..d9c4c72 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pantilt.c @@ -0,0 +1,109 @@ +#include "pantilt.h" + +/** + * pantilt_inst + * + * Instantiate a pantilt device structure. + * + * @param pwm_v_base Base address of the vertical PWM component. + * @param pwm_h_base Base address of the horizontal PWM component. + */ +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) { + pantilt_dev dev; + dev.pwm_v = pwm_inst(pwm_v_base); + dev.pwm_h = pwm_inst(pwm_h_base); + + return dev; +} + +/** + * pantilt_init + * + * Initializes the pantilt device. + * + * @param dev pantilt device structure. + */ +void pantilt_init(pantilt_dev *dev) { + pwm_init(&(dev->pwm_v)); + pwm_init(&(dev->pwm_h)); +} + +/** + * pantilt_configure_vertical + * + * Configure the vertical PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_v), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_configure_horizontal + * + * Configure the horizontal PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_h), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_start_vertical + * + * Starts the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_vertical(pantilt_dev *dev) { + pwm_start(&(dev->pwm_v)); +} + +/** + * pantilt_start_horizontal + * + * Starts the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_horizontal(pantilt_dev *dev) { + pwm_start(&(dev->pwm_h)); +} + +/** + * pantilt_stop_vertical + * + * Stops the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_vertical(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_v)); +} + +/** + * pantilt_stop_horizontal + * + * Stops the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_horizontal(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_h)); +} diff --git a/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pantilt.h b/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pantilt.h new file mode 100644 index 0000000..1f17500 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pantilt.h @@ -0,0 +1,39 @@ +#ifndef __PANTILT_H__ +#define __PANTILT_H__ + +#include "pwm/pwm.h" + +/* joysticks device structure */ +typedef struct pantilt_dev { + pwm_dev pwm_v; /* Vertical PWM device handle */ + pwm_dev pwm_h; /* Horizontal PWM device handle */ +} pantilt_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz + +#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms + +/* Vertical servo */ +#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms +#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms + +/* Horizontal servo */ +#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms +#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms + +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base); + +void pantilt_init(pantilt_dev *dev); + +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_start_vertical(pantilt_dev *dev); +void pantilt_start_horizontal(pantilt_dev *dev); +void pantilt_stop_vertical(pantilt_dev *dev); +void pantilt_stop_horizontal(pantilt_dev *dev); + +#endif /* __PANTILT_H__ */ diff --git a/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm.c b/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm.c new file mode 100644 index 0000000..293be53 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm.c @@ -0,0 +1,71 @@ +#include + +#include "pwm.h" +#include "pwm_regs.h" + +#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000)) + + +/** + * pwm_inst + * + * Instantiate a pwm device structure. + * + * @param base Base address of the component. + */ +pwm_dev pwm_inst(void *base) { + pwm_dev dev; + + dev.base = base; + + return dev; +} + +/** + * pwm_init + * + * Initializes the pwm device. This function stops the controller. + * + * @param dev pwm device structure. + */ +void pwm_init(pwm_dev *dev) { + pwm_stop(dev); +} + +/** + * pwm_configure + * + * Configure pwm component. + * + * @param dev pwm device structure. + * @param duty_cycle pwm duty cycle in us. + * @param period pwm period in us. + * @param module_frequency frequency at which the component is clocked. + */ +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) { + + IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency)); + IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency)); +} + +/** + * pwm_start + * + * Starts the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_start(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} + +/** + * pwm_stop + * + * Stops the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_stop(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK); +} diff --git a/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm.h b/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm.h new file mode 100644 index 0000000..e2987f4 --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm.h @@ -0,0 +1,21 @@ +#ifndef __PWM_H__ +#define __PWM_H__ + +#include + +/* pwm device structure */ +typedef struct pwm_dev { + void *base; /* Base address of component */ +} pwm_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ +pwm_dev pwm_inst(void *base); + +void pwm_init(pwm_dev *dev); +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency); +void pwm_start(pwm_dev *dev); +void pwm_stop(pwm_dev *dev); + +#endif /* __PWM_H__ */ diff --git a/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm_regs.h b/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm_regs.h new file mode 100644 index 0000000..488583d --- /dev/null +++ b/cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm_regs.h @@ -0,0 +1,11 @@ +#ifndef __PWM_REGS_H__ +#define __PWM_REGS_H__ + +#define PWM_PERIOD_OFST (0 * 4) /* RW */ +#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */ +#define PWM_CTRL_OFST (2 * 4) /* WO */ + +#define PWM_CTRL_STOP_MASK (0) +#define PWM_CTRL_START_MASK (1) + +#endif /* __PWM_REGS_H__ */ diff --git a/cs309-psoc/lab_3_0/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd b/cs309-psoc/lab_3_0/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd new file mode 100644 index 0000000..d56414a --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd @@ -0,0 +1,172 @@ +-- ############################################################################# +-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +-- +-- BOARD : PrSoC extension board for DE0-Nano-SoC +-- Author : Florian Depraz based on Sahand Kashani-Akhavan work +-- Revision : 1.1 +-- Creation date : 06/02/2016 +-- +-- Syntax Rule : GROUP_NAME_N[bit] +-- +-- GROUP : specify a particular interface (ex: SDR_) +-- NAME : signal name (ex: CONFIG, D, ...) +-- bit : signal index +-- _N : to specify an active-low signal +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; + +entity DE0_Nano_SoC_PrSoC_extn_board_top_level is + port( + ------------------------------- + -- Comment ALL unused ports. -- + ------------------------------- + + -- CLOCK + FPGA_CLK1_50 : in std_logic; + -- FPGA_CLK2_50 : in std_logic; + -- FPGA_CLK3_50 : in std_logic; + + -- KEY on DE0 Nano SoC + KEY_N : in std_logic_vector(1 downto 0); + + -- LEDs on DE0 Nano SoC + -- LED : out std_logic_vector(7 downto 0); + + -- SWITCHES on DE0 Nano SoC + -- SW : in std_logic_vector(3 downto 0); + + -- Servomotors pwm + SERVO_0 : out std_logic; + SERVO_1 : out std_logic; + + -- ADC Joysticks + J0_SPI_CS_n : out std_logic; + J0_SPI_MOSI : out std_logic; + J0_SPI_MISO : in std_logic; + J0_SPI_CLK : out std_logic; + + -- Lepton + CAM_TH_SPI_CS_N : out std_logic; + CAM_TH_MISO : in std_logic; + CAM_TH_MOSI : out std_logic; + CAM_TH_CLK : out std_logic; + + -- PCA9637 + -- PIO_SCL : inout std_logic; + -- PIO_SDA : inout std_logic; + -- PIO_INT_N : in std_logic; + -- RESET_N : out std_logic; + + -- OV7670 + -- CAM_D : in std_logic_vector(9 downto 0); + -- CAM_PIX_CLK : in std_logic; + -- CAM_LV : in std_logic; + -- CAM_FV : in std_logic; + -- CAM_SYS_CLK : out std_logic; + + -- VGA and LCD shared signals + -- VIDEO_CLK : out std_logic; + -- VIDEO_VSYNC : out std_logic; + -- VIDEO_HSYNC : out std_logic; + -- VIDEO_B : out std_logic_vector(7 downto 0); + -- VIDEO_G : out std_logic_vector(7 downto 0); + -- VIDEO_R : out std_logic_vector(7 downto 0); + + -- LCD Specific signals + -- LCD_DE : out std_logic; + -- LCD_PIN_DAV_N : ? ?? std_logic; + -- LCD_DISPLAY_EN : out std_logic; + -- SPI_MISO : in std_logic; + -- SPI_ENA_N : out std_logic; + -- SPI_CLK : out std_logic; + -- SPI_MOSI : out std_logic; + -- SPI_DAT : inout std_logic; + + -- I2C TOUCH SCREEN + -- TS_SCL : inout std_logic; + -- TS_SDA : inout std_logic; + + -- BLUETOOTH (BLE) + -- BLT_TXD : in std_logic; + -- BLT_RXD : out std_logic; + + -- I2C For VGA, PAL and OV7670 cameras + -- CAM_PAL_VGA_SDA : inout std_logic; + -- CAM_PAL_VGA_SCL : inout std_logic; + + -- ONE WIRE + -- BOARD_ID : inout std_logic; + + -- PAL Camera + -- PAL_VD_VD : in std_logic_vector(7 downto 0); + -- PAL_VD_VSO : in std_logic; + -- PAL_VD_HSO : in std_logic; + -- PAL_VD_CLKO : in std_logic; + -- PAL_PWDN : out std_logic; + + -- WIFI + -- FROM_ESP_TXD : in std_logic; + -- TO_ESP_RXD : out std_logic; + + -- LED RGB + -- LED_BGR : out std_logic; + + -- HPS + HPS_CONV_USB_N : inout std_logic; + HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); + HPS_DDR3_BA : out std_logic_vector(2 downto 0); + HPS_DDR3_CAS_N : out std_logic; + HPS_DDR3_CK_N : out std_logic; + HPS_DDR3_CK_P : out std_logic; + HPS_DDR3_CKE : out std_logic; + HPS_DDR3_CS_N : out std_logic; + HPS_DDR3_DM : out std_logic_vector(3 downto 0); + HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); + HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); + HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); + HPS_DDR3_ODT : out std_logic; + HPS_DDR3_RAS_N : out std_logic; + HPS_DDR3_RESET_N : out std_logic; + HPS_DDR3_RZQ : in std_logic; + HPS_DDR3_WE_N : out std_logic; + HPS_ENET_GTX_CLK : out std_logic; + HPS_ENET_INT_N : inout std_logic; + HPS_ENET_MDC : out std_logic; + HPS_ENET_MDIO : inout std_logic; + HPS_ENET_RX_CLK : in std_logic; + HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); + HPS_ENET_RX_DV : in std_logic; + HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); + HPS_ENET_TX_EN : out std_logic; + HPS_GSENSOR_INT : inout std_logic; + HPS_I2C0_SCLK : inout std_logic; + HPS_I2C0_SDAT : inout std_logic; + HPS_I2C1_SCLK : inout std_logic; + HPS_I2C1_SDAT : inout std_logic; + HPS_KEY_N : inout std_logic; + HPS_LED : inout std_logic; + HPS_LTC_GPIO : inout std_logic; + HPS_SD_CLK : out std_logic; + HPS_SD_CMD : inout std_logic; + HPS_SD_DATA : inout std_logic_vector(3 downto 0); + HPS_SPIM_CLK : out std_logic; + HPS_SPIM_MISO : in std_logic; + HPS_SPIM_MOSI : out std_logic; + HPS_SPIM_SS : inout std_logic; + HPS_UART_RX : in std_logic; + HPS_UART_TX : out std_logic; + HPS_USB_CLKOUT : in std_logic; + HPS_USB_DATA : inout std_logic_vector(7 downto 0); + HPS_USB_DIR : in std_logic; + HPS_USB_NXT : in std_logic; + HPS_USB_STP : out std_logic + ); +end entity DE0_Nano_SoC_PrSoC_extn_board_top_level; + +architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is + +begin + +end; diff --git a/cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204.vhd b/cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204.vhd new file mode 100644 index 0000000..af0aafb --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204.vhd @@ -0,0 +1,138 @@ +-- ############################################################################# +-- mcp3204.vhd +-- =========== +-- MCP3204 Avalon-MM slave interface. +-- +-- Register map +-- +-------+-----------+--------+------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +-------+-----------+--------+------------------------------------+ +-- | 0 | CHANNEL_0 | RO | 12-bit digital value of channel 0. | +-- +-------+-----------+--------+------------------------------------+ +-- | 1 | CHANNEL_1 | RO | 12-bit digital value of channel 1. | +-- +-------+-----------+--------+------------------------------------+ +-- | 2 | CHANNEL_2 | RO | 12-bit digital value of channel 2. | +-- +-------+-----------+--------+------------------------------------+ +-- | 3 | CHANNEL_3 | RO | 12-bit digital value of channel 3. | +-- +-------+-----------+--------+------------------------------------+ +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity mcp3204 is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + readdata : out std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic; + SCLK : out std_logic + ); +end entity; + +architecture arch of mcp3204 is + constant NUM_CHANNELS : positive := 4; + constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS)))); + + type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range); + signal data_reg : data_array; + + signal spi_busy, spi_start, spi_datavalid : std_logic; + signal spi_channel : std_logic_vector(1 downto 0); + signal spi_data : std_logic_vector(11 downto 0); + + type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA); + signal state : state_t; + + signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0); + +begin + SPI : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => spi_busy, + start => spi_start, + channel => spi_channel, + data_valid => spi_datavalid, + data => spi_data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + -- FSM that dictates which channel is being read. The state of the component + -- should be thought as the pair (state, channel) + p_fsm : process(reset, clk) + begin + if reset = '1' then + state <= READY; + channel <= (others => '0'); + elsif rising_edge(clk) then + case state is + when READY => + if spi_busy = '0' then + state <= INIT_READ_CHANNEL; + end if; + + when INIT_READ_CHANNEL => + state <= WAIT_FOR_DATA; + + when WAIT_FOR_DATA => + if spi_datavalid = '1' then + state <= READY; + channel <= channel + 1; + end if; + end case; + end if; + end process p_fsm; + + -- Updates the internal registers when a new data is available + p_data : process(reset, clk) + begin + if reset = '1' then + for i in 0 to NUM_CHANNELS - 1 loop + data_reg(i) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + if state = WAIT_FOR_DATA and spi_datavalid = '1' then + data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data; + end if; + end if; + end process p_data; + + spi_start <= '1' when state = INIT_READ_CHANNEL else '0'; + spi_channel <= std_logic_vector(channel); + + -- Interface with the Avalon Switch Fabric + p_avalon_read : process(reset, clk) + begin + if reset = '1' then + readdata <= (others => '0'); + elsif rising_edge(clk) then + if read = '1' then + readdata <= data_reg(to_integer(unsigned(address))); + end if; + end if; + end process p_avalon_read; + +end architecture; diff --git a/cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl b/cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl new file mode 100644 index 0000000..757514d --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl @@ -0,0 +1,137 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 18:14:06 CET 2017 +# DO NOT MODIFY + + +# +# mcp3204 "mcp3204" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.18:14:06 +# 4-Channel 12-Bit A/D Converter with SPI Serial Interface +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module mcp3204 +# +set_module_property DESCRIPTION "4-Channel 12-Bit A/D Converter with SPI Serial Interface" +set_module_property NAME mcp3204 +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Joystick +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME mcp3204 +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL mcp3204 +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file mcp3204.vhd VHDL PATH mcp3204.vhd TOP_LEVEL_FILE +add_fileset_file mcp3204_spi.vhd VHDL PATH mcp3204_spi.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end CS_N cs_n Output 1 +add_interface_port conduit_end MOSI mosi Output 1 +add_interface_port conduit_end MISO miso Input 1 +add_interface_port conduit_end SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd b/cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd new file mode 100644 index 0000000..f5e072e --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd @@ -0,0 +1,87 @@ +-- ############################################################################# +-- mcp3204_spi.vhd +-- =============== +-- MCP3204 SPI interface. +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Author : () +-- Revision : 1 +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mcp3204_spi is + port( + -- 50 MHz + clk : in std_logic; + reset : in std_logic; + busy : out std_logic; + start : in std_logic; + channel : in std_logic_vector(1 downto 0); + data_valid : out std_logic; + data : out std_logic_vector(11 downto 0); + + -- 1 MHz + SCLK : out std_logic; + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); +end mcp3204_spi; + +architecture rtl of mcp3204_spi is + signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24 + signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz + signal reg_rising_edge_sclk : std_logic := '0'; + signal reg_falling_edge_sclk : std_logic := '0'; + + signal reg_sclk : std_logic := '0'; + +begin + clk_divider_generation : process(clk, reset) + begin + if reset = '1' then + reg_clk_divider_counter <= (others => '0'); + elsif rising_edge(clk) then + reg_clk_divider_counter <= reg_clk_divider_counter + 1; + reg_spi_en <= '0'; + reg_rising_edge_sclk <= '0'; + reg_falling_edge_sclk <= '0'; + + if reg_clk_divider_counter = 24 then + reg_clk_divider_counter <= (others => '0'); + reg_spi_en <= '1'; + + if reg_sclk = '0' then + reg_rising_edge_sclk <= '1'; + elsif reg_sclk = '1' then + reg_falling_edge_sclk <= '1'; + end if; + end if; + end if; + end process; + + SCLK_generation : process(clk, reset) + begin + if reset = '1' then + reg_sclk <= '0'; + elsif rising_edge(clk) then + if reg_spi_en = '1' then + reg_sclk <= not reg_sclk; + end if; + end if; + end process; + + STATE_LOGIC : process(clk, reset) + begin + -- TODO: complete this process + if reset = '1' then + elsif rising_edge(clk) then + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_3_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd b/cs309-psoc/lab_3_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd new file mode 100644 index 0000000..1bb61d2 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd @@ -0,0 +1,103 @@ +-- ############################################################################# +-- tb_mcp3204_spi.vhd +-- ================== +-- Testbench for MCP3204 SPI interface. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 1 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_mcp3204_spi is +end entity; + +architecture rtl of tb_mcp3204_spi is + constant CLK_PERIOD : time := 20 ns; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal sim_finished : boolean := false; + + -- mcp3204_spi ------------------------------------------------------------ + signal busy : std_logic := '0'; + signal start : std_logic := '0'; + signal channel : std_logic_vector(1 downto 0) := (others => '0'); + signal data_valid : std_logic := '0'; + signal data : std_logic_vector(11 downto 0) := (others => '0'); + signal SCLK : std_logic := '0'; + signal CS_N : std_logic := '1'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '0'; + +begin + duv : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => busy, + start => start, + channel => channel, + data_valid => data_valid, + data => data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_finished; + + sim : process + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + reset <= '1'; + + wait for CLK_PERIOD / 2; + reset <= '0'; + end procedure async_reset; + + procedure spi_transfer(constant channel_number : natural range 0 to 3) is + begin + if busy = '1' then + wait until busy = '0'; + + else + wait until falling_edge(clk); + start <= '1'; + channel <= std_logic_vector(to_unsigned(channel_number, channel'length)); + + wait until falling_edge(clk); + start <= '0'; + channel <= (others => '0'); + + wait until rising_edge(data_valid); + wait until falling_edge(busy); + end if; + end procedure spi_transfer; + + begin + async_reset; + + MISO <= '1'; + spi_transfer(0); + + MISO <= '0'; + spi_transfer(1); + + MISO <= '1'; + spi_transfer(2); + + MISO <= '0'; + spi_transfer(3); + + sim_finished <= true; + wait; + end process sim; +end architecture rtl; + + diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd new file mode 100644 index 0000000..9769bb8 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd @@ -0,0 +1,139 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.utils.all; + +entity avalon_st_spi_master is + generic( + INPUT_CLK_FREQ : integer := 50000000; + SPI_SCLK_FREQ : integer := 10000000; + CPOL : integer := 1; + CPHA : integer := 1 + ); + port( + -- Input clock + clk : in std_logic; + + -- Reset + reset : in std_logic; + spi_cs_n : in std_logic; + -- Sink Avalon ST Interface + mosi_sink_data : in std_logic_vector(7 downto 0); + mosi_sink_valid : in std_logic; + mosi_sink_ready : out std_logic; + + -- Source Avalon ST Interface + miso_src_data : out std_logic_vector(7 downto 0); + miso_src_valid : out std_logic; + + -- SPI Master signals + SCLK : out std_logic; + MISO : in std_logic; + MOSI : out std_logic; + CS_n : out std_logic + ); +end avalon_st_spi_master; + +architecture rtl of avalon_st_spi_master is + constant SCLK_PRESCALER_MAX : integer := INPUT_CLK_FREQ / SPI_SCLK_FREQ / 2; + signal sclk_prescaler : unsigned(bitlength(SCLK_PRESCALER_MAX) downto 0); + signal sclk_toggle : std_logic; + + signal new_sink_buffer, cur_sink_buffer : std_logic_vector(mosi_sink_data'range); + signal new_sink_buffer_busy, cur_sink_buffer_busy : std_logic; + + signal miso_src_buffer : std_logic_vector(7 downto 0); + + signal spi_done, i_sclk : std_logic; + signal spi_bit_index : unsigned(2 downto 0); +begin + CS_n <= spi_cs_n; + + p_sclk_prescaler : process(clk, reset) is + begin + if reset = '1' then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + elsif rising_edge(clk) then + if sclk_prescaler = SCLK_PRESCALER_MAX then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + else + sclk_prescaler <= sclk_prescaler + 1; + end if; + end if; + end process p_sclk_prescaler; + sclk_toggle <= '1' when sclk_prescaler = SCLK_PRESCALER_MAX else '0'; + + p_avalon_st_sink : process(clk, reset) is + begin + if reset = '1' then + new_sink_buffer_busy <= '0'; + new_sink_buffer <= (others => '0'); + elsif rising_edge(clk) then + if mosi_sink_valid = '1' then + if new_sink_buffer_busy = '0' and cur_sink_buffer_busy = '1' then + new_sink_buffer <= mosi_sink_data; + new_sink_buffer_busy <= '1'; + end if; + elsif new_sink_buffer_busy = '1' and cur_sink_buffer_busy = '0' then + new_sink_buffer_busy <= '0'; + end if; + end if; + end process p_avalon_st_sink; + mosi_sink_ready <= not new_sink_buffer_busy; + + p_cur_buffer : process(clk, reset) is + begin + if reset = '1' then + cur_sink_buffer <= (others => '0'); + cur_sink_buffer_busy <= '0'; + elsif rising_edge(clk) then + if mosi_sink_valid = '1' and cur_sink_buffer_busy = '0' then + cur_sink_buffer <= mosi_sink_data; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '0' and new_sink_buffer_busy = '1' then + cur_sink_buffer <= new_sink_buffer; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '1' and spi_done = '1' then + cur_sink_buffer_busy <= '0'; + end if; + end if; + end process p_cur_buffer; + + p_spi : process(clk, reset) is + begin + if reset = '1' then + spi_done <= '0'; + i_sclk <= to_unsigned(CPOL, 1)(0); + spi_bit_index <= "000"; + MOSI <= '0'; + miso_src_data <= (others => '0'); + miso_src_valid <= '0'; + miso_src_buffer <= (others => '0'); + + elsif rising_edge(clk) then + spi_done <= '0'; + miso_src_valid <= '0'; + if cur_sink_buffer_busy = '1' and sclk_toggle = '1' then + if i_sclk /= to_unsigned(CPHA, 1)(0) then + if spi_bit_index = "111" then + spi_done <= '1'; + spi_bit_index <= "000"; + miso_src_valid <= '1'; + miso_src_data <= miso_src_buffer(7 downto 1) & MISO; + else + MOSI <= cur_sink_buffer(7 - to_integer(spi_bit_index)); + miso_src_buffer(7 - to_integer(spi_bit_index)) <= MISO; + spi_bit_index <= spi_bit_index + 1; + + end if; + + end if; + + i_sclk <= not i_sclk; + + end if; + end if; + end process p_spi; + SCLK <= i_sclk; + +end rtl; diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/byte2pix.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/byte2pix.vhd new file mode 100644 index 0000000..b888ba9 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/byte2pix.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------- +-- Title : Byte stream to pixel converter for the Lepton Camera +-- Project : PrSoC +------------------------------------------------------------------------------- +-- File : byte2pix.vhd +-- Author : Philemon Orphee Favrod +-- Company : +-- Created : 2016-03-21 +-- Last update: 2017-03-19 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: Converts a byte stream to a 14-bit pixel stream. +------------------------------------------------------------------------------- +-- Copyright (c) 2016 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2016-03-21 1.0 pofavrod Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity byte2pix is + port( + clk, reset : in std_logic; + byte_data : in std_logic_vector(7 downto 0); + byte_valid : in std_logic; + byte_sof : in std_logic; + byte_eof : in std_logic; + pix_data : out std_logic_vector(13 downto 0); + pix_valid : out std_logic; + pix_sof : out std_logic; + pix_eof : out std_logic); + +end byte2pix; + +architecture rtl of byte2pix is + signal last_sof : std_logic; + signal msb : std_logic_vector(5 downto 0); + signal cnt : std_logic; -- used to skip msb sampling every other time +begin + process(clk, reset) + begin + if reset = '1' then + msb <= (others => '0'); + cnt <= '0'; + last_sof <= '0'; + elsif rising_edge(clk) then + if byte_valid = '1' then + if cnt = '0' then + msb <= byte_data(5 downto 0); + last_sof <= byte_sof; + end if; + cnt <= not cnt; + end if; + end if; + end process; + + process(clk, reset) + begin + if reset = '1' then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + elsif rising_edge(clk) then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + + if byte_valid = '1' then + if cnt = '1' then + pix_data <= msb & byte_data; + pix_valid <= '1'; + pix_sof <= last_sof; + pix_eof <= byte_eof; + end if; + end if; + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd new file mode 100644 index 0000000..d4b4812 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd @@ -0,0 +1,192 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: dual_ported_ram.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +entity dual_ported_ram is + port( + clock : in std_logic := '1'; + data : in std_logic_vector(15 downto 0); + rdaddress : in std_logic_vector(12 downto 0); + wraddress : in std_logic_vector(12 downto 0); + wren : in std_logic := '0'; + q : out std_logic_vector(15 downto 0) + ); +end dual_ported_ram; + +architecture SYN of dual_ported_ram is + signal sub_wire0 : std_logic_vector(15 downto 0); + +begin + q <= sub_wire0(15 downto 0); + + altsyncram_component : altsyncram + generic map( + address_aclr_b => "NONE", + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 8192, + numwords_b => 8192, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "CLOCK0", + power_up_uninitialized => "FALSE", + read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => 13, + widthad_b => 13, + width_a => 16, + width_b => 16, + width_byteena_a => 1 + ) + port map( + address_a => wraddress, + address_b => rdaddress, + clock0 => clock, + data_a => data, + wren_a => wren, + q_b => sub_wire0 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]" +-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 +-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton.vhd new file mode 100644 index 0000000..82678ba --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton.vhd @@ -0,0 +1,288 @@ +-- Lepton Avalon Memory-Mapped Slave Interface +-- Author: Philémon Favrod (philemon.favrod@epfl.ch) +-- Modified by: Sahand Kashani-Akhavan (sahand.kashani-akhavan@epfl.ch) +-- Revision: 2 + +-- Register map +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 0 | COMMAND | WO | Command | +-- | | | | - Writing 1 starts capturing a frame & resets the | +-- | | | | ERROR bit (bit 1) in the STATUS register. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 1 | STATUS | RO | Status | +-- | | | | - Bit 0: 0 --> no capture in progress. | +-- | | | | 1 --> capture in progress. | +-- | | | | - Bit 1: 0 --> previous capture successful. | +-- | | | | 1 --> error during previous capture. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 2 | MIN | RO | Minimum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 3 | MAX | RO | Maximum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4 | SUM_LSB | RO | Sum of all pixels in frame (low 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 5 | SUM_MSB | RO | Sum of all pixels in frame (high 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 6 | ROW_IDX | RO | Current line being captured (1 <= ROW_IDX <= 60). | +-- | | | | Available for debugging purposes. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 7 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8 - 4807 | RAW BUFFER | RO | View into RAW pixel buffer. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4808 - 8191 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8192 - 12991 | ADJUSTED BUFFER | RO | View into adjusted (scaled) pixel buffer. | +-- | | | | Values are scaled between MIN and MAX. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 12992 - 16383 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton is + port( + clk : in std_logic; + reset : in std_logic; + address : in std_logic_vector(13 downto 0); + readdata : out std_logic_vector(15 downto 0); + writedata : in std_logic_vector(15 downto 0); + read : in std_logic; + write : in std_logic; + + SCLK : out std_logic; + CSn : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); + +end lepton; + +architecture rtl of lepton is + signal spi_cs_n : std_logic; + signal spi_mosi_data : std_logic_vector(7 downto 0); + signal spi_mosi_valid : std_logic; + signal spi_mosi_ready : std_logic; + signal spi_miso_data : std_logic_vector(7 downto 0); + signal spi_miso_valid : std_logic; + signal lepton_manager_start : std_logic; + signal lepton_manager_error : std_logic; + signal byte_data : std_logic_vector(7 downto 0); + signal byte_valid : std_logic; + signal byte_sof : std_logic; + signal byte_eof : std_logic; + signal pix_data : std_logic_vector(13 downto 0); + signal pix_valid : std_logic; + signal pix_sof : std_logic; + signal pix_eof : std_logic; + signal stat_min : std_logic_vector(13 downto 0); + signal stat_max : std_logic_vector(13 downto 0); + signal stat_sum : std_logic_vector(26 downto 0); + signal stat_valid : std_logic; + signal ram_data : std_logic_vector(15 downto 0); + signal ram_wren : std_logic; + signal ram_wraddress : std_logic_vector(12 downto 0); + signal ram_rdaddress : std_logic_vector(12 downto 0); + signal ram_q : std_logic_vector(15 downto 0); + signal row_idx : std_logic_vector(5 downto 0); + signal raw_pixel : std_logic_vector(13 downto 0); + signal raw_max : std_logic_vector(13 downto 0); + signal raw_min : std_logic_vector(13 downto 0); + signal raw_sum : std_logic_vector(26 downto 0); + signal adjusted_pixel : std_logic_vector(13 downto 0); + + constant COMMAND_REG_OFFSET : std_logic_vector(address'range) := "00000000000000"; + constant STATUS_REG_OFFSET : std_logic_vector(address'range) := "00000000000001"; + constant MIN_REG_OFFSET : std_logic_vector(address'range) := "00000000000010"; + constant MAX_REG_OFFSET : std_logic_vector(address'range) := "00000000000011"; + constant SUM_LSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000100"; + constant SUM_MSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000101"; + constant ROW_IDX_REG_OFFSET : std_logic_vector(address'range) := "00000000000110"; + constant BUFFER_REG_OFFSET : unsigned(address'range) := "00000000001000"; + constant ADJUSTED_BUFFER_REG_OFFSET : unsigned(address'range) := "10000000000000"; + + constant IMAGE_SIZE : integer := 80 * 60; + constant BUFFER_REG_LIMIT : unsigned(address'range) := unsigned(BUFFER_REG_OFFSET) + IMAGE_SIZE; + + constant ADJUSTED_BUFFER_LIMIT : unsigned(address'range) := unsigned(ADJUSTED_BUFFER_REG_OFFSET) + IMAGE_SIZE; + + signal max_reg : std_logic_vector(stat_max'range); + signal min_reg : std_logic_vector(stat_min'range); + signal sum_reg : std_logic_vector(stat_sum'range); + signal error_reg : std_logic; + +begin + spi_controller0 : entity work.avalon_st_spi_master + port map( + clk => clk, + reset => reset, + spi_cs_n => spi_cs_n, + mosi_sink_data => spi_mosi_data, + mosi_sink_valid => spi_mosi_valid, + mosi_sink_ready => spi_mosi_ready, + miso_src_data => spi_miso_data, + miso_src_valid => spi_miso_valid, + SCLK => SCLK, + MISO => MISO, + MOSI => MOSI, + CS_n => CSn + ); + + lepton_manager0 : entity work.lepton_manager + port map( + clk => clk, + reset => reset, + spi_miso_sink_data => spi_miso_data, + spi_miso_sink_valid => spi_miso_valid, + spi_mosi_src_data => spi_mosi_data, + spi_mosi_src_valid => spi_mosi_valid, + spi_mosi_src_ready => spi_mosi_ready, + lepton_out_data => byte_data, + lepton_out_valid => byte_valid, + lepton_out_sof => byte_sof, + lepton_out_eof => byte_eof, + row_idx => row_idx, + error => lepton_manager_error, + start => lepton_manager_start, + spi_cs_n => spi_cs_n + ); + + byte2pix0 : entity work.byte2pix + port map( + clk => clk, + reset => reset, + byte_data => byte_data, + byte_valid => byte_valid, + byte_sof => byte_sof, + byte_eof => byte_eof, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof + ); + + lepton_stats0 : entity work.lepton_stats + port map( + reset => reset, + clk => clk, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + stat_min => stat_min, + stat_max => stat_max, + stat_sum => stat_sum, + stat_valid => stat_valid + ); + + ram_writer0 : entity work.ram_writer + port map( + clk => clk, + reset => reset, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + ram_data => ram_data, + ram_wren => ram_wren, + ram_wraddress => ram_wraddress + ); + + dual_ported_ram0 : entity work.dual_ported_ram + port map( + clock => clk, + data => ram_data, + rdaddress => ram_rdaddress, + wraddress => ram_wraddress, + wren => ram_wren, + q => ram_q + ); + + level_adjuster0 : entity work.level_adjuster + port map( + clk => clk, + raw_pixel => ram_q(13 downto 0), + raw_max => max_reg, + raw_min => min_reg, + raw_sum => sum_reg, + adjusted_pixel => adjusted_pixel + ); + + p_lepton_start : process(clk, reset) + begin + if reset = '1' then + lepton_manager_start <= '0'; + error_reg <= '0'; + elsif rising_edge(clk) then + if write = '1' and address = COMMAND_REG_OFFSET then + lepton_manager_start <= writedata(0); + error_reg <= '0'; + elsif pix_eof = '1' then + lepton_manager_start <= '0'; + elsif lepton_manager_error = '1' then + error_reg <= '1'; + end if; + end if; + end process p_lepton_start; + + p_stat_reg : process(clk, reset) + begin + if reset = '1' then + min_reg <= (others => '0'); + max_reg <= (others => '0'); + sum_reg <= (others => '0'); + elsif rising_edge(clk) then + if stat_valid = '1' then + min_reg <= stat_min; + max_reg <= stat_max; + sum_reg <= stat_sum; + end if; + end if; + end process p_stat_reg; + + p_read : process(clk, reset) + begin + if reset = '1' then + readdata <= (others => '0'); + ram_rdaddress <= (others => '0'); + elsif rising_edge(clk) then + readdata <= (others => '0'); + if read = '1' then + case address is + when STATUS_REG_OFFSET => + readdata(1) <= error_reg; + readdata(0) <= lepton_manager_start; + + when MIN_REG_OFFSET => + readdata <= "00" & min_reg; + + when MAX_REG_OFFSET => + readdata <= "00" & max_reg; + + when SUM_MSB_REG_OFFSET => + readdata <= "00000" & sum_reg(26 downto 16); + + when SUM_LSB_REG_OFFSET => + readdata <= sum_reg(15 downto 0); + + when ROW_IDX_REG_OFFSET => + readdata(5 downto 0) <= row_idx; + + when others => + if unsigned(address) >= BUFFER_REG_OFFSET and unsigned(address) < BUFFER_REG_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= ram_q; + elsif unsigned(address) >= ADJUSTED_BUFFER_REG_OFFSET and unsigned(address) < ADJUSTED_BUFFER_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - ADJUSTED_BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= "00" & adjusted_pixel; + end if; + end case; + end if; + end if; + end process p_read; + +end rtl; diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_hw.tcl b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_hw.tcl new file mode 100644 index 0000000..d62e01b --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_hw.tcl @@ -0,0 +1,148 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 19:05:24 CET 2017 +# DO NOT MODIFY + + +# +# lepton "lepton" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.19:05:24 +# IR Camera 80x60 +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module lepton +# +set_module_property DESCRIPTION "IR Camera 80x60" +set_module_property NAME lepton +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Camera +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME lepton +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL lepton +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file avalon_st_spi_master.vhd VHDL PATH avalon_st_spi_master.vhd +add_fileset_file byte2pix.vhd VHDL PATH byte2pix.vhd +add_fileset_file dual_ported_ram.vhd VHDL PATH dual_ported_ram.vhd +add_fileset_file lepton.vhd VHDL PATH lepton.vhd TOP_LEVEL_FILE +add_fileset_file lepton_manager.vhd VHDL PATH lepton_manager.vhd +add_fileset_file lepton_stats.vhd VHDL PATH lepton_stats.vhd +add_fileset_file ram_writer.vhd VHDL PATH ram_writer.vhd +add_fileset_file utils.vhd VHDL PATH utils.vhd +add_fileset_file level_adjuster.vhd VHDL PATH level_adjuster.vhd +add_fileset_file lpm_divider.vhd VHDL PATH lpm_divider.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitStates 9 +set_interface_property avalon_slave_0 readWaitTime 9 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 14 +add_interface_port avalon_slave_0 readdata readdata Output 16 +add_interface_port avalon_slave_0 writedata writedata Input 16 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point spi +# +add_interface spi conduit end +set_interface_property spi associatedClock clock +set_interface_property spi associatedReset "" +set_interface_property spi ENABLED true +set_interface_property spi EXPORT_OF "" +set_interface_property spi PORT_NAME_MAP "" +set_interface_property spi CMSIS_SVD_VARIABLES "" +set_interface_property spi SVD_ADDRESS_GROUP "" + +add_interface_port spi CSn cs_n Output 1 +add_interface_port spi MISO miso Input 1 +add_interface_port spi MOSI mosi Output 1 +add_interface_port spi SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_manager.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_manager.vhd new file mode 100644 index 0000000..1580be1 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_manager.vhd @@ -0,0 +1,235 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_manager is + generic( + INPUT_CLK_FREQ : integer := 50000000); + port( + clk : in std_logic := '0'; + reset : in std_logic := '0'; + + -- Avalon ST Sink to receive SPI data + spi_miso_sink_data : in std_logic_vector(7 downto 0); + spi_miso_sink_valid : in std_logic; + + -- Avalon ST Source to send SPI data + spi_mosi_src_data : out std_logic_vector(7 downto 0); + spi_mosi_src_valid : out std_logic; + spi_mosi_src_ready : in std_logic := '0'; + + -- Filtered output to retransmit cleaned data (without the discard packets, see Lepton Datasheet on page 31) + -- lepton_out_data is valid on rising edge when lepton_src_valid = '1' + lepton_out_data : out std_logic_vector(7 downto 0); + lepton_out_valid : out std_logic; + lepton_out_sof : out std_logic; + lepton_out_eof : out std_logic; + + -- Some status + row_idx : out std_logic_vector(5 downto 0); + error : out std_logic; + + -- Avalon MM Slave interface for configuration + start : in std_logic; + + -- The SPI Chip Select (Active low !) + spi_cs_n : out std_logic := '0'); +end entity lepton_manager; + +architecture rtl of lepton_manager is + type state_t is (Idle, CSn, ReadHeader, ReadPayload, DiscardPayload, WaitBeforeIdle); + signal state, next_state : state_t; + + signal header_3_last_nibbles : std_logic_vector(11 downto 0); + + constant CLOCK_TICKS_PER_37_MS : integer := 37 * (INPUT_CLK_FREQ / 1e3); -- the timeout delay for a frame + constant CLOCK_TICKS_PER_200_MS : integer := 200 * (INPUT_CLK_FREQ / 1e3); + constant CLOCK_TICKS_PER_200_NS : integer := (200 * (INPUT_CLK_FREQ / 1e6)) / 1e3; + constant BYTES_PER_HEADER : integer := 4; + constant BYTES_PER_PAYLOAD : integer := 160; + + constant NUMBER_OF_LINES_PER_FRAME : positive := 60; + signal counter, counter_max : integer range 1 to CLOCK_TICKS_PER_200_MS; + signal line_counter : integer range 1 to NUMBER_OF_LINES_PER_FRAME; + signal timeout_counter : integer range 1 to CLOCK_TICKS_PER_37_MS; + signal counter_enabled : boolean; + signal waited_long_enough : boolean; + signal header_end, payload_end : boolean; +begin + + -- purpose: register for state + p_fsm : process(clk, reset) + begin + if reset = '1' then + state <= Idle; + elsif rising_edge(clk) then + state <= next_state; + end if; + end process p_fsm; + + -- purpose: compute the next state + p_nsl : process(header_3_last_nibbles, header_end, payload_end, start, spi_miso_sink_valid, state, waited_long_enough, line_counter) + begin + next_state <= state; + + case state is + when Idle => + if waited_long_enough and start = '1' then + next_state <= CSn; + end if; + + when CSn => + if waited_long_enough then + next_state <= ReadHeader; + end if; + + when ReadHeader => + if header_end then + if header_3_last_nibbles(11 downto 8) = X"F" then + next_state <= DiscardPayload; + else + next_state <= ReadPayload; + end if; + end if; + + when DiscardPayload | ReadPayload => + if payload_end then + next_state <= ReadHeader; + + if line_counter = NUMBER_OF_LINES_PER_FRAME then + next_state <= WaitBeforeIdle; + end if; + end if; + + when WaitBeforeIdle => + if spi_miso_sink_valid = '1' then + next_state <= Idle; + end if; + + end case; + end process p_nsl; + + p_counter : process(clk, reset) + begin + if reset = '1' then + counter <= 1; + line_counter <= 1; + elsif rising_edge(clk) then + if counter = counter_max and counter_enabled then + counter <= 1; + + if state = ReadPayload then + if line_counter = NUMBER_OF_LINES_PER_FRAME then + line_counter <= 1; + else + line_counter <= line_counter + 1; + end if; + end if; + + elsif counter_enabled then + counter <= counter + 1; + end if; + end if; + end process p_counter; + + p_error : process(clk, reset) + begin + if reset = '1' then + error <= '0'; + timeout_counter <= 1; + elsif rising_edge(clk) then + if state /= ReadHeader and state /= ReadPayload and state /= ReadHeader then + timeout_counter <= 1; + error <= '0'; + else + if timeout_counter = CLOCK_TICKS_PER_37_MS then + error <= '1'; + else + timeout_counter <= timeout_counter + 1; + end if; + end if; + if state = ReadPayload and header_3_last_nibbles /= std_logic_vector(to_unsigned(line_counter - 1, header_3_last_nibbles'length)) then + error <= '1'; + end if; + end if; + end process p_error; + + -- purpose: wire the datapath + p_datapath : process(counter, counter_enabled, counter_max, line_counter, spi_miso_sink_data, spi_miso_sink_valid, spi_mosi_src_ready, state) + variable counter_ended : boolean; + + begin + counter_max <= 1; + counter_enabled <= true; + waited_long_enough <= false; + lepton_out_data <= (others => '0'); + lepton_out_valid <= '0'; + lepton_out_sof <= '0'; + lepton_out_eof <= '0'; + spi_mosi_src_valid <= '0'; + spi_mosi_src_data <= (others => '0'); + spi_cs_n <= '0'; + header_end <= false; + payload_end <= false; + + counter_ended := (counter = counter_max and counter_enabled); + + case state is + when Idle => + counter_max <= CLOCK_TICKS_PER_200_MS; + waited_long_enough <= counter_ended; + spi_cs_n <= '1'; + + when CSn => + counter_max <= CLOCK_TICKS_PER_200_NS; + waited_long_enough <= counter_ended; + + when ReadHeader => + counter_max <= BYTES_PER_HEADER; + counter_enabled <= spi_miso_sink_valid = '1'; + header_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when ReadPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + lepton_out_data <= spi_miso_sink_data; + lepton_out_valid <= spi_miso_sink_valid; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + if spi_miso_sink_valid = '1' then + if counter = 1 and counter_enabled and line_counter = 1 then + lepton_out_sof <= '1'; + elsif counter_ended and line_counter = NUMBER_OF_LINES_PER_FRAME then + lepton_out_eof <= '1'; + end if; + end if; + + when DiscardPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when others => null; + end case; + end process p_datapath; + + p_capture_header : process(clk, reset) + begin + if reset = '1' then + header_3_last_nibbles <= X"000"; + elsif rising_edge(clk) then + if state = ReadHeader and spi_miso_sink_valid = '1' then + if counter = 1 then + header_3_last_nibbles(11 downto 8) <= spi_miso_sink_data(3 downto 0); + elsif counter = 2 then + header_3_last_nibbles(7 downto 0) <= spi_miso_sink_data; + end if; + end if; + end if; + end process p_capture_header; + + row_idx <= std_logic_vector(to_unsigned(line_counter, row_idx'length)); + +end architecture rtl; diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_stats.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_stats.vhd new file mode 100644 index 0000000..6e060df --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_stats.vhd @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_stats is + port( + clk : in std_logic; + reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + stat_min : out std_logic_vector(13 downto 0); + stat_max : out std_logic_vector(13 downto 0); + stat_sum : out std_logic_vector(26 downto 0); + stat_valid : out std_logic); +end lepton_stats; + +architecture rtl of lepton_stats is +begin + -- TODO : complete this architecture +end rtl; diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/level_adjuster.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/level_adjuster.vhd new file mode 100644 index 0000000..0169af1 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/level_adjuster.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity level_adjuster is + port( + clk : in std_logic; + raw_pixel : in std_logic_vector(13 downto 0); + raw_max : in std_logic_vector(13 downto 0); + raw_min : in std_logic_vector(13 downto 0); + raw_sum : in std_logic_vector(26 downto 0); + adjusted_pixel : out std_logic_vector(13 downto 0)); +end level_adjuster; + +architecture rtl of level_adjuster is + component lpm_divider + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0)); + end component; + +begin + -- TODO : complete this architecture +end rtl; diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lpm_divider.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lpm_divider.vhd new file mode 100644 index 0000000..f8de4a6 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lpm_divider.vhd @@ -0,0 +1,133 @@ +-- megafunction wizard: %LPM_DIVIDE% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_DIVIDE + +-- ============================================================ +-- File Name: lpm_divider.vhd +-- Megafunction Name(s): +-- LPM_DIVIDE +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library lpm; +use lpm.all; + +entity lpm_divider is + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); +end lpm_divider; + +architecture SYN of lpm_divider is + signal sub_wire0 : std_logic_vector(27 downto 0); + signal sub_wire1 : std_logic_vector(13 downto 0); + + component lpm_divide + generic( + lpm_drepresentation : string; + lpm_hint : string; + lpm_nrepresentation : string; + lpm_pipeline : natural; + lpm_type : string; + lpm_widthd : natural; + lpm_widthn : natural + ); + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); + end component; + +begin + quotient <= sub_wire0(27 downto 0); + remain <= sub_wire1(13 downto 0); + + LPM_DIVIDE_component : LPM_DIVIDE + generic map( + lpm_drepresentation => "UNSIGNED", + lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE", + lpm_nrepresentation => "UNSIGNED", + lpm_pipeline => 5, + lpm_type => "LPM_DIVIDE", + lpm_widthd => 14, + lpm_widthn => 28 + ) + port map( + clock => clock, + denom => denom, + numer => numer, + quotient => sub_wire0, + remain => sub_wire1 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" +-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1" +-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" +-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" +-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "14" +-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "28" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: denom 0 0 14 0 INPUT NODEFVAL "denom[13..0]" +-- Retrieval info: USED_PORT: numer 0 0 28 0 INPUT NODEFVAL "numer[27..0]" +-- Retrieval info: USED_PORT: quotient 0 0 28 0 OUTPUT NODEFVAL "quotient[27..0]" +-- Retrieval info: USED_PORT: remain 0 0 14 0 OUTPUT NODEFVAL "remain[13..0]" +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @denom 0 0 14 0 denom 0 0 14 0 +-- Retrieval info: CONNECT: @numer 0 0 28 0 numer 0 0 28 0 +-- Retrieval info: CONNECT: quotient 0 0 28 0 @quotient 0 0 28 0 +-- Retrieval info: CONNECT: remain 0 0 14 0 @remain 0 0 14 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/ram_writer.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/ram_writer.vhd new file mode 100644 index 0000000..8912cdb --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/ram_writer.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram_writer is + port( + clk, reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + ram_data : out std_logic_vector(15 downto 0); + ram_wren : out std_logic; + ram_wraddress : out std_logic_vector(12 downto 0)); + +end ram_writer; + +architecture rtl of ram_writer is + signal wraddress_counter : unsigned(ram_wraddress'range); +begin + p_address_gen : process(clk, reset) + begin + if reset = '1' then + wraddress_counter <= (others => '0'); + elsif rising_edge(clk) then + if pix_eof = '1' then + wraddress_counter <= (others => '0'); + elsif pix_valid = '1' then + wraddress_counter <= wraddress_counter + 1; + end if; + end if; + end process p_address_gen; + + ram_data <= "00" & pix_data; + ram_wren <= pix_valid; + ram_wraddress <= std_logic_vector(wraddress_counter); + +end rtl; diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/utils.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/utils.vhd new file mode 100644 index 0000000..83105ad --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/utils.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package utils is + function bitlength(number : positive) return positive; + +end package utils; + +package body utils is + + -- purpose: returns the minimum # of bits needed to represent the input number + function bitlength(number : positive) return positive is + variable acc : positive := 1; + variable i : natural := 0; + begin + while True loop + if acc > number then + return i; + end if; + + acc := acc * 2; + i := i + 1; + end loop; + end function bitlength; + +end package body utils; diff --git a/cs309-psoc/lab_3_0/hw/hdl/lepton/tb/lepton_tb.vhd b/cs309-psoc/lab_3_0/hw/hdl/lepton/tb/lepton_tb.vhd new file mode 100644 index 0000000..f134613 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/lepton/tb/lepton_tb.vhd @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity lepton_tb is +end lepton_tb; + +architecture tb of lepton_tb is + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal address : std_logic_vector(13 downto 0) := (others => '0'); + signal readdata : std_logic_vector(15 downto 0) := (others => '0'); + signal writedata : std_logic_vector(15 downto 0) := (others => '0'); + signal read : std_logic := '0'; + signal write : std_logic := '0'; + signal SCLK : std_logic := '0'; + signal CSn : std_logic := '0'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '1'; + + constant CLK_PERIOD : time := 20 ns; + + signal sim_ended : boolean := false; + +begin + dut : entity work.lepton + port map( + clk => clk, + reset => reset, + address => address, + readdata => readdata, + writedata => writedata, + read => read, + write => write, + SCLK => SCLK, + CSn => CSn, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_ended else '0'; + + miso_gen : process + variable seed1, seed2 : positive; + variable rand : real; + begin + if sim_ended then + wait; + else + uniform(seed1, seed2, rand); + wait until rising_edge(SCLK); + MISO <= to_unsigned(integer(rand), 1)(0); + + end if; + end process; + + stimuli : process + begin + reset <= '1'; + write <= '0'; + + wait for 2 * CLK_PERIOD; + reset <= '0'; + + wait for CLK_PERIOD; + write <= '1'; + writedata(0) <= '1'; + wait for CLK_PERIOD; + write <= '0'; + + wait for 17 ms; + sim_ended <= true; + wait; + end process; + +end tb; diff --git a/cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm.vhd b/cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm.vhd new file mode 100644 index 0000000..1b5cdc3 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm.vhd @@ -0,0 +1,42 @@ +-- ############################################################################# +-- pwm.vhd +-- ======= +-- PWM memory-mapped Avalon slave interface. +-- +-- Author : () +-- Author : () +-- Revision : +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity pwm is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + write : in std_logic; + readdata : out std_logic_vector(31 downto 0); + writedata : in std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + pwm_out : out std_logic + ); +end pwm; + +architecture rtl of pwm is + +begin + +end architecture rtl; diff --git a/cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm_constants.vhd b/cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm_constants.vhd new file mode 100644 index 0000000..bfff03b --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm_constants.vhd @@ -0,0 +1,61 @@ +-- ############################################################################# +-- pwm_constants.vhd +-- ================= +-- This package contains constants used in the PWM design files. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pwm_constants is + -- Register map + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | RegNo | Name | Access | Description | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW period to apply to the | + -- | | | | next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT period of the | + -- | | | | ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to | + -- | | | | the next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT duty cycle of | + -- | | | | the ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.| + -- | | | | Writing 1 to this register starts the PWM. | + -- | | | | | + -- | | | | >> Reading this register always returns 0. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00"; + constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01"; + constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10"; + + -- Default values of registers after reset (BEFORE writing START to the CTRL + -- register with a new configuration) + constant DEFAULT_PERIOD : natural := 4; + constant DEFAULT_DUTY_CYCLE : natural := 2; +end package pwm_constants; + +package body pwm_constants is + +end package body pwm_constants; diff --git a/cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm_hw.tcl b/cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm_hw.tcl new file mode 100644 index 0000000..df7d92a --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm_hw.tcl @@ -0,0 +1,135 @@ +# TCL File Generated by Component Editor 16.0 +# Tue Feb 28 12:18:00 CET 2017 +# DO NOT MODIFY + + +# +# pwm "pwm" v1.0 +# 2017.02.28.12:18:00 +# Pan-tilt +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module pwm +# +set_module_property DESCRIPTION Pan-tilt +set_module_property NAME pwm +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Pan-tilt +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME pwm +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE +add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +add_interface_port avalon_slave_0 writedata writedata Input 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end pwm_out pwm Output 1 diff --git a/cs309-psoc/lab_3_0/hw/hdl/pantilt/tb/tb_pwm.vhd b/cs309-psoc/lab_3_0/hw/hdl/pantilt/tb/tb_pwm.vhd new file mode 100644 index 0000000..ff2dee7 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/hdl/pantilt/tb/tb_pwm.vhd @@ -0,0 +1,205 @@ +-- ############################################################################# +-- tb_pwm.vhd +-- ========== +-- Testbench for PWM memory-mapped Avalon slave interface. +-- +-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity tb_pwm is +end entity; + +architecture rtl of tb_pwm is + + -- 50 MHz clock + constant CLK_PERIOD : time := 20 ns; + + -- Signal used to end simulator when we finished submitting our test cases + signal sim_finished : boolean := false; + + -- PWM PORTS + signal clk : std_logic; + signal reset : std_logic; + signal address : std_logic_vector(1 downto 0); + signal read : std_logic; + signal write : std_logic; + signal readdata : std_logic_vector(31 downto 0); + signal writedata : std_logic_vector(31 downto 0); + signal pwm_out : std_logic; + + -- Values of registers we are going to use to configure the PWM unit + constant CONFIG_PERIOD : natural := 100; + constant CONFIG_DUTY_CYCLE : natural := 20; + constant CONFIG_CTRL_START : natural := 1; + constant CONFIG_CTRL_STOP : natural := 0; + +begin + + -- Instantiate DUT + dut : entity work.pwm + port map( + clk => clk, + reset => reset, + address => address, + read => read, + write => write, + readdata => readdata, + writedata => writedata, + pwm_out => pwm_out + ); + + -- Generate clk signal + clk_generation : process + begin + if not sim_finished then + clk <= '1'; + wait for CLK_PERIOD / 2; + clk <= '0'; + wait for CLK_PERIOD / 2; + else + wait; + end if; + end process clk_generation; + + -- Test PWM + simulation : process + + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + + reset <= '1'; + wait for CLK_PERIOD / 2; + + reset <= '0'; + wait for CLK_PERIOD / 4; + end procedure async_reset; + + procedure write_register(constant ofst : in std_logic_vector(1 downto 0); + constant val : in natural) is + begin + wait until rising_edge(clk); + + address <= ofst; + write <= '1'; + writedata <= std_logic_vector(to_unsigned(val, writedata'length)); + wait until rising_edge(clk); + + address <= (others => '0'); + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + end procedure write_register; + + procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is + begin + wait until rising_edge(clk); + + address <= ofst; + read <= '1'; + -- The read has a 1 cycle wait-state, so we need to keep the read + -- signal high for 2 clock cycles. + wait until rising_edge(clk); + wait until rising_edge(clk); + + address <= (others => '0'); + read <= '0'; + wait until rising_edge(clk); + end procedure read_register; + + procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0); + constant expected_val : in natural) is + begin + read_register(ofst); + + case ofst is + when REG_PERIOD_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected PERIOD: " & + "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "PERIOD_expected = " & integer'image(expected_val) + severity error; + + when REG_DUTY_CYCLE_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected DUTY_CYCLE: " & + "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "DUTY_CYCLE_expected = " & integer'image(expected_val) + severity error; + + when REG_CTRL_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected CTRL: " & + "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "CTRL_expected = " & integer'image(expected_val) + severity error; + + when others => + null; + end case; + end procedure read_register_check; + + begin + + -- Default values + reset <= '0'; + address <= (others => '0'); + read <= '0'; + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + + -- Reset the circuit + async_reset; + + -- Write desired configuration to PWM Avalon-MM slave. + write_register(REG_PERIOD_OFST, CONFIG_PERIOD); + write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + + -- Read back configuration from PWM Avalon-MM slave. Note that we have + -- not started the PWM unit yet, so the new configuration must not be + -- read back at this point (as per the register map). + read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Start PWM + write_register(REG_CTRL_OFST, CONFIG_CTRL_START); + + -- Wait until PWM pulses for the first time after we sent START. + wait until rising_edge(pwm_out); + + -- Read back configuration from PWM Avalon-MM slave. Now that we have + -- started the PWM unit, we should be able to read back the + -- configuration we wrote (as per the register map). + read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Wait for 2 PWM periods to finish + wait for 2 * CLK_PERIOD * CONFIG_PERIOD; + + -- Stop PWM. + write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP); + + -- Wait for PWM period to finish + wait for 1 * CLK_PERIOD * CONFIG_PERIOD; + + -- Instruct "clk_generation" process to halt execution. + sim_finished <= true; + + -- Make this process wait indefinitely (it will never re-execute from + -- its beginning again). + wait; + end process simulation; +end architecture rtl; + diff --git a/cs309-psoc/lab_3_0/hw/quartus/ip/components.ipx b/cs309-psoc/lab_3_0/hw/quartus/ip/components.ipx new file mode 100644 index 0000000..7536257 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/quartus/ip/components.ipx @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_3_0/hw/quartus/lab_3_0.qpf b/cs309-psoc/lab_3_0/hw/quartus/lab_3_0.qpf new file mode 100644 index 0000000..e983985 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/quartus/lab_3_0.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition +# Date created = 11:03:02 February 05, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.1" +DATE = "11:03:02 February 05, 2016" + +# Revisions + +PROJECT_REVISION = "lab_3_0" diff --git a/cs309-psoc/lab_3_0/hw/quartus/lab_3_0.qsf b/cs309-psoc/lab_3_0/hw/quartus/lab_3_0.qsf new file mode 100644 index 0000000..47370a6 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/quartus/lab_3_0.qsf @@ -0,0 +1,811 @@ +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 + +set_global_assignment -name SMART_RECOMPILE OFF +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level + +set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +set_global_assignment -name SDC_FILE lab_3_0.sdc + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA4U23C6 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO Extention OV7670 CAMERA +#============================================================ +set_location_assignment PIN_AE15 -to CAM_D[0] +set_location_assignment PIN_AE15 -to CAM_D_0 +set_location_assignment PIN_AF17 -to CAM_D[1] +set_location_assignment PIN_AF17 -to CAM_D_1 +set_location_assignment PIN_AH8 -to CAM_D[2] +set_location_assignment PIN_AH8 -to CAM_D_2 +set_location_assignment PIN_AG8 -to CAM_D[3] +set_location_assignment PIN_AG8 -to CAM_D_3 +set_location_assignment PIN_U13 -to CAM_D[4] +set_location_assignment PIN_U13 -to CAM_D_4 +set_location_assignment PIN_U14 -to CAM_D[5] +set_location_assignment PIN_U14 -to CAM_D_5 +set_location_assignment PIN_AG9 -to CAM_D[6] +set_location_assignment PIN_AG9 -to CAM_D_6 +set_location_assignment PIN_AG10 -to CAM_D[7] +set_location_assignment PIN_AG10 -to CAM_D_7 +set_location_assignment PIN_AF13 -to CAM_D[8] +set_location_assignment PIN_AF13 -to CAM_D_8 +set_location_assignment PIN_AG13 -to CAM_D[9] +set_location_assignment PIN_AG13 -to CAM_D_9 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9 + +#============================================================ +# Arduino Extension LEPTON CAMERA THERMAL CAM_TH +#============================================================ +set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N +set_location_assignment PIN_AG16 -to CAM_TH_MOSI +set_location_assignment PIN_AH11 -to CAM_TH_MISO +set_location_assignment PIN_AH12 -to CAM_TH_CLK +set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA +set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL + +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#============================================================ +# HPS +#============================================================ +set_location_assignment PIN_C6 -to HPS_CONV_USB_N +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0] +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0 +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1] +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1 +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2] +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2 +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3] +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3 +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4] +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4 +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5] +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5 +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6] +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6 +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7] +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7 +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8] +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8 +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9] +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9 +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10] +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10 +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11] +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11 +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12] +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12 +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13] +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13 +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14] +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14 +set_location_assignment PIN_A27 -to HPS_DDR3_BA[0] +set_location_assignment PIN_A27 -to HPS_DDR3_BA_0 +set_location_assignment PIN_H25 -to HPS_DDR3_BA[1] +set_location_assignment PIN_H25 -to HPS_DDR3_BA_1 +set_location_assignment PIN_G25 -to HPS_DDR3_BA[2] +set_location_assignment PIN_G25 -to HPS_DDR3_BA_2 +set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N +set_location_assignment PIN_L28 -to HPS_DDR3_CKE +set_location_assignment PIN_N20 -to HPS_DDR3_CK_N +set_location_assignment PIN_N21 -to HPS_DDR3_CK_P +set_location_assignment PIN_L21 -to HPS_DDR3_CS_N +set_location_assignment PIN_G28 -to HPS_DDR3_DM[0] +set_location_assignment PIN_G28 -to HPS_DDR3_DM_0 +set_location_assignment PIN_P28 -to HPS_DDR3_DM[1] +set_location_assignment PIN_P28 -to HPS_DDR3_DM_1 +set_location_assignment PIN_W28 -to HPS_DDR3_DM[2] +set_location_assignment PIN_W28 -to HPS_DDR3_DM_2 +set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3] +set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3 +set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0] +set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0 +set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1] +set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1 +set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2] +set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2 +set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3] +set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3 +set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4] +set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4 +set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5] +set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5 +set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6] +set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6 +set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7] +set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7 +set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8] +set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8 +set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9] +set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9 +set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10] +set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10 +set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11] +set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11 +set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12] +set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12 +set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13] +set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13 +set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14] +set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14 +set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15] +set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15 +set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16] +set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16 +set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17] +set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17 +set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18] +set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18 +set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19] +set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19 +set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20] +set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20 +set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21] +set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21 +set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22] +set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22 +set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23] +set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23 +set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24] +set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24 +set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25] +set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25 +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26] +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26 +set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27] +set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27 +set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28] +set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28 +set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29] +set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29 +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30] +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30 +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31] +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31 +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0] +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0 +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1] +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1 +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2] +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2 +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3] +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3 +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0] +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0 +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1] +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1 +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2] +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2 +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3] +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3 +set_location_assignment PIN_D28 -to HPS_DDR3_ODT +set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N +set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N +set_location_assignment PIN_D25 -to HPS_DDR3_RZQ +set_location_assignment PIN_E25 -to HPS_DDR3_WE_N +set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK +set_location_assignment PIN_B14 -to HPS_ENET_INT_N +set_location_assignment PIN_A13 -to HPS_ENET_MDC +set_location_assignment PIN_E16 -to HPS_ENET_MDIO +set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0] +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0 +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1] +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1 +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2] +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2 +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3] +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3 +set_location_assignment PIN_J13 -to HPS_ENET_RX_DV +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0] +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0 +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1] +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1 +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2] +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2 +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3] +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3 +set_location_assignment PIN_A12 -to HPS_ENET_TX_EN +set_location_assignment PIN_A17 -to HPS_GSENSOR_INT +set_location_assignment PIN_C18 -to HPS_I2C0_SCLK +set_location_assignment PIN_A19 -to HPS_I2C0_SDAT +set_location_assignment PIN_K18 -to HPS_I2C1_SCLK +set_location_assignment PIN_A21 -to HPS_I2C1_SDAT +set_location_assignment PIN_J18 -to HPS_KEY_N +set_location_assignment PIN_A20 -to HPS_LED +set_location_assignment PIN_H13 -to HPS_LTC_GPIO +set_location_assignment PIN_B8 -to HPS_SD_CLK +set_location_assignment PIN_D14 -to HPS_SD_CMD +set_location_assignment PIN_C13 -to HPS_SD_DATA[0] +set_location_assignment PIN_C13 -to HPS_SD_DATA_0 +set_location_assignment PIN_B6 -to HPS_SD_DATA[1] +set_location_assignment PIN_B6 -to HPS_SD_DATA_1 +set_location_assignment PIN_B11 -to HPS_SD_DATA[2] +set_location_assignment PIN_B11 -to HPS_SD_DATA_2 +set_location_assignment PIN_B9 -to HPS_SD_DATA[3] +set_location_assignment PIN_B9 -to HPS_SD_DATA_3 +set_location_assignment PIN_C19 -to HPS_SPIM_CLK +set_location_assignment PIN_B19 -to HPS_SPIM_MISO +set_location_assignment PIN_B16 -to HPS_SPIM_MOSI +set_location_assignment PIN_C16 -to HPS_SPIM_SS +set_location_assignment PIN_A22 -to HPS_UART_RX +set_location_assignment PIN_B21 -to HPS_UART_TX +set_location_assignment PIN_G4 -to HPS_USB_CLKOUT +set_location_assignment PIN_C10 -to HPS_USB_DATA[0] +set_location_assignment PIN_C10 -to HPS_USB_DATA_0 +set_location_assignment PIN_F5 -to HPS_USB_DATA[1] +set_location_assignment PIN_F5 -to HPS_USB_DATA_1 +set_location_assignment PIN_C9 -to HPS_USB_DATA[2] +set_location_assignment PIN_C9 -to HPS_USB_DATA_2 +set_location_assignment PIN_C4 -to HPS_USB_DATA[3] +set_location_assignment PIN_C4 -to HPS_USB_DATA_3 +set_location_assignment PIN_C8 -to HPS_USB_DATA[4] +set_location_assignment PIN_C8 -to HPS_USB_DATA_4 +set_location_assignment PIN_D4 -to HPS_USB_DATA[5] +set_location_assignment PIN_D4 -to HPS_USB_DATA_5 +set_location_assignment PIN_C7 -to HPS_USB_DATA[6] +set_location_assignment PIN_C7 -to HPS_USB_DATA_6 +set_location_assignment PIN_F4 -to HPS_USB_DATA[7] +set_location_assignment PIN_F4 -to HPS_USB_DATA_7 +set_location_assignment PIN_E5 -to HPS_USB_DIR +set_location_assignment PIN_D5 -to HPS_USB_NXT +set_location_assignment PIN_C5 -to HPS_USB_STP + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY_N +#============================================================ +set_location_assignment PIN_AH17 -to KEY_N[0] +set_location_assignment PIN_AH17 -to KEY_N_0 +set_location_assignment PIN_AH16 -to KEY_N[1] +set_location_assignment PIN_AH16 -to KEY_N_1 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_W15 -to LED_0 +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_AA24 -to LED_1 +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V16 -to LED_2 +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_V15 -to LED_3 +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AF26 -to LED_4 +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_AE26 -to LED_5 +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_Y16 -to LED_6 +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_AA23 -to LED_7 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7 + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_L10 -to SW[0] +set_location_assignment PIN_L10 -to SW_0 +set_location_assignment PIN_L9 -to SW[1] +set_location_assignment PIN_L9 -to SW_1 +set_location_assignment PIN_H6 -to SW[2] +set_location_assignment PIN_H6 -to SW_2 +set_location_assignment PIN_H5 -to SW[3] +set_location_assignment PIN_H5 -to SW_3 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3 + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_V12 -to PIO_INT_N +set_location_assignment PIN_AE11 -to PIO_SCL +set_location_assignment PIN_AE12 -to PIO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA + +set_location_assignment PIN_AF7 -to PIR_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT + +set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA +set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL +set_location_assignment PIN_T11 -to CAM_SYS_CLK +set_location_assignment PIN_AG6 -to CAM_LV +set_location_assignment PIN_AH2 -to CAM_PIX_CLK +set_location_assignment PIN_AE4 -to CAM_FV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV + +set_location_assignment PIN_Y8 -to PAL_VD_HSO +set_location_assignment PIN_AB4 -to PAL_VD_VSO +set_location_assignment PIN_AG5 -to PAL_VD_VD[0] +set_location_assignment PIN_AG5 -to PAL_VD_VD_0 +set_location_assignment PIN_AH5 -to PAL_VD_VD[1] +set_location_assignment PIN_AH5 -to PAL_VD_VD_1 +set_location_assignment PIN_AH6 -to PAL_VD_VD[2] +set_location_assignment PIN_AH6 -to PAL_VD_VD_2 +set_location_assignment PIN_T8 -to PAL_VD_VD[3] +set_location_assignment PIN_T8 -to PAL_VD_VD_3 +set_location_assignment PIN_T12 -to PAL_VD_VD[4] +set_location_assignment PIN_T12 -to PAL_VD_VD_4 +set_location_assignment PIN_Y5 -to PAL_VD_VD[5] +set_location_assignment PIN_Y5 -to PAL_VD_VD_5 +set_location_assignment PIN_Y4 -to PAL_VD_VD[6] +set_location_assignment PIN_Y4 -to PAL_VD_VD_6 +set_location_assignment PIN_W8 -to PAL_VD_VD[7] +set_location_assignment PIN_W8 -to PAL_VD_VD_7 +set_location_assignment PIN_AH4 -to PAL_VD_CLKO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO + +set_location_assignment PIN_AH3 -to SERVO_0 +set_location_assignment PIN_AF4 -to SERVO_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1 + +set_location_assignment PIN_AD12 -to J0_SPI_CLK +set_location_assignment PIN_AD11 -to J0_SPI_MISO +set_location_assignment PIN_AF9 -to J0_SPI_CS_N +set_location_assignment PIN_AD10 -to J0_SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI + +set_location_assignment PIN_AF5 -to FROM_ESP_TXD +set_location_assignment PIN_T13 -to TO_ESP_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD + +set_location_assignment PIN_AE7 -to SPI_MISO +set_location_assignment PIN_AF6 -to SPI_ENA_N +set_location_assignment PIN_AE8 -to SPI_CLK +set_location_assignment PIN_AE9 -to SPI_MOSI +set_location_assignment PIN_AF10 -to SPI_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT + +set_location_assignment PIN_AF11 -to LED_BGR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_AA15 -to RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N + +set_location_assignment PIN_AG28 -to TS_SCL +set_location_assignment PIN_AH27 -to TS_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA + +set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N +set_location_assignment PIN_AG26 -to LCD_DE +set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN + +set_location_assignment PIN_AH24 -to BLT_TXD +set_location_assignment PIN_AE22 -to BLT_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD + +set_location_assignment PIN_AG20 -to BOARD_ID +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID + +set_location_assignment PIN_AF21 -to VIDEO_HSYNC +set_location_assignment PIN_AG19 -to VIDEO_VSYNC +set_location_assignment PIN_AF20 -to VIDEO_CLK +set_location_assignment PIN_AG23 -to VIDEO_B[0] +set_location_assignment PIN_AG23 -to VIDEO_B_0 +set_location_assignment PIN_AH23 -to VIDEO_B[1] +set_location_assignment PIN_AH23 -to VIDEO_B_1 +set_location_assignment PIN_AF25 -to VIDEO_B[2] +set_location_assignment PIN_AF25 -to VIDEO_B_2 +set_location_assignment PIN_AG24 -to VIDEO_B[3] +set_location_assignment PIN_AG24 -to VIDEO_B_3 +set_location_assignment PIN_AA19 -to VIDEO_B[4] +set_location_assignment PIN_AA19 -to VIDEO_B_4 +set_location_assignment PIN_AH26 -to VIDEO_B[5] +set_location_assignment PIN_AH26 -to VIDEO_B_5 +set_location_assignment PIN_AG18 -to VIDEO_B[6] +set_location_assignment PIN_AG18 -to VIDEO_B_6 +set_location_assignment PIN_AC23 -to VIDEO_B[7] +set_location_assignment PIN_AC23 -to VIDEO_B_7 +set_location_assignment PIN_AH22 -to VIDEO_G[0] +set_location_assignment PIN_AH22 -to VIDEO_G_0 +set_location_assignment PIN_AF22 -to VIDEO_G[1] +set_location_assignment PIN_AF22 -to VIDEO_G_1 +set_location_assignment PIN_AD20 -to VIDEO_G[2] +set_location_assignment PIN_AD20 -to VIDEO_G_2 +set_location_assignment PIN_AE24 -to VIDEO_G[3] +set_location_assignment PIN_AE24 -to VIDEO_G_3 +set_location_assignment PIN_AE20 -to VIDEO_G[4] +set_location_assignment PIN_AE20 -to VIDEO_G_4 +set_location_assignment PIN_AD19 -to VIDEO_G[5] +set_location_assignment PIN_AD19 -to VIDEO_G_5 +set_location_assignment PIN_AF18 -to VIDEO_G[6] +set_location_assignment PIN_AF18 -to VIDEO_G_6 +set_location_assignment PIN_AE19 -to VIDEO_G[7] +set_location_assignment PIN_AE19 -to VIDEO_G_7 +set_location_assignment PIN_AC22 -to VIDEO_R[0] +set_location_assignment PIN_AC22 -to VIDEO_R_0 +set_location_assignment PIN_AA18 -to VIDEO_R[1] +set_location_assignment PIN_AA18 -to VIDEO_R_1 +set_location_assignment PIN_AE23 -to VIDEO_R[2] +set_location_assignment PIN_AE23 -to VIDEO_R_2 +set_location_assignment PIN_AD23 -to VIDEO_R[3] +set_location_assignment PIN_AD23 -to VIDEO_R_3 +set_location_assignment PIN_AH18 -to VIDEO_R[4] +set_location_assignment PIN_AH18 -to VIDEO_R_4 +set_location_assignment PIN_AG21 -to VIDEO_R[5] +set_location_assignment PIN_AG21 -to VIDEO_R_5 +set_location_assignment PIN_AH21 -to VIDEO_R[6] +set_location_assignment PIN_AH21 -to VIDEO_R_6 +set_location_assignment PIN_AH19 -to VIDEO_R[7] +set_location_assignment PIN_AH19 -to VIDEO_R_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7 diff --git a/cs309-psoc/lab_3_0/hw/quartus/lab_3_0.sdc b/cs309-psoc/lab_3_0/hw/quartus/lab_3_0.sdc new file mode 100644 index 0000000..16a41f3 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/quartus/lab_3_0.sdc @@ -0,0 +1,6 @@ +create_clock -period 20 [get_ports FPGA_CLK1_50] +create_clock -period 20 [get_ports FPGA_CLK2_50] +create_clock -period 20 [get_ports FPGA_CLK3_50] + +derive_pll_clocks +derive_clock_uncertainty diff --git a/cs309-psoc/lab_3_0/hw/quartus/soc_system.qsys b/cs309-psoc/lab_3_0/hw/quartus/soc_system.qsys new file mode 100644 index 0000000..35e5167 --- /dev/null +++ b/cs309-psoc/lab_3_0/hw/quartus/soc_system.qsys @@ -0,0 +1,649 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + 0x000000000000000000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_3_0/lab_3_0.pdf b/cs309-psoc/lab_3_0/lab_3_0.pdf new file mode 100644 index 0000000..9962d03 Binary files /dev/null and b/cs309-psoc/lab_3_0/lab_3_0.pdf differ diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/app.c b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/app.c new file mode 100644 index 0000000..3d78b2a --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/app.c @@ -0,0 +1,89 @@ +#include +#include +#include +#include +#include + +#include "pantilt/pantilt.h" +#include "joysticks/joysticks.h" +#include "lepton/lepton.h" + +/* TODO : include suitable header files to have access to peripheral addresses. */ +#include ... + +#define SLEEP_DURATION (1000) + +// Servos +#define PANTILT_PWM_V_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_V_MIN_DUTY_CYCLE_US + PANTILT_PWM_V_MAX_DUTY_CYCLE_US) / 2) +#define PANTILT_PWM_H_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_H_MIN_DUTY_CYCLE_US + PANTILT_PWM_H_MAX_DUTY_CYCLE_US) / 2) + +// Right joystick horizontal threshold for triggering lepton capture +#define LEPTON_RIGHT_JOYSTICK_HORIZONTAL_TRIGGER_THRESHOLD ((uint32_t) (0.8 * JOYSTICKS_MAX_VALUE)) + +uint32_t interpolate(uint32_t input, + uint32_t input_lower_bound, + uint32_t input_upper_bound, + uint32_t output_lower_bound, + uint32_t output_upper_bound) { + /* TODO : complete this function */ +} + +void handle_pantilt(pantilt_dev *pantilt, joysticks_dev *joysticks) { + // Read LEFT joystick position + uint32_t left_joystick_v = joysticks_read_left_vertical(joysticks); + uint32_t left_joystick_h = joysticks_read_left_horizontal(joysticks); + + // Interpolate LEFT joystick position between SERVO_x_MIN_DUTY_CYCLE_US + // and SERVO_x_MAX_DUTY_CYCLE_US + uint32_t pantilt_v_duty_us = interpolate(left_joystick_v, + JOYSTICKS_MIN_VALUE, + JOYSTICKS_MAX_VALUE, + PANTILT_PWM_V_MIN_DUTY_CYCLE_US, + PANTILT_PWM_V_MAX_DUTY_CYCLE_US); + uint32_t pantilt_h_duty_us = interpolate(left_joystick_h, + JOYSTICKS_MIN_VALUE, + JOYSTICKS_MAX_VALUE, + PANTILT_PWM_H_MIN_DUTY_CYCLE_US, + PANTILT_PWM_H_MAX_DUTY_CYCLE_US); + + // Configure servos with interpolated joystick values + pantilt_configure_vertical(pantilt, pantilt_v_duty_us); + pantilt_configure_horizontal(pantilt, pantilt_h_duty_us); +} + +void handle_lepton(joysticks_dev *joysticks, lepton_dev *lepton) { + /* TODO : complete this function */ + + // Read RIGHT joystick position, and if it is greater than a certain + // threshold, then launch a capture with the lepton controller and print the + // output to STDOUT. +} + +int main(void) { + // Hardware control structures + pantilt_dev pantilt = pantilt_inst(...); /* TODO */ + joysticks_dev joysticks = joysticks_inst(...); /* TODO */ + lepton_dev lepton = lepton_inst(...); /* TODO */ + + // Initialize hardware + pantilt_init(&pantilt); + joysticks_init(&joysticks); + lepton_init(&lepton); + + // Center servos. + pantilt_configure_vertical(&pantilt, PANTILT_PWM_V_CENTER_DUTY_CYCLE_US); + pantilt_configure_horizontal(&pantilt, PANTILT_PWM_H_CENTER_DUTY_CYCLE_US); + pantilt_start_vertical(&pantilt); + pantilt_start_horizontal(&pantilt); + + // Control servos with LEFT joystick, capture thermal image with RIGHT joystick. + while (true) { + handle_pantilt(&pantilt, &joysticks); + handle_lepton(&joysticks, &lepton); + + // Sleep for a while to avoid excessive sensitivity + for (uint32_t i = 0; i < SLEEP_DURATION; i++); + } + + return EXIT_SUCCESS; +} diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/joysticks.c b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/joysticks.c new file mode 100644 index 0000000..c50fcd0 --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/joysticks.c @@ -0,0 +1,83 @@ +#include "joysticks.h" + +#define JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL (0) +#define JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL (1) +#define JOYSTICK_LEFT_VRY_MCP3204_CHANNEL (2) +#define JOYSTICK_LEFT_VRX_MCP3204_CHANNEL (3) + +/** + * joysticks_inst + * + * Instantiate a joysticks device structure. + * + * @param base Base address of the MCP3204 component connected to the joysticks. + */ +joysticks_dev joysticks_inst(void *mcp3204_base) { + joysticks_dev dev; + dev.mcp3204 = mcp3204_inst((void *) mcp3204_base); + + return dev; +} + +/** + * joysticks_init + * + * Initializes the joysticks device. + * + * @param dev joysticks device structure. + */ +void joysticks_init(joysticks_dev *dev) { + mcp3204_init(&(dev->mcp3204)); +} + +/** + * joysticks_read_left_vertical + * + * Returns the vertical position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_vertical(joysticks_dev *dev) { + /* TODO : complete this function */ + + // Need to compensate for 90 degree rotation. +} + +/** + * joysticks_read_left_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) { + /* TODO : complete this function */ +} + +/** + * joysticks_read_right_vertical + * + * Returns the vertical position of the right joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_vertical(joysticks_dev *dev) { + /* TODO : complete this function */ + + // Need to compensate for 90 degree rotation. +} + +/** + * joysticks_read_right_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) { + /* TODO : complete this function */ +} diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/joysticks.h b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/joysticks.h new file mode 100644 index 0000000..ac9c383 --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/joysticks.h @@ -0,0 +1,27 @@ +#ifndef __JOYSTICKS_H__ +#define __JOYSTICKS_H__ + +#include "mcp3204/mcp3204.h" + +/* joysticks device structure */ +typedef struct joysticks_dev { + mcp3204_dev mcp3204; /* MCP3204 device handle */ +} joysticks_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define JOYSTICKS_MIN_VALUE (MCP3204_MIN_VALUE) +#define JOYSTICKS_MAX_VALUE (MCP3204_MAX_VALUE) + +joysticks_dev joysticks_inst(void *mcp3204_base); + +void joysticks_init(joysticks_dev *dev); + +uint32_t joysticks_read_left_vertical(joysticks_dev *dev); +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev); +uint32_t joysticks_read_right_vertical(joysticks_dev *dev); +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev); + +#endif /* __JOYSTICKS_H__ */ diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.c b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.c new file mode 100644 index 0000000..6215dde --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.c @@ -0,0 +1,43 @@ +#include +#include + +#include "mcp3204.h" + +#define MCP3204_NUM_CHANNELS (4) + +/** + * mcp3204_inst + * + * Instantiate a mcp3204 device structure. + * + * @param base Base address of the component. + */ +mcp3204_dev mcp3204_inst(void *base) { + mcp3204_dev dev; + dev.base = base; + + return dev; +} + +/** + * mcp3204_init + * + * Initializes the mcp3204 device. + * + * @param dev mcp3204 device structure. + */ +void mcp3204_init(mcp3204_dev *dev) { + return; +} + +/** + * mcp3204_read + * + * Reads the register corresponding to the supplied channel parameter. + * + * @param dev mcp3204 device structure. + * @param channel channel to be read + */ +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) { + /* TODO : complete this function */ +} diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.h b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.h new file mode 100644 index 0000000..3b2b2e6 --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.h @@ -0,0 +1,23 @@ +#ifndef __MCP3204_H__ +#define __MCP3204_H__ + +#include + +/* mcp3204 device structure */ +typedef struct mcp3204_dev { + void *base; /* Base address of component */ +} mcp3204_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define MCP3204_MIN_VALUE (0) +#define MCP3204_MAX_VALUE (4095) + +mcp3204_dev mcp3204_inst(void *base); + +void mcp3204_init(mcp3204_dev *dev); +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel); + +#endif /* __MCP3204_H__ */ diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204_regs.h b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204_regs.h new file mode 100644 index 0000000..b1c78cd --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204_regs.h @@ -0,0 +1,9 @@ +#ifndef __MCP3204_REGS_H__ +#define __MCP3204_REGS_H__ + +#define MCP3204_CHANNEL_0_OFST (0 * 4) /* RO */ +#define MCP3204_CHANNEL_1_OFST (1 * 4) /* RO */ +#define MCP3204_CHANNEL_2_OFST (2 * 4) /* RO */ +#define MCP3204_CHANNEL_3_OFST (3 * 4) /* RO */ + +#endif /* __MCP3204_REGS_H__ */ diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/lepton/lepton.c b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/lepton/lepton.c new file mode 100644 index 0000000..8925d22 --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/lepton/lepton.c @@ -0,0 +1,118 @@ +#include +#include +#include +#include +#include + +#include "lepton_regs.h" +#include "lepton.h" + +/** + * lepton_inst + * + * Instantiate a lepton device structure. + * + * @param base Base address of the component. + */ +lepton_dev lepton_inst(void *base) { + lepton_dev dev; + dev.base = base; + + return dev; +} + +/** + * lepton_init + * + * Initializes the lepton device. + * + * @param dev lepton device structure. + */ +void lepton_init(lepton_dev *dev) { + return; +} + +/** + * lepton_start_capture + * + * Instructs the device to start the frame capture process. + * + * @param dev lepton device structure. + */ +void lepton_start_capture(lepton_dev *dev) { + /* TODO : complete this function */ +} + +/** + * lepton_error_check + * + * @abstract Check for errors at the device level. + * @param dev lepton device structure. + * @return true if there was an error, and false otherwise. + */ +bool lepton_error_check(lepton_dev *dev) { + /* TODO : complete this function */ +} + +/** + * lepton_wait_until_eof + * + * Waits until the frame being captured has been fully received and saved in the + * internal memory. + * + * @param dev lepton device structure. + */ +void lepton_wait_until_eof(lepton_dev *dev) { + /* TODO : complete this function */ +} + +/** + * lepton_save_capture + * + * Saves the captured frame on the host filesystem under the supplied filename. + * The frame will be saved in PGM format. + * + * @param dev lepton device structure. + * @param adjusted Setting this parameter to false will cause RAW sensor data to + * be written to the file. + * Setting this parameter to true will cause a preprocessed image + * (with a stretched dynamic range) to be saved to the file. + * + * @param fname the output file name. + */ +void lepton_save_capture(lepton_dev *dev, bool adjusted, const char *fname) { + FILE *fp = fopen(fname, "w"); + assert(fp); + + const uint8_t num_rows = 60; + const uint8_t num_cols = 80; + + uint16_t offset = LEPTON_REGS_RAW_BUFFER_OFST; + uint16_t max_value = IORD_16DIRECT(dev->base, LEPTON_REGS_MAX_OFST); + if (adjusted) { + offset = LEPTON_REGS_ADJUSTED_BUFFER_OFST; + max_value = 0x3fff; + } + + /* Write PGM header */ + fprintf(fp, "P2\n%" PRIu8 " %" PRIu8 "\n%" PRIu16, num_cols, num_rows, max_value); + + /* Write body */ + uint8_t row = 0; + for (row = 0; row < num_rows; ++row) { + fprintf(fp, "\n"); + + uint8_t col = 0; + for (col = 0; col < num_cols; ++col) { + if (col > 0) { + fprintf(fp, " "); + } + + uint16_t current_ofst = offset + (row * num_cols + col) * sizeof(uint16_t); + uint16_t pix_value = IORD_16DIRECT(dev->base, current_ofst); + fprintf(fp, "%" PRIu16, pix_value); + } + } + + assert(!fclose(fp)); +} diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/lepton/lepton.h b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/lepton/lepton.h new file mode 100644 index 0000000..cf197d2 --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/lepton/lepton.h @@ -0,0 +1,23 @@ +#ifndef __LEPTON_H__ +#define __LEPTON_H__ + +#include + +/* lepton device structure */ +typedef struct { + void *base; /* Base address of the component */ +} lepton_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +lepton_dev lepton_inst(void *base); + +void lepton_init(lepton_dev *dev); +void lepton_start_capture(lepton_dev *dev); +void lepton_wait_until_eof(lepton_dev *dev); +bool lepton_error_check(lepton_dev *dev); +void lepton_save_capture(lepton_dev *dev, bool adjusted, const char *fname); + +#endif /* __LEPTON_H__ */ diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/lepton/lepton_regs.h b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/lepton/lepton_regs.h new file mode 100644 index 0000000..db24244 --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/lepton/lepton_regs.h @@ -0,0 +1,25 @@ +#ifndef __LEPTON_REGS_H__ +#define __LEPTON_REGS_H__ + +/* Register offsets */ +#define LEPTON_REGS_COMMAND_OFST ( 0 * 2) /* WO */ +#define LEPTON_REGS_STATUS_OFST ( 1 * 2) /* RO */ +#define LEPTON_REGS_MIN_OFST ( 2 * 2) /* RO */ +#define LEPTON_REGS_MAX_OFST ( 3 * 2) /* RO */ +#define LEPTON_REGS_SUM_LSB_OFST ( 4 * 2) /* RO */ +#define LEPTON_REGS_SUM_MSB_OFST ( 5 * 2) /* RO */ +#define LEPTON_REGS_ROW_IDX_OFST ( 6 * 2) /* RO */ +#define LEPTON_REGS_RAW_BUFFER_OFST ( 8 * 2) /* RO */ +#define LEPTON_REGS_ADJUSTED_BUFFER_OFST (8192 * 2) /* RO */ + +/* Command register */ +#define LEPTON_COMMAND_START (0x0001) + +/* Status register */ +#define LEPTON_STATUS_CAPTURE_IN_PROGRESS_MASK (1 << 0) +#define LEPTON_STATUS_ERROR_MASK (1 << 1) + +#define LEPTON_REGS_BUFFER_NUM_PIXELS (80 * 60) +#define LEPTON_REGS_BUFFER_BYTELENGTH (LEPTON_REGS_BUFFER_NUM_PIXELS * 2) + +#endif /* __LEPTON_REGS_H__ */ diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pantilt.c b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pantilt.c new file mode 100644 index 0000000..d9c4c72 --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pantilt.c @@ -0,0 +1,109 @@ +#include "pantilt.h" + +/** + * pantilt_inst + * + * Instantiate a pantilt device structure. + * + * @param pwm_v_base Base address of the vertical PWM component. + * @param pwm_h_base Base address of the horizontal PWM component. + */ +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) { + pantilt_dev dev; + dev.pwm_v = pwm_inst(pwm_v_base); + dev.pwm_h = pwm_inst(pwm_h_base); + + return dev; +} + +/** + * pantilt_init + * + * Initializes the pantilt device. + * + * @param dev pantilt device structure. + */ +void pantilt_init(pantilt_dev *dev) { + pwm_init(&(dev->pwm_v)); + pwm_init(&(dev->pwm_h)); +} + +/** + * pantilt_configure_vertical + * + * Configure the vertical PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_v), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_configure_horizontal + * + * Configure the horizontal PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_h), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_start_vertical + * + * Starts the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_vertical(pantilt_dev *dev) { + pwm_start(&(dev->pwm_v)); +} + +/** + * pantilt_start_horizontal + * + * Starts the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_horizontal(pantilt_dev *dev) { + pwm_start(&(dev->pwm_h)); +} + +/** + * pantilt_stop_vertical + * + * Stops the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_vertical(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_v)); +} + +/** + * pantilt_stop_horizontal + * + * Stops the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_horizontal(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_h)); +} diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pantilt.h b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pantilt.h new file mode 100644 index 0000000..1f17500 --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pantilt.h @@ -0,0 +1,39 @@ +#ifndef __PANTILT_H__ +#define __PANTILT_H__ + +#include "pwm/pwm.h" + +/* joysticks device structure */ +typedef struct pantilt_dev { + pwm_dev pwm_v; /* Vertical PWM device handle */ + pwm_dev pwm_h; /* Horizontal PWM device handle */ +} pantilt_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz + +#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms + +/* Vertical servo */ +#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms +#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms + +/* Horizontal servo */ +#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms +#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms + +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base); + +void pantilt_init(pantilt_dev *dev); + +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_start_vertical(pantilt_dev *dev); +void pantilt_start_horizontal(pantilt_dev *dev); +void pantilt_stop_vertical(pantilt_dev *dev); +void pantilt_stop_horizontal(pantilt_dev *dev); + +#endif /* __PANTILT_H__ */ diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pwm/pwm.c b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pwm/pwm.c new file mode 100644 index 0000000..c8b89b6 --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pwm/pwm.c @@ -0,0 +1,66 @@ +#include + +#include "pwm.h" +#include "pwm_regs.h" + +/** + * pwm_inst + * + * Instantiate a pwm device structure. + * + * @param base Base address of the component. + */ +pwm_dev pwm_inst(void *base) { + pwm_dev dev; + + dev.base = base; + + return dev; +} + +/** + * pwm_init + * + * Initializes the pwm device. This function stops the controller. + * + * @param dev pwm device structure. + */ +void pwm_init(pwm_dev *dev) { + pwm_stop(dev); +} + +/** + * pwm_configure + * + * Configure pwm component. + * + * @param dev pwm device structure. + * @param duty_cycle pwm duty cycle in us. + * @param period pwm period in us. + * @param module_frequency frequency at which the component is clocked. + */ +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) { + /* TODO : complete this function */ +} + +/** + * pwm_start + * + * Starts the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_start(pwm_dev *dev) { + /* TODO : complete this function */ +} + +/** + * pwm_stop + * + * Stops the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_stop(pwm_dev *dev) { + /* TODO : complete this function */ +} diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pwm/pwm.h b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pwm/pwm.h new file mode 100644 index 0000000..e2987f4 --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pwm/pwm.h @@ -0,0 +1,21 @@ +#ifndef __PWM_H__ +#define __PWM_H__ + +#include + +/* pwm device structure */ +typedef struct pwm_dev { + void *base; /* Base address of component */ +} pwm_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ +pwm_dev pwm_inst(void *base); + +void pwm_init(pwm_dev *dev); +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency); +void pwm_start(pwm_dev *dev); +void pwm_stop(pwm_dev *dev); + +#endif /* __PWM_H__ */ diff --git a/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pwm/pwm_regs.h b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pwm/pwm_regs.h new file mode 100644 index 0000000..488583d --- /dev/null +++ b/cs309-psoc/lab_3_0/sw/hps/application/lab_3_0/pantilt/pwm/pwm_regs.h @@ -0,0 +1,11 @@ +#ifndef __PWM_REGS_H__ +#define __PWM_REGS_H__ + +#define PWM_PERIOD_OFST (0 * 4) /* RW */ +#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */ +#define PWM_CTRL_OFST (2 * 4) /* WO */ + +#define PWM_CTRL_STOP_MASK (0) +#define PWM_CTRL_START_MASK (1) + +#endif /* __PWM_REGS_H__ */ diff --git a/cs309-psoc/lab_3_1/create_linux_system.sh b/cs309-psoc/lab_3_1/create_linux_system.sh new file mode 100755 index 0000000..7e6e433 --- /dev/null +++ b/cs309-psoc/lab_3_1/create_linux_system.sh @@ -0,0 +1,514 @@ +#!/bin/bash -x + +# =================================================================================== +# usage: create_linux_system.sh [sdcard_device] +# +# positional arguments: +# sdcard_device path to sdcard device file [ex: "/dev/sdb", "/dev/mmcblk0"] +# =================================================================================== + +# make sure to be in the same directory as this script +script_dir_abs=$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd ) +cd "${script_dir_abs}" + +# constants #################################################################### +quartus_dir="$(readlink -m "hw/quartus")" +quartus_project_name="$(basename "$(find "${quartus_dir}" -name "*.qpf")" .qpf)" +quartus_sof_file="$(readlink -m "${quartus_dir}/output_files/${quartus_project_name}.sof")" + +fpga_device_part_number="5CSEMA4U23C6" # 5CSEMA5F31C6 + +preloader_dir="$(readlink -m "sw/hps/preloader")" +preloader_settings_dir="$(readlink -m "${quartus_dir}/hps_isw_handoff/soc_system_hps_0")" +preloader_settings_file="$(readlink -m "${preloader_dir}/settings.bsp")" +preloader_source_tgz_file="$(readlink -m "${SOCEDS_DEST_ROOT}/host_tools/altera/preloader/uboot-socfpga.tar.gz")" +preloader_bin_file="${preloader_dir}/preloader-mkpimage.bin" + +uboot_src_dir="$(readlink -m "sw/hps/u-boot")" +uboot_src_git_repo="git://git.denx.de/u-boot.git" +uboot_src_git_checkout_commit="b104b3dc1dd90cdbf67ccf3c51b06e4f1592fe91" +uboot_src_make_config_file="socfpga_de0_nano_soc_defconfig" # socfpga_cyclone5_config +uboot_src_config_file="${uboot_src_dir}/include/configs/socfpga_de0_nano_soc.h" # socfpga_cyclone5_socdk.h +uboot_script_file="$(readlink -m "${uboot_src_dir}/u-boot.script")" +uboot_img_file="$(readlink -m "${uboot_src_dir}/u-boot.img")" + +linux_dir="$(readlink -m "sw/hps/linux")" +linux_src_git_repo="https://github.com/altera-opensource/linux-socfpga.git" +linux_src_dir="$(readlink -m "${linux_dir}/source")" +linux_src_git_checkout_commit="9735a22799b9214d17d3c231fe377fc852f042e9" +linux_src_make_config_file="socfpga_defconfig" +linux_kernel_mem_arg="1024M" +linux_zImage_file="$(readlink -m "${linux_src_dir}/arch/arm/boot/zImage")" +linux_dtb_file="$(readlink -m "${linux_src_dir}/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dtb")" # socfpga_cyclone5_socdk.dtb + +rootfs_dir="${linux_dir}/rootfs" +rootfs_chroot_dir="$(readlink -m ${rootfs_dir}/ubuntu-core-rootfs)" +rootfs_src_tgz_link="http://cdimage.ubuntu.com/ubuntu-base/releases/14.04.5/release/ubuntu-base-14.04.5-base-armhf.tar.gz" +rootfs_src_tgz_file="$(readlink -m "${rootfs_dir}/${rootfs_src_tgz_link##*/}")" +rootfs_system_config_script_file="${rootfs_dir}/config_system.sh" +rootfs_post_install_config_script_file="${rootfs_dir}/config_post_install.sh" + +sdcard_fat32_dir="$(readlink -m "sdcard/fat32")" +sdcard_fat32_rbf_file="$(readlink -m "${sdcard_fat32_dir}/socfpga.rbf")" +sdcard_fat32_uboot_img_file="$(readlink -m "${sdcard_fat32_dir}/$(basename "${uboot_img_file}")")" +sdcard_fat32_uboot_scr_file="$(readlink -m "${sdcard_fat32_dir}/u-boot.scr")" +sdcard_fat32_zImage_file="$(readlink -m "${sdcard_fat32_dir}/zImage")" +sdcard_fat32_dtb_file="$(readlink -m "${sdcard_fat32_dir}/socfpga.dtb")" + +sdcard_dev="$(readlink -m "${1}")" + +sdcard_ext3_rootfs_tgz_file="$(readlink -m "sdcard/ext3_rootfs.tar.gz")" + +sdcard_a2_dir="$(readlink -m "sdcard/a2")" +sdcard_a2_preloader_bin_file="$(readlink -m "${sdcard_a2_dir}/$(basename "${preloader_bin_file}")")" + +sdcard_partition_size_fat32="32M" +sdcard_partition_size_linux="512M" + +sdcard_partition_number_fat32="1" +sdcard_partition_number_ext3="2" +sdcard_partition_number_a2="3" + +if [ "$(echo "${sdcard_dev}" | grep -P "/dev/sd\w.*$")" ]; then + sdcard_dev_fat32_id="${sdcard_partition_number_fat32}" + sdcard_dev_ext3_id="${sdcard_partition_number_ext3}" + sdcard_dev_a2_id="${sdcard_partition_number_a2}" +elif [ "$(echo "${sdcard_dev}" | grep -P "/dev/mmcblk\w.*$")" ]; then + sdcard_dev_fat32_id="p${sdcard_partition_number_fat32}" + sdcard_dev_ext3_id="p${sdcard_partition_number_ext3}" + sdcard_dev_a2_id="p${sdcard_partition_number_a2}" +fi + +sdcard_dev_fat32="${sdcard_dev}${sdcard_dev_fat32_id}" +sdcard_dev_ext3="${sdcard_dev}${sdcard_dev_ext3_id}" +sdcard_dev_a2="${sdcard_dev}${sdcard_dev_a2_id}" +sdcard_dev_fat32_mount_point="$(readlink -m "sdcard/mount_point_fat32")" +sdcard_dev_ext3_mount_point="$(readlink -m "sdcard/mount_point_ext3")" + +# compile_quartus_project() #################################################### +compile_quartus_project() { + # change working directory to quartus directory + pushd "${quartus_dir}" + + # delete old artifacts + rm -rf "c5_pin_model_dump.txt" \ + "db/" \ + "hps_isw_handoff/" \ + "hps_sdram_p0_all_pins.txt" \ + "incremental_db/" \ + "output_files/" \ + "soc_system.sopcinfo" \ + "soc_system/" \ + "${quartus_project_name}.qws" \ + "${sdcard_fat32_rbf_file}" + + qsys-generate "soc_system.qsys" --synthesis=VHDL --output-directory="soc_system/" --part="${fpga_device_part_number}" + + # Analysis and synthesis + quartus_map "${quartus_project_name}" + + # Execute HPS DDR3 pin assignment TCL script + # it is normal for the following script to report an error, but it was + # sucessfully executed + #ddr3_pin_assignment_script="$(find . -name "hps_sdram_p0_pin_assignments.tcl")" + #quartus_sta -t "${ddr3_pin_assignment_script}" "${quartus_project_name}" + + # Fitter + quartus_fit "${quartus_project_name}" + + # Assembler + quartus_asm "${quartus_project_name}" + + #ddr3_pin_assignment_script="$(find . -name "hps_sdram_p0_pin_assignments.tcl")" + #quartus_sta -t "${ddr3_pin_assignment_script}" "${quartus_project_name}" + quartus_sta "${quartus_project_name}" + + # convert .sof to .rbf in associated sdcard directory + quartus_cpf -c "${quartus_sof_file}" "${sdcard_fat32_rbf_file}" + + # change working directory back to script directory + popd +} + +# compile_preloader() ########################################################## +compile_preloader() { + # delete old artifacts + rm -rf "${preloader_dir}" \ + "${sdcard_a2_preloader_bin_file}" + + # create directory for preloader + mkdir -p "${preloader_dir}" + + # change working directory to preloader directory + pushd "${preloader_dir}" + + # create bsp settings file + bsp-create-settings \ + --bsp-dir "${preloader_dir}" \ + --preloader-settings-dir "${preloader_settings_dir}" \ + --settings "${preloader_settings_file}" \ + --type spl \ + --set spl.CROSS_COMPILE "arm-altera-eabi-" \ + --set spl.PRELOADER_TGZ "${preloader_source_tgz_file}" \ + --set spl.boot.BOOTROM_HANDSHAKE_CFGIO "1" \ + --set spl.boot.BOOT_FROM_NAND "0" \ + --set spl.boot.BOOT_FROM_QSPI "0" \ + --set spl.boot.BOOT_FROM_RAM "0" \ + --set spl.boot.BOOT_FROM_SDMMC "1" \ + --set spl.boot.CHECKSUM_NEXT_IMAGE "1" \ + --set spl.boot.EXE_ON_FPGA "0" \ + --set spl.boot.FAT_BOOT_PARTITION "1" \ + --set spl.boot.FAT_LOAD_PAYLOAD_NAME "$(basename "${uboot_img_file}")" \ + --set spl.boot.FAT_SUPPORT "1" \ + --set spl.boot.FPGA_DATA_BASE "0xffff0000" \ + --set spl.boot.FPGA_DATA_MAX_SIZE "0x10000" \ + --set spl.boot.FPGA_MAX_SIZE "0x10000" \ + --set spl.boot.NAND_NEXT_BOOT_IMAGE "0xc0000" \ + --set spl.boot.QSPI_NEXT_BOOT_IMAGE "0x60000" \ + --set spl.boot.RAMBOOT_PLLRESET "1" \ + --set spl.boot.SDMMC_NEXT_BOOT_IMAGE "0x40000" \ + --set spl.boot.SDRAM_SCRUBBING "0" \ + --set spl.boot.SDRAM_SCRUB_BOOT_REGION_END "0x2000000" \ + --set spl.boot.SDRAM_SCRUB_BOOT_REGION_START "0x1000000" \ + --set spl.boot.SDRAM_SCRUB_REMAIN_REGION "1" \ + --set spl.boot.STATE_REG_ENABLE "1" \ + --set spl.boot.WARMRST_SKIP_CFGIO "1" \ + --set spl.boot.WATCHDOG_ENABLE "1" \ + --set spl.debug.DEBUG_MEMORY_ADDR "0xfffffd00" \ + --set spl.debug.DEBUG_MEMORY_SIZE "0x200" \ + --set spl.debug.DEBUG_MEMORY_WRITE "0" \ + --set spl.debug.HARDWARE_DIAGNOSTIC "0" \ + --set spl.debug.SEMIHOSTING "0" \ + --set spl.debug.SKIP_SDRAM "0" \ + --set spl.performance.SERIAL_SUPPORT "1" \ + --set spl.reset_assert.DMA "0" \ + --set spl.reset_assert.GPIO0 "0" \ + --set spl.reset_assert.GPIO1 "0" \ + --set spl.reset_assert.GPIO2 "0" \ + --set spl.reset_assert.L4WD1 "0" \ + --set spl.reset_assert.OSC1TIMER1 "0" \ + --set spl.reset_assert.SDR "0" \ + --set spl.reset_assert.SPTIMER0 "0" \ + --set spl.reset_assert.SPTIMER1 "0" \ + --set spl.warm_reset_handshake.ETR "1" \ + --set spl.warm_reset_handshake.FPGA "1" \ + --set spl.warm_reset_handshake.SDRAM "0" + + # generate bsp + bsp-generate-files \ + --bsp-dir "${preloader_dir}" \ + --settings "${preloader_settings_file}" + + # compile preloader + make -j4 + + # copy artifacts to associated sdcard directory + cp "${preloader_bin_file}" "${sdcard_a2_preloader_bin_file}" + + # change working directory back to script directory + popd +} + +# compile_uboot ################################################################ +compile_uboot() { + # delete old artifacts + rm -rf "${sdcard_fat32_uboot_scr_file}" \ + "${sdcard_fat32_uboot_img_file}" + + # if uboot source tree doesn't exist, then download it + if [ ! -d "${uboot_src_dir}" ]; then + git clone "${uboot_src_git_repo}" "${uboot_src_dir}" + fi + + # change working directory to uboot source tree directory + pushd "${uboot_src_dir}" + + # use cross compiler instead of standard x86 version of gcc + export CROSS_COMPILE=arm-linux-gnueabihf- + + # clean up source tree + make distclean + + # checkout the following commit (tested and working): + git checkout "${uboot_src_git_checkout_commit}" + + # configure uboot for socfpga_cyclone5 architecture + make "${uboot_src_make_config_file}" + + ## patch the uboot configuration file that describes environment variables + # replace value of CONFIG_BOOTCOMMAND macro (we will always use a script for configuring everything) + # result: + # #define CONFIG_BOOTCOMMAND "run callscript" + perl -pi -e 's/^(#define\s+CONFIG_BOOTCOMMAND)(.*)/$1\t"run callscript"/g' "${uboot_src_config_file}" + + # replace value of CONFIG_EXTRA_ENV_SETTINGS macro + # result: + # #define CONFIG_EXTRA_ENV_SETTINGS \ + # "scriptfile=u-boot.scr" "\0" \ + # "fpgadata=0x2000000" "\0" \ + # "callscript=fatload mmc 0:1 $fpgadata $scriptfile;" \ + # "source $fpgadata" "\0" + perl -pi -e 'BEGIN{undef $/;} s/^(#define\s+CONFIG_EXTRA_ENV_SETTINGS)(.*)#include/$1\t"scriptfile=u-boot.scr\\0" "fpgadata=0x2000000\\0" "callscript=fatload mmc 0:1 \$fpgadata \$scriptfile; source \$fpgadata\\0"\n\n#include/smg' "${uboot_src_config_file}" + + # compile uboot + make -j4 + + # create uboot script + cat < "${uboot_script_file}" +################################################################################ +echo --- Resetting Env variables --- + +# reset environment variables to default +env default -a + +echo --- Setting Env variables --- + +# Set the kernel image +setenv bootimage $(basename ${sdcard_fat32_zImage_file}); + +# address to which the device tree will be loaded +setenv fdtaddr 0x00000100 + +# Set the devicetree image +setenv fdtimage $(basename ${sdcard_fat32_dtb_file}); + +# set kernel boot arguments, then boot the kernel +setenv mmcboot 'setenv bootargs mem=${linux_kernel_mem_arg} console=ttyS0,115200 root=\${mmcroot} rw rootwait; \ +bootz \${loadaddr} - \${fdtaddr}'; + +# load linux kernel image and device tree to memory +setenv mmcload 'mmc rescan; \ +\${mmcloadcmd} mmc 0:\${mmcloadpart} \${loadaddr} \${bootimage}; \ +\${mmcloadcmd} mmc 0:\${mmcloadpart} \${fdtaddr} \${fdtimage}' + +# command to be executed to read from sdcard +setenv mmcloadcmd fatload + +# sdcard fat32 partition number +setenv mmcloadpart ${sdcard_partition_number_fat32} + +# sdcard ext3 identifier +setenv mmcroot /dev/mmcblk0p${sdcard_partition_number_ext3} + +# standard input/output +setenv stderr serial +setenv stdin serial +setenv stdout serial + +# save environment to sdcard (not needed, but useful to avoid CRC errors on a new sdcard) +saveenv + +################################################################################ +echo --- Programming FPGA --- + +# load rbf from FAT partition into memory +fatload mmc 0:1 \${fpgadata} $(basename ${sdcard_fat32_rbf_file}); + +# program FPGA +fpga load 0 \${fpgadata} \${filesize}; + +# enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges +bridge enable; + +################################################################################ +echo --- Booting Linux --- + +# load linux kernel image and device tree to memory +run mmcload; + +# set kernel boot arguments, then boot the kernel +run mmcboot; +EOF + + # compile uboot script to binary form + mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "${quartus_project_name}" -d "${uboot_script_file}" "${sdcard_fat32_uboot_scr_file}" + + # copy artifacts to associated sdcard directory + cp "${uboot_img_file}" "${sdcard_fat32_uboot_img_file}" + + # change working directory back to script directory + popd +} + +# compile_linux() ############################################################## +compile_linux() { + # if linux source tree doesn't exist, then download it + if [ ! -d "${linux_src_dir}" ]; then + git clone "${linux_src_git_repo}" "${linux_src_dir}" + fi + + # change working directory to linux source tree directory + pushd "${linux_src_dir}" + + # compile for the ARM architecture + export ARCH=arm + + # use cross compiler instead of standard x86 version of gcc + export CROSS_COMPILE=arm-linux-gnueabihf- + + # clean up source tree + make distclean + + # checkout the following commit (tested and working): + git checkout "${linux_src_git_checkout_commit}" + + # configure kernel for socfpga architecture + make "${linux_src_make_config_file}" + + # compile zImage + make -j4 zImage + + # compile device tree + make -j4 "$(basename "${linux_dtb_file}")" + + # copy artifacts to associated sdcard directory + cp "${linux_zImage_file}" "${sdcard_fat32_zImage_file}" + cp "${linux_dtb_file}" "${sdcard_fat32_dtb_file}" + + # change working directory back to script directory + popd +} + +# create_rootfs() ############################################################## +create_rootfs() { + # if rootfs tarball doesn't exist, then download it + if [ ! -f "${rootfs_src_tgz_file}" ]; then + wget "${rootfs_src_tgz_link}" -O "${rootfs_src_tgz_file}" + fi + + # delete old artifacts + sudo rm -rf "${rootfs_chroot_dir}" \ + "${sdcard_ext3_rootfs_tgz_file}" + + # create dir to extract rootfs + mkdir -p "${rootfs_chroot_dir}" + + # extract ubuntu core rootfs + pushd "${rootfs_chroot_dir}" + sudo tar -xzpf "${rootfs_src_tgz_file}" + popd + + # copy chroot SYSTEM configuration script to chroot directory + sudo cp "${rootfs_system_config_script_file}" "${rootfs_chroot_dir}" + + # edit chroot environment's /etc/rc.local to execute the rootfs + # configuration script + sudo tee "${rootfs_chroot_dir}/etc/rc.local" > "/dev/null" < 4095 t a2 (2048 is default first sector) + # n p 1 +32M t 1 b (4096 is default first sector) + # n p 2 +512M t 2 83 (69632 is default first sector) + # w + # result + # Device Boot Start End Sectors Size Id Type + # /dev/sdb1 4096 69631 65536 32M b W95 FAT32 + # /dev/sdb2 69632 1118207 1048576 512M 83 Linux + # /dev/sdb3 2048 4095 2048 1M a2 unknown + # note that you can choose any size for the FAT32 and Linux partitions, + # but the a2 partition must be 1M. + + # automatically partitioning the sdcard + # wipe partition table + sudo dd if="/dev/zero" of="${sdcard_dev}" bs=512 count=1 + + # create partitions + # no need to specify the partition number for the first invocation of + # the "t" command in fdisk, because there is only 1 partition at this + # point + echo -e "n\np\n3\n\n4095\nt\na2\nn\np\n1\n\n+${sdcard_partition_size_fat32}\nt\n1\nb\nn\np\n2\n\n+${sdcard_partition_size_linux}\nt\n2\n83\nw\nq\n" | sudo fdisk "${sdcard_dev}" + + # create filesystems + sudo mkfs.vfat "${sdcard_dev_fat32}" + sudo mkfs.ext3 -F "${sdcard_dev_ext3}" +} + +# write_sdcard() ############################################################### +write_sdcard() { + # create mount point for sdcard + mkdir -p "${sdcard_dev_fat32_mount_point}" + mkdir -p "${sdcard_dev_ext3_mount_point}" + + # mount sdcard partitions + sudo mount "${sdcard_dev_fat32}" "${sdcard_dev_fat32_mount_point}" + sudo mount "${sdcard_dev_ext3}" "${sdcard_dev_ext3_mount_point}" + + # preloader + sudo dd if="${sdcard_a2_preloader_bin_file}" of="${sdcard_dev_a2}" bs=64K seek=0 + + # fpga .rbf, uboot .img, uboot .scr, linux zImage, linux .dtb + sudo cp "${sdcard_fat32_dir}"/* "${sdcard_dev_fat32_mount_point}" + + # linux rootfs + pushd "${sdcard_dev_ext3_mount_point}" + sudo tar -xzf "${sdcard_ext3_rootfs_tgz_file}" + popd + + # flush write buffers to target + sudo sync + + # unmount sdcard partitions + sudo umount "${sdcard_dev_fat32_mount_point}" + sudo umount "${sdcard_dev_ext3_mount_point}" + + # delete mount points for sdcard + rm -rf "${sdcard_dev_fat32_mount_point}" + rm -rf "${sdcard_dev_ext3_mount_point}" +} + +# Script execution ############################################################# + +# Report script line number on any error (non-zero exit code). +trap 'echo "Error on line ${LINENO}" 1>&2' ERR +set -e + +# Create sdcard output directories +mkdir -p "${sdcard_a2_dir}" +mkdir -p "${sdcard_fat32_dir}" + +compile_quartus_project +compile_preloader +compile_uboot +compile_linux +create_rootfs + +# Write sdcard if it exists +if [ -z "${sdcard_dev}" ]; then + echo "sdcard argument not provided => no sdcard written." + +elif [ -b "${sdcard_dev}" ]; then + partition_sdcard + write_sdcard +fi + +# Make sure MSEL = 000000 diff --git a/cs309-psoc/lab_3_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd b/cs309-psoc/lab_3_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd new file mode 100644 index 0000000..ff7fc2a --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd @@ -0,0 +1,330 @@ +-- ############################################################################# +-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +-- +-- BOARD : PrSoC extension board for DE0-Nano-SoC +-- Author : Florian Depraz based on Sahand Kashani-Akhavan work +-- Revision : 1.1 +-- Creation date : 06/02/2016 +-- +-- Syntax Rule : GROUP_NAME_N[bit] +-- +-- GROUP : specify a particular interface (ex: SDR_) +-- NAME : signal name (ex: CONFIG, D, ...) +-- bit : signal index +-- _N : to specify an active-low signal +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; + +entity DE0_Nano_SoC_PrSoC_extn_board_top_level is + port( + ------------------------------- + -- Comment ALL unused ports. -- + ------------------------------- + + -- CLOCK + FPGA_CLK1_50 : in std_logic; + -- FPGA_CLK2_50 : in std_logic; + -- FPGA_CLK3_50 : in std_logic; + + -- KEY on DE0 Nano SoC + KEY_N : in std_logic_vector(1 downto 0); + + -- LEDs on DE0 Nano SoC + -- LED : out std_logic_vector(7 downto 0); + + -- SWITCHES on DE0 Nano SoC + -- SW : in std_logic_vector(3 downto 0); + + -- Servomotors pwm + SERVO_0 : out std_logic; + SERVO_1 : out std_logic; + + -- ADC Joysticks + J0_SPI_CS_n : out std_logic; + J0_SPI_MOSI : out std_logic; + J0_SPI_MISO : in std_logic; + J0_SPI_CLK : out std_logic; + + -- Lepton + CAM_TH_SPI_CS_N : out std_logic; + CAM_TH_MISO : in std_logic; + CAM_TH_MOSI : out std_logic; + CAM_TH_CLK : out std_logic; + + -- PCA9637 + -- PIO_SCL : inout std_logic; + -- PIO_SDA : inout std_logic; + -- PIO_INT_N : in std_logic; + -- RESET_N : out std_logic; + + -- OV7670 + -- CAM_D : in std_logic_vector(9 downto 0); + -- CAM_PIX_CLK : in std_logic; + -- CAM_LV : in std_logic; + -- CAM_FV : in std_logic; + -- CAM_SYS_CLK : out std_logic; + + -- VGA and LCD shared signals + -- VIDEO_CLK : out std_logic; + -- VIDEO_VSYNC : out std_logic; + -- VIDEO_HSYNC : out std_logic; + -- VIDEO_B : out std_logic_vector(7 downto 0); + -- VIDEO_G : out std_logic_vector(7 downto 0); + -- VIDEO_R : out std_logic_vector(7 downto 0); + + -- LCD Specific signals + -- LCD_DE : out std_logic; + -- LCD_PIN_DAV_N : ? ?? std_logic; + -- LCD_DISPLAY_EN : out std_logic; + -- SPI_MISO : in std_logic; + -- SPI_ENA_N : out std_logic; + -- SPI_CLK : out std_logic; + -- SPI_MOSI : out std_logic; + -- SPI_DAT : inout std_logic; + + -- I2C TOUCH SCREEN + -- TS_SCL : inout std_logic; + -- TS_SDA : inout std_logic; + + -- BLUETOOTH (BLE) + -- BLT_TXD : in std_logic; + -- BLT_RXD : out std_logic; + + -- I2C For VGA, PAL and OV7670 cameras + -- CAM_PAL_VGA_SDA : inout std_logic; + -- CAM_PAL_VGA_SCL : inout std_logic; + + -- ONE WIRE + -- BOARD_ID : inout std_logic; + + -- PAL Camera + -- PAL_VD_VD : in std_logic_vector(7 downto 0); + -- PAL_VD_VSO : in std_logic; + -- PAL_VD_HSO : in std_logic; + -- PAL_VD_CLKO : in std_logic; + -- PAL_PWDN : out std_logic; + + -- WIFI + -- FROM_ESP_TXD : in std_logic; + -- TO_ESP_RXD : out std_logic; + + -- LED RGB + -- LED_BGR : out std_logic; + + -- HPS + HPS_CONV_USB_N : inout std_logic; + HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); + HPS_DDR3_BA : out std_logic_vector(2 downto 0); + HPS_DDR3_CAS_N : out std_logic; + HPS_DDR3_CK_N : out std_logic; + HPS_DDR3_CK_P : out std_logic; + HPS_DDR3_CKE : out std_logic; + HPS_DDR3_CS_N : out std_logic; + HPS_DDR3_DM : out std_logic_vector(3 downto 0); + HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); + HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); + HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); + HPS_DDR3_ODT : out std_logic; + HPS_DDR3_RAS_N : out std_logic; + HPS_DDR3_RESET_N : out std_logic; + HPS_DDR3_RZQ : in std_logic; + HPS_DDR3_WE_N : out std_logic; + HPS_ENET_GTX_CLK : out std_logic; + HPS_ENET_INT_N : inout std_logic; + HPS_ENET_MDC : out std_logic; + HPS_ENET_MDIO : inout std_logic; + HPS_ENET_RX_CLK : in std_logic; + HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); + HPS_ENET_RX_DV : in std_logic; + HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); + HPS_ENET_TX_EN : out std_logic; + HPS_GSENSOR_INT : inout std_logic; + HPS_I2C0_SCLK : inout std_logic; + HPS_I2C0_SDAT : inout std_logic; + HPS_I2C1_SCLK : inout std_logic; + HPS_I2C1_SDAT : inout std_logic; + HPS_KEY_N : inout std_logic; + -- HPS_LED : inout std_logic; + HPS_LTC_GPIO : inout std_logic; + HPS_SD_CLK : out std_logic; + HPS_SD_CMD : inout std_logic; + HPS_SD_DATA : inout std_logic_vector(3 downto 0); + HPS_SPIM_CLK : out std_logic; + HPS_SPIM_MISO : in std_logic; + HPS_SPIM_MOSI : out std_logic; + HPS_SPIM_SS : inout std_logic; + HPS_UART_RX : in std_logic; + HPS_UART_TX : out std_logic; + HPS_USB_CLKOUT : in std_logic; + HPS_USB_DATA : inout std_logic_vector(7 downto 0); + HPS_USB_DIR : in std_logic; + HPS_USB_NXT : in std_logic; + HPS_USB_STP : out std_logic + ); +end entity DE0_Nano_SoC_PrSoC_extn_board_top_level; + +architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is + component soc_system is + port ( + clk_clk : in std_logic := 'X'; -- clk + hps_0_ddr_mem_a : out std_logic_vector(14 downto 0); -- mem_a + hps_0_ddr_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba + hps_0_ddr_mem_ck : out std_logic; -- mem_ck + hps_0_ddr_mem_ck_n : out std_logic; -- mem_ck_n + hps_0_ddr_mem_cke : out std_logic; -- mem_cke + hps_0_ddr_mem_cs_n : out std_logic; -- mem_cs_n + hps_0_ddr_mem_ras_n : out std_logic; -- mem_ras_n + hps_0_ddr_mem_cas_n : out std_logic; -- mem_cas_n + hps_0_ddr_mem_we_n : out std_logic; -- mem_we_n + hps_0_ddr_mem_reset_n : out std_logic; -- mem_reset_n + hps_0_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq + hps_0_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs + hps_0_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n + hps_0_ddr_mem_odt : out std_logic; -- mem_odt + hps_0_ddr_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm + hps_0_ddr_oct_rzqin : in std_logic := 'X'; -- oct_rzqin + hps_0_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK + hps_0_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0 + hps_0_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1 + hps_0_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2 + hps_0_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3 + hps_0_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0 + hps_0_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO + hps_0_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC + hps_0_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL + hps_0_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL + hps_0_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK + hps_0_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1 + hps_0_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2 + hps_0_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3 + hps_0_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD + hps_0_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0 + hps_0_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1 + hps_0_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK + hps_0_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2 + hps_0_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3 + hps_0_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0 + hps_0_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1 + hps_0_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2 + hps_0_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3 + hps_0_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4 + hps_0_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5 + hps_0_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6 + hps_0_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7 + hps_0_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK + hps_0_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP + hps_0_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR + hps_0_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT + hps_0_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK + hps_0_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI + hps_0_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO + hps_0_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0 + hps_0_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX + hps_0_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX + hps_0_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA + hps_0_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL + hps_0_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA + hps_0_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL + hps_0_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09 + hps_0_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35 + hps_0_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40 + hps_0_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54 + hps_0_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61 + lepton_0_spi_cs_n : out std_logic; -- cs_n + lepton_0_spi_miso : in std_logic := 'X'; -- miso + lepton_0_spi_mosi : out std_logic; -- mosi + lepton_0_spi_sclk : out std_logic; -- sclk + mcp3204_0_conduit_end_cs_n : out std_logic; -- cs_n + mcp3204_0_conduit_end_mosi : out std_logic; -- mosi + mcp3204_0_conduit_end_miso : in std_logic := 'X'; -- miso + mcp3204_0_conduit_end_sclk : out std_logic; -- sclk + pwm_0_conduit_end_pwm : out std_logic; -- pwm + pwm_1_conduit_end_pwm : out std_logic; -- pwm + reset_reset_n : in std_logic := 'X' -- reset_n + ); + end component soc_system; + + + begin + u0 : component soc_system + port map ( + clk_clk => FPGA_CLK1_50, -- clk.clk + hps_0_ddr_mem_a => HPS_DDR3_ADDR, -- hps_0_ddr.mem_a + hps_0_ddr_mem_ba => HPS_DDR3_BA, -- .mem_ba + hps_0_ddr_mem_ck => HPS_DDR3_CK_P, -- .mem_ck + hps_0_ddr_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n + hps_0_ddr_mem_cke => HPS_DDR3_CKE, -- .mem_cke + hps_0_ddr_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n + hps_0_ddr_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n + hps_0_ddr_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n + hps_0_ddr_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n + hps_0_ddr_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n + hps_0_ddr_mem_dq => HPS_DDR3_DQ, -- .mem_dq + hps_0_ddr_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs + hps_0_ddr_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n + hps_0_ddr_mem_odt => HPS_DDR3_ODT, -- .mem_odt + hps_0_ddr_mem_dm => HPS_DDR3_DM, -- .mem_dm + hps_0_ddr_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin + hps_0_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK, -- hps_0_io.hps_io_emac1_inst_TX_CLK + hps_0_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0), -- .hps_io_emac1_inst_TXD0 + hps_0_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1), -- .hps_io_emac1_inst_TXD1 + hps_0_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), -- .hps_io_emac1_inst_TXD2 + hps_0_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), -- .hps_io_emac1_inst_TXD3 + hps_0_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), -- .hps_io_emac1_inst_RXD0 + hps_0_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO, -- .hps_io_emac1_inst_MDIO + hps_0_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC, -- .hps_io_emac1_inst_MDC + hps_0_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV, -- .hps_io_emac1_inst_RX_CTL + hps_0_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN, -- .hps_io_emac1_inst_TX_CTL + hps_0_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK, -- .hps_io_emac1_inst_RX_CLK + hps_0_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), -- .hps_io_emac1_inst_RXD1 + hps_0_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), -- .hps_io_emac1_inst_RXD2 + hps_0_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), -- .hps_io_emac1_inst_RXD3 + hps_0_io_hps_io_sdio_inst_CMD => HPS_SD_CMD, -- .hps_io_sdio_inst_CMD + hps_0_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), -- .hps_io_sdio_inst_D0 + hps_0_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), -- .hps_io_sdio_inst_D1 + hps_0_io_hps_io_sdio_inst_CLK => HPS_SD_CLK, -- .hps_io_sdio_inst_CLK + hps_0_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), -- .hps_io_sdio_inst_D2 + hps_0_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), -- .hps_io_sdio_inst_D3 + hps_0_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), -- .hps_io_usb1_inst_D0 + hps_0_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), -- .hps_io_usb1_inst_D1 + hps_0_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), -- .hps_io_usb1_inst_D2 + hps_0_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), -- .hps_io_usb1_inst_D3 + hps_0_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), -- .hps_io_usb1_inst_D4 + hps_0_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), -- .hps_io_usb1_inst_D5 + hps_0_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), -- .hps_io_usb1_inst_D6 + hps_0_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), -- .hps_io_usb1_inst_D7 + hps_0_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT, -- .hps_io_usb1_inst_CLK + hps_0_io_hps_io_usb1_inst_STP => HPS_USB_STP, -- .hps_io_usb1_inst_STP + hps_0_io_hps_io_usb1_inst_DIR => HPS_USB_DIR, -- .hps_io_usb1_inst_DIR + hps_0_io_hps_io_usb1_inst_NXT => HPS_USB_NXT, -- .hps_io_usb1_inst_NXT + hps_0_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK, -- .hps_io_spim1_inst_CLK + hps_0_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI, -- .hps_io_spim1_inst_MOSI + hps_0_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO, -- .hps_io_spim1_inst_MISO + hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS, -- .hps_io_spim1_inst_SS0 + hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX, -- .hps_io_uart0_inst_RX + hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX, -- .hps_io_uart0_inst_TX + hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C0_SDAT, -- .hps_io_i2c0_inst_SDA + hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C0_SCLK, -- .hps_io_i2c0_inst_SCL + hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C1_SDAT, -- .hps_io_i2c1_inst_SDA + hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C1_SCLK, -- .hps_io_i2c1_inst_SCL + hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N, -- .hps_io_gpio_inst_GPIO09 + hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N, -- .hps_io_gpio_inst_GPIO35 + hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO, -- .hps_io_gpio_inst_GPIO40 + hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N, -- .hps_io_gpio_inst_GPIO54 + hps_0_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT, -- .hps_io_gpio_inst_GPIO61 + lepton_0_spi_cs_n => CAM_TH_SPI_CS_N, -- lepton_0_spi.cs_n + lepton_0_spi_miso => CAM_TH_MISO, -- .miso + lepton_0_spi_mosi => CAM_TH_MOSI, -- .mosi + lepton_0_spi_sclk => CAM_TH_CLK, -- .sclk + mcp3204_0_conduit_end_cs_n => J0_SPI_CS_n, -- mcp3204_0_conduit_end.cs_n + mcp3204_0_conduit_end_mosi => J0_SPI_MOSI, -- .mosi + mcp3204_0_conduit_end_miso => J0_SPI_MISO, -- .miso + mcp3204_0_conduit_end_sclk => J0_SPI_CLK, -- .sclk + pwm_0_conduit_end_pwm => SERVO_0, -- pwm_0_conduit_end.pwm + pwm_1_conduit_end_pwm => SERVO_1, -- pwm_1_conduit_end.pwm + reset_reset_n => KEY_N(0) -- reset.reset_n + ); + +end; diff --git a/cs309-psoc/lab_3_1/hw/hdl/joysticks/hdl/mcp3204.vhd b/cs309-psoc/lab_3_1/hw/hdl/joysticks/hdl/mcp3204.vhd new file mode 100644 index 0000000..af0aafb --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/joysticks/hdl/mcp3204.vhd @@ -0,0 +1,138 @@ +-- ############################################################################# +-- mcp3204.vhd +-- =========== +-- MCP3204 Avalon-MM slave interface. +-- +-- Register map +-- +-------+-----------+--------+------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +-------+-----------+--------+------------------------------------+ +-- | 0 | CHANNEL_0 | RO | 12-bit digital value of channel 0. | +-- +-------+-----------+--------+------------------------------------+ +-- | 1 | CHANNEL_1 | RO | 12-bit digital value of channel 1. | +-- +-------+-----------+--------+------------------------------------+ +-- | 2 | CHANNEL_2 | RO | 12-bit digital value of channel 2. | +-- +-------+-----------+--------+------------------------------------+ +-- | 3 | CHANNEL_3 | RO | 12-bit digital value of channel 3. | +-- +-------+-----------+--------+------------------------------------+ +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity mcp3204 is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + readdata : out std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic; + SCLK : out std_logic + ); +end entity; + +architecture arch of mcp3204 is + constant NUM_CHANNELS : positive := 4; + constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS)))); + + type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range); + signal data_reg : data_array; + + signal spi_busy, spi_start, spi_datavalid : std_logic; + signal spi_channel : std_logic_vector(1 downto 0); + signal spi_data : std_logic_vector(11 downto 0); + + type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA); + signal state : state_t; + + signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0); + +begin + SPI : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => spi_busy, + start => spi_start, + channel => spi_channel, + data_valid => spi_datavalid, + data => spi_data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + -- FSM that dictates which channel is being read. The state of the component + -- should be thought as the pair (state, channel) + p_fsm : process(reset, clk) + begin + if reset = '1' then + state <= READY; + channel <= (others => '0'); + elsif rising_edge(clk) then + case state is + when READY => + if spi_busy = '0' then + state <= INIT_READ_CHANNEL; + end if; + + when INIT_READ_CHANNEL => + state <= WAIT_FOR_DATA; + + when WAIT_FOR_DATA => + if spi_datavalid = '1' then + state <= READY; + channel <= channel + 1; + end if; + end case; + end if; + end process p_fsm; + + -- Updates the internal registers when a new data is available + p_data : process(reset, clk) + begin + if reset = '1' then + for i in 0 to NUM_CHANNELS - 1 loop + data_reg(i) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + if state = WAIT_FOR_DATA and spi_datavalid = '1' then + data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data; + end if; + end if; + end process p_data; + + spi_start <= '1' when state = INIT_READ_CHANNEL else '0'; + spi_channel <= std_logic_vector(channel); + + -- Interface with the Avalon Switch Fabric + p_avalon_read : process(reset, clk) + begin + if reset = '1' then + readdata <= (others => '0'); + elsif rising_edge(clk) then + if read = '1' then + readdata <= data_reg(to_integer(unsigned(address))); + end if; + end if; + end process p_avalon_read; + +end architecture; diff --git a/cs309-psoc/lab_3_1/hw/hdl/joysticks/hdl/mcp3204_hw.tcl b/cs309-psoc/lab_3_1/hw/hdl/joysticks/hdl/mcp3204_hw.tcl new file mode 100644 index 0000000..757514d --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/joysticks/hdl/mcp3204_hw.tcl @@ -0,0 +1,137 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 18:14:06 CET 2017 +# DO NOT MODIFY + + +# +# mcp3204 "mcp3204" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.18:14:06 +# 4-Channel 12-Bit A/D Converter with SPI Serial Interface +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module mcp3204 +# +set_module_property DESCRIPTION "4-Channel 12-Bit A/D Converter with SPI Serial Interface" +set_module_property NAME mcp3204 +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Joystick +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME mcp3204 +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL mcp3204 +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file mcp3204.vhd VHDL PATH mcp3204.vhd TOP_LEVEL_FILE +add_fileset_file mcp3204_spi.vhd VHDL PATH mcp3204_spi.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end CS_N cs_n Output 1 +add_interface_port conduit_end MOSI mosi Output 1 +add_interface_port conduit_end MISO miso Input 1 +add_interface_port conduit_end SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_3_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd b/cs309-psoc/lab_3_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd new file mode 100644 index 0000000..f5e072e --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd @@ -0,0 +1,87 @@ +-- ############################################################################# +-- mcp3204_spi.vhd +-- =============== +-- MCP3204 SPI interface. +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Author : () +-- Revision : 1 +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mcp3204_spi is + port( + -- 50 MHz + clk : in std_logic; + reset : in std_logic; + busy : out std_logic; + start : in std_logic; + channel : in std_logic_vector(1 downto 0); + data_valid : out std_logic; + data : out std_logic_vector(11 downto 0); + + -- 1 MHz + SCLK : out std_logic; + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); +end mcp3204_spi; + +architecture rtl of mcp3204_spi is + signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24 + signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz + signal reg_rising_edge_sclk : std_logic := '0'; + signal reg_falling_edge_sclk : std_logic := '0'; + + signal reg_sclk : std_logic := '0'; + +begin + clk_divider_generation : process(clk, reset) + begin + if reset = '1' then + reg_clk_divider_counter <= (others => '0'); + elsif rising_edge(clk) then + reg_clk_divider_counter <= reg_clk_divider_counter + 1; + reg_spi_en <= '0'; + reg_rising_edge_sclk <= '0'; + reg_falling_edge_sclk <= '0'; + + if reg_clk_divider_counter = 24 then + reg_clk_divider_counter <= (others => '0'); + reg_spi_en <= '1'; + + if reg_sclk = '0' then + reg_rising_edge_sclk <= '1'; + elsif reg_sclk = '1' then + reg_falling_edge_sclk <= '1'; + end if; + end if; + end if; + end process; + + SCLK_generation : process(clk, reset) + begin + if reset = '1' then + reg_sclk <= '0'; + elsif rising_edge(clk) then + if reg_spi_en = '1' then + reg_sclk <= not reg_sclk; + end if; + end if; + end process; + + STATE_LOGIC : process(clk, reset) + begin + -- TODO: complete this process + if reset = '1' then + elsif rising_edge(clk) then + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_3_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd b/cs309-psoc/lab_3_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd new file mode 100644 index 0000000..1bb61d2 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd @@ -0,0 +1,103 @@ +-- ############################################################################# +-- tb_mcp3204_spi.vhd +-- ================== +-- Testbench for MCP3204 SPI interface. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 1 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_mcp3204_spi is +end entity; + +architecture rtl of tb_mcp3204_spi is + constant CLK_PERIOD : time := 20 ns; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal sim_finished : boolean := false; + + -- mcp3204_spi ------------------------------------------------------------ + signal busy : std_logic := '0'; + signal start : std_logic := '0'; + signal channel : std_logic_vector(1 downto 0) := (others => '0'); + signal data_valid : std_logic := '0'; + signal data : std_logic_vector(11 downto 0) := (others => '0'); + signal SCLK : std_logic := '0'; + signal CS_N : std_logic := '1'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '0'; + +begin + duv : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => busy, + start => start, + channel => channel, + data_valid => data_valid, + data => data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_finished; + + sim : process + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + reset <= '1'; + + wait for CLK_PERIOD / 2; + reset <= '0'; + end procedure async_reset; + + procedure spi_transfer(constant channel_number : natural range 0 to 3) is + begin + if busy = '1' then + wait until busy = '0'; + + else + wait until falling_edge(clk); + start <= '1'; + channel <= std_logic_vector(to_unsigned(channel_number, channel'length)); + + wait until falling_edge(clk); + start <= '0'; + channel <= (others => '0'); + + wait until rising_edge(data_valid); + wait until falling_edge(busy); + end if; + end procedure spi_transfer; + + begin + async_reset; + + MISO <= '1'; + spi_transfer(0); + + MISO <= '0'; + spi_transfer(1); + + MISO <= '1'; + spi_transfer(2); + + MISO <= '0'; + spi_transfer(3); + + sim_finished <= true; + wait; + end process sim; +end architecture rtl; + + diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd new file mode 100644 index 0000000..9769bb8 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd @@ -0,0 +1,139 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.utils.all; + +entity avalon_st_spi_master is + generic( + INPUT_CLK_FREQ : integer := 50000000; + SPI_SCLK_FREQ : integer := 10000000; + CPOL : integer := 1; + CPHA : integer := 1 + ); + port( + -- Input clock + clk : in std_logic; + + -- Reset + reset : in std_logic; + spi_cs_n : in std_logic; + -- Sink Avalon ST Interface + mosi_sink_data : in std_logic_vector(7 downto 0); + mosi_sink_valid : in std_logic; + mosi_sink_ready : out std_logic; + + -- Source Avalon ST Interface + miso_src_data : out std_logic_vector(7 downto 0); + miso_src_valid : out std_logic; + + -- SPI Master signals + SCLK : out std_logic; + MISO : in std_logic; + MOSI : out std_logic; + CS_n : out std_logic + ); +end avalon_st_spi_master; + +architecture rtl of avalon_st_spi_master is + constant SCLK_PRESCALER_MAX : integer := INPUT_CLK_FREQ / SPI_SCLK_FREQ / 2; + signal sclk_prescaler : unsigned(bitlength(SCLK_PRESCALER_MAX) downto 0); + signal sclk_toggle : std_logic; + + signal new_sink_buffer, cur_sink_buffer : std_logic_vector(mosi_sink_data'range); + signal new_sink_buffer_busy, cur_sink_buffer_busy : std_logic; + + signal miso_src_buffer : std_logic_vector(7 downto 0); + + signal spi_done, i_sclk : std_logic; + signal spi_bit_index : unsigned(2 downto 0); +begin + CS_n <= spi_cs_n; + + p_sclk_prescaler : process(clk, reset) is + begin + if reset = '1' then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + elsif rising_edge(clk) then + if sclk_prescaler = SCLK_PRESCALER_MAX then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + else + sclk_prescaler <= sclk_prescaler + 1; + end if; + end if; + end process p_sclk_prescaler; + sclk_toggle <= '1' when sclk_prescaler = SCLK_PRESCALER_MAX else '0'; + + p_avalon_st_sink : process(clk, reset) is + begin + if reset = '1' then + new_sink_buffer_busy <= '0'; + new_sink_buffer <= (others => '0'); + elsif rising_edge(clk) then + if mosi_sink_valid = '1' then + if new_sink_buffer_busy = '0' and cur_sink_buffer_busy = '1' then + new_sink_buffer <= mosi_sink_data; + new_sink_buffer_busy <= '1'; + end if; + elsif new_sink_buffer_busy = '1' and cur_sink_buffer_busy = '0' then + new_sink_buffer_busy <= '0'; + end if; + end if; + end process p_avalon_st_sink; + mosi_sink_ready <= not new_sink_buffer_busy; + + p_cur_buffer : process(clk, reset) is + begin + if reset = '1' then + cur_sink_buffer <= (others => '0'); + cur_sink_buffer_busy <= '0'; + elsif rising_edge(clk) then + if mosi_sink_valid = '1' and cur_sink_buffer_busy = '0' then + cur_sink_buffer <= mosi_sink_data; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '0' and new_sink_buffer_busy = '1' then + cur_sink_buffer <= new_sink_buffer; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '1' and spi_done = '1' then + cur_sink_buffer_busy <= '0'; + end if; + end if; + end process p_cur_buffer; + + p_spi : process(clk, reset) is + begin + if reset = '1' then + spi_done <= '0'; + i_sclk <= to_unsigned(CPOL, 1)(0); + spi_bit_index <= "000"; + MOSI <= '0'; + miso_src_data <= (others => '0'); + miso_src_valid <= '0'; + miso_src_buffer <= (others => '0'); + + elsif rising_edge(clk) then + spi_done <= '0'; + miso_src_valid <= '0'; + if cur_sink_buffer_busy = '1' and sclk_toggle = '1' then + if i_sclk /= to_unsigned(CPHA, 1)(0) then + if spi_bit_index = "111" then + spi_done <= '1'; + spi_bit_index <= "000"; + miso_src_valid <= '1'; + miso_src_data <= miso_src_buffer(7 downto 1) & MISO; + else + MOSI <= cur_sink_buffer(7 - to_integer(spi_bit_index)); + miso_src_buffer(7 - to_integer(spi_bit_index)) <= MISO; + spi_bit_index <= spi_bit_index + 1; + + end if; + + end if; + + i_sclk <= not i_sclk; + + end if; + end if; + end process p_spi; + SCLK <= i_sclk; + +end rtl; diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/byte2pix.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/byte2pix.vhd new file mode 100644 index 0000000..b888ba9 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/byte2pix.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------- +-- Title : Byte stream to pixel converter for the Lepton Camera +-- Project : PrSoC +------------------------------------------------------------------------------- +-- File : byte2pix.vhd +-- Author : Philemon Orphee Favrod +-- Company : +-- Created : 2016-03-21 +-- Last update: 2017-03-19 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: Converts a byte stream to a 14-bit pixel stream. +------------------------------------------------------------------------------- +-- Copyright (c) 2016 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2016-03-21 1.0 pofavrod Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity byte2pix is + port( + clk, reset : in std_logic; + byte_data : in std_logic_vector(7 downto 0); + byte_valid : in std_logic; + byte_sof : in std_logic; + byte_eof : in std_logic; + pix_data : out std_logic_vector(13 downto 0); + pix_valid : out std_logic; + pix_sof : out std_logic; + pix_eof : out std_logic); + +end byte2pix; + +architecture rtl of byte2pix is + signal last_sof : std_logic; + signal msb : std_logic_vector(5 downto 0); + signal cnt : std_logic; -- used to skip msb sampling every other time +begin + process(clk, reset) + begin + if reset = '1' then + msb <= (others => '0'); + cnt <= '0'; + last_sof <= '0'; + elsif rising_edge(clk) then + if byte_valid = '1' then + if cnt = '0' then + msb <= byte_data(5 downto 0); + last_sof <= byte_sof; + end if; + cnt <= not cnt; + end if; + end if; + end process; + + process(clk, reset) + begin + if reset = '1' then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + elsif rising_edge(clk) then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + + if byte_valid = '1' then + if cnt = '1' then + pix_data <= msb & byte_data; + pix_valid <= '1'; + pix_sof <= last_sof; + pix_eof <= byte_eof; + end if; + end if; + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd new file mode 100644 index 0000000..d4b4812 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd @@ -0,0 +1,192 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: dual_ported_ram.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +entity dual_ported_ram is + port( + clock : in std_logic := '1'; + data : in std_logic_vector(15 downto 0); + rdaddress : in std_logic_vector(12 downto 0); + wraddress : in std_logic_vector(12 downto 0); + wren : in std_logic := '0'; + q : out std_logic_vector(15 downto 0) + ); +end dual_ported_ram; + +architecture SYN of dual_ported_ram is + signal sub_wire0 : std_logic_vector(15 downto 0); + +begin + q <= sub_wire0(15 downto 0); + + altsyncram_component : altsyncram + generic map( + address_aclr_b => "NONE", + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 8192, + numwords_b => 8192, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "CLOCK0", + power_up_uninitialized => "FALSE", + read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => 13, + widthad_b => 13, + width_a => 16, + width_b => 16, + width_byteena_a => 1 + ) + port map( + address_a => wraddress, + address_b => rdaddress, + clock0 => clock, + data_a => data, + wren_a => wren, + q_b => sub_wire0 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]" +-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 +-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton.vhd new file mode 100644 index 0000000..82678ba --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton.vhd @@ -0,0 +1,288 @@ +-- Lepton Avalon Memory-Mapped Slave Interface +-- Author: Philémon Favrod (philemon.favrod@epfl.ch) +-- Modified by: Sahand Kashani-Akhavan (sahand.kashani-akhavan@epfl.ch) +-- Revision: 2 + +-- Register map +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 0 | COMMAND | WO | Command | +-- | | | | - Writing 1 starts capturing a frame & resets the | +-- | | | | ERROR bit (bit 1) in the STATUS register. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 1 | STATUS | RO | Status | +-- | | | | - Bit 0: 0 --> no capture in progress. | +-- | | | | 1 --> capture in progress. | +-- | | | | - Bit 1: 0 --> previous capture successful. | +-- | | | | 1 --> error during previous capture. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 2 | MIN | RO | Minimum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 3 | MAX | RO | Maximum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4 | SUM_LSB | RO | Sum of all pixels in frame (low 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 5 | SUM_MSB | RO | Sum of all pixels in frame (high 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 6 | ROW_IDX | RO | Current line being captured (1 <= ROW_IDX <= 60). | +-- | | | | Available for debugging purposes. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 7 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8 - 4807 | RAW BUFFER | RO | View into RAW pixel buffer. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4808 - 8191 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8192 - 12991 | ADJUSTED BUFFER | RO | View into adjusted (scaled) pixel buffer. | +-- | | | | Values are scaled between MIN and MAX. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 12992 - 16383 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton is + port( + clk : in std_logic; + reset : in std_logic; + address : in std_logic_vector(13 downto 0); + readdata : out std_logic_vector(15 downto 0); + writedata : in std_logic_vector(15 downto 0); + read : in std_logic; + write : in std_logic; + + SCLK : out std_logic; + CSn : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); + +end lepton; + +architecture rtl of lepton is + signal spi_cs_n : std_logic; + signal spi_mosi_data : std_logic_vector(7 downto 0); + signal spi_mosi_valid : std_logic; + signal spi_mosi_ready : std_logic; + signal spi_miso_data : std_logic_vector(7 downto 0); + signal spi_miso_valid : std_logic; + signal lepton_manager_start : std_logic; + signal lepton_manager_error : std_logic; + signal byte_data : std_logic_vector(7 downto 0); + signal byte_valid : std_logic; + signal byte_sof : std_logic; + signal byte_eof : std_logic; + signal pix_data : std_logic_vector(13 downto 0); + signal pix_valid : std_logic; + signal pix_sof : std_logic; + signal pix_eof : std_logic; + signal stat_min : std_logic_vector(13 downto 0); + signal stat_max : std_logic_vector(13 downto 0); + signal stat_sum : std_logic_vector(26 downto 0); + signal stat_valid : std_logic; + signal ram_data : std_logic_vector(15 downto 0); + signal ram_wren : std_logic; + signal ram_wraddress : std_logic_vector(12 downto 0); + signal ram_rdaddress : std_logic_vector(12 downto 0); + signal ram_q : std_logic_vector(15 downto 0); + signal row_idx : std_logic_vector(5 downto 0); + signal raw_pixel : std_logic_vector(13 downto 0); + signal raw_max : std_logic_vector(13 downto 0); + signal raw_min : std_logic_vector(13 downto 0); + signal raw_sum : std_logic_vector(26 downto 0); + signal adjusted_pixel : std_logic_vector(13 downto 0); + + constant COMMAND_REG_OFFSET : std_logic_vector(address'range) := "00000000000000"; + constant STATUS_REG_OFFSET : std_logic_vector(address'range) := "00000000000001"; + constant MIN_REG_OFFSET : std_logic_vector(address'range) := "00000000000010"; + constant MAX_REG_OFFSET : std_logic_vector(address'range) := "00000000000011"; + constant SUM_LSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000100"; + constant SUM_MSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000101"; + constant ROW_IDX_REG_OFFSET : std_logic_vector(address'range) := "00000000000110"; + constant BUFFER_REG_OFFSET : unsigned(address'range) := "00000000001000"; + constant ADJUSTED_BUFFER_REG_OFFSET : unsigned(address'range) := "10000000000000"; + + constant IMAGE_SIZE : integer := 80 * 60; + constant BUFFER_REG_LIMIT : unsigned(address'range) := unsigned(BUFFER_REG_OFFSET) + IMAGE_SIZE; + + constant ADJUSTED_BUFFER_LIMIT : unsigned(address'range) := unsigned(ADJUSTED_BUFFER_REG_OFFSET) + IMAGE_SIZE; + + signal max_reg : std_logic_vector(stat_max'range); + signal min_reg : std_logic_vector(stat_min'range); + signal sum_reg : std_logic_vector(stat_sum'range); + signal error_reg : std_logic; + +begin + spi_controller0 : entity work.avalon_st_spi_master + port map( + clk => clk, + reset => reset, + spi_cs_n => spi_cs_n, + mosi_sink_data => spi_mosi_data, + mosi_sink_valid => spi_mosi_valid, + mosi_sink_ready => spi_mosi_ready, + miso_src_data => spi_miso_data, + miso_src_valid => spi_miso_valid, + SCLK => SCLK, + MISO => MISO, + MOSI => MOSI, + CS_n => CSn + ); + + lepton_manager0 : entity work.lepton_manager + port map( + clk => clk, + reset => reset, + spi_miso_sink_data => spi_miso_data, + spi_miso_sink_valid => spi_miso_valid, + spi_mosi_src_data => spi_mosi_data, + spi_mosi_src_valid => spi_mosi_valid, + spi_mosi_src_ready => spi_mosi_ready, + lepton_out_data => byte_data, + lepton_out_valid => byte_valid, + lepton_out_sof => byte_sof, + lepton_out_eof => byte_eof, + row_idx => row_idx, + error => lepton_manager_error, + start => lepton_manager_start, + spi_cs_n => spi_cs_n + ); + + byte2pix0 : entity work.byte2pix + port map( + clk => clk, + reset => reset, + byte_data => byte_data, + byte_valid => byte_valid, + byte_sof => byte_sof, + byte_eof => byte_eof, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof + ); + + lepton_stats0 : entity work.lepton_stats + port map( + reset => reset, + clk => clk, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + stat_min => stat_min, + stat_max => stat_max, + stat_sum => stat_sum, + stat_valid => stat_valid + ); + + ram_writer0 : entity work.ram_writer + port map( + clk => clk, + reset => reset, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + ram_data => ram_data, + ram_wren => ram_wren, + ram_wraddress => ram_wraddress + ); + + dual_ported_ram0 : entity work.dual_ported_ram + port map( + clock => clk, + data => ram_data, + rdaddress => ram_rdaddress, + wraddress => ram_wraddress, + wren => ram_wren, + q => ram_q + ); + + level_adjuster0 : entity work.level_adjuster + port map( + clk => clk, + raw_pixel => ram_q(13 downto 0), + raw_max => max_reg, + raw_min => min_reg, + raw_sum => sum_reg, + adjusted_pixel => adjusted_pixel + ); + + p_lepton_start : process(clk, reset) + begin + if reset = '1' then + lepton_manager_start <= '0'; + error_reg <= '0'; + elsif rising_edge(clk) then + if write = '1' and address = COMMAND_REG_OFFSET then + lepton_manager_start <= writedata(0); + error_reg <= '0'; + elsif pix_eof = '1' then + lepton_manager_start <= '0'; + elsif lepton_manager_error = '1' then + error_reg <= '1'; + end if; + end if; + end process p_lepton_start; + + p_stat_reg : process(clk, reset) + begin + if reset = '1' then + min_reg <= (others => '0'); + max_reg <= (others => '0'); + sum_reg <= (others => '0'); + elsif rising_edge(clk) then + if stat_valid = '1' then + min_reg <= stat_min; + max_reg <= stat_max; + sum_reg <= stat_sum; + end if; + end if; + end process p_stat_reg; + + p_read : process(clk, reset) + begin + if reset = '1' then + readdata <= (others => '0'); + ram_rdaddress <= (others => '0'); + elsif rising_edge(clk) then + readdata <= (others => '0'); + if read = '1' then + case address is + when STATUS_REG_OFFSET => + readdata(1) <= error_reg; + readdata(0) <= lepton_manager_start; + + when MIN_REG_OFFSET => + readdata <= "00" & min_reg; + + when MAX_REG_OFFSET => + readdata <= "00" & max_reg; + + when SUM_MSB_REG_OFFSET => + readdata <= "00000" & sum_reg(26 downto 16); + + when SUM_LSB_REG_OFFSET => + readdata <= sum_reg(15 downto 0); + + when ROW_IDX_REG_OFFSET => + readdata(5 downto 0) <= row_idx; + + when others => + if unsigned(address) >= BUFFER_REG_OFFSET and unsigned(address) < BUFFER_REG_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= ram_q; + elsif unsigned(address) >= ADJUSTED_BUFFER_REG_OFFSET and unsigned(address) < ADJUSTED_BUFFER_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - ADJUSTED_BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= "00" & adjusted_pixel; + end if; + end case; + end if; + end if; + end process p_read; + +end rtl; diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton_hw.tcl b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton_hw.tcl new file mode 100644 index 0000000..d62e01b --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton_hw.tcl @@ -0,0 +1,148 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 19:05:24 CET 2017 +# DO NOT MODIFY + + +# +# lepton "lepton" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.19:05:24 +# IR Camera 80x60 +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module lepton +# +set_module_property DESCRIPTION "IR Camera 80x60" +set_module_property NAME lepton +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Camera +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME lepton +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL lepton +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file avalon_st_spi_master.vhd VHDL PATH avalon_st_spi_master.vhd +add_fileset_file byte2pix.vhd VHDL PATH byte2pix.vhd +add_fileset_file dual_ported_ram.vhd VHDL PATH dual_ported_ram.vhd +add_fileset_file lepton.vhd VHDL PATH lepton.vhd TOP_LEVEL_FILE +add_fileset_file lepton_manager.vhd VHDL PATH lepton_manager.vhd +add_fileset_file lepton_stats.vhd VHDL PATH lepton_stats.vhd +add_fileset_file ram_writer.vhd VHDL PATH ram_writer.vhd +add_fileset_file utils.vhd VHDL PATH utils.vhd +add_fileset_file level_adjuster.vhd VHDL PATH level_adjuster.vhd +add_fileset_file lpm_divider.vhd VHDL PATH lpm_divider.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitStates 9 +set_interface_property avalon_slave_0 readWaitTime 9 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 14 +add_interface_port avalon_slave_0 readdata readdata Output 16 +add_interface_port avalon_slave_0 writedata writedata Input 16 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point spi +# +add_interface spi conduit end +set_interface_property spi associatedClock clock +set_interface_property spi associatedReset "" +set_interface_property spi ENABLED true +set_interface_property spi EXPORT_OF "" +set_interface_property spi PORT_NAME_MAP "" +set_interface_property spi CMSIS_SVD_VARIABLES "" +set_interface_property spi SVD_ADDRESS_GROUP "" + +add_interface_port spi CSn cs_n Output 1 +add_interface_port spi MISO miso Input 1 +add_interface_port spi MOSI mosi Output 1 +add_interface_port spi SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton_manager.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton_manager.vhd new file mode 100644 index 0000000..1580be1 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton_manager.vhd @@ -0,0 +1,235 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_manager is + generic( + INPUT_CLK_FREQ : integer := 50000000); + port( + clk : in std_logic := '0'; + reset : in std_logic := '0'; + + -- Avalon ST Sink to receive SPI data + spi_miso_sink_data : in std_logic_vector(7 downto 0); + spi_miso_sink_valid : in std_logic; + + -- Avalon ST Source to send SPI data + spi_mosi_src_data : out std_logic_vector(7 downto 0); + spi_mosi_src_valid : out std_logic; + spi_mosi_src_ready : in std_logic := '0'; + + -- Filtered output to retransmit cleaned data (without the discard packets, see Lepton Datasheet on page 31) + -- lepton_out_data is valid on rising edge when lepton_src_valid = '1' + lepton_out_data : out std_logic_vector(7 downto 0); + lepton_out_valid : out std_logic; + lepton_out_sof : out std_logic; + lepton_out_eof : out std_logic; + + -- Some status + row_idx : out std_logic_vector(5 downto 0); + error : out std_logic; + + -- Avalon MM Slave interface for configuration + start : in std_logic; + + -- The SPI Chip Select (Active low !) + spi_cs_n : out std_logic := '0'); +end entity lepton_manager; + +architecture rtl of lepton_manager is + type state_t is (Idle, CSn, ReadHeader, ReadPayload, DiscardPayload, WaitBeforeIdle); + signal state, next_state : state_t; + + signal header_3_last_nibbles : std_logic_vector(11 downto 0); + + constant CLOCK_TICKS_PER_37_MS : integer := 37 * (INPUT_CLK_FREQ / 1e3); -- the timeout delay for a frame + constant CLOCK_TICKS_PER_200_MS : integer := 200 * (INPUT_CLK_FREQ / 1e3); + constant CLOCK_TICKS_PER_200_NS : integer := (200 * (INPUT_CLK_FREQ / 1e6)) / 1e3; + constant BYTES_PER_HEADER : integer := 4; + constant BYTES_PER_PAYLOAD : integer := 160; + + constant NUMBER_OF_LINES_PER_FRAME : positive := 60; + signal counter, counter_max : integer range 1 to CLOCK_TICKS_PER_200_MS; + signal line_counter : integer range 1 to NUMBER_OF_LINES_PER_FRAME; + signal timeout_counter : integer range 1 to CLOCK_TICKS_PER_37_MS; + signal counter_enabled : boolean; + signal waited_long_enough : boolean; + signal header_end, payload_end : boolean; +begin + + -- purpose: register for state + p_fsm : process(clk, reset) + begin + if reset = '1' then + state <= Idle; + elsif rising_edge(clk) then + state <= next_state; + end if; + end process p_fsm; + + -- purpose: compute the next state + p_nsl : process(header_3_last_nibbles, header_end, payload_end, start, spi_miso_sink_valid, state, waited_long_enough, line_counter) + begin + next_state <= state; + + case state is + when Idle => + if waited_long_enough and start = '1' then + next_state <= CSn; + end if; + + when CSn => + if waited_long_enough then + next_state <= ReadHeader; + end if; + + when ReadHeader => + if header_end then + if header_3_last_nibbles(11 downto 8) = X"F" then + next_state <= DiscardPayload; + else + next_state <= ReadPayload; + end if; + end if; + + when DiscardPayload | ReadPayload => + if payload_end then + next_state <= ReadHeader; + + if line_counter = NUMBER_OF_LINES_PER_FRAME then + next_state <= WaitBeforeIdle; + end if; + end if; + + when WaitBeforeIdle => + if spi_miso_sink_valid = '1' then + next_state <= Idle; + end if; + + end case; + end process p_nsl; + + p_counter : process(clk, reset) + begin + if reset = '1' then + counter <= 1; + line_counter <= 1; + elsif rising_edge(clk) then + if counter = counter_max and counter_enabled then + counter <= 1; + + if state = ReadPayload then + if line_counter = NUMBER_OF_LINES_PER_FRAME then + line_counter <= 1; + else + line_counter <= line_counter + 1; + end if; + end if; + + elsif counter_enabled then + counter <= counter + 1; + end if; + end if; + end process p_counter; + + p_error : process(clk, reset) + begin + if reset = '1' then + error <= '0'; + timeout_counter <= 1; + elsif rising_edge(clk) then + if state /= ReadHeader and state /= ReadPayload and state /= ReadHeader then + timeout_counter <= 1; + error <= '0'; + else + if timeout_counter = CLOCK_TICKS_PER_37_MS then + error <= '1'; + else + timeout_counter <= timeout_counter + 1; + end if; + end if; + if state = ReadPayload and header_3_last_nibbles /= std_logic_vector(to_unsigned(line_counter - 1, header_3_last_nibbles'length)) then + error <= '1'; + end if; + end if; + end process p_error; + + -- purpose: wire the datapath + p_datapath : process(counter, counter_enabled, counter_max, line_counter, spi_miso_sink_data, spi_miso_sink_valid, spi_mosi_src_ready, state) + variable counter_ended : boolean; + + begin + counter_max <= 1; + counter_enabled <= true; + waited_long_enough <= false; + lepton_out_data <= (others => '0'); + lepton_out_valid <= '0'; + lepton_out_sof <= '0'; + lepton_out_eof <= '0'; + spi_mosi_src_valid <= '0'; + spi_mosi_src_data <= (others => '0'); + spi_cs_n <= '0'; + header_end <= false; + payload_end <= false; + + counter_ended := (counter = counter_max and counter_enabled); + + case state is + when Idle => + counter_max <= CLOCK_TICKS_PER_200_MS; + waited_long_enough <= counter_ended; + spi_cs_n <= '1'; + + when CSn => + counter_max <= CLOCK_TICKS_PER_200_NS; + waited_long_enough <= counter_ended; + + when ReadHeader => + counter_max <= BYTES_PER_HEADER; + counter_enabled <= spi_miso_sink_valid = '1'; + header_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when ReadPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + lepton_out_data <= spi_miso_sink_data; + lepton_out_valid <= spi_miso_sink_valid; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + if spi_miso_sink_valid = '1' then + if counter = 1 and counter_enabled and line_counter = 1 then + lepton_out_sof <= '1'; + elsif counter_ended and line_counter = NUMBER_OF_LINES_PER_FRAME then + lepton_out_eof <= '1'; + end if; + end if; + + when DiscardPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when others => null; + end case; + end process p_datapath; + + p_capture_header : process(clk, reset) + begin + if reset = '1' then + header_3_last_nibbles <= X"000"; + elsif rising_edge(clk) then + if state = ReadHeader and spi_miso_sink_valid = '1' then + if counter = 1 then + header_3_last_nibbles(11 downto 8) <= spi_miso_sink_data(3 downto 0); + elsif counter = 2 then + header_3_last_nibbles(7 downto 0) <= spi_miso_sink_data; + end if; + end if; + end if; + end process p_capture_header; + + row_idx <= std_logic_vector(to_unsigned(line_counter, row_idx'length)); + +end architecture rtl; diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton_stats.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton_stats.vhd new file mode 100644 index 0000000..4b5cc91 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lepton_stats.vhd @@ -0,0 +1,78 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_stats is + port( + clk : in std_logic; + reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + stat_min : out std_logic_vector(13 downto 0); + stat_max : out std_logic_vector(13 downto 0); + stat_sum : out std_logic_vector(26 downto 0); + stat_valid : out std_logic); +end lepton_stats; + +architecture rtl of lepton_stats is + + -- The accumulated sum, min and max of the pixel values + signal curr_min : unsigned(13 downto 0); + signal curr_max : unsigned(13 downto 0); + signal curr_sum : unsigned(26 downto 0); + + -- The next value of the registers + signal next_min : unsigned(13 downto 0); + signal next_max : unsigned(13 downto 0); + signal next_sum : unsigned(26 downto 0); + +begin + + -- This is the synchronous transition logic + transition_logic : process(clk, reset) + begin + if reset = '1' then + curr_sum <= (others => '0'); + curr_min <= (others => '0'); + curr_max <= (others => '0'); + elsif rising_edge(clk) then + curr_min <= next_min; + curr_max <= next_max; + curr_sum <= next_sum; + end if; + end process; + + -- This is the combinatorial transition logic + next_min <= + curr_min when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_min when unsigned(pix_data) >= curr_min else + unsigned(pix_data); + + next_max <= + curr_max when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_max when unsigned(pix_data) <= curr_max else + unsigned(pix_data); + + next_sum <= + curr_sum when pix_valid = '0' else + unsigned((26 downto 14 => '0') & pix_data) when pix_sof = '1' else + curr_sum + unsigned((26 downto 14 => '0') & pix_data); + + -- This is the synchronous output logic + output_logic : process(clk, reset) + begin + if rising_edge(clk) then + stat_valid <= pix_eof; + end if; + end process; + + -- This is the combinatorial output logic + stat_min <= std_logic_vector(curr_min); + stat_max <= std_logic_vector(curr_max); + stat_sum <= std_logic_vector(curr_sum); + +end rtl; diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/level_adjuster.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/level_adjuster.vhd new file mode 100644 index 0000000..6b3053d --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/level_adjuster.vhd @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity level_adjuster is + port( + clk : in std_logic; + raw_pixel : in std_logic_vector(13 downto 0); + raw_max : in std_logic_vector(13 downto 0); + raw_min : in std_logic_vector(13 downto 0); + raw_sum : in std_logic_vector(26 downto 0); + adjusted_pixel : out std_logic_vector(13 downto 0)); +end level_adjuster; + +architecture rtl of level_adjuster is + component lpm_divider + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0)); + end component; + + -- Intermediate signals needed by the divider + signal numer : std_logic_vector(27 downto 0); + signal denom : std_logic_vector(13 downto 0); + signal quot : std_logic_vector(27 downto 0); + +begin + + -- Computation of the intermediate signals + numer <= std_logic_vector((13 downto 0 => '1') * (unsigned(raw_pixel) - unsigned(raw_min))); + denom <= std_logic_vector(unsigned(raw_max) - unsigned(raw_min)); + + -- We compute the remaineder of (x - min) / (max - min) + divider : lpm_divider port map( + clock => clk, + numer => numer, + denom => denom, + quotient => quot, + remain => open + ); + + -- And we only keep the LSB of the quotient (we know the MSB must be 0) + adjusted_pixel <= + (adjusted_pixel'range => '0') when denom = (denom'range => '0') else + quot(13 downto 0); + +end rtl; diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lpm_divider.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lpm_divider.vhd new file mode 100644 index 0000000..f8de4a6 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/lpm_divider.vhd @@ -0,0 +1,133 @@ +-- megafunction wizard: %LPM_DIVIDE% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_DIVIDE + +-- ============================================================ +-- File Name: lpm_divider.vhd +-- Megafunction Name(s): +-- LPM_DIVIDE +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library lpm; +use lpm.all; + +entity lpm_divider is + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); +end lpm_divider; + +architecture SYN of lpm_divider is + signal sub_wire0 : std_logic_vector(27 downto 0); + signal sub_wire1 : std_logic_vector(13 downto 0); + + component lpm_divide + generic( + lpm_drepresentation : string; + lpm_hint : string; + lpm_nrepresentation : string; + lpm_pipeline : natural; + lpm_type : string; + lpm_widthd : natural; + lpm_widthn : natural + ); + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); + end component; + +begin + quotient <= sub_wire0(27 downto 0); + remain <= sub_wire1(13 downto 0); + + LPM_DIVIDE_component : LPM_DIVIDE + generic map( + lpm_drepresentation => "UNSIGNED", + lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE", + lpm_nrepresentation => "UNSIGNED", + lpm_pipeline => 5, + lpm_type => "LPM_DIVIDE", + lpm_widthd => 14, + lpm_widthn => 28 + ) + port map( + clock => clock, + denom => denom, + numer => numer, + quotient => sub_wire0, + remain => sub_wire1 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" +-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1" +-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" +-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" +-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "14" +-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "28" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: denom 0 0 14 0 INPUT NODEFVAL "denom[13..0]" +-- Retrieval info: USED_PORT: numer 0 0 28 0 INPUT NODEFVAL "numer[27..0]" +-- Retrieval info: USED_PORT: quotient 0 0 28 0 OUTPUT NODEFVAL "quotient[27..0]" +-- Retrieval info: USED_PORT: remain 0 0 14 0 OUTPUT NODEFVAL "remain[13..0]" +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @denom 0 0 14 0 denom 0 0 14 0 +-- Retrieval info: CONNECT: @numer 0 0 28 0 numer 0 0 28 0 +-- Retrieval info: CONNECT: quotient 0 0 28 0 @quotient 0 0 28 0 +-- Retrieval info: CONNECT: remain 0 0 14 0 @remain 0 0 14 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/ram_writer.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/ram_writer.vhd new file mode 100644 index 0000000..8912cdb --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/ram_writer.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram_writer is + port( + clk, reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + ram_data : out std_logic_vector(15 downto 0); + ram_wren : out std_logic; + ram_wraddress : out std_logic_vector(12 downto 0)); + +end ram_writer; + +architecture rtl of ram_writer is + signal wraddress_counter : unsigned(ram_wraddress'range); +begin + p_address_gen : process(clk, reset) + begin + if reset = '1' then + wraddress_counter <= (others => '0'); + elsif rising_edge(clk) then + if pix_eof = '1' then + wraddress_counter <= (others => '0'); + elsif pix_valid = '1' then + wraddress_counter <= wraddress_counter + 1; + end if; + end if; + end process p_address_gen; + + ram_data <= "00" & pix_data; + ram_wren <= pix_valid; + ram_wraddress <= std_logic_vector(wraddress_counter); + +end rtl; diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/utils.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/utils.vhd new file mode 100644 index 0000000..83105ad --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/hdl/utils.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package utils is + function bitlength(number : positive) return positive; + +end package utils; + +package body utils is + + -- purpose: returns the minimum # of bits needed to represent the input number + function bitlength(number : positive) return positive is + variable acc : positive := 1; + variable i : natural := 0; + begin + while True loop + if acc > number then + return i; + end if; + + acc := acc * 2; + i := i + 1; + end loop; + end function bitlength; + +end package body utils; diff --git a/cs309-psoc/lab_3_1/hw/hdl/lepton/tb/lepton_tb.vhd b/cs309-psoc/lab_3_1/hw/hdl/lepton/tb/lepton_tb.vhd new file mode 100644 index 0000000..f134613 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/lepton/tb/lepton_tb.vhd @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity lepton_tb is +end lepton_tb; + +architecture tb of lepton_tb is + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal address : std_logic_vector(13 downto 0) := (others => '0'); + signal readdata : std_logic_vector(15 downto 0) := (others => '0'); + signal writedata : std_logic_vector(15 downto 0) := (others => '0'); + signal read : std_logic := '0'; + signal write : std_logic := '0'; + signal SCLK : std_logic := '0'; + signal CSn : std_logic := '0'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '1'; + + constant CLK_PERIOD : time := 20 ns; + + signal sim_ended : boolean := false; + +begin + dut : entity work.lepton + port map( + clk => clk, + reset => reset, + address => address, + readdata => readdata, + writedata => writedata, + read => read, + write => write, + SCLK => SCLK, + CSn => CSn, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_ended else '0'; + + miso_gen : process + variable seed1, seed2 : positive; + variable rand : real; + begin + if sim_ended then + wait; + else + uniform(seed1, seed2, rand); + wait until rising_edge(SCLK); + MISO <= to_unsigned(integer(rand), 1)(0); + + end if; + end process; + + stimuli : process + begin + reset <= '1'; + write <= '0'; + + wait for 2 * CLK_PERIOD; + reset <= '0'; + + wait for CLK_PERIOD; + write <= '1'; + writedata(0) <= '1'; + wait for CLK_PERIOD; + write <= '0'; + + wait for 17 ms; + sim_ended <= true; + wait; + end process; + +end tb; diff --git a/cs309-psoc/lab_3_1/hw/hdl/pantilt/hdl/pwm.vhd b/cs309-psoc/lab_3_1/hw/hdl/pantilt/hdl/pwm.vhd new file mode 100644 index 0000000..1b5cdc3 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/pantilt/hdl/pwm.vhd @@ -0,0 +1,42 @@ +-- ############################################################################# +-- pwm.vhd +-- ======= +-- PWM memory-mapped Avalon slave interface. +-- +-- Author : () +-- Author : () +-- Revision : +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity pwm is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + write : in std_logic; + readdata : out std_logic_vector(31 downto 0); + writedata : in std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + pwm_out : out std_logic + ); +end pwm; + +architecture rtl of pwm is + +begin + +end architecture rtl; diff --git a/cs309-psoc/lab_3_1/hw/hdl/pantilt/hdl/pwm_constants.vhd b/cs309-psoc/lab_3_1/hw/hdl/pantilt/hdl/pwm_constants.vhd new file mode 100644 index 0000000..bfff03b --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/pantilt/hdl/pwm_constants.vhd @@ -0,0 +1,61 @@ +-- ############################################################################# +-- pwm_constants.vhd +-- ================= +-- This package contains constants used in the PWM design files. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pwm_constants is + -- Register map + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | RegNo | Name | Access | Description | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW period to apply to the | + -- | | | | next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT period of the | + -- | | | | ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to | + -- | | | | the next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT duty cycle of | + -- | | | | the ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.| + -- | | | | Writing 1 to this register starts the PWM. | + -- | | | | | + -- | | | | >> Reading this register always returns 0. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00"; + constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01"; + constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10"; + + -- Default values of registers after reset (BEFORE writing START to the CTRL + -- register with a new configuration) + constant DEFAULT_PERIOD : natural := 4; + constant DEFAULT_DUTY_CYCLE : natural := 2; +end package pwm_constants; + +package body pwm_constants is + +end package body pwm_constants; diff --git a/cs309-psoc/lab_3_1/hw/hdl/pantilt/hdl/pwm_hw.tcl b/cs309-psoc/lab_3_1/hw/hdl/pantilt/hdl/pwm_hw.tcl new file mode 100644 index 0000000..df7d92a --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/pantilt/hdl/pwm_hw.tcl @@ -0,0 +1,135 @@ +# TCL File Generated by Component Editor 16.0 +# Tue Feb 28 12:18:00 CET 2017 +# DO NOT MODIFY + + +# +# pwm "pwm" v1.0 +# 2017.02.28.12:18:00 +# Pan-tilt +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module pwm +# +set_module_property DESCRIPTION Pan-tilt +set_module_property NAME pwm +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Pan-tilt +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME pwm +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE +add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +add_interface_port avalon_slave_0 writedata writedata Input 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end pwm_out pwm Output 1 diff --git a/cs309-psoc/lab_3_1/hw/hdl/pantilt/tb/tb_pwm.vhd b/cs309-psoc/lab_3_1/hw/hdl/pantilt/tb/tb_pwm.vhd new file mode 100644 index 0000000..ff2dee7 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/hdl/pantilt/tb/tb_pwm.vhd @@ -0,0 +1,205 @@ +-- ############################################################################# +-- tb_pwm.vhd +-- ========== +-- Testbench for PWM memory-mapped Avalon slave interface. +-- +-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity tb_pwm is +end entity; + +architecture rtl of tb_pwm is + + -- 50 MHz clock + constant CLK_PERIOD : time := 20 ns; + + -- Signal used to end simulator when we finished submitting our test cases + signal sim_finished : boolean := false; + + -- PWM PORTS + signal clk : std_logic; + signal reset : std_logic; + signal address : std_logic_vector(1 downto 0); + signal read : std_logic; + signal write : std_logic; + signal readdata : std_logic_vector(31 downto 0); + signal writedata : std_logic_vector(31 downto 0); + signal pwm_out : std_logic; + + -- Values of registers we are going to use to configure the PWM unit + constant CONFIG_PERIOD : natural := 100; + constant CONFIG_DUTY_CYCLE : natural := 20; + constant CONFIG_CTRL_START : natural := 1; + constant CONFIG_CTRL_STOP : natural := 0; + +begin + + -- Instantiate DUT + dut : entity work.pwm + port map( + clk => clk, + reset => reset, + address => address, + read => read, + write => write, + readdata => readdata, + writedata => writedata, + pwm_out => pwm_out + ); + + -- Generate clk signal + clk_generation : process + begin + if not sim_finished then + clk <= '1'; + wait for CLK_PERIOD / 2; + clk <= '0'; + wait for CLK_PERIOD / 2; + else + wait; + end if; + end process clk_generation; + + -- Test PWM + simulation : process + + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + + reset <= '1'; + wait for CLK_PERIOD / 2; + + reset <= '0'; + wait for CLK_PERIOD / 4; + end procedure async_reset; + + procedure write_register(constant ofst : in std_logic_vector(1 downto 0); + constant val : in natural) is + begin + wait until rising_edge(clk); + + address <= ofst; + write <= '1'; + writedata <= std_logic_vector(to_unsigned(val, writedata'length)); + wait until rising_edge(clk); + + address <= (others => '0'); + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + end procedure write_register; + + procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is + begin + wait until rising_edge(clk); + + address <= ofst; + read <= '1'; + -- The read has a 1 cycle wait-state, so we need to keep the read + -- signal high for 2 clock cycles. + wait until rising_edge(clk); + wait until rising_edge(clk); + + address <= (others => '0'); + read <= '0'; + wait until rising_edge(clk); + end procedure read_register; + + procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0); + constant expected_val : in natural) is + begin + read_register(ofst); + + case ofst is + when REG_PERIOD_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected PERIOD: " & + "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "PERIOD_expected = " & integer'image(expected_val) + severity error; + + when REG_DUTY_CYCLE_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected DUTY_CYCLE: " & + "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "DUTY_CYCLE_expected = " & integer'image(expected_val) + severity error; + + when REG_CTRL_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected CTRL: " & + "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "CTRL_expected = " & integer'image(expected_val) + severity error; + + when others => + null; + end case; + end procedure read_register_check; + + begin + + -- Default values + reset <= '0'; + address <= (others => '0'); + read <= '0'; + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + + -- Reset the circuit + async_reset; + + -- Write desired configuration to PWM Avalon-MM slave. + write_register(REG_PERIOD_OFST, CONFIG_PERIOD); + write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + + -- Read back configuration from PWM Avalon-MM slave. Note that we have + -- not started the PWM unit yet, so the new configuration must not be + -- read back at this point (as per the register map). + read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Start PWM + write_register(REG_CTRL_OFST, CONFIG_CTRL_START); + + -- Wait until PWM pulses for the first time after we sent START. + wait until rising_edge(pwm_out); + + -- Read back configuration from PWM Avalon-MM slave. Now that we have + -- started the PWM unit, we should be able to read back the + -- configuration we wrote (as per the register map). + read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Wait for 2 PWM periods to finish + wait for 2 * CLK_PERIOD * CONFIG_PERIOD; + + -- Stop PWM. + write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP); + + -- Wait for PWM period to finish + wait for 1 * CLK_PERIOD * CONFIG_PERIOD; + + -- Instruct "clk_generation" process to halt execution. + sim_finished <= true; + + -- Make this process wait indefinitely (it will never re-execute from + -- its beginning again). + wait; + end process simulation; +end architecture rtl; + diff --git a/cs309-psoc/lab_3_1/hw/quartus/ip/components.ipx b/cs309-psoc/lab_3_1/hw/quartus/ip/components.ipx new file mode 100644 index 0000000..7536257 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/quartus/ip/components.ipx @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_3_1/hw/quartus/lab_3_1.qpf b/cs309-psoc/lab_3_1/hw/quartus/lab_3_1.qpf new file mode 100644 index 0000000..5212307 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/quartus/lab_3_1.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition +# Date created = 11:03:02 February 05, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.1" +DATE = "11:03:02 February 05, 2016" + +# Revisions + +PROJECT_REVISION = "lab_3_1" diff --git a/cs309-psoc/lab_3_1/hw/quartus/lab_3_1.qsf b/cs309-psoc/lab_3_1/hw/quartus/lab_3_1.qsf new file mode 100644 index 0000000..1f84b4e --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/quartus/lab_3_1.qsf @@ -0,0 +1,1379 @@ +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" + +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA4U23C6 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO Extention OV7670 CAMERA +#============================================================ +set_location_assignment PIN_AE15 -to CAM_D[0] +set_location_assignment PIN_AE15 -to CAM_D_0 +set_location_assignment PIN_AF17 -to CAM_D[1] +set_location_assignment PIN_AF17 -to CAM_D_1 +set_location_assignment PIN_AH8 -to CAM_D[2] +set_location_assignment PIN_AH8 -to CAM_D_2 +set_location_assignment PIN_AG8 -to CAM_D[3] +set_location_assignment PIN_AG8 -to CAM_D_3 +set_location_assignment PIN_U13 -to CAM_D[4] +set_location_assignment PIN_U13 -to CAM_D_4 +set_location_assignment PIN_U14 -to CAM_D[5] +set_location_assignment PIN_U14 -to CAM_D_5 +set_location_assignment PIN_AG9 -to CAM_D[6] +set_location_assignment PIN_AG9 -to CAM_D_6 +set_location_assignment PIN_AG10 -to CAM_D[7] +set_location_assignment PIN_AG10 -to CAM_D_7 +set_location_assignment PIN_AF13 -to CAM_D[8] +set_location_assignment PIN_AF13 -to CAM_D_8 +set_location_assignment PIN_AG13 -to CAM_D[9] +set_location_assignment PIN_AG13 -to CAM_D_9 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9 + +#============================================================ +# Arduino Extension LEPTON CAMERA THERMAL CAM_TH +#============================================================ +set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N +set_location_assignment PIN_AG16 -to CAM_TH_MOSI +set_location_assignment PIN_AH11 -to CAM_TH_MISO +set_location_assignment PIN_AH12 -to CAM_TH_CLK +set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA +set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL + +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#============================================================ +# HPS +#============================================================ +set_location_assignment PIN_C6 -to HPS_CONV_USB_N +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0] +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0 +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1] +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1 +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2] +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2 +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3] +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3 +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4] +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4 +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5] +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5 +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6] +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6 +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7] +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7 +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8] +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8 +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9] +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9 +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10] +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10 +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11] +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11 +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12] +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12 +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13] +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13 +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14] +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14 +set_location_assignment PIN_A27 -to HPS_DDR3_BA[0] +set_location_assignment PIN_A27 -to HPS_DDR3_BA_0 +set_location_assignment PIN_H25 -to HPS_DDR3_BA[1] +set_location_assignment PIN_H25 -to HPS_DDR3_BA_1 +set_location_assignment PIN_G25 -to HPS_DDR3_BA[2] +set_location_assignment PIN_G25 -to HPS_DDR3_BA_2 +set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N +set_location_assignment PIN_L28 -to HPS_DDR3_CKE +set_location_assignment PIN_N20 -to HPS_DDR3_CK_N +set_location_assignment PIN_N21 -to HPS_DDR3_CK_P +set_location_assignment PIN_L21 -to HPS_DDR3_CS_N +set_location_assignment PIN_G28 -to HPS_DDR3_DM[0] +set_location_assignment PIN_G28 -to HPS_DDR3_DM_0 +set_location_assignment PIN_P28 -to HPS_DDR3_DM[1] +set_location_assignment PIN_P28 -to HPS_DDR3_DM_1 +set_location_assignment PIN_W28 -to HPS_DDR3_DM[2] +set_location_assignment PIN_W28 -to HPS_DDR3_DM_2 +set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3] +set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3 +set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0] +set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0 +set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1] +set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1 +set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2] +set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2 +set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3] +set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3 +set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4] +set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4 +set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5] +set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5 +set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6] +set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6 +set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7] +set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7 +set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8] +set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8 +set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9] +set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9 +set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10] +set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10 +set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11] +set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11 +set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12] +set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12 +set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13] +set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13 +set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14] +set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14 +set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15] +set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15 +set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16] +set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16 +set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17] +set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17 +set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18] +set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18 +set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19] +set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19 +set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20] +set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20 +set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21] +set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21 +set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22] +set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22 +set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23] +set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23 +set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24] +set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24 +set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25] +set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25 +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26] +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26 +set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27] +set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27 +set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28] +set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28 +set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29] +set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29 +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30] +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30 +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31] +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31 +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0] +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0 +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1] +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1 +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2] +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2 +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3] +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3 +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0] +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0 +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1] +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1 +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2] +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2 +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3] +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3 +set_location_assignment PIN_D28 -to HPS_DDR3_ODT +set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N +set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N +set_location_assignment PIN_D25 -to HPS_DDR3_RZQ +set_location_assignment PIN_E25 -to HPS_DDR3_WE_N +set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK +set_location_assignment PIN_B14 -to HPS_ENET_INT_N +set_location_assignment PIN_A13 -to HPS_ENET_MDC +set_location_assignment PIN_E16 -to HPS_ENET_MDIO +set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0] +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0 +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1] +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1 +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2] +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2 +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3] +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3 +set_location_assignment PIN_J13 -to HPS_ENET_RX_DV +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0] +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0 +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1] +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1 +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2] +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2 +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3] +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3 +set_location_assignment PIN_A12 -to HPS_ENET_TX_EN +set_location_assignment PIN_A17 -to HPS_GSENSOR_INT +set_location_assignment PIN_C18 -to HPS_I2C0_SCLK +set_location_assignment PIN_A19 -to HPS_I2C0_SDAT +set_location_assignment PIN_K18 -to HPS_I2C1_SCLK +set_location_assignment PIN_A21 -to HPS_I2C1_SDAT +set_location_assignment PIN_J18 -to HPS_KEY_N +set_location_assignment PIN_A20 -to HPS_LED +set_location_assignment PIN_H13 -to HPS_LTC_GPIO +set_location_assignment PIN_B8 -to HPS_SD_CLK +set_location_assignment PIN_D14 -to HPS_SD_CMD +set_location_assignment PIN_C13 -to HPS_SD_DATA[0] +set_location_assignment PIN_C13 -to HPS_SD_DATA_0 +set_location_assignment PIN_B6 -to HPS_SD_DATA[1] +set_location_assignment PIN_B6 -to HPS_SD_DATA_1 +set_location_assignment PIN_B11 -to HPS_SD_DATA[2] +set_location_assignment PIN_B11 -to HPS_SD_DATA_2 +set_location_assignment PIN_B9 -to HPS_SD_DATA[3] +set_location_assignment PIN_B9 -to HPS_SD_DATA_3 +set_location_assignment PIN_C19 -to HPS_SPIM_CLK +set_location_assignment PIN_B19 -to HPS_SPIM_MISO +set_location_assignment PIN_B16 -to HPS_SPIM_MOSI +set_location_assignment PIN_C16 -to HPS_SPIM_SS +set_location_assignment PIN_A22 -to HPS_UART_RX +set_location_assignment PIN_B21 -to HPS_UART_TX +set_location_assignment PIN_G4 -to HPS_USB_CLKOUT +set_location_assignment PIN_C10 -to HPS_USB_DATA[0] +set_location_assignment PIN_C10 -to HPS_USB_DATA_0 +set_location_assignment PIN_F5 -to HPS_USB_DATA[1] +set_location_assignment PIN_F5 -to HPS_USB_DATA_1 +set_location_assignment PIN_C9 -to HPS_USB_DATA[2] +set_location_assignment PIN_C9 -to HPS_USB_DATA_2 +set_location_assignment PIN_C4 -to HPS_USB_DATA[3] +set_location_assignment PIN_C4 -to HPS_USB_DATA_3 +set_location_assignment PIN_C8 -to HPS_USB_DATA[4] +set_location_assignment PIN_C8 -to HPS_USB_DATA_4 +set_location_assignment PIN_D4 -to HPS_USB_DATA[5] +set_location_assignment PIN_D4 -to HPS_USB_DATA_5 +set_location_assignment PIN_C7 -to HPS_USB_DATA[6] +set_location_assignment PIN_C7 -to HPS_USB_DATA_6 +set_location_assignment PIN_F4 -to HPS_USB_DATA[7] +set_location_assignment PIN_F4 -to HPS_USB_DATA_7 +set_location_assignment PIN_E5 -to HPS_USB_DIR +set_location_assignment PIN_D5 -to HPS_USB_NXT +set_location_assignment PIN_C5 -to HPS_USB_STP + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY_N +#============================================================ +set_location_assignment PIN_AH17 -to KEY_N[0] +set_location_assignment PIN_AH17 -to KEY_N_0 +set_location_assignment PIN_AH16 -to KEY_N[1] +set_location_assignment PIN_AH16 -to KEY_N_1 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_W15 -to LED_0 +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_AA24 -to LED_1 +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V16 -to LED_2 +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_V15 -to LED_3 +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AF26 -to LED_4 +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_AE26 -to LED_5 +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_Y16 -to LED_6 +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_AA23 -to LED_7 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7 + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_L10 -to SW[0] +set_location_assignment PIN_L10 -to SW_0 +set_location_assignment PIN_L9 -to SW[1] +set_location_assignment PIN_L9 -to SW_1 +set_location_assignment PIN_H6 -to SW[2] +set_location_assignment PIN_H6 -to SW_2 +set_location_assignment PIN_H5 -to SW[3] +set_location_assignment PIN_H5 -to SW_3 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3 + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_V12 -to PIO_INT_N +set_location_assignment PIN_AE11 -to PIO_SCL +set_location_assignment PIN_AE12 -to PIO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA + +set_location_assignment PIN_AF7 -to PIR_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT + +set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA +set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL +set_location_assignment PIN_T11 -to CAM_SYS_CLK +set_location_assignment PIN_AG6 -to CAM_LV +set_location_assignment PIN_AH2 -to CAM_PIX_CLK +set_location_assignment PIN_AE4 -to CAM_FV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV + +set_location_assignment PIN_Y8 -to PAL_VD_HSO +set_location_assignment PIN_AB4 -to PAL_VD_VSO +set_location_assignment PIN_AG5 -to PAL_VD_VD[0] +set_location_assignment PIN_AG5 -to PAL_VD_VD_0 +set_location_assignment PIN_AH5 -to PAL_VD_VD[1] +set_location_assignment PIN_AH5 -to PAL_VD_VD_1 +set_location_assignment PIN_AH6 -to PAL_VD_VD[2] +set_location_assignment PIN_AH6 -to PAL_VD_VD_2 +set_location_assignment PIN_T8 -to PAL_VD_VD[3] +set_location_assignment PIN_T8 -to PAL_VD_VD_3 +set_location_assignment PIN_T12 -to PAL_VD_VD[4] +set_location_assignment PIN_T12 -to PAL_VD_VD_4 +set_location_assignment PIN_Y5 -to PAL_VD_VD[5] +set_location_assignment PIN_Y5 -to PAL_VD_VD_5 +set_location_assignment PIN_Y4 -to PAL_VD_VD[6] +set_location_assignment PIN_Y4 -to PAL_VD_VD_6 +set_location_assignment PIN_W8 -to PAL_VD_VD[7] +set_location_assignment PIN_W8 -to PAL_VD_VD_7 +set_location_assignment PIN_AH4 -to PAL_VD_CLKO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO + +set_location_assignment PIN_AH3 -to SERVO_0 +set_location_assignment PIN_AF4 -to SERVO_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1 + +set_location_assignment PIN_AD12 -to J0_SPI_CLK +set_location_assignment PIN_AD11 -to J0_SPI_MISO +set_location_assignment PIN_AF9 -to J0_SPI_CS_N +set_location_assignment PIN_AD10 -to J0_SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI + +set_location_assignment PIN_AF5 -to FROM_ESP_TXD +set_location_assignment PIN_T13 -to TO_ESP_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD + +set_location_assignment PIN_AE7 -to SPI_MISO +set_location_assignment PIN_AF6 -to SPI_ENA_N +set_location_assignment PIN_AE8 -to SPI_CLK +set_location_assignment PIN_AE9 -to SPI_MOSI +set_location_assignment PIN_AF10 -to SPI_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT + +set_location_assignment PIN_AF11 -to LED_BGR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_AA15 -to RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N + +set_location_assignment PIN_AG28 -to TS_SCL +set_location_assignment PIN_AH27 -to TS_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA + +set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N +set_location_assignment PIN_AG26 -to LCD_DE +set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN + +set_location_assignment PIN_AH24 -to BLT_TXD +set_location_assignment PIN_AE22 -to BLT_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD + +set_location_assignment PIN_AG20 -to BOARD_ID +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID + +set_location_assignment PIN_AF21 -to VIDEO_HSYNC +set_location_assignment PIN_AG19 -to VIDEO_VSYNC +set_location_assignment PIN_AF20 -to VIDEO_CLK +set_location_assignment PIN_AG23 -to VIDEO_B[0] +set_location_assignment PIN_AG23 -to VIDEO_B_0 +set_location_assignment PIN_AH23 -to VIDEO_B[1] +set_location_assignment PIN_AH23 -to VIDEO_B_1 +set_location_assignment PIN_AF25 -to VIDEO_B[2] +set_location_assignment PIN_AF25 -to VIDEO_B_2 +set_location_assignment PIN_AG24 -to VIDEO_B[3] +set_location_assignment PIN_AG24 -to VIDEO_B_3 +set_location_assignment PIN_AA19 -to VIDEO_B[4] +set_location_assignment PIN_AA19 -to VIDEO_B_4 +set_location_assignment PIN_AH26 -to VIDEO_B[5] +set_location_assignment PIN_AH26 -to VIDEO_B_5 +set_location_assignment PIN_AG18 -to VIDEO_B[6] +set_location_assignment PIN_AG18 -to VIDEO_B_6 +set_location_assignment PIN_AC23 -to VIDEO_B[7] +set_location_assignment PIN_AC23 -to VIDEO_B_7 +set_location_assignment PIN_AH22 -to VIDEO_G[0] +set_location_assignment PIN_AH22 -to VIDEO_G_0 +set_location_assignment PIN_AF22 -to VIDEO_G[1] +set_location_assignment PIN_AF22 -to VIDEO_G_1 +set_location_assignment PIN_AD20 -to VIDEO_G[2] +set_location_assignment PIN_AD20 -to VIDEO_G_2 +set_location_assignment PIN_AE24 -to VIDEO_G[3] +set_location_assignment PIN_AE24 -to VIDEO_G_3 +set_location_assignment PIN_AE20 -to VIDEO_G[4] +set_location_assignment PIN_AE20 -to VIDEO_G_4 +set_location_assignment PIN_AD19 -to VIDEO_G[5] +set_location_assignment PIN_AD19 -to VIDEO_G_5 +set_location_assignment PIN_AF18 -to VIDEO_G[6] +set_location_assignment PIN_AF18 -to VIDEO_G_6 +set_location_assignment PIN_AE19 -to VIDEO_G[7] +set_location_assignment PIN_AE19 -to VIDEO_G_7 +set_location_assignment PIN_AC22 -to VIDEO_R[0] +set_location_assignment PIN_AC22 -to VIDEO_R_0 +set_location_assignment PIN_AA18 -to VIDEO_R[1] +set_location_assignment PIN_AA18 -to VIDEO_R_1 +set_location_assignment PIN_AE23 -to VIDEO_R[2] +set_location_assignment PIN_AE23 -to VIDEO_R_2 +set_location_assignment PIN_AD23 -to VIDEO_R[3] +set_location_assignment PIN_AD23 -to VIDEO_R_3 +set_location_assignment PIN_AH18 -to VIDEO_R[4] +set_location_assignment PIN_AH18 -to VIDEO_R_4 +set_location_assignment PIN_AG21 -to VIDEO_R[5] +set_location_assignment PIN_AG21 -to VIDEO_R_5 +set_location_assignment PIN_AH21 -to VIDEO_R[6] +set_location_assignment PIN_AH21 -to VIDEO_R_6 +set_location_assignment PIN_AH19 -to VIDEO_R[7] +set_location_assignment PIN_AH19 -to VIDEO_R_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7 + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_AG13 -to ARDUINO_IO[0] +set_location_assignment PIN_AG13 -to ARDUINO_IO_0 +set_location_assignment PIN_AF13 -to ARDUINO_IO[1] +set_location_assignment PIN_AF13 -to ARDUINO_IO_1 +set_location_assignment PIN_AG10 -to ARDUINO_IO[2] +set_location_assignment PIN_AG10 -to ARDUINO_IO_2 +set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +set_location_assignment PIN_AG9 -to ARDUINO_IO_3 +set_location_assignment PIN_U14 -to ARDUINO_IO[4] +set_location_assignment PIN_U14 -to ARDUINO_IO_4 +set_location_assignment PIN_U13 -to ARDUINO_IO[5] +set_location_assignment PIN_U13 -to ARDUINO_IO_5 +set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +set_location_assignment PIN_AG8 -to ARDUINO_IO_6 +set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +set_location_assignment PIN_AH8 -to ARDUINO_IO_7 +set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +set_location_assignment PIN_AF17 -to ARDUINO_IO_8 +set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +set_location_assignment PIN_AE15 -to ARDUINO_IO_9 +set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +set_location_assignment PIN_AF15 -to ARDUINO_IO_10 +set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +set_location_assignment PIN_AG16 -to ARDUINO_IO_11 +set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +set_location_assignment PIN_AH11 -to ARDUINO_IO_12 +set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +set_location_assignment PIN_AH12 -to ARDUINO_IO_13 +set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +set_location_assignment PIN_AH9 -to ARDUINO_IO_14 +set_location_assignment PIN_AG11 -to ARDUINO_IO[15] +set_location_assignment PIN_AG11 -to ARDUINO_IO_15 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_9 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_11 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_12 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_13 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_14 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_15 +set_location_assignment PIN_V12 -to GPIO_0[0] +set_location_assignment PIN_V12 -to GPIO_0_0 +set_location_assignment PIN_AF7 -to GPIO_0[1] +set_location_assignment PIN_AF7 -to GPIO_0_1 +set_location_assignment PIN_W12 -to GPIO_0[2] +set_location_assignment PIN_W12 -to GPIO_0_2 +set_location_assignment PIN_AF8 -to GPIO_0[3] +set_location_assignment PIN_AF8 -to GPIO_0_3 +set_location_assignment PIN_Y8 -to GPIO_0[4] +set_location_assignment PIN_Y8 -to GPIO_0_4 +set_location_assignment PIN_AB4 -to GPIO_0[5] +set_location_assignment PIN_AB4 -to GPIO_0_5 +set_location_assignment PIN_W8 -to GPIO_0[6] +set_location_assignment PIN_W8 -to GPIO_0_6 +set_location_assignment PIN_Y4 -to GPIO_0[7] +set_location_assignment PIN_Y4 -to GPIO_0_7 +set_location_assignment PIN_Y5 -to GPIO_0[8] +set_location_assignment PIN_Y5 -to GPIO_0_8 +set_location_assignment PIN_U11 -to GPIO_0[9] +set_location_assignment PIN_U11 -to GPIO_0_9 +set_location_assignment PIN_T8 -to GPIO_0[10] +set_location_assignment PIN_T8 -to GPIO_0_10 +set_location_assignment PIN_T12 -to GPIO_0[11] +set_location_assignment PIN_T12 -to GPIO_0_11 +set_location_assignment PIN_AH5 -to GPIO_0[12] +set_location_assignment PIN_AH5 -to GPIO_0_12 +set_location_assignment PIN_AH6 -to GPIO_0[13] +set_location_assignment PIN_AH6 -to GPIO_0_13 +set_location_assignment PIN_AH4 -to GPIO_0[14] +set_location_assignment PIN_AH4 -to GPIO_0_14 +set_location_assignment PIN_AG5 -to GPIO_0[15] +set_location_assignment PIN_AG5 -to GPIO_0_15 +set_location_assignment PIN_AH3 -to GPIO_0[16] +set_location_assignment PIN_AH3 -to GPIO_0_16 +set_location_assignment PIN_AH2 -to GPIO_0[17] +set_location_assignment PIN_AH2 -to GPIO_0_17 +set_location_assignment PIN_AF4 -to GPIO_0[18] +set_location_assignment PIN_AF4 -to GPIO_0_18 +set_location_assignment PIN_AG6 -to GPIO_0[19] +set_location_assignment PIN_AG6 -to GPIO_0_19 +set_location_assignment PIN_AF5 -to GPIO_0[20] +set_location_assignment PIN_AF5 -to GPIO_0_20 +set_location_assignment PIN_AE4 -to GPIO_0[21] +set_location_assignment PIN_AE4 -to GPIO_0_21 +set_location_assignment PIN_T13 -to GPIO_0[22] +set_location_assignment PIN_T13 -to GPIO_0_22 +set_location_assignment PIN_T11 -to GPIO_0[23] +set_location_assignment PIN_T11 -to GPIO_0_23 +set_location_assignment PIN_AE7 -to GPIO_0[24] +set_location_assignment PIN_AE7 -to GPIO_0_24 +set_location_assignment PIN_AF6 -to GPIO_0[25] +set_location_assignment PIN_AF6 -to GPIO_0_25 +set_location_assignment PIN_AF9 -to GPIO_0[26] +set_location_assignment PIN_AF9 -to GPIO_0_26 +set_location_assignment PIN_AE8 -to GPIO_0[27] +set_location_assignment PIN_AE8 -to GPIO_0_27 +set_location_assignment PIN_AD10 -to GPIO_0[28] +set_location_assignment PIN_AD10 -to GPIO_0_28 +set_location_assignment PIN_AE9 -to GPIO_0[29] +set_location_assignment PIN_AE9 -to GPIO_0_29 +set_location_assignment PIN_AD11 -to GPIO_0[30] +set_location_assignment PIN_AD11 -to GPIO_0_30 +set_location_assignment PIN_AF10 -to GPIO_0[31] +set_location_assignment PIN_AF10 -to GPIO_0_31 +set_location_assignment PIN_AD12 -to GPIO_0[32] +set_location_assignment PIN_AD12 -to GPIO_0_32 +set_location_assignment PIN_AE11 -to GPIO_0[33] +set_location_assignment PIN_AE11 -to GPIO_0_33 +set_location_assignment PIN_AF11 -to GPIO_0[34] +set_location_assignment PIN_AF11 -to GPIO_0_34 +set_location_assignment PIN_AE12 -to GPIO_0[35] +set_location_assignment PIN_AE12 -to GPIO_0_35 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_9 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_11 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_12 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_13 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_14 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_15 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_16 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_17 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_18 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_19 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_20 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_21 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_22 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_23 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_24 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_26 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_28 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_29 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_30 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_31 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_32 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_33 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_34 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_35 +set_location_assignment PIN_Y15 -to GPIO_1[0] +set_location_assignment PIN_Y15 -to GPIO_1_0 +set_location_assignment PIN_AG28 -to GPIO_1[1] +set_location_assignment PIN_AG28 -to GPIO_1_1 +set_location_assignment PIN_AA15 -to GPIO_1[2] +set_location_assignment PIN_AA15 -to GPIO_1_2 +set_location_assignment PIN_AH27 -to GPIO_1[3] +set_location_assignment PIN_AH27 -to GPIO_1_3 +set_location_assignment PIN_AG26 -to GPIO_1[4] +set_location_assignment PIN_AG26 -to GPIO_1_4 +set_location_assignment PIN_AH24 -to GPIO_1[5] +set_location_assignment PIN_AH24 -to GPIO_1_5 +set_location_assignment PIN_AF23 -to GPIO_1[6] +set_location_assignment PIN_AF23 -to GPIO_1_6 +set_location_assignment PIN_AE22 -to GPIO_1[7] +set_location_assignment PIN_AE22 -to GPIO_1_7 +set_location_assignment PIN_AF21 -to GPIO_1[8] +set_location_assignment PIN_AF21 -to GPIO_1_8 +set_location_assignment PIN_AG20 -to GPIO_1[9] +set_location_assignment PIN_AG20 -to GPIO_1_9 +set_location_assignment PIN_AG19 -to GPIO_1[10] +set_location_assignment PIN_AG19 -to GPIO_1_10 +set_location_assignment PIN_AF20 -to GPIO_1[11] +set_location_assignment PIN_AF20 -to GPIO_1_11 +set_location_assignment PIN_AC23 -to GPIO_1[12] +set_location_assignment PIN_AC23 -to GPIO_1_12 +set_location_assignment PIN_AG18 -to GPIO_1[13] +set_location_assignment PIN_AG18 -to GPIO_1_13 +set_location_assignment PIN_AH26 -to GPIO_1[14] +set_location_assignment PIN_AH26 -to GPIO_1_14 +set_location_assignment PIN_AA19 -to GPIO_1[15] +set_location_assignment PIN_AA19 -to GPIO_1_15 +set_location_assignment PIN_AG24 -to GPIO_1[16] +set_location_assignment PIN_AG24 -to GPIO_1_16 +set_location_assignment PIN_AF25 -to GPIO_1[17] +set_location_assignment PIN_AF25 -to GPIO_1_17 +set_location_assignment PIN_AH23 -to GPIO_1[18] +set_location_assignment PIN_AH23 -to GPIO_1_18 +set_location_assignment PIN_AG23 -to GPIO_1[19] +set_location_assignment PIN_AG23 -to GPIO_1_19 +set_location_assignment PIN_AE19 -to GPIO_1[20] +set_location_assignment PIN_AE19 -to GPIO_1_20 +set_location_assignment PIN_AF18 -to GPIO_1[21] +set_location_assignment PIN_AF18 -to GPIO_1_21 +set_location_assignment PIN_AD19 -to GPIO_1[22] +set_location_assignment PIN_AD19 -to GPIO_1_22 +set_location_assignment PIN_AE20 -to GPIO_1[23] +set_location_assignment PIN_AE20 -to GPIO_1_23 +set_location_assignment PIN_AE24 -to GPIO_1[24] +set_location_assignment PIN_AE24 -to GPIO_1_24 +set_location_assignment PIN_AD20 -to GPIO_1[25] +set_location_assignment PIN_AD20 -to GPIO_1_25 +set_location_assignment PIN_AF22 -to GPIO_1[26] +set_location_assignment PIN_AF22 -to GPIO_1_26 +set_location_assignment PIN_AH22 -to GPIO_1[27] +set_location_assignment PIN_AH22 -to GPIO_1_27 +set_location_assignment PIN_AH19 -to GPIO_1[28] +set_location_assignment PIN_AH19 -to GPIO_1_28 +set_location_assignment PIN_AH21 -to GPIO_1[29] +set_location_assignment PIN_AH21 -to GPIO_1_29 +set_location_assignment PIN_AG21 -to GPIO_1[30] +set_location_assignment PIN_AG21 -to GPIO_1_30 +set_location_assignment PIN_AH18 -to GPIO_1[31] +set_location_assignment PIN_AH18 -to GPIO_1_31 +set_location_assignment PIN_AD23 -to GPIO_1[32] +set_location_assignment PIN_AD23 -to GPIO_1_32 +set_location_assignment PIN_AE23 -to GPIO_1[33] +set_location_assignment PIN_AE23 -to GPIO_1_33 +set_location_assignment PIN_AA18 -to GPIO_1[34] +set_location_assignment PIN_AA18 -to GPIO_1_34 +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AC22 -to GPIO_1_35 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_9 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_11 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_12 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_13 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_14 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_15 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_16 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_17 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_18 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_19 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_20 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_21 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_22 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_23 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_24 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_26 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_28 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_29 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_30 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_31 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_32 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_33 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_34 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_35 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name QSYS_FILE soc_system.qsys +set_global_assignment -name SOURCE_FILE soc_system/soc_system.cmp +set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +set_global_assignment -name SDC_FILE lab_3_1.sdc +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_P -tag __hps_sdram_p0 +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_P -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_N -tag __hps_sdram_p0 +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[0] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[10] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[11] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[12] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[13] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[14] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[1] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[2] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[3] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[4] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[5] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[6] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[7] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[8] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[9] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[0] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[1] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[2] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CAS_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CKE -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CS_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ODT -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RAS_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_WE_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RESET_N -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[10] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[11] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[12] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[13] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[14] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[4] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[5] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[6] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[7] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[8] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[9] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CAS_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CKE -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CS_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ODT -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RAS_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_WE_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RESET_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_P -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_N -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -tag __hps_sdram_p0 +set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to u0|hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0 +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to u0|hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0 +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON +set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name ECO_REGENERATE_REPORT ON +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON \ No newline at end of file diff --git a/cs309-psoc/lab_3_1/hw/quartus/lab_3_1.sdc b/cs309-psoc/lab_3_1/hw/quartus/lab_3_1.sdc new file mode 100644 index 0000000..16a41f3 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/quartus/lab_3_1.sdc @@ -0,0 +1,6 @@ +create_clock -period 20 [get_ports FPGA_CLK1_50] +create_clock -period 20 [get_ports FPGA_CLK2_50] +create_clock -period 20 [get_ports FPGA_CLK3_50] + +derive_pll_clocks +derive_clock_uncertainty diff --git a/cs309-psoc/lab_3_1/hw/quartus/soc_system.qsys b/cs309-psoc/lab_3_1/hw/quartus/soc_system.qsys new file mode 100644 index 0000000..c43f742 --- /dev/null +++ b/cs309-psoc/lab_3_1/hw/quartus/soc_system.qsys @@ -0,0 +1,915 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + 0x000000000000000000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_3_1/lab_3_1.pdf b/cs309-psoc/lab_3_1/lab_3_1.pdf new file mode 100644 index 0000000..ebb19ef Binary files /dev/null and b/cs309-psoc/lab_3_1/lab_3_1.pdf differ diff --git a/cs309-psoc/lab_3_1/sw/hps/application/hps_soc_system.h b/cs309-psoc/lab_3_1/sw/hps/application/hps_soc_system.h new file mode 100644 index 0000000..6d58999 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/hps_soc_system.h @@ -0,0 +1,67 @@ +#ifndef _ALTERA_HPS_SOC_SYSTEM_H_ +#define _ALTERA_HPS_SOC_SYSTEM_H_ + +/* + * This file was automatically generated by the swinfo2header utility. + * + * Created from SOPC Builder system 'soc_system' in + * file 'hw/quartus/soc_system.sopcinfo'. + */ + +/* + * This file contains macros for module 'hps_0' and devices + * connected to the following master: + * h2f_lw_axi_master + * + * Do not include this header file and another header file created for a + * different module or master group at the same time. + * Doing so may result in duplicate macro names. + * Instead, use the system header file which has macros with unique names. + */ + +/* + * Macros for device 'lepton_0', class 'lepton' + * The macros are prefixed with 'LEPTON_0_'. + * The prefix is the slave descriptor. + */ +#define LEPTON_0_COMPONENT_TYPE lepton +#define LEPTON_0_COMPONENT_NAME lepton_0 +#define LEPTON_0_BASE 0x40000 +#define LEPTON_0_SPAN 32768 +#define LEPTON_0_END 0x47fff + +/* + * Macros for device 'mcp3204_0', class 'mcp3204' + * The macros are prefixed with 'MCP3204_0_'. + * The prefix is the slave descriptor. + */ +#define MCP3204_0_COMPONENT_TYPE mcp3204 +#define MCP3204_0_COMPONENT_NAME mcp3204_0 +#define MCP3204_0_BASE 0x49000 +#define MCP3204_0_SPAN 16 +#define MCP3204_0_END 0x4900f + +/* + * Macros for device 'pwm_1', class 'pwm' + * The macros are prefixed with 'PWM_1_'. + * The prefix is the slave descriptor. + */ +#define PWM_1_COMPONENT_TYPE pwm +#define PWM_1_COMPONENT_NAME pwm_1 +#define PWM_1_BASE 0x49010 +#define PWM_1_SPAN 16 +#define PWM_1_END 0x4901f + +/* + * Macros for device 'pwm_0', class 'pwm' + * The macros are prefixed with 'PWM_0_'. + * The prefix is the slave descriptor. + */ +#define PWM_0_COMPONENT_TYPE pwm +#define PWM_0_COMPONENT_NAME pwm_0 +#define PWM_0_BASE 0x49020 +#define PWM_0_SPAN 16 +#define PWM_0_END 0x4902f + + +#endif /* _ALTERA_HPS_SOC_SYSTEM_H_ */ diff --git a/cs309-psoc/lab_3_1/sw/hps/application/iorw.h b/cs309-psoc/lab_3_1/sw/hps/application/iorw.h new file mode 100644 index 0000000..67b35a6 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/iorw.h @@ -0,0 +1,24 @@ +#ifndef __IORW_H__ +#define __IORW_H__ + +#ifdef __nios2_arch__ + #include + + #define io_write_8(base, ofst, data) (IOWR_8DIRECT((base), (ofst), (data))) + #define io_write_16(base, ofst, data) (IOWR_16DIRECT((base), (ofst), (data))) + #define io_write_32(base, ofst, data) (IOWR_32DIRECT((base), (ofst), (data))) + #define io_read_8(base, ofst) (IORD_8DIRECT((base), (ofst))) + #define io_read_16(base, ofst) (IORD_16DIRECT((base), (ofst))) + #define io_read_32(base, ofst) (IORD_32DIRECT((base), (ofst))) +#else + #include + + #define io_write_8(base, ofst, data) (alt_write_byte((uintptr_t) (base) + (ofst), (data))) + #define io_write_16(base, ofst, data) (alt_write_hword((uintptr_t) (base) + (ofst), (data))) + #define io_write_32(base, ofst, data) (alt_write_word((uintptr_t) (base) + (ofst), (data))) + #define io_read_8(base, ofst) (alt_read_byte((uintptr_t) (base) + (ofst))) + #define io_read_16(base, ofst) (alt_read_hword((uintptr_t) (base) + (ofst))) + #define io_read_32(base, ofst) (alt_read_word((uintptr_t) (base) + (ofst))) +#endif + +#endif \ No newline at end of file diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/app.c b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/app.c new file mode 100644 index 0000000..c493fd8 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/app.c @@ -0,0 +1,96 @@ +#include +#include +#include +#include +#include +#include + +#include "pantilt/pantilt.h" +#include "joysticks/joysticks.h" +#include "lepton/lepton.h" + + +#define SLEEP_DURATION (1000) + +// Servos +#define PANTILT_PWM_V_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_V_MIN_DUTY_CYCLE_US + PANTILT_PWM_V_MAX_DUTY_CYCLE_US) / 2) +#define PANTILT_PWM_H_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_H_MIN_DUTY_CYCLE_US + PANTILT_PWM_H_MAX_DUTY_CYCLE_US) / 2) + +// Right joystick horizontal threshold for triggering lepton capture +#define LEPTON_RIGHT_JOYSTICK_HORIZONTAL_TRIGGER_THRESHOLD ((uint32_t) (0.8 * JOYSTICKS_MAX_VALUE)) + +uint32_t interpolate(uint32_t input, + uint32_t input_min, + uint32_t input_max, + uint32_t output_min, + uint32_t output_max) { + return (input - input_min) * (output_max - output_min) / (input_max - input_min) + output_min; +} + +void handle_pantilt(pantilt_dev *pantilt, joysticks_dev *joysticks) { + // Read LEFT joystick position + uint32_t left_joystick_v = joysticks_read_left_vertical(joysticks); + uint32_t left_joystick_h = joysticks_read_left_horizontal(joysticks); + + // Interpolate LEFT joystick position between SERVO_x_MIN_DUTY_CYCLE_US + // and SERVO_x_MAX_DUTY_CYCLE_US + uint32_t pantilt_v_duty_us = interpolate(left_joystick_v, + JOYSTICKS_MIN_VALUE, + JOYSTICKS_MAX_VALUE, + PANTILT_PWM_V_MIN_DUTY_CYCLE_US, + PANTILT_PWM_V_MAX_DUTY_CYCLE_US); + uint32_t pantilt_h_duty_us = interpolate(left_joystick_h, + JOYSTICKS_MIN_VALUE, + JOYSTICKS_MAX_VALUE, + PANTILT_PWM_H_MIN_DUTY_CYCLE_US, + PANTILT_PWM_H_MAX_DUTY_CYCLE_US); + + // Configure servos with interpolated joystick values + pantilt_configure_vertical(pantilt, pantilt_v_duty_us); + pantilt_configure_horizontal(pantilt, pantilt_h_duty_us); +} + +void handle_lepton(joysticks_dev *joysticks, lepton_dev *lepton) { + uint32_t h = joysticks_read_right_horizontal(joysticks); + uint32_t v = joysticks_read_right_vertical(joysticks); + + // If the norm of the joystick's movement is greater than half of the max value, we capture + if (4 * h * h + v * v >= MCP3204_MAX_VALUE * MCP3204_MAX_VALUE) { + do { + lepton_start_capture(lepton); + lepton_wait_until_eof(lepton); + } while(lepton_error_check(lepton)); + + lepton_save_capture(lepton, true, stdout); + } +} + +int main(void) { + // Hardware control structures + pantilt_dev pantilt = pantilt_inst((void*) PWM_0_BASE, (void*) PWM_1_BASE); + joysticks_dev joysticks = joysticks_inst((void*) MCP3204_0_BASE); + lepton_dev lepton = lepton_inst((void*) LEPTON_0_BASE); + + // Initialize hardware + pantilt_init(&pantilt); + joysticks_init(&joysticks); + lepton_init(&lepton); + + // Center servos. + pantilt_configure_vertical(&pantilt, PANTILT_PWM_V_CENTER_DUTY_CYCLE_US); + pantilt_configure_horizontal(&pantilt, PANTILT_PWM_H_CENTER_DUTY_CYCLE_US); + pantilt_start_vertical(&pantilt); + pantilt_start_horizontal(&pantilt); + + // Control servos with LEFT joystick, capture thermal image with RIGHT joystick. + while (true) { + handle_pantilt(&pantilt, &joysticks); + handle_lepton(&joysticks, &lepton); + + // Sleep for a while to avoid excessive sensitivity + uint32_t i = 0; + for (; i < SLEEP_DURATION; i++); + } + + return EXIT_SUCCESS; +} diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/joysticks.c b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/joysticks.c new file mode 100644 index 0000000..a84c8d4 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/joysticks.c @@ -0,0 +1,79 @@ +#include "joysticks.h" + +#define JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL (0) +#define JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL (1) +#define JOYSTICK_LEFT_VRY_MCP3204_CHANNEL (2) +#define JOYSTICK_LEFT_VRX_MCP3204_CHANNEL (3) + +/** + * joysticks_inst + * + * Instantiate a joysticks device structure. + * + * @param base Base address of the MCP3204 component connected to the joysticks. + */ +joysticks_dev joysticks_inst(void *mcp3204_base) { + joysticks_dev dev; + dev.mcp3204 = mcp3204_inst((void *) mcp3204_base); + + return dev; +} + +/** + * joysticks_init + * + * Initializes the joysticks device. + * + * @param dev joysticks device structure. + */ +void joysticks_init(joysticks_dev *dev) { + mcp3204_init(&(dev->mcp3204)); +} + +/** + * joysticks_read_left_vertical + * + * Returns the vertical position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204, JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL); +} + +/** + * joysticks_read_left_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204, JOYSTICK_LEFT_VRX_MCP3204_CHANNEL); +} + +/** + * joysticks_read_right_vertical + * + * Returns the vertical position of the right joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204, JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL); +} + +/** + * joysticks_read_right_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204, JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL); +} diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/joysticks.h b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/joysticks.h new file mode 100644 index 0000000..ac9c383 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/joysticks.h @@ -0,0 +1,27 @@ +#ifndef __JOYSTICKS_H__ +#define __JOYSTICKS_H__ + +#include "mcp3204/mcp3204.h" + +/* joysticks device structure */ +typedef struct joysticks_dev { + mcp3204_dev mcp3204; /* MCP3204 device handle */ +} joysticks_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define JOYSTICKS_MIN_VALUE (MCP3204_MIN_VALUE) +#define JOYSTICKS_MAX_VALUE (MCP3204_MAX_VALUE) + +joysticks_dev joysticks_inst(void *mcp3204_base); + +void joysticks_init(joysticks_dev *dev); + +uint32_t joysticks_read_left_vertical(joysticks_dev *dev); +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev); +uint32_t joysticks_read_right_vertical(joysticks_dev *dev); +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev); + +#endif /* __JOYSTICKS_H__ */ diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.c b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.c new file mode 100644 index 0000000..1210e31 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.c @@ -0,0 +1,44 @@ +#include "mcp3204.h" +#include "iorw.h" + +#define MCP3204_NUM_CHANNELS (4) + +/** + * mcp3204_inst + * + * Instantiate a mcp3204 device structure. + * + * @param base Base address of the component. + */ +mcp3204_dev mcp3204_inst(void *base) { + mcp3204_dev dev; + dev.base = base; + + return dev; +} + +/** + * mcp3204_init + * + * Initializes the mcp3204 device. + * + * @param dev mcp3204 device structure. + */ +void mcp3204_init(mcp3204_dev *dev) { + return; +} + +/** + * mcp3204_read + * + * Reads the register corresponding to the supplied channel parameter. + * + * @param dev mcp3204 device structure. + * @param channel channel to be read + */ +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) { + if (channel >= 4) + return 0; + + return io_read_32(dev->base, channel * 4); +} diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.h b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.h new file mode 100644 index 0000000..3b2b2e6 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204.h @@ -0,0 +1,23 @@ +#ifndef __MCP3204_H__ +#define __MCP3204_H__ + +#include + +/* mcp3204 device structure */ +typedef struct mcp3204_dev { + void *base; /* Base address of component */ +} mcp3204_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define MCP3204_MIN_VALUE (0) +#define MCP3204_MAX_VALUE (4095) + +mcp3204_dev mcp3204_inst(void *base); + +void mcp3204_init(mcp3204_dev *dev); +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel); + +#endif /* __MCP3204_H__ */ diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204_regs.h b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204_regs.h new file mode 100644 index 0000000..b1c78cd --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/joysticks/mcp3204/mcp3204_regs.h @@ -0,0 +1,9 @@ +#ifndef __MCP3204_REGS_H__ +#define __MCP3204_REGS_H__ + +#define MCP3204_CHANNEL_0_OFST (0 * 4) /* RO */ +#define MCP3204_CHANNEL_1_OFST (1 * 4) /* RO */ +#define MCP3204_CHANNEL_2_OFST (2 * 4) /* RO */ +#define MCP3204_CHANNEL_3_OFST (3 * 4) /* RO */ + +#endif /* __MCP3204_REGS_H__ */ diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/lepton/lepton.c b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/lepton/lepton.c new file mode 100644 index 0000000..64cfcf1 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/lepton/lepton.c @@ -0,0 +1,117 @@ +#include +#include +#include +#include + +#include "lepton_regs.h" +#include "lepton.h" +#include "iorw.h" + +/** + * lepton_inst + * + * Instantiate a lepton device structure. + * + * @param base Base address of the component. + */ +lepton_dev lepton_inst(void *base) { + lepton_dev dev; + dev.base = base; + + return dev; +} + +/** + * lepton_init + * + * Initializes the lepton device. + * + * @param dev lepton device structure. + */ +void lepton_init(lepton_dev *dev) { + return; +} + +/** + * lepton_start_capture + * + * Instructs the device to start the frame capture process. + * + * @param dev lepton device structure. + */ +void lepton_start_capture(lepton_dev *dev) { + io_write_16(dev->base, LEPTON_REGS_COMMAND_OFST, 0x1); +} + +/** + * lepton_error_check + * + * @abstract Check for errors at the device level. + * @param dev lepton device structure. + * @return true if there was an error, and false otherwise. + */ +bool lepton_error_check(lepton_dev *dev) { + return (io_read_16(dev->base, LEPTON_REGS_STATUS_OFST) & 0x2) != 0; +} + +/** + * lepton_wait_until_eof + * + * Waits until the frame being captured has been fully received and saved in the + * internal memory. + * + * @param dev lepton device structure. + */ +void lepton_wait_until_eof(lepton_dev *dev) { + while (io_read_16(dev->base, LEPTON_REGS_STATUS_OFST) & 0x1); +} + +/** + * lepton_save_capture + * + * Saves the captured frame on the host filesystem under the supplied filename. + * The frame will be saved in PGM format. + * + * @param dev lepton device structure. + * @param adjusted Setting this parameter to false will cause RAW sensor data to + * be written to the file. + * Setting this parameter to true will cause a preprocessed image + * (with a stretched dynamic range) to be saved to the file. + * + * @param fname the output file name. + */ +void lepton_save_capture(lepton_dev *dev, bool adjusted, FILE* file) { + assert(file); + + const uint8_t num_rows = 60; + const uint8_t num_cols = 80; + + uint16_t offset = LEPTON_REGS_RAW_BUFFER_OFST; + uint16_t max_value = io_read_16(dev->base, LEPTON_REGS_MAX_OFST); + if (adjusted) { + offset = LEPTON_REGS_ADJUSTED_BUFFER_OFST; + max_value = 0x3fff; + } + + /* Write PGM header */ + fprintf(file, "P2\n%" PRIu8 " %" PRIu8 "\n%" PRIu16, num_cols, num_rows, max_value); + + /* Write body */ + uint8_t row = 0; + for (row = 0; row < num_rows; ++row) { + fprintf(file, "\n"); + + uint8_t col = 0; + for (col = 0; col < num_cols; ++col) { + if (col > 0) { + fprintf(file, " "); + } + + uint16_t current_ofst = offset + (row * num_cols + col) * sizeof(uint16_t); + uint16_t pix_value = io_read_16(dev->base, current_ofst); + fprintf(file, "%" PRIu16, pix_value); + } + } + + assert(!fclose(file)); +} diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/lepton/lepton.h b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/lepton/lepton.h new file mode 100644 index 0000000..b642abb --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/lepton/lepton.h @@ -0,0 +1,23 @@ +#ifndef __LEPTON_H__ +#define __LEPTON_H__ + +#include + +/* lepton device structure */ +typedef struct { + void *base; /* Base address of the component */ +} lepton_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +lepton_dev lepton_inst(void *base); + +void lepton_init(lepton_dev *dev); +void lepton_start_capture(lepton_dev *dev); +void lepton_wait_until_eof(lepton_dev *dev); +bool lepton_error_check(lepton_dev *dev); +void lepton_save_capture(lepton_dev *dev, bool adjusted, FILE* file); + +#endif /* __LEPTON_H__ */ diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/lepton/lepton_regs.h b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/lepton/lepton_regs.h new file mode 100644 index 0000000..db24244 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/lepton/lepton_regs.h @@ -0,0 +1,25 @@ +#ifndef __LEPTON_REGS_H__ +#define __LEPTON_REGS_H__ + +/* Register offsets */ +#define LEPTON_REGS_COMMAND_OFST ( 0 * 2) /* WO */ +#define LEPTON_REGS_STATUS_OFST ( 1 * 2) /* RO */ +#define LEPTON_REGS_MIN_OFST ( 2 * 2) /* RO */ +#define LEPTON_REGS_MAX_OFST ( 3 * 2) /* RO */ +#define LEPTON_REGS_SUM_LSB_OFST ( 4 * 2) /* RO */ +#define LEPTON_REGS_SUM_MSB_OFST ( 5 * 2) /* RO */ +#define LEPTON_REGS_ROW_IDX_OFST ( 6 * 2) /* RO */ +#define LEPTON_REGS_RAW_BUFFER_OFST ( 8 * 2) /* RO */ +#define LEPTON_REGS_ADJUSTED_BUFFER_OFST (8192 * 2) /* RO */ + +/* Command register */ +#define LEPTON_COMMAND_START (0x0001) + +/* Status register */ +#define LEPTON_STATUS_CAPTURE_IN_PROGRESS_MASK (1 << 0) +#define LEPTON_STATUS_ERROR_MASK (1 << 1) + +#define LEPTON_REGS_BUFFER_NUM_PIXELS (80 * 60) +#define LEPTON_REGS_BUFFER_BYTELENGTH (LEPTON_REGS_BUFFER_NUM_PIXELS * 2) + +#endif /* __LEPTON_REGS_H__ */ diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pantilt.c b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pantilt.c new file mode 100644 index 0000000..d9c4c72 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pantilt.c @@ -0,0 +1,109 @@ +#include "pantilt.h" + +/** + * pantilt_inst + * + * Instantiate a pantilt device structure. + * + * @param pwm_v_base Base address of the vertical PWM component. + * @param pwm_h_base Base address of the horizontal PWM component. + */ +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) { + pantilt_dev dev; + dev.pwm_v = pwm_inst(pwm_v_base); + dev.pwm_h = pwm_inst(pwm_h_base); + + return dev; +} + +/** + * pantilt_init + * + * Initializes the pantilt device. + * + * @param dev pantilt device structure. + */ +void pantilt_init(pantilt_dev *dev) { + pwm_init(&(dev->pwm_v)); + pwm_init(&(dev->pwm_h)); +} + +/** + * pantilt_configure_vertical + * + * Configure the vertical PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_v), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_configure_horizontal + * + * Configure the horizontal PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_h), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_start_vertical + * + * Starts the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_vertical(pantilt_dev *dev) { + pwm_start(&(dev->pwm_v)); +} + +/** + * pantilt_start_horizontal + * + * Starts the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_horizontal(pantilt_dev *dev) { + pwm_start(&(dev->pwm_h)); +} + +/** + * pantilt_stop_vertical + * + * Stops the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_vertical(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_v)); +} + +/** + * pantilt_stop_horizontal + * + * Stops the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_horizontal(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_h)); +} diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pantilt.h b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pantilt.h new file mode 100644 index 0000000..1f17500 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pantilt.h @@ -0,0 +1,39 @@ +#ifndef __PANTILT_H__ +#define __PANTILT_H__ + +#include "pwm/pwm.h" + +/* joysticks device structure */ +typedef struct pantilt_dev { + pwm_dev pwm_v; /* Vertical PWM device handle */ + pwm_dev pwm_h; /* Horizontal PWM device handle */ +} pantilt_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz + +#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms + +/* Vertical servo */ +#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms +#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms + +/* Horizontal servo */ +#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms +#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms + +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base); + +void pantilt_init(pantilt_dev *dev); + +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_start_vertical(pantilt_dev *dev); +void pantilt_start_horizontal(pantilt_dev *dev); +void pantilt_stop_vertical(pantilt_dev *dev); +void pantilt_stop_horizontal(pantilt_dev *dev); + +#endif /* __PANTILT_H__ */ diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pwm/pwm.c b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pwm/pwm.c new file mode 100644 index 0000000..39fa34d --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pwm/pwm.c @@ -0,0 +1,68 @@ +#include "pwm.h" +#include "pwm_regs.h" +#include "iorw.h" + +#define MICROSEC_TO_CLK(time, freq) ((time) * ((freq) / 1000000)) + +/** + * pwm_inst + * + * Instantiate a pwm device structure. + * + * @param base Base address of the component. + */ +pwm_dev pwm_inst(void *base) { + pwm_dev dev; + + dev.base = base; + + return dev; +} + +/** + * pwm_init + * + * Initializes the pwm device. This function stops the controller. + * + * @param dev pwm device structure. + */ +void pwm_init(pwm_dev *dev) { + pwm_stop(dev); +} + +/** + * pwm_configure + * + * Configure pwm component. + * + * @param dev pwm device structure. + * @param duty_cycle pwm duty cycle in us. + * @param period pwm period in us. + * @param module_frequency frequency at which the component is clocked. + */ +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) { + io_write_32(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency)); + io_write_32(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency)); +} + +/** + * pwm_start + * + * Starts the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_start(pwm_dev *dev) { + io_write_32(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} + +/** + * pwm_stop + * + * Stops the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_stop(pwm_dev *dev) { + io_write_32(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pwm/pwm.h b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pwm/pwm.h new file mode 100644 index 0000000..e2987f4 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pwm/pwm.h @@ -0,0 +1,21 @@ +#ifndef __PWM_H__ +#define __PWM_H__ + +#include + +/* pwm device structure */ +typedef struct pwm_dev { + void *base; /* Base address of component */ +} pwm_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ +pwm_dev pwm_inst(void *base); + +void pwm_init(pwm_dev *dev); +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency); +void pwm_start(pwm_dev *dev); +void pwm_stop(pwm_dev *dev); + +#endif /* __PWM_H__ */ diff --git a/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pwm/pwm_regs.h b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pwm/pwm_regs.h new file mode 100644 index 0000000..488583d --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/application/lab_3_0/pantilt/pwm/pwm_regs.h @@ -0,0 +1,11 @@ +#ifndef __PWM_REGS_H__ +#define __PWM_REGS_H__ + +#define PWM_PERIOD_OFST (0 * 4) /* RW */ +#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */ +#define PWM_CTRL_OFST (2 * 4) /* WO */ + +#define PWM_CTRL_STOP_MASK (0) +#define PWM_CTRL_START_MASK (1) + +#endif /* __PWM_REGS_H__ */ diff --git a/cs309-psoc/lab_3_1/sw/hps/linux/rootfs/config_post_install.sh b/cs309-psoc/lab_3_1/sw/hps/linux/rootfs/config_post_install.sh new file mode 100755 index 0000000..1ccae61 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/linux/rootfs/config_post_install.sh @@ -0,0 +1,22 @@ +#!/bin/bash -x +# apt sources +# uncomment the "deb" lines (no need to uncomment "deb src" lines) + +# Edit the “/etc/apt/sources.list” file to configure the package manager. This +# file contains a list of mirrors that the package manager queries. By default, +# this file has all fields commented out, so the package manager will not have +# access to any mirrors. The following command uncomments all commented out +# lines starting with "deb". These contain the mirrors we are interested in. +sudo perl -pi -e 's/^#+\s+(deb\s+http)/$1/g' "/etc/apt/sources.list" + +# When writing our linux applications, we want to use ARM DS-5’s remote +# debugging feature to automatically transfer our binaries to the target device +# and to start a debugging session. The remote debugging feature requires an SSH +# server and a remote gdb server to be available on the target. These are easy +# to install as we have a package manager available +sudo apt update +sudo apt -y install ssh gdbserver + +# Allow root SSH login with password (needed so we can use ARM DS-5 for remote +# debugging) +sudo perl -pi -e 's/^(PermitRootLogin) without-password$/$1 yes/g' "/etc/ssh/sshd_config" diff --git a/cs309-psoc/lab_3_1/sw/hps/linux/rootfs/config_system.sh b/cs309-psoc/lab_3_1/sw/hps/linux/rootfs/config_system.sh new file mode 100755 index 0000000..e0c89b8 --- /dev/null +++ b/cs309-psoc/lab_3_1/sw/hps/linux/rootfs/config_system.sh @@ -0,0 +1,74 @@ +#!/bin/bash -x +# Configure the locale to have proper language support. +localedef -i en_US -c -f UTF-8 en_US.UTF-8 +dpkg-reconfigure locales +# Configure the timezone. +echo "Europe/Zurich" > "/etc/timezone" +dpkg-reconfigure -f noninteractive tzdata +# Set the machine’s hostname. +echo "DE0-Nano-SoC" > "/etc/hostname" +tee "/etc/hosts" >"/dev/null" < "/dev/null" < "/dev/null" < "/dev/null" < "/dev/null" < # OVERWRITE : Overwrite with your previous implementation. +│   │   │   │   └── mcp3204.vhd +│   │   │   └── tb +│   │   │   ├── tb_mcp3204_spi.vhd +│   │   │   └── tb_mcp3204.vhd +│   │   ├── lepton +│   │   │   ├── hdl +│   │   │   │   ├── avalon_st_spi_master.vhd +│   │   │   │   ├── byte2pix.vhd +│   │   │   │   ├── dual_ported_ram.vhd +│   │   │   │   ├── lepton_hw.tcl +│   │   │   │   ├── lepton_manager.vhd +│   │   │   │   ├── lepton_stats.vhd -----------------------> # OVERWRITE : Overwrite with your previous implementation. +│   │   │   │   ├── lepton.vhd +│   │   │   │   ├── level_adjuster.vhd ---------------------> # OVERWRITE : Overwrite with your previous implementation. +│   │   │   │   ├── lpm_divider.vhd +│   │   │   │   ├── ram_writer.vhd +│   │   │   │   └── utils.vhd +│   │   │   └── tb +│   │   │   └── lepton_tb.vhd +│   │   └── pantilt +│   │   ├── hdl +│   │   │   ├── pwm_constants.vhd ----------------------> # OVERWRITE : Overwrite with your previous implementation. +│   │   │   ├── pwm_hw.tcl +│   │   │   └── pwm.vhd --------------------------------> # OVERWRITE : Overwrite with your previous implementation. +│   │   └── tb +│   │   └── tb_pwm.vhd +│   ├── modelsim +│   └── quartus +│   ├── ip +│   │   └── components.ipx +│   ├── lab_4_0.qpf +│   ├── lab_4_0.qsf +│   ├── lab_4_0.sdc +│   └── soc_system.qsys +├── README +└── sw + └── hps + ├── application + │   ├── hw_headers + │   └── lab_4_0 + │   ├── app.c ----------------------------------> # TODO : Your lab_4_0 mini-project application code goes here. + │   ├── displays + │   │   ├── batman_320x240.jpg -----------------> # IMAGE : sample input images for "fbv" binary. + │   │   ├── batman_480x272.jpg -----------------> # IMAGE : sample input images for "fbv" binary. + │   │   ├── fb_multiple_buffering_example.c ----> # DEMO : how to use a framebuffer driver. + │   │   └── fbv --------------------------------> # BINARY : "framebuffer viewer" outputs an image to a framebuffer device (http://freecode.com/projects/fbv). + │   ├── io_custom.h + │   ├── joysticks + │   │   ├── joysticks.c ------------------------> # OVERWRITE : Overwrite with your previous implementation. + │   │   ├── joysticks.h ------------------------> # OVERWRITE : Overwrite with your previous implementation. + │   │   └── mcp3204 + │   │   ├── mcp3204.c ----------------------> # OVERWRITE : Overwrite with your previous implementation. + │   │   ├── mcp3204.h ----------------------> # OVERWRITE : Overwrite with your previous implementation. + │   │   └── mcp3204_regs.h -----------------> # OVERWRITE : Overwrite with your previous implementation. + │   ├── lepton + │   │   ├── lepton.c ---------------------------> # OVERWRITE : Overwrite with your previous implementation. + │   │   ├── lepton.h ---------------------------> # OVERWRITE : Overwrite with your previous implementation. + │   │   └── lepton_regs.h ----------------------> # OVERWRITE : Overwrite with your previous implementation. + │   └── pantilt + │   ├── pantilt.c --------------------------> # OVERWRITE : Overwrite with your previous implementation. + │   ├── pantilt.h --------------------------> # OVERWRITE : Overwrite with your previous implementation. + │   └── pwm + │   ├── pwm.c --------------------------> # OVERWRITE : Overwrite with your previous implementation. + │   ├── pwm.h --------------------------> # OVERWRITE : Overwrite with your previous implementation. + │   └── pwm_regs.h ---------------------> # OVERWRITE : Overwrite with your previous implementation. + └── linux + ├── device_tree + │   └── socfpga_cyclone5_de0_sockit_prsoc.dts --> # DEMO : source code of our custom device tree. + ├── driver + │   └── fbdev + │   ├── Makefile ---------------------------> # DEMO : makefile of our custom framebuffer driver. + │   └── prsoc_fbdev.c ----------------------> # DEMO : source code of our custom framebuffer driver. + └── rootfs + ├── config_post_install.sh + └── config_system.sh + +35 directories, 59 files diff --git a/cs309-psoc/lab_4_0/create_hw_headers.sh b/cs309-psoc/lab_4_0/create_hw_headers.sh new file mode 100755 index 0000000..caeb340 --- /dev/null +++ b/cs309-psoc/lab_4_0/create_hw_headers.sh @@ -0,0 +1,14 @@ +#!/bin/bash -x + +# make sure to be in the same directory as this script +script_dir_abs=$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd ) +cd "${script_dir_abs}" + +rm -rf sw/hps/application/hw_headers + +# create target directory if not present +mkdir -p sw/hps/application/hw_headers + +sopc-create-header-files \ +hw/quartus/soc_system.sopcinfo \ +--output-dir sw/hps/application/hw_headers diff --git a/cs309-psoc/lab_4_0/create_linux_system.sh b/cs309-psoc/lab_4_0/create_linux_system.sh new file mode 100755 index 0000000..5718006 --- /dev/null +++ b/cs309-psoc/lab_4_0/create_linux_system.sh @@ -0,0 +1,510 @@ +#!/bin/bash -x + +# =================================================================================== +# usage: create_linux_system.sh [sdcard_device] +# +# positional arguments: +# sdcard_device path to sdcard device file [ex: "/dev/sdb", "/dev/mmcblk0"] +# =================================================================================== + +# make sure to be in the same directory as this script +script_dir_abs=$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd ) +cd "${script_dir_abs}" + +# constants #################################################################### +quartus_dir="$(readlink -m "hw/quartus")" +quartus_project_name="$(basename "$(find "${quartus_dir}" -name "*.qpf")" .qpf)" +quartus_sof_file="$(readlink -m "${quartus_dir}/output_files/${quartus_project_name}.sof")" + +fpga_device_part_number="5CSEMA4U23C6" # 5CSEMA5F31C6 + +preloader_dir="$(readlink -m "sw/hps/preloader")" +preloader_settings_dir="$(readlink -m "${quartus_dir}/hps_isw_handoff/soc_system_hps_0")" +preloader_settings_file="$(readlink -m "${preloader_dir}/settings.bsp")" +preloader_source_tgz_file="$(readlink -m "${SOCEDS_DEST_ROOT}/host_tools/altera/preloader/uboot-socfpga.tar.gz")" +preloader_bin_file="${preloader_dir}/preloader-mkpimage.bin" + +uboot_src_dir="$(readlink -m "sw/hps/u-boot")" +uboot_src_git_repo="git://git.denx.de/u-boot.git" +uboot_src_git_checkout_commit="b104b3dc1dd90cdbf67ccf3c51b06e4f1592fe91" +uboot_src_make_config_file="socfpga_de0_nano_soc_defconfig" # socfpga_cyclone5_config +uboot_src_config_file="${uboot_src_dir}/include/configs/socfpga_de0_nano_soc.h" # socfpga_cyclone5_socdk.h +uboot_script_file="$(readlink -m "${uboot_src_dir}/u-boot.script")" +uboot_img_file="$(readlink -m "${uboot_src_dir}/u-boot.img")" + +linux_dir="$(readlink -m "sw/hps/linux")" +linux_src_git_repo="https://github.com/altera-opensource/linux-socfpga.git" +linux_src_dir="$(readlink -m "${linux_dir}/source")" +linux_src_git_checkout_commit="9735a22799b9214d17d3c231fe377fc852f042e9" +linux_src_make_config_file="socfpga_defconfig" +linux_kernel_mem_arg="1024M" +linux_zImage_file="$(readlink -m "${linux_src_dir}/arch/arm/boot/zImage")" +linux_dtb_file="$(readlink -m "${linux_src_dir}/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dtb")" # socfpga_cyclone5_socdk.dtb + +rootfs_dir="${linux_dir}/rootfs" +rootfs_chroot_dir="$(readlink -m ${rootfs_dir}/ubuntu-core-rootfs)" +rootfs_src_tgz_link="http://cdimage.ubuntu.com/ubuntu-base/releases/14.04.5/release/ubuntu-base-14.04.5-base-armhf.tar.gz" +rootfs_src_tgz_file="$(readlink -m "${rootfs_dir}/${rootfs_src_tgz_link##*/}")" +rootfs_system_config_script_file="${rootfs_dir}/config_system.sh" +rootfs_post_install_config_script_file="${rootfs_dir}/config_post_install.sh" + +sdcard_fat32_dir="$(readlink -m "sdcard/fat32")" +sdcard_fat32_rbf_file="$(readlink -m "${sdcard_fat32_dir}/socfpga.rbf")" +sdcard_fat32_uboot_img_file="$(readlink -m "${sdcard_fat32_dir}/$(basename "${uboot_img_file}")")" +sdcard_fat32_uboot_scr_file="$(readlink -m "${sdcard_fat32_dir}/u-boot.scr")" +sdcard_fat32_zImage_file="$(readlink -m "${sdcard_fat32_dir}/zImage")" +sdcard_fat32_dtb_file="$(readlink -m "${sdcard_fat32_dir}/socfpga.dtb")" + +sdcard_dev="$(readlink -m "${1}")" + +sdcard_ext3_rootfs_tgz_file="$(readlink -m "sdcard/ext3_rootfs.tar.gz")" + +sdcard_a2_dir="$(readlink -m "sdcard/a2")" +sdcard_a2_preloader_bin_file="$(readlink -m "${sdcard_a2_dir}/$(basename "${preloader_bin_file}")")" + +sdcard_partition_size_fat32="32M" +sdcard_partition_size_linux="512M" + +sdcard_partition_number_fat32="1" +sdcard_partition_number_ext3="2" +sdcard_partition_number_a2="3" + +if [ "$(echo "${sdcard_dev}" | grep -P "/dev/sd\w.*$")" ]; then + sdcard_dev_fat32_id="${sdcard_partition_number_fat32}" + sdcard_dev_ext3_id="${sdcard_partition_number_ext3}" + sdcard_dev_a2_id="${sdcard_partition_number_a2}" +elif [ "$(echo "${sdcard_dev}" | grep -P "/dev/mmcblk\w.*$")" ]; then + sdcard_dev_fat32_id="p${sdcard_partition_number_fat32}" + sdcard_dev_ext3_id="p${sdcard_partition_number_ext3}" + sdcard_dev_a2_id="p${sdcard_partition_number_a2}" +fi + +sdcard_dev_fat32="${sdcard_dev}${sdcard_dev_fat32_id}" +sdcard_dev_ext3="${sdcard_dev}${sdcard_dev_ext3_id}" +sdcard_dev_a2="${sdcard_dev}${sdcard_dev_a2_id}" +sdcard_dev_fat32_mount_point="$(readlink -m "sdcard/mount_point_fat32")" +sdcard_dev_ext3_mount_point="$(readlink -m "sdcard/mount_point_ext3")" + +# compile_quartus_project() #################################################### +compile_quartus_project() { + # change working directory to quartus directory + pushd "${quartus_dir}" + + # delete old artifacts + rm -rf "c5_pin_model_dump.txt" \ + "db/" \ + "hps_isw_handoff/" \ + "hps_sdram_p0_all_pins.txt" \ + "incremental_db/" \ + "output_files/" \ + "soc_system.sopcinfo" \ + "soc_system/" \ + "${quartus_project_name}.qws" \ + "${sdcard_fat32_rbf_file}" + + qsys-generate "soc_system.qsys" --synthesis=VHDL --output-directory="soc_system/" --part="${fpga_device_part_number}" + + # Analysis and synthesis + quartus_map "${quartus_project_name}" + + # Execute HPS DDR3 pin assignment TCL script + # it is normal for the following script to report an error, but it was + # sucessfully executed + ddr3_pin_assignment_script="$(find . -name "hps_sdram_p0_pin_assignments.tcl")" + quartus_sta -t "${ddr3_pin_assignment_script}" "${quartus_project_name}" + + # Fitter + quartus_fit "${quartus_project_name}" + + # Assembler + quartus_asm "${quartus_project_name}" + + # convert .sof to .rbf in associated sdcard directory + quartus_cpf -c "${quartus_sof_file}" "${sdcard_fat32_rbf_file}" + + # change working directory back to script directory + popd +} + +# compile_preloader() ########################################################## +compile_preloader() { + # delete old artifacts + rm -rf "${preloader_dir}" \ + "${sdcard_a2_preloader_bin_file}" + + # create directory for preloader + mkdir -p "${preloader_dir}" + + # change working directory to preloader directory + pushd "${preloader_dir}" + + # create bsp settings file + bsp-create-settings \ + --bsp-dir "${preloader_dir}" \ + --preloader-settings-dir "${preloader_settings_dir}" \ + --settings "${preloader_settings_file}" \ + --type spl \ + --set spl.CROSS_COMPILE "arm-altera-eabi-" \ + --set spl.PRELOADER_TGZ "${preloader_source_tgz_file}" \ + --set spl.boot.BOOTROM_HANDSHAKE_CFGIO "1" \ + --set spl.boot.BOOT_FROM_NAND "0" \ + --set spl.boot.BOOT_FROM_QSPI "0" \ + --set spl.boot.BOOT_FROM_RAM "0" \ + --set spl.boot.BOOT_FROM_SDMMC "1" \ + --set spl.boot.CHECKSUM_NEXT_IMAGE "1" \ + --set spl.boot.EXE_ON_FPGA "0" \ + --set spl.boot.FAT_BOOT_PARTITION "1" \ + --set spl.boot.FAT_LOAD_PAYLOAD_NAME "$(basename "${uboot_img_file}")" \ + --set spl.boot.FAT_SUPPORT "1" \ + --set spl.boot.FPGA_DATA_BASE "0xffff0000" \ + --set spl.boot.FPGA_DATA_MAX_SIZE "0x10000" \ + --set spl.boot.FPGA_MAX_SIZE "0x10000" \ + --set spl.boot.NAND_NEXT_BOOT_IMAGE "0xc0000" \ + --set spl.boot.QSPI_NEXT_BOOT_IMAGE "0x60000" \ + --set spl.boot.RAMBOOT_PLLRESET "1" \ + --set spl.boot.SDMMC_NEXT_BOOT_IMAGE "0x40000" \ + --set spl.boot.SDRAM_SCRUBBING "0" \ + --set spl.boot.SDRAM_SCRUB_BOOT_REGION_END "0x2000000" \ + --set spl.boot.SDRAM_SCRUB_BOOT_REGION_START "0x1000000" \ + --set spl.boot.SDRAM_SCRUB_REMAIN_REGION "1" \ + --set spl.boot.STATE_REG_ENABLE "1" \ + --set spl.boot.WARMRST_SKIP_CFGIO "1" \ + --set spl.boot.WATCHDOG_ENABLE "1" \ + --set spl.debug.DEBUG_MEMORY_ADDR "0xfffffd00" \ + --set spl.debug.DEBUG_MEMORY_SIZE "0x200" \ + --set spl.debug.DEBUG_MEMORY_WRITE "0" \ + --set spl.debug.HARDWARE_DIAGNOSTIC "0" \ + --set spl.debug.SEMIHOSTING "0" \ + --set spl.debug.SKIP_SDRAM "0" \ + --set spl.performance.SERIAL_SUPPORT "1" \ + --set spl.reset_assert.DMA "0" \ + --set spl.reset_assert.GPIO0 "0" \ + --set spl.reset_assert.GPIO1 "0" \ + --set spl.reset_assert.GPIO2 "0" \ + --set spl.reset_assert.L4WD1 "0" \ + --set spl.reset_assert.OSC1TIMER1 "0" \ + --set spl.reset_assert.SDR "0" \ + --set spl.reset_assert.SPTIMER0 "0" \ + --set spl.reset_assert.SPTIMER1 "0" \ + --set spl.warm_reset_handshake.ETR "1" \ + --set spl.warm_reset_handshake.FPGA "1" \ + --set spl.warm_reset_handshake.SDRAM "0" + + # generate bsp + bsp-generate-files \ + --bsp-dir "${preloader_dir}" \ + --settings "${preloader_settings_file}" + + # compile preloader + make -j4 + + # copy artifacts to associated sdcard directory + cp "${preloader_bin_file}" "${sdcard_a2_preloader_bin_file}" + + # change working directory back to script directory + popd +} + +# compile_uboot ################################################################ +compile_uboot() { + # delete old artifacts + rm -rf "${sdcard_fat32_uboot_scr_file}" \ + "${sdcard_fat32_uboot_img_file}" + + # if uboot source tree doesn't exist, then download it + if [ ! -d "${uboot_src_dir}" ]; then + git clone "${uboot_src_git_repo}" "${uboot_src_dir}" + fi + + # change working directory to uboot source tree directory + pushd "${uboot_src_dir}" + + # use cross compiler instead of standard x86 version of gcc + export CROSS_COMPILE=arm-linux-gnueabihf- + + # clean up source tree + make distclean + + # checkout the following commit (tested and working): + git checkout "${uboot_src_git_checkout_commit}" + + # configure uboot for socfpga_cyclone5 architecture + make "${uboot_src_make_config_file}" + + ## patch the uboot configuration file that describes environment variables + # replace value of CONFIG_BOOTCOMMAND macro (we will always use a script for configuring everything) + # result: + # #define CONFIG_BOOTCOMMAND "run callscript" + perl -pi -e 's/^(#define\s+CONFIG_BOOTCOMMAND)(.*)/$1\t"run callscript"/g' "${uboot_src_config_file}" + + # replace value of CONFIG_EXTRA_ENV_SETTINGS macro + # result: + # #define CONFIG_EXTRA_ENV_SETTINGS \ + # "scriptfile=u-boot.scr" "\0" \ + # "fpgadata=0x2000000" "\0" \ + # "callscript=fatload mmc 0:1 $fpgadata $scriptfile;" \ + # "source $fpgadata" "\0" + perl -pi -e 'BEGIN{undef $/;} s/^(#define\s+CONFIG_EXTRA_ENV_SETTINGS)(.*)#include/$1\t"scriptfile=u-boot.scr\\0" "fpgadata=0x2000000\\0" "callscript=fatload mmc 0:1 \$fpgadata \$scriptfile; source \$fpgadata\\0"\n\n#include/smg' "${uboot_src_config_file}" + + # compile uboot + make -j4 + + # create uboot script + cat < "${uboot_script_file}" +################################################################################ +echo --- Resetting Env variables --- + +# reset environment variables to default +env default -a + +echo --- Setting Env variables --- + +# Set the kernel image +setenv bootimage $(basename ${sdcard_fat32_zImage_file}); + +# address to which the device tree will be loaded +setenv fdtaddr 0x00000100 + +# Set the devicetree image +setenv fdtimage $(basename ${sdcard_fat32_dtb_file}); + +# set kernel boot arguments, then boot the kernel +setenv mmcboot 'setenv bootargs mem=${linux_kernel_mem_arg} console=ttyS0,115200 root=\${mmcroot} rw rootwait; \ +bootz \${loadaddr} - \${fdtaddr}'; + +# load linux kernel image and device tree to memory +setenv mmcload 'mmc rescan; \ +\${mmcloadcmd} mmc 0:\${mmcloadpart} \${loadaddr} \${bootimage}; \ +\${mmcloadcmd} mmc 0:\${mmcloadpart} \${fdtaddr} \${fdtimage}' + +# command to be executed to read from sdcard +setenv mmcloadcmd fatload + +# sdcard fat32 partition number +setenv mmcloadpart ${sdcard_partition_number_fat32} + +# sdcard ext3 identifier +setenv mmcroot /dev/mmcblk0p${sdcard_partition_number_ext3} + +# standard input/output +setenv stderr serial +setenv stdin serial +setenv stdout serial + +# save environment to sdcard (not needed, but useful to avoid CRC errors on a new sdcard) +saveenv + +################################################################################ +echo --- Programming FPGA --- + +# load rbf from FAT partition into memory +fatload mmc 0:1 \${fpgadata} $(basename ${sdcard_fat32_rbf_file}); + +# program FPGA +fpga load 0 \${fpgadata} \${filesize}; + +# enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges +bridge enable; + +################################################################################ +echo --- Booting Linux --- + +# load linux kernel image and device tree to memory +run mmcload; + +# set kernel boot arguments, then boot the kernel +run mmcboot; +EOF + + # compile uboot script to binary form + mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "${quartus_project_name}" -d "${uboot_script_file}" "${sdcard_fat32_uboot_scr_file}" + + # copy artifacts to associated sdcard directory + cp "${uboot_img_file}" "${sdcard_fat32_uboot_img_file}" + + # change working directory back to script directory + popd +} + +# compile_linux() ############################################################## +compile_linux() { + # if linux source tree doesn't exist, then download it + if [ ! -d "${linux_src_dir}" ]; then + git clone "${linux_src_git_repo}" "${linux_src_dir}" + fi + + # change working directory to linux source tree directory + pushd "${linux_src_dir}" + + # compile for the ARM architecture + export ARCH=arm + + # use cross compiler instead of standard x86 version of gcc + export CROSS_COMPILE=arm-linux-gnueabihf- + + # clean up source tree + make distclean + + # checkout the following commit (tested and working): + git checkout "${linux_src_git_checkout_commit}" + + # configure kernel for socfpga architecture + make "${linux_src_make_config_file}" + + # compile zImage + make -j4 zImage + + # compile device tree + make -j4 "$(basename "${linux_dtb_file}")" + + # copy artifacts to associated sdcard directory + cp "${linux_zImage_file}" "${sdcard_fat32_zImage_file}" + cp "${linux_dtb_file}" "${sdcard_fat32_dtb_file}" + + # change working directory back to script directory + popd +} + +# create_rootfs() ############################################################## +create_rootfs() { + # if rootfs tarball doesn't exist, then download it + if [ ! -f "${rootfs_src_tgz_file}" ]; then + wget "${rootfs_src_tgz_link}" -O "${rootfs_src_tgz_file}" + fi + + # delete old artifacts + sudo rm -rf "${rootfs_chroot_dir}" \ + "${sdcard_ext3_rootfs_tgz_file}" + + # create dir to extract rootfs + mkdir -p "${rootfs_chroot_dir}" + + # extract ubuntu core rootfs + pushd "${rootfs_chroot_dir}" + sudo tar -xzpf "${rootfs_src_tgz_file}" + popd + + # copy chroot SYSTEM configuration script to chroot directory + sudo cp "${rootfs_system_config_script_file}" "${rootfs_chroot_dir}" + + # edit chroot environment's /etc/rc.local to execute the rootfs + # configuration script + sudo tee "${rootfs_chroot_dir}/etc/rc.local" > "/dev/null" < 4095 t a2 (2048 is default first sector) + # n p 1 +32M t 1 b (4096 is default first sector) + # n p 2 +512M t 2 83 (69632 is default first sector) + # w + # result + # Device Boot Start End Sectors Size Id Type + # /dev/sdb1 4096 69631 65536 32M b W95 FAT32 + # /dev/sdb2 69632 1118207 1048576 512M 83 Linux + # /dev/sdb3 2048 4095 2048 1M a2 unknown + # note that you can choose any size for the FAT32 and Linux partitions, + # but the a2 partition must be 1M. + + # automatically partitioning the sdcard + # wipe partition table + sudo dd if="/dev/zero" of="${sdcard_dev}" bs=512 count=1 + + # create partitions + # no need to specify the partition number for the first invocation of + # the "t" command in fdisk, because there is only 1 partition at this + # point + echo -e "n\np\n3\n\n4095\nt\na2\nn\np\n1\n\n+${sdcard_partition_size_fat32}\nt\n1\nb\nn\np\n2\n\n+${sdcard_partition_size_linux}\nt\n2\n83\nw\nq\n" | sudo fdisk "${sdcard_dev}" + + # create filesystems + sudo mkfs.vfat "${sdcard_dev_fat32}" + sudo mkfs.ext3 -F "${sdcard_dev_ext3}" +} + +# write_sdcard() ############################################################### +write_sdcard() { + # create mount point for sdcard + mkdir -p "${sdcard_dev_fat32_mount_point}" + mkdir -p "${sdcard_dev_ext3_mount_point}" + + # mount sdcard partitions + sudo mount "${sdcard_dev_fat32}" "${sdcard_dev_fat32_mount_point}" + sudo mount "${sdcard_dev_ext3}" "${sdcard_dev_ext3_mount_point}" + + # preloader + sudo dd if="${sdcard_a2_preloader_bin_file}" of="${sdcard_dev_a2}" bs=64K seek=0 + + # fpga .rbf, uboot .img, uboot .scr, linux zImage, linux .dtb + sudo cp "${sdcard_fat32_dir}"/* "${sdcard_dev_fat32_mount_point}" + + # linux rootfs + pushd "${sdcard_dev_ext3_mount_point}" + sudo tar -xzf "${sdcard_ext3_rootfs_tgz_file}" + popd + + # flush write buffers to target + sudo sync + + # unmount sdcard partitions + sudo umount "${sdcard_dev_fat32_mount_point}" + sudo umount "${sdcard_dev_ext3_mount_point}" + + # delete mount points for sdcard + rm -rf "${sdcard_dev_fat32_mount_point}" + rm -rf "${sdcard_dev_ext3_mount_point}" +} + +# Script execution ############################################################# + +# Report script line number on any error (non-zero exit code). +trap 'echo "Error on line ${LINENO}" 1>&2' ERR +set -e + +# Create sdcard output directories +mkdir -p "${sdcard_a2_dir}" +mkdir -p "${sdcard_fat32_dir}" + +compile_quartus_project +compile_preloader +compile_uboot +compile_linux +create_rootfs + +# Write sdcard if it exists +if [ -z "${sdcard_dev}" ]; then + echo "sdcard argument not provided => no sdcard written." + +elif [ -b "${sdcard_dev}" ]; then + partition_sdcard + write_sdcard +fi + +# Make sure MSEL = 000000 diff --git a/cs309-psoc/lab_4_0/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd b/cs309-psoc/lab_4_0/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd new file mode 100644 index 0000000..52de847 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd @@ -0,0 +1,347 @@ +-- ############################################################################# +-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +-- +-- BOARD : PrSoC extension board for DE0-Nano-SoC +-- Author : Florian Depraz based on Sahand Kashani-Akhavan work +-- Revision : 1.1 +-- Creation date : 06/02/2016 +-- +-- Syntax Rule : GROUP_NAME_N[bit] +-- +-- GROUP : specify a particular interface (ex: SDR_) +-- NAME : signal name (ex: CONFIG, D, ...) +-- bit : signal index +-- _N : to specify an active-low signal +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; + +entity DE0_Nano_SoC_PrSoC_extn_board_top_level is + port( + ------------------------------- + -- Comment ALL unused ports. -- + ------------------------------- + + -- CLOCK + FPGA_CLK1_50 : in std_logic; + -- FPGA_CLK2_50 : in std_logic; + -- FPGA_CLK3_50 : in std_logic; + + -- KEY on DE0 Nano SoC + KEY_N : in std_logic_vector(1 downto 0); + + -- LEDs on DE0 Nano SoC + -- LED : out std_logic_vector(7 downto 0); + + -- SWITCHES on DE0 Nano SoC + -- SW : in std_logic_vector(3 downto 0); + + -- Servomotors pwm + SERVO_0 : out std_logic; + SERVO_1 : out std_logic; + + -- ADC Joysticks + J0_SPI_CS_n : out std_logic; + J0_SPI_MOSI : out std_logic; + J0_SPI_MISO : in std_logic; + J0_SPI_CLK : out std_logic; + + -- Lepton + CAM_TH_SPI_CS_N : out std_logic; + CAM_TH_MISO : in std_logic; + CAM_TH_MOSI : out std_logic; + CAM_TH_CLK : out std_logic; + + -- PCA9637 + -- PIO_SCL : inout std_logic; + -- PIO_SDA : inout std_logic; + -- PIO_INT_N : in std_logic; + -- RESET_N : out std_logic; + + -- OV7670 + -- CAM_D : in std_logic_vector(9 downto 0); + -- CAM_PIX_CLK : in std_logic; + -- CAM_LV : in std_logic; + -- CAM_FV : in std_logic; + -- CAM_SYS_CLK : out std_logic; + + -- VGA and LCD shared signals + VIDEO_CLK : out std_logic; + VIDEO_VSYNC : out std_logic; + VIDEO_HSYNC : out std_logic; + VIDEO_B : out std_logic_vector(7 downto 0); + VIDEO_G : out std_logic_vector(7 downto 0); + VIDEO_R : out std_logic_vector(7 downto 0); + + -- LCD Specific signals + LCD_DE : out std_logic; + -- LCD_PIN_DAV_N : ? ?? std_logic; + LCD_DISPLAY_EN : out std_logic; + -- SPI_MISO : in std_logic; + -- SPI_ENA_N : out std_logic; + -- SPI_CLK : out std_logic; + -- SPI_MOSI : out std_logic; + -- SPI_DAT : inout std_logic; + + -- I2C TOUCH SCREEN + -- TS_SCL : inout std_logic; + -- TS_SDA : inout std_logic; + + -- BLUETOOTH (BLE) + -- BLT_TXD : in std_logic; + -- BLT_RXD : out std_logic; + + -- I2C For VGA, PAL and OV7670 cameras + -- CAM_PAL_VGA_SDA : inout std_logic; + -- CAM_PAL_VGA_SCL : inout std_logic; + + -- ONE WIRE + -- BOARD_ID : inout std_logic; + + -- PAL Camera + -- PAL_VD_VD : in std_logic_vector(7 downto 0); + -- PAL_VD_VSO : in std_logic; + -- PAL_VD_HSO : in std_logic; + -- PAL_VD_CLKO : in std_logic; + -- PAL_PWDN : out std_logic; + + -- WIFI + -- FROM_ESP_TXD : in std_logic; + -- TO_ESP_RXD : out std_logic; + + -- LED RGB + -- LED_BGR : out std_logic; + + -- HPS + HPS_CONV_USB_N : inout std_logic; + HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); + HPS_DDR3_BA : out std_logic_vector(2 downto 0); + HPS_DDR3_CAS_N : out std_logic; + HPS_DDR3_CK_N : out std_logic; + HPS_DDR3_CK_P : out std_logic; + HPS_DDR3_CKE : out std_logic; + HPS_DDR3_CS_N : out std_logic; + HPS_DDR3_DM : out std_logic_vector(3 downto 0); + HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); + HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); + HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); + HPS_DDR3_ODT : out std_logic; + HPS_DDR3_RAS_N : out std_logic; + HPS_DDR3_RESET_N : out std_logic; + HPS_DDR3_RZQ : in std_logic; + HPS_DDR3_WE_N : out std_logic; + HPS_ENET_GTX_CLK : out std_logic; + HPS_ENET_INT_N : inout std_logic; + HPS_ENET_MDC : out std_logic; + HPS_ENET_MDIO : inout std_logic; + HPS_ENET_RX_CLK : in std_logic; + HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); + HPS_ENET_RX_DV : in std_logic; + HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); + HPS_ENET_TX_EN : out std_logic; + HPS_GSENSOR_INT : inout std_logic; + HPS_I2C0_SCLK : inout std_logic; + HPS_I2C0_SDAT : inout std_logic; + HPS_I2C1_SCLK : inout std_logic; + HPS_I2C1_SDAT : inout std_logic; + HPS_KEY_N : inout std_logic; + HPS_LED : inout std_logic; + HPS_LTC_GPIO : inout std_logic; + HPS_SD_CLK : out std_logic; + HPS_SD_CMD : inout std_logic; + HPS_SD_DATA : inout std_logic_vector(3 downto 0); + HPS_SPIM_CLK : out std_logic; + HPS_SPIM_MISO : in std_logic; + HPS_SPIM_MOSI : out std_logic; + HPS_SPIM_SS : inout std_logic; + HPS_UART_RX : in std_logic; + HPS_UART_TX : out std_logic; + HPS_USB_CLKOUT : in std_logic; + HPS_USB_DATA : inout std_logic_vector(7 downto 0); + HPS_USB_DIR : in std_logic; + HPS_USB_NXT : in std_logic; + HPS_USB_STP : out std_logic + ); +end entity DE0_Nano_SoC_PrSoC_extn_board_top_level; + +architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is + component soc_system is + port( + clk_clk : in std_logic := 'X'; + reset_reset_n : in std_logic := 'X'; + hps_0_ddr_mem_a : out std_logic_vector(14 downto 0); + hps_0_ddr_mem_ba : out std_logic_vector(2 downto 0); + hps_0_ddr_mem_ck : out std_logic; + hps_0_ddr_mem_ck_n : out std_logic; + hps_0_ddr_mem_cke : out std_logic; + hps_0_ddr_mem_cs_n : out std_logic; + hps_0_ddr_mem_ras_n : out std_logic; + hps_0_ddr_mem_cas_n : out std_logic; + hps_0_ddr_mem_we_n : out std_logic; + hps_0_ddr_mem_reset_n : out std_logic; + hps_0_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); + hps_0_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); + hps_0_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); + hps_0_ddr_mem_odt : out std_logic; + hps_0_ddr_mem_dm : out std_logic_vector(3 downto 0); + hps_0_ddr_oct_rzqin : in std_logic := 'X'; + hps_0_io_hps_io_emac1_inst_TX_CLK : out std_logic; + hps_0_io_hps_io_emac1_inst_TX_CTL : out std_logic; + hps_0_io_hps_io_emac1_inst_TXD0 : out std_logic; + hps_0_io_hps_io_emac1_inst_TXD1 : out std_logic; + hps_0_io_hps_io_emac1_inst_TXD2 : out std_logic; + hps_0_io_hps_io_emac1_inst_TXD3 : out std_logic; + hps_0_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; + hps_0_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; + hps_0_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; + hps_0_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; + hps_0_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; + hps_0_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; + hps_0_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; + hps_0_io_hps_io_emac1_inst_MDC : out std_logic; + hps_0_io_hps_io_sdio_inst_CLK : out std_logic; + hps_0_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; + hps_0_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; + hps_0_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; + hps_0_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; + hps_0_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_STP : out std_logic; + hps_0_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; + hps_0_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; + hps_0_io_hps_io_spim1_inst_CLK : out std_logic; + hps_0_io_hps_io_spim1_inst_MOSI : out std_logic; + hps_0_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; + hps_0_io_hps_io_spim1_inst_SS0 : out std_logic; + hps_0_io_hps_io_uart0_inst_RX : in std_logic := 'X'; + hps_0_io_hps_io_uart0_inst_TX : out std_logic; + hps_0_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; + hps_0_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; + hps_0_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; + hps_0_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; + hps_0_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; + hps_0_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; + hps_0_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; + hps_0_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; + hps_0_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; + hps_0_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; + pwm_0_conduit_end_pwm : out std_logic; + pwm_1_conduit_end_pwm : out std_logic; + mcp3204_0_conduit_end_cs_n : out std_logic; + mcp3204_0_conduit_end_mosi : out std_logic; + mcp3204_0_conduit_end_miso : in std_logic := 'X'; + mcp3204_0_conduit_end_sclk : out std_logic; + lepton_0_spi_cs_n : out std_logic; + lepton_0_spi_mosi : out std_logic; + lepton_0_spi_miso : in std_logic := 'X'; + lepton_0_spi_sclk : out std_logic; + pixclk_clk : out std_logic; + vga_hsync : out std_logic; + vga_vsync : out std_logic; + vga_r : out std_logic_vector(7 downto 0); + vga_g : out std_logic_vector(7 downto 0); + vga_b : out std_logic_vector(7 downto 0); + vga_de : out std_logic + ); + end component soc_system; + +begin + soc_system_inst : component soc_system + port map( + clk_clk => FPGA_CLK1_50, + reset_reset_n => KEY_N(0), + hps_0_ddr_mem_a => HPS_DDR3_ADDR, + hps_0_ddr_mem_ba => HPS_DDR3_BA, + hps_0_ddr_mem_ck => HPS_DDR3_CK_P, + hps_0_ddr_mem_ck_n => HPS_DDR3_CK_N, + hps_0_ddr_mem_cke => HPS_DDR3_CKE, + hps_0_ddr_mem_cs_n => HPS_DDR3_CS_N, + hps_0_ddr_mem_ras_n => HPS_DDR3_RAS_N, + hps_0_ddr_mem_cas_n => HPS_DDR3_CAS_N, + hps_0_ddr_mem_we_n => HPS_DDR3_WE_N, + hps_0_ddr_mem_reset_n => HPS_DDR3_RESET_N, + hps_0_ddr_mem_dq => HPS_DDR3_DQ, + hps_0_ddr_mem_dqs => HPS_DDR3_DQS_P, + hps_0_ddr_mem_dqs_n => HPS_DDR3_DQS_N, + hps_0_ddr_mem_odt => HPS_DDR3_ODT, + hps_0_ddr_mem_dm => HPS_DDR3_DM, + hps_0_ddr_oct_rzqin => HPS_DDR3_RZQ, + hps_0_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK, + hps_0_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN, + hps_0_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0), + hps_0_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1), + hps_0_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), + hps_0_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), + hps_0_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK, + hps_0_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV, + hps_0_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), + hps_0_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), + hps_0_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), + hps_0_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), + hps_0_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO, + hps_0_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC, + hps_0_io_hps_io_sdio_inst_CLK => HPS_SD_CLK, + hps_0_io_hps_io_sdio_inst_CMD => HPS_SD_CMD, + hps_0_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), + hps_0_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), + hps_0_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), + hps_0_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), + hps_0_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT, + hps_0_io_hps_io_usb1_inst_STP => HPS_USB_STP, + hps_0_io_hps_io_usb1_inst_DIR => HPS_USB_DIR, + hps_0_io_hps_io_usb1_inst_NXT => HPS_USB_NXT, + hps_0_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), + hps_0_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), + hps_0_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), + hps_0_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), + hps_0_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), + hps_0_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), + hps_0_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), + hps_0_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), + hps_0_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK, + hps_0_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI, + hps_0_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO, + hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS, + hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX, + hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX, + hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C0_SDAT, + hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C0_SCLK, + hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C1_SDAT, + hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C1_SCLK, + hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N, + hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N, + hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO, + hps_0_io_hps_io_gpio_inst_GPIO53 => HPS_LED, + hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N, + hps_0_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT, + pwm_0_conduit_end_pwm => SERVO_0, + pwm_1_conduit_end_pwm => SERVO_1, + mcp3204_0_conduit_end_cs_n => J0_SPI_CS_n, + mcp3204_0_conduit_end_mosi => J0_SPI_MOSI, + mcp3204_0_conduit_end_miso => J0_SPI_MISO, + mcp3204_0_conduit_end_sclk => J0_SPI_CLK, + lepton_0_spi_cs_n => CAM_TH_SPI_CS_N, + lepton_0_spi_mosi => CAM_TH_MOSI, + lepton_0_spi_miso => CAM_TH_MISO, + lepton_0_spi_sclk => CAM_TH_CLK, + pixclk_clk => VIDEO_CLK, + vga_hsync => VIDEO_HSYNC, + vga_vsync => VIDEO_VSYNC, + vga_r => VIDEO_R, + vga_g => VIDEO_G, + vga_b => VIDEO_B, + vga_de => LCD_DE + ); + + LCD_DISPLAY_EN <= '1'; + +end; diff --git a/cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/dc_video_fifo.vhd b/cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/dc_video_fifo.vhd new file mode 100644 index 0000000..4540905 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/dc_video_fifo.vhd @@ -0,0 +1,214 @@ +-- megafunction wizard: %FIFO% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo_mixed_widths + +-- ============================================================ +-- File Name: dc_video_fifo.vhd +-- Megafunction Name(s): +-- dcfifo_mixed_widths +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dc_video_fifo IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (95 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0) + ); +END dc_video_fifo; + + +ARCHITECTURE SYN OF dc_video_fifo IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (8 DOWNTO 0); + + + + COMPONENT dcfifo_mixed_widths + GENERIC ( + add_usedw_msb_bit : STRING; + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + lpm_widthu_r : NATURAL; + lpm_width_r : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + read_aclr_synch : STRING; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + aclr : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (95 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(23 DOWNTO 0); + rdempty <= sub_wire1; + wrusedw <= sub_wire2(8 DOWNTO 0); + + dcfifo_mixed_widths_component : dcfifo_mixed_widths + GENERIC MAP ( + add_usedw_msb_bit => "ON", + intended_device_family => "Cyclone V", + lpm_numwords => 256, + lpm_showahead => "ON", + lpm_type => "dcfifo_mixed_widths", + lpm_width => 96, + lpm_widthu => 9, + lpm_widthu_r => 11, + lpm_width_r => 24, + overflow_checking => "ON", + rdsync_delaypipe => 5, + read_aclr_synch => "OFF", + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 5 + ) + PORT MAP ( + aclr => aclr, + data => data, + rdclk => rdclk, + rdreq => rdreq, + wrclk => wrclk, + wrreq => wrreq, + q => sub_wire0, + rdempty => sub_wire1, + wrusedw => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "256" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "2" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "96" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "1" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "1" +-- Retrieval info: PRIVATE: output_width NUMERIC "24" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "96" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "11" +-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "24" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" +-- Retrieval info: USED_PORT: data 0 0 96 0 INPUT NODEFVAL "data[95..0]" +-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]" +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +-- Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]" +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 96 0 data 0 0 96 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0 +-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +-- Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL dc_video_fifo.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dc_video_fifo.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dc_video_fifo.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dc_video_fifo.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dc_video_fifo_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/framebuffer_manager.vhd b/cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/framebuffer_manager.vhd new file mode 100644 index 0000000..02c6bce --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/framebuffer_manager.vhd @@ -0,0 +1,363 @@ +------------------------------------------------------------------------------- +-- Title : Frame Buffer Manager +-- Project : From FPGA to Linux: An embedded system exploration +------------------------------------------------------------------------------- +-- File : framebuffer_manager.vhd +-- Author : Philemon Orphee Favrod +-- Company : +-- Created : 2016-03-10 +-- Last update: 2017-02-21 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: DMA-capable unit that manages reads to a framebuffer. +------------------------------------------------------------------------------- +-- Copyright (c) 2016 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2016-03-10 1.0 P. Favrod Created +-- 2016-04-25 1.1 P. Favrod Debuged +-- 2016-05-23 1.2 P. Favrod Increased bandwidth + fifo sync @ VFP +-- 2016-05-29 1.3 P. Favrod Added MSB to FIFO + removed wrfull +------------------------------------------------------------------------------- +-- Register Memory Mapping +-- +-------+--------+-----+-----+-----+-----+----+-----------+ +-- | Regno | Access | B31 | ... | B10 | ... | B1 | B0 | +-- +-------+--------+-----+-----+-----+-----+----+-----------+ +-- | 0 | R/W | FRAME_START_ADDRESS | +-- +-------+--------+----------------------------------------+ +-- | 1 | R/W | FRAME_PIXEL_PER_LINE | +-- +-------+--------+----------------------------------------+ +-- | 2 | R/W | FRAME_LINES_PER_FRAME | +-- +-------+--------+----------------------------------------+ +-- | 3 | R/W | FRAME_EOL_BYTE_OFFSET | +-- +-------+--------+----------------------------------------+ +-- | 4 | WO | COMMAND_REGISTER | +-- +-------+--------+---------------------------+------------+ +-- | 5 | R/W | | FB_BURST_COUNT | +-- +-------+--------+-----------+----------------------------+ +-- +-- Command register: +-- [0] Enable DMA loop +-- [1] Disable DMA loop +-- [2] Enable interrupts +-- [3] Disable interrupts +-- [4] Acknowledge IRQ +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity framebuffer_manager is + + port( + clk : in std_logic; + pixclk : in std_logic; + reset : in std_logic; + + -- Avalon-MM Slave Interface + as_address : in std_logic_vector(3 downto 0); + as_read : in std_logic; + as_readdata : out std_logic_vector(31 downto 0); + as_write : in std_logic; + as_writedata : in std_logic_vector(31 downto 0); + + -- Avalon-MM Master Interface + am_address : out std_logic_vector(31 downto 0); + am_waitrequest : in std_logic; + am_burstcount : out std_logic_vector(10 downto 0); + am_read : out std_logic; + am_readdata : in std_logic_vector(127 downto 0); + am_readdatavalid : in std_logic; + + frame_sync : in std_logic; + + -- Interrupt Sender Interface + irq : out std_logic; + + -- Avalon-ST Source Interface + src_data : out std_logic_vector(23 downto 0); + src_valid : out std_logic; + src_ready : in std_logic); +end framebuffer_manager; + +architecture rtl of framebuffer_manager is + + constant MAX_BURST_COUNT : integer := 1024; + + constant FRAME_START_ADDRESS_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(0, as_address'length)); + constant FRAME_PIXEL_PER_LINE_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(1, as_address'length)); + constant FRAME_LINES_PER_FRAME_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(2, as_address'length)); + constant FRAME_EOL_BYTE_OFFSET_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(3, as_address'length)); + constant FB_COMMAND_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(4, as_address'length)); + constant FB_BURST_COUNT_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(5, as_address'length)); + + signal start_address : integer; + signal current_address : integer; + signal pix_per_line, pix_per_line_copy : integer; + signal num_lines, num_lines_copy : integer; + signal eol_byte_offset, eol_byte_offset_copy : integer; + signal enabled : boolean; + signal burst_count, burst_count_copy : integer; + signal irq_enabled : boolean; + signal irq_acknowledged : boolean; + + signal burst_counter : integer range 1 to MAX_BURST_COUNT; + signal pix_counter : integer; + signal line_counter : integer; + + type state is (IDLE, MEMSTARTREAD, MEMRESTARTREAD, MEMREAD, FLUSHBURST, WAITSYNC); + signal current_state : state; + + constant INTERNAL_FIFO_DEPTH : integer := 256; + signal fifo_clr : std_logic; + signal fifo_data_in : std_logic_vector(95 downto 0); + signal fifo_data_out : std_logic_vector(23 downto 0); + signal fifo_read : std_logic; + signal fifo_write : std_logic; + signal fifo_usedw : std_logic_vector(8 downto 0); + signal fifo_freew : integer range 0 to INTERNAL_FIFO_DEPTH; + signal fifo_empty : std_logic; + signal fifo_large_enough : boolean; +begin + dc_video_fifo_inst : entity work.dc_video_fifo port map ( + aclr => fifo_clr, + data => fifo_data_in, + rdclk => pixclk, + rdreq => fifo_read, + wrclk => clk, + wrreq => fifo_write, + q => fifo_data_out, + rdempty => fifo_empty, + wrusedw => fifo_usedw); + + fifo_write <= am_readdatavalid and not fifo_clr when current_state = MEMREAD else '0'; + fifo_read <= src_ready and not fifo_empty; + fifo_clr <= '1' when current_state = IDLE else '0'; + fifo_freew <= INTERNAL_FIFO_DEPTH - to_integer(unsigned(fifo_usedw)); + fifo_large_enough <= fifo_freew >= burst_count_copy; + fifo_data_in <= am_readdata(119 downto 96) & am_readdata(87 downto 64) & am_readdata(55 downto 32) & am_readdata(23 downto 0); + + src_data <= fifo_data_out when fifo_empty = '0' else X"ff0000"; + src_valid <= not fifo_empty; + + p_as_write : process (clk, reset) + begin + if reset = '1' then + start_address <= 0; + pix_per_line <= 0; + num_lines <= 0; + eol_byte_offset <= 0; + burst_count <= 4; + enabled <= false; + irq_enabled <= false; + irq_acknowledged <= false; + + elsif rising_edge(clk) then + + irq_acknowledged <= false; + + if as_write = '1' then + case as_address is + when FRAME_START_ADDRESS_REGNO => + start_address <= to_integer(unsigned(as_writedata)); + + when FRAME_PIXEL_PER_LINE_REGNO => + pix_per_line <= to_integer(unsigned(as_writedata)); + + when FRAME_LINES_PER_FRAME_REGNO => + num_lines <= to_integer(unsigned(as_writedata)); + + when FRAME_EOL_BYTE_OFFSET_REGNO => + eol_byte_offset <= to_integer(unsigned(as_writedata)); + + when FB_COMMAND_REGNO => + if as_writedata(0) = '1' then + enabled <= true; + end if; + + if as_writedata(1) = '1' then + enabled <= false; + end if; + + if as_writedata(2) = '1' then + irq_enabled <= true; + end if; + + if as_writedata(3) = '1' then + irq_enabled <= false; + end if; + + if as_writedata(4) = '1' then + irq_acknowledged <= true; + end if; + + when FB_BURST_COUNT_REGNO => + if unsigned(as_writedata) > MAX_BURST_COUNT then + burst_count <= MAX_BURST_COUNT; + else + burst_count <= to_integer(unsigned(as_writedata)); + end if; + + when others => null; + end case; + end if; + + end if; + end process p_as_write; + + p_as_read : process (clk, reset) + begin + if reset = '1' then + as_readdata <= (others => '0'); + + elsif rising_edge(clk) then + + as_readdata <= (others => '0'); + + if as_read = '1' then + case as_address is + when FRAME_START_ADDRESS_REGNO => + as_readdata <= std_logic_vector(to_unsigned(start_address, as_readdata'length)); + + when FRAME_PIXEL_PER_LINE_REGNO => + as_readdata <= std_logic_vector(to_unsigned(pix_per_line, as_readdata'length)); + + when FRAME_LINES_PER_FRAME_REGNO => + as_readdata <= std_logic_vector(to_unsigned(num_lines, as_readdata'length)); + + when FRAME_EOL_BYTE_OFFSET_REGNO => + as_readdata <= std_logic_vector(to_unsigned(eol_byte_offset, as_readdata'length)); + + when FB_BURST_COUNT_REGNO => + as_readdata <= std_logic_vector(to_unsigned(burst_count, as_readdata'length)); + + when others => null; + end case; + end if; + + end if; + end process p_as_read; + + + p_fsm : process (clk, reset) + begin + if reset = '1' then + + current_address <= 0; + pix_per_line_copy <= 0; + num_lines_copy <= 0; + eol_byte_offset_copy <= 0; + burst_count_copy <= 0; + + burst_counter <= 1; + pix_counter <= 0; + line_counter <= 0; + + current_state <= IDLE; + + elsif rising_edge(clk) then + -- If the interrupts have been disabled or acknowledged + -- we deassert the interrupt request line. + if not irq_enabled or irq_acknowledged then + irq <= '0'; + end if; + + case current_state is + when IDLE => + -- In IDLE state, wait for enabled to be high Then, save a copy of registers + -- in shadow registers and start reading memory. + if enabled then + current_address <= start_address; + pix_per_line_copy <= pix_per_line; + num_lines_copy <= num_lines; + eol_byte_offset_copy <= eol_byte_offset; + burst_count_copy <= burst_count; + current_state <= MEMSTARTREAD; + + pix_counter <= 4 * burst_count; -- so that when pix_counter = + -- pix_per_line_copy we are done + line_counter <= 1; + end if; + + -- wait state for the DC fifo signal to be updated + when MEMRESTARTREAD => + current_state <= MEMSTARTREAD; + + when MEMSTARTREAD => + -- If there is room for a full burst in the FIFO and + -- no wait request on the bus, we start reading! + if fifo_large_enough and am_waitrequest = '0' then + burst_counter <= 1; + current_state <= MEMREAD; + end if; + + when MEMREAD => + -- If a valid data is received + if am_readdatavalid = '1' then + + -- If in the middle of a burst, increment the burst counter + if burst_counter < burst_count_copy then + burst_counter <= burst_counter + 1; + else + + -- If in the middle of a line, increment the pixel counter and the + -- address accordingly + if pix_counter < pix_per_line_copy then + pix_counter <= pix_counter + 4 * burst_count_copy; + current_address <= current_address + 16 * burst_count_copy; + current_state <= MEMRESTARTREAD; + + -- If at the end of a line, increment the line counter and the + -- address accordingly. Reset pix_counter too! + elsif line_counter < num_lines_copy then + line_counter <= line_counter + 1; + pix_counter <= 4 * burst_count_copy; + current_address <= current_address + 16 * burst_count_copy + eol_byte_offset_copy; + current_state <= MEMRESTARTREAD; + + -- If at the end of a frame, go back to WAITSYNC until blanking + else + current_state <= WAITSYNC; + + -- End of frame => IRQ! + if irq_enabled then + irq <= '1'; + end if; + + end if; + + + end if; + + end if; + + if frame_sync = '1' then + current_state <= FLUSHBURST; + end if; + + when FLUSHBURST => + if burst_counter = burst_count_copy then + current_state <= IDLE; + + elsif am_readdatavalid = '1' then + burst_counter <= burst_counter + 1; + end if; + + when WAITSYNC => + -- Wait for vertical blanking to occur to avoid filling the FIFO + -- just before it is cleared! + if frame_sync = '1' then + current_state <= IDLE; + end if; + + when others => null; + end case; + end if; + end process p_fsm; + + am_address <= std_logic_vector(to_unsigned(current_address, am_address'length)); + am_read <= '1' when fifo_large_enough and current_state = MEMSTARTREAD else '0'; + am_burstcount <= std_logic_vector(to_unsigned(burst_count_copy, am_burstcount'length)); +end architecture; diff --git a/cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/framebuffer_manager_hw.tcl b/cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/framebuffer_manager_hw.tcl new file mode 100644 index 0000000..77f83d5 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/framebuffer_manager_hw.tcl @@ -0,0 +1,233 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 18:18:01 CET 2017 +# DO NOT MODIFY + + +# +# framebuffer_manager "framebuffer_manager" v1.0 +# 2017.02.05.18:18:01 +# +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module framebuffer_manager +# +set_module_property DESCRIPTION "" +set_module_property NAME framebuffer_manager +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP LCD +set_module_property AUTHOR "Philemon Favrod" +set_module_property DISPLAY_NAME framebuffer_manager +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL framebuffer_manager +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file framebuffer_manager.vhd VHDL PATH framebuffer_manager.vhd TOP_LEVEL_FILE +add_fileset_file dc_video_fifo.vhd VHDL PATH dc_video_fifo.vhd + + +# +# parameters +# + + +# +# module assignments +# +set_module_assignment embeddedsw.dts.compatible prsoc,framebuffer-manager +set_module_assignment embeddedsw.dts.group any +set_module_assignment embeddedsw.dts.vendor prsoc + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point interrupt_sender +# +add_interface interrupt_sender interrupt end +set_interface_property interrupt_sender associatedAddressablePoint "" +set_interface_property interrupt_sender associatedClock clock +set_interface_property interrupt_sender associatedReset reset +set_interface_property interrupt_sender bridgedReceiverOffset "" +set_interface_property interrupt_sender bridgesToReceiver "" +set_interface_property interrupt_sender ENABLED true +set_interface_property interrupt_sender EXPORT_OF "" +set_interface_property interrupt_sender PORT_NAME_MAP "" +set_interface_property interrupt_sender CMSIS_SVD_VARIABLES "" +set_interface_property interrupt_sender SVD_ADDRESS_GROUP "" + +add_interface_port interrupt_sender irq irq Output 1 + + +# +# connection point csr +# +add_interface csr avalon end +set_interface_property csr addressUnits WORDS +set_interface_property csr associatedClock clock +set_interface_property csr associatedReset reset +set_interface_property csr bitsPerSymbol 8 +set_interface_property csr burstOnBurstBoundariesOnly false +set_interface_property csr burstcountUnits WORDS +set_interface_property csr explicitAddressSpan 0 +set_interface_property csr holdTime 0 +set_interface_property csr linewrapBursts false +set_interface_property csr maximumPendingReadTransactions 0 +set_interface_property csr maximumPendingWriteTransactions 0 +set_interface_property csr readLatency 0 +set_interface_property csr readWaitTime 1 +set_interface_property csr setupTime 0 +set_interface_property csr timingUnits Cycles +set_interface_property csr writeWaitTime 0 +set_interface_property csr ENABLED true +set_interface_property csr EXPORT_OF "" +set_interface_property csr PORT_NAME_MAP "" +set_interface_property csr CMSIS_SVD_VARIABLES "" +set_interface_property csr SVD_ADDRESS_GROUP "" + +add_interface_port csr as_address address Input 4 +add_interface_port csr as_read read Input 1 +add_interface_port csr as_readdata readdata Output 32 +add_interface_port csr as_write write Input 1 +add_interface_port csr as_writedata writedata Input 32 +set_interface_assignment csr embeddedsw.configuration.isFlash 0 +set_interface_assignment csr embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment csr embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment csr embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point dma +# +add_interface dma avalon start +set_interface_property dma addressUnits SYMBOLS +set_interface_property dma associatedClock clock +set_interface_property dma associatedReset reset +set_interface_property dma bitsPerSymbol 8 +set_interface_property dma burstOnBurstBoundariesOnly false +set_interface_property dma burstcountUnits WORDS +set_interface_property dma doStreamReads false +set_interface_property dma doStreamWrites false +set_interface_property dma holdTime 0 +set_interface_property dma linewrapBursts false +set_interface_property dma maximumPendingReadTransactions 0 +set_interface_property dma maximumPendingWriteTransactions 0 +set_interface_property dma readLatency 0 +set_interface_property dma readWaitTime 1 +set_interface_property dma setupTime 0 +set_interface_property dma timingUnits Cycles +set_interface_property dma writeWaitTime 0 +set_interface_property dma ENABLED true +set_interface_property dma EXPORT_OF "" +set_interface_property dma PORT_NAME_MAP "" +set_interface_property dma CMSIS_SVD_VARIABLES "" +set_interface_property dma SVD_ADDRESS_GROUP "" + +add_interface_port dma am_address address Output 32 +add_interface_port dma am_burstcount burstcount Output 11 +add_interface_port dma am_read read Output 1 +add_interface_port dma am_readdata readdata Input 128 +add_interface_port dma am_readdatavalid readdatavalid Input 1 +add_interface_port dma am_waitrequest waitrequest Input 1 + + +# +# connection point video_out +# +add_interface video_out avalon_streaming start +set_interface_property video_out associatedClock pixclk +set_interface_property video_out associatedReset reset +set_interface_property video_out dataBitsPerSymbol 24 +set_interface_property video_out errorDescriptor "" +set_interface_property video_out firstSymbolInHighOrderBits true +set_interface_property video_out maxChannel 0 +set_interface_property video_out readyLatency 0 +set_interface_property video_out ENABLED true +set_interface_property video_out EXPORT_OF "" +set_interface_property video_out PORT_NAME_MAP "" +set_interface_property video_out CMSIS_SVD_VARIABLES "" +set_interface_property video_out SVD_ADDRESS_GROUP "" + +add_interface_port video_out src_data data Output 24 +add_interface_port video_out src_valid valid Output 1 +add_interface_port video_out src_ready ready Input 1 + + +# +# connection point sync +# +add_interface sync conduit end +set_interface_property sync associatedClock clock +set_interface_property sync associatedReset "" +set_interface_property sync ENABLED true +set_interface_property sync EXPORT_OF "" +set_interface_property sync PORT_NAME_MAP "" +set_interface_property sync CMSIS_SVD_VARIABLES "" +set_interface_property sync SVD_ADDRESS_GROUP "" + +add_interface_port sync frame_sync frame_sync Input 1 + + +# +# connection point pixclk +# +add_interface pixclk clock end +set_interface_property pixclk clockRate 0 +set_interface_property pixclk ENABLED true +set_interface_property pixclk EXPORT_OF "" +set_interface_property pixclk PORT_NAME_MAP "" +set_interface_property pixclk CMSIS_SVD_VARIABLES "" +set_interface_property pixclk SVD_ADDRESS_GROUP "" + +add_interface_port pixclk pixclk clk Input 1 + diff --git a/cs309-psoc/lab_4_0/hw/hdl/displays/vga_sequencer/hdl/vga_sequencer.vhd b/cs309-psoc/lab_4_0/hw/hdl/displays/vga_sequencer/hdl/vga_sequencer.vhd new file mode 100644 index 0000000..6162ca3 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/displays/vga_sequencer/hdl/vga_sequencer.vhd @@ -0,0 +1,358 @@ + +--+--------+------------+-------------------------------------------------------------------+ +--| Offset | Name | Description | +--+--------+------------+-------------------------------------------------------------------+ +--| 0x0 | CSR | [0] Enable/Disable | +--| 0x1 | HBP | [15..0] Horizontal Back Porch (in DCLK) | +--| 0x2 | HFP | [15..0] Horizontal Front Porch (in DCLK) | +--| 0x3 | VBP | [15..0] Vertical Back Porch (in # lines) | +--| 0x4 | VFP | [15..0] Vertical Front Porch (in # lines) | +--| 0x5 | HDATA | [15..0] Horizontal data (in DCLK) | +--| 0x6 | VDATA | [15..0] [15..0] Vertical data (in # lines) | +--| 0x7 | HSync | [15..0] HSync width (in DCLK) | +--| 0x8 | Vsync | [15..0] VSync width (in # lines) | +--+--------+------------+-------------------------------------------------------------------+ +-- +-- As usual, the horizontal timings are specified in number of data clock +-- cycles, and the vertical timings are specified in number of lines. +-- +-- For naming conventions, please refer to the following diagram: +-- +----------------------------------------------------------------------------------------------+----- +-- | A | B | C | D | ... +-- +----------------------------------------------------------------------------------------------+----- +-- --+ +------------------------------------------------------------------------------------------+ +- +-- | | | | +-- +---+ +---+ +-- +-- A is the pulse width +-- B is the back porch +-- C is the valid data +-- D is the front porch + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vga_sequencer is + generic ( + HBP_DEFAULT : positive := 12; + HFP_DEFAULT : positive := 18; + VBP_DEFAULT : positive := 8; + VFP_DEFAULT : positive := 20; + HDATA_DEFAULT : positive := 240; + VDATA_DEFAULT : positive := 320; + HSYNC_DEFAULT : positive := 2; + VSYNC_DEFAULT : positive := 7); + port ( + pixclk : in std_logic; -- A copy of the pixclk from the PLL + clk : in std_logic; -- The clock of the bus + reset : in std_logic; + + -- Avalon-MM CSR Interface + address : in std_logic_vector(4 downto 0); + read, write : in std_logic; + readdata : out std_logic_vector(31 downto 0); + writedata : in std_logic_vector(31 downto 0); + + -- Avalon-ST sink Interface + sink_data : in std_logic_vector(23 downto 0); + sink_valid : in std_logic; + sink_ready : out std_logic; + + -- TFT Interface + r : out std_logic_vector(7 downto 0); + g : out std_logic_vector(7 downto 0); + b : out std_logic_vector(7 downto 0); + hsync : out std_logic; + vsync : out std_logic; + de : out std_logic; + + -- Indicates when we enter the front porch of the vertical sync. + -- Used to flush the FIFO and restart reading the frame in memory. + frame_sync : out std_logic); +end entity vga_sequencer; + +architecture rtl of vga_sequencer is + + -- Both counters should be able to count up to the addition of any four 16-bit numbers. + signal horizontal_counter, horizontal_max : unsigned(19 downto 0); + constant HORIZONTAL_COUNTER_RESET : unsigned(horizontal_counter'range) := to_unsigned(1, horizontal_counter'length); + signal vertical_counter, vertical_max : unsigned(19 downto 0); + constant VERTICAL_COUNTER_RESET : unsigned(horizontal_counter'range) := to_unsigned(1, horizontal_counter'length); + + -- Registers + signal hbp, hfp, vbp, vfp, hdata_width, vdata_width, hsync_width, vsync_width : unsigned(15 downto 0); + + signal enabled : boolean; + + -- Output registers + signal i_r : std_logic_vector(7 downto 0); + signal i_g : std_logic_vector(7 downto 0); + signal i_b : std_logic_vector(7 downto 0); + signal i_hsync : std_logic; + signal i_vsync : std_logic; + signal i_de : std_logic; + + -- couting becomes true whenever enabled is true and sink_valid='1' + signal counting : boolean; + + constant CSR_REG_OFST : unsigned(address'range) := to_unsigned(0, address'length); + constant HBP_REG_OFST : unsigned(address'range) := to_unsigned(1, address'length); + constant HFP_REG_OFST : unsigned(address'range) := to_unsigned(2, address'length); + constant VBP_REG_OFST : unsigned(address'range) := to_unsigned(3, address'length); + constant VFP_REG_OFST : unsigned(address'range) := to_unsigned(4, address'length); + constant HDATA_REG_OFST : unsigned(address'range) := to_unsigned(5, address'length); + constant VDATA_REG_OFST : unsigned(address'range) := to_unsigned(6, address'length); + constant HSYNC_REG_OFST : unsigned(address'range) := to_unsigned(7, address'length); + constant VSYNC_REG_OFST : unsigned(address'range) := to_unsigned(8, address'length); +begin + + p_csr_write : process (clk, reset) + begin + if reset = '1' then + enabled <= false; + hbp <= to_unsigned(HBP_DEFAULT, hbp'length); + hfp <= to_unsigned(HFP_DEFAULT, hfp'length); + vbp <= to_unsigned(VBP_DEFAULT, vbp'length); + vfp <= to_unsigned(VFP_DEFAULT, vfp'length); + hdata_width <= to_unsigned(HDATA_DEFAULT, hdata_width'length); + vdata_width <= to_unsigned(VDATA_DEFAULT, vdata_width'length); + hsync_width <= to_unsigned(HSYNC_DEFAULT, hsync_width'length); + vsync_width <= to_unsigned(VSYNC_DEFAULT, vsync_width'length); + + elsif rising_edge(clk) then + if write = '1' then + case unsigned(address) is + -- Status + when CSR_REG_OFST => + if writedata(0) = '1' then + enabled <= true; + else + enabled <= false; + end if; + + -- HBP + when HBP_REG_OFST => + hbp <= unsigned(writedata(15 downto 0)); + + -- HFP + when HFP_REG_OFST => + hfp <= unsigned(writedata(15 downto 0)); + + -- VBP + when VBP_REG_OFST => + vbp <= unsigned(writedata(15 downto 0)); + + -- VFP + when VFP_REG_OFST => + vfp <= unsigned(writedata(15 downto 0)); + + -- HDATA + when HDATA_REG_OFST => + hdata_width <= unsigned(writedata(15 downto 0)); + + -- VDATA + when VDATA_REG_OFST => + vdata_width <= unsigned(writedata(15 downto 0)); + + -- HSYNC + when HSYNC_REG_OFST => + hsync_width <= unsigned(writedata(15 downto 0)); + + -- VSYNC + when VSYNC_REG_OFST => + vsync_width <= unsigned(writedata(15 downto 0)); + + + when others => null; + end case; + end if; + end if; + end process p_csr_write; + + p_csr_read : process (clk, reset) + begin + if reset = '1' then + readdata <= (others => '0'); + elsif rising_edge(clk) then + readdata <= (others => '0'); + if read = '1' then + case unsigned(address) is + -- Status + when CSR_REG_OFST => + readdata <= (others => '0'); + if enabled then + readdata(0) <= '1'; + end if; + + -- HBP + when HBP_REG_OFST => + readdata(15 downto 0) <= std_logic_vector(hbp); + + -- HFP + when HFP_REG_OFST => + readdata(15 downto 0) <= std_logic_vector(hfp); + + -- VBP + when VBP_REG_OFST => + readdata(15 downto 0) <= std_logic_vector(vbp); + + -- VFP + when VFP_REG_OFST => + readdata(15 downto 0) <= std_logic_vector(vfp); + + -- HDATA + when HDATA_REG_OFST => + readdata(15 downto 0) <= std_logic_vector(hdata_width); + + -- VDATA + when VDATA_REG_OFST => + readdata(15 downto 0) <= std_logic_vector(vdata_width); + + -- HSYNC + when HSYNC_REG_OFST => + readdata(15 downto 0) <= std_logic_vector(hsync_width); + + -- VSYNC + when VSYNC_REG_OFST => + readdata(15 downto 0) <= std_logic_vector(vsync_width); + + when others => null; + end case; + end if; + end if; + end process p_csr_read; + + horizontal_max <= + resize(hsync_width, horizontal_max 'length) + + resize(hbp, horizontal_max'length) + + resize(hdata_width, horizontal_max'length) + + resize(hfp, horizontal_max'length); + + vertical_max <= + resize(vsync_width, horizontal_max 'length) + + resize(vbp, horizontal_max'length) + + resize(vdata_width, horizontal_max'length) + + resize(vfp, horizontal_max'length); + + p_cnt_trigger : process (pixclk, reset) + begin + if reset = '1' then + counting <= false; + elsif rising_edge(pixclk) then + + if enabled and sink_valid = '1' then + counting <= true; + + elsif not enabled then + counting <= false; + end if; + + end if; + end process p_cnt_trigger; + + p_horizontal_count : process (pixclk, reset) + begin + if reset = '1' then + horizontal_counter <= HORIZONTAL_COUNTER_RESET; + elsif rising_edge(pixclk) then + horizontal_counter <= HORIZONTAL_COUNTER_RESET; + if counting and horizontal_counter < horizontal_max then + horizontal_counter <= horizontal_counter + 1; + end if; + end if; + end process p_horizontal_count; + + p_vertical_count : process (pixclk, reset) + begin + if reset = '1' then + vertical_counter <= VERTICAL_COUNTER_RESET; + elsif rising_edge(pixclk) then + if counting then + if horizontal_counter = horizontal_max then + if vertical_counter < vertical_max then + vertical_counter <= vertical_counter + 1; + else + vertical_counter <= VERTICAL_COUNTER_RESET; + end if; + end if; + else + vertical_counter <= VERTICAL_COUNTER_RESET; + end if; + end if; + end process p_vertical_count; + + p_hsync_vsync_gen : process (counting, horizontal_counter, hsync_width, + vertical_counter, vsync_width) + begin + -- HSYNC generation + i_hsync <= '1'; + if horizontal_counter <= hsync_width then + i_hsync <= '0'; + end if; + + -- VSYNC generation + i_vsync <= '1'; + if vertical_counter <= vsync_width then + i_vsync <= '0'; + end if; + + if not counting then + i_vsync <= '1'; + i_hsync <= '1'; + end if; + + end process p_hsync_vsync_gen; + + p_rgb_out : process (hbp, hdata_width, horizontal_counter, hsync_width, + sink_data, vbp, vdata_width, vertical_counter, + vsync_width) + begin + i_r <= (others => '0'); + i_g <= (others => '0'); + i_b <= (others => '0'); + i_de <= '0'; + sink_ready <= '0'; + frame_sync <= '0'; + + if + vertical_counter > (resize(vsync_width, vertical_counter'length) + resize(vbp, vertical_counter'length)) and + vertical_counter <= (resize(vsync_width, vertical_counter'length) + resize(vbp, vertical_counter'length) + resize(vdata_width, vertical_counter'length)) and + horizontal_counter > (resize(hsync_width, horizontal_counter'length) + resize(hbp, horizontal_counter'length)) and + horizontal_counter <= (resize(hsync_width, horizontal_counter'length) + resize(hbp, horizontal_counter'length) + resize(hdata_width, horizontal_counter'length)) + then + i_de <= '1'; + i_r <= sink_data(23 downto 16); + i_g <= sink_data(15 downto 8); + i_b <= sink_data(7 downto 0); + sink_ready <= '1'; + end if; + + if + vertical_counter > (resize(vsync_width, vertical_counter'length) + resize(vbp, vertical_counter'length) + resize(vdata_width, vertical_counter'length)) + then + frame_sync <= '1'; + end if; + + end process p_rgb_out; + + p_output_reg : process (pixclk, reset) + begin + if reset = '1' then + r <= (others => '0'); + g <= (others => '0'); + b <= (others => '0'); + de <= '0'; + hsync <= '1'; + vsync <= '1'; + elsif rising_edge(pixclk) then + de <= i_de; + r <= i_r; + g <= i_g; + b <= i_b; + vsync <= i_vsync; + hsync <= i_hsync; + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_4_0/hw/hdl/displays/vga_sequencer/hdl/vga_sequencer_hw.tcl b/cs309-psoc/lab_4_0/hw/hdl/displays/vga_sequencer/hdl/vga_sequencer_hw.tcl new file mode 100644 index 0000000..7822e40 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/displays/vga_sequencer/hdl/vga_sequencer_hw.tcl @@ -0,0 +1,247 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 18:18:28 CET 2017 +# DO NOT MODIFY + + +# +# vga_sequencer "vga_sequencer" v1.0 +# 2017.02.05.18:18:28 +# +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module vga_sequencer +# +set_module_property DESCRIPTION "" +set_module_property NAME vga_sequencer +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP LCD +set_module_property AUTHOR "Philemon Favrod" +set_module_property DISPLAY_NAME vga_sequencer +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL vga_sequencer +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file vga_sequencer.vhd VHDL PATH vga_sequencer.vhd TOP_LEVEL_FILE + + +# +# parameters +# +add_parameter HBP_DEFAULT POSITIVE 12 +set_parameter_property HBP_DEFAULT DEFAULT_VALUE 12 +set_parameter_property HBP_DEFAULT DISPLAY_NAME HBP_DEFAULT +set_parameter_property HBP_DEFAULT TYPE POSITIVE +set_parameter_property HBP_DEFAULT UNITS None +set_parameter_property HBP_DEFAULT ALLOWED_RANGES 1:2147483647 +set_parameter_property HBP_DEFAULT HDL_PARAMETER true +add_parameter HFP_DEFAULT POSITIVE 18 +set_parameter_property HFP_DEFAULT DEFAULT_VALUE 18 +set_parameter_property HFP_DEFAULT DISPLAY_NAME HFP_DEFAULT +set_parameter_property HFP_DEFAULT TYPE POSITIVE +set_parameter_property HFP_DEFAULT UNITS None +set_parameter_property HFP_DEFAULT ALLOWED_RANGES 1:2147483647 +set_parameter_property HFP_DEFAULT HDL_PARAMETER true +add_parameter VBP_DEFAULT POSITIVE 8 +set_parameter_property VBP_DEFAULT DEFAULT_VALUE 8 +set_parameter_property VBP_DEFAULT DISPLAY_NAME VBP_DEFAULT +set_parameter_property VBP_DEFAULT TYPE POSITIVE +set_parameter_property VBP_DEFAULT UNITS None +set_parameter_property VBP_DEFAULT ALLOWED_RANGES 1:2147483647 +set_parameter_property VBP_DEFAULT HDL_PARAMETER true +add_parameter VFP_DEFAULT POSITIVE 20 +set_parameter_property VFP_DEFAULT DEFAULT_VALUE 20 +set_parameter_property VFP_DEFAULT DISPLAY_NAME VFP_DEFAULT +set_parameter_property VFP_DEFAULT TYPE POSITIVE +set_parameter_property VFP_DEFAULT UNITS None +set_parameter_property VFP_DEFAULT ALLOWED_RANGES 1:2147483647 +set_parameter_property VFP_DEFAULT HDL_PARAMETER true +add_parameter HDATA_DEFAULT POSITIVE 240 +set_parameter_property HDATA_DEFAULT DEFAULT_VALUE 240 +set_parameter_property HDATA_DEFAULT DISPLAY_NAME HDATA_DEFAULT +set_parameter_property HDATA_DEFAULT TYPE POSITIVE +set_parameter_property HDATA_DEFAULT UNITS None +set_parameter_property HDATA_DEFAULT ALLOWED_RANGES 1:2147483647 +set_parameter_property HDATA_DEFAULT HDL_PARAMETER true +add_parameter VDATA_DEFAULT POSITIVE 320 +set_parameter_property VDATA_DEFAULT DEFAULT_VALUE 320 +set_parameter_property VDATA_DEFAULT DISPLAY_NAME VDATA_DEFAULT +set_parameter_property VDATA_DEFAULT TYPE POSITIVE +set_parameter_property VDATA_DEFAULT UNITS None +set_parameter_property VDATA_DEFAULT ALLOWED_RANGES 1:2147483647 +set_parameter_property VDATA_DEFAULT HDL_PARAMETER true +add_parameter HSYNC_DEFAULT POSITIVE 2 +set_parameter_property HSYNC_DEFAULT DEFAULT_VALUE 2 +set_parameter_property HSYNC_DEFAULT DISPLAY_NAME HSYNC_DEFAULT +set_parameter_property HSYNC_DEFAULT TYPE POSITIVE +set_parameter_property HSYNC_DEFAULT UNITS None +set_parameter_property HSYNC_DEFAULT ALLOWED_RANGES 1:2147483647 +set_parameter_property HSYNC_DEFAULT HDL_PARAMETER true +add_parameter VSYNC_DEFAULT POSITIVE 7 +set_parameter_property VSYNC_DEFAULT DEFAULT_VALUE 7 +set_parameter_property VSYNC_DEFAULT DISPLAY_NAME VSYNC_DEFAULT +set_parameter_property VSYNC_DEFAULT TYPE POSITIVE +set_parameter_property VSYNC_DEFAULT UNITS None +set_parameter_property VSYNC_DEFAULT ALLOWED_RANGES 1:2147483647 +set_parameter_property VSYNC_DEFAULT HDL_PARAMETER true + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point csr +# +add_interface csr avalon end +set_interface_property csr addressUnits WORDS +set_interface_property csr associatedClock clock +set_interface_property csr associatedReset reset +set_interface_property csr bitsPerSymbol 8 +set_interface_property csr burstOnBurstBoundariesOnly false +set_interface_property csr burstcountUnits WORDS +set_interface_property csr explicitAddressSpan 0 +set_interface_property csr holdTime 0 +set_interface_property csr linewrapBursts false +set_interface_property csr maximumPendingReadTransactions 0 +set_interface_property csr maximumPendingWriteTransactions 0 +set_interface_property csr readLatency 0 +set_interface_property csr readWaitTime 1 +set_interface_property csr setupTime 0 +set_interface_property csr timingUnits Cycles +set_interface_property csr writeWaitTime 0 +set_interface_property csr ENABLED true +set_interface_property csr EXPORT_OF "" +set_interface_property csr PORT_NAME_MAP "" +set_interface_property csr CMSIS_SVD_VARIABLES "" +set_interface_property csr SVD_ADDRESS_GROUP "" + +add_interface_port csr address address Input 5 +add_interface_port csr read read Input 1 +add_interface_port csr write write Input 1 +add_interface_port csr readdata readdata Output 32 +add_interface_port csr writedata writedata Input 32 +set_interface_assignment csr embeddedsw.configuration.isFlash 0 +set_interface_assignment csr embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment csr embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment csr embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point out +# +add_interface out conduit end +set_interface_property out associatedClock clock +set_interface_property out associatedReset "" +set_interface_property out ENABLED true +set_interface_property out EXPORT_OF "" +set_interface_property out PORT_NAME_MAP "" +set_interface_property out CMSIS_SVD_VARIABLES "" +set_interface_property out SVD_ADDRESS_GROUP "" + +add_interface_port out hsync hsync Output 1 +add_interface_port out g g Output 8 +add_interface_port out b b Output 8 +add_interface_port out de de Output 1 +add_interface_port out vsync vsync Output 1 +add_interface_port out r r Output 8 + + +# +# connection point in +# +add_interface in avalon_streaming end +set_interface_property in associatedClock pixclk +set_interface_property in associatedReset reset +set_interface_property in dataBitsPerSymbol 24 +set_interface_property in errorDescriptor "" +set_interface_property in firstSymbolInHighOrderBits true +set_interface_property in maxChannel 0 +set_interface_property in readyLatency 0 +set_interface_property in ENABLED true +set_interface_property in EXPORT_OF "" +set_interface_property in PORT_NAME_MAP "" +set_interface_property in CMSIS_SVD_VARIABLES "" +set_interface_property in SVD_ADDRESS_GROUP "" + +add_interface_port in sink_ready ready Output 1 +add_interface_port in sink_valid valid Input 1 +add_interface_port in sink_data data Input 24 + + +# +# connection point pixclk +# +add_interface pixclk clock end +set_interface_property pixclk clockRate 0 +set_interface_property pixclk ENABLED true +set_interface_property pixclk EXPORT_OF "" +set_interface_property pixclk PORT_NAME_MAP "" +set_interface_property pixclk CMSIS_SVD_VARIABLES "" +set_interface_property pixclk SVD_ADDRESS_GROUP "" + +add_interface_port pixclk pixclk clk Input 1 + + +# +# connection point frame_sync +# +add_interface frame_sync conduit end +set_interface_property frame_sync associatedClock clock +set_interface_property frame_sync associatedReset "" +set_interface_property frame_sync ENABLED true +set_interface_property frame_sync EXPORT_OF "" +set_interface_property frame_sync PORT_NAME_MAP "" +set_interface_property frame_sync CMSIS_SVD_VARIABLES "" +set_interface_property frame_sync SVD_ADDRESS_GROUP "" + +add_interface_port frame_sync frame_sync frame_sync Output 1 + diff --git a/cs309-psoc/lab_4_0/hw/hdl/joysticks/hdl/mcp3204.vhd b/cs309-psoc/lab_4_0/hw/hdl/joysticks/hdl/mcp3204.vhd new file mode 100644 index 0000000..af0aafb --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/joysticks/hdl/mcp3204.vhd @@ -0,0 +1,138 @@ +-- ############################################################################# +-- mcp3204.vhd +-- =========== +-- MCP3204 Avalon-MM slave interface. +-- +-- Register map +-- +-------+-----------+--------+------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +-------+-----------+--------+------------------------------------+ +-- | 0 | CHANNEL_0 | RO | 12-bit digital value of channel 0. | +-- +-------+-----------+--------+------------------------------------+ +-- | 1 | CHANNEL_1 | RO | 12-bit digital value of channel 1. | +-- +-------+-----------+--------+------------------------------------+ +-- | 2 | CHANNEL_2 | RO | 12-bit digital value of channel 2. | +-- +-------+-----------+--------+------------------------------------+ +-- | 3 | CHANNEL_3 | RO | 12-bit digital value of channel 3. | +-- +-------+-----------+--------+------------------------------------+ +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity mcp3204 is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + readdata : out std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic; + SCLK : out std_logic + ); +end entity; + +architecture arch of mcp3204 is + constant NUM_CHANNELS : positive := 4; + constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS)))); + + type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range); + signal data_reg : data_array; + + signal spi_busy, spi_start, spi_datavalid : std_logic; + signal spi_channel : std_logic_vector(1 downto 0); + signal spi_data : std_logic_vector(11 downto 0); + + type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA); + signal state : state_t; + + signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0); + +begin + SPI : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => spi_busy, + start => spi_start, + channel => spi_channel, + data_valid => spi_datavalid, + data => spi_data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + -- FSM that dictates which channel is being read. The state of the component + -- should be thought as the pair (state, channel) + p_fsm : process(reset, clk) + begin + if reset = '1' then + state <= READY; + channel <= (others => '0'); + elsif rising_edge(clk) then + case state is + when READY => + if spi_busy = '0' then + state <= INIT_READ_CHANNEL; + end if; + + when INIT_READ_CHANNEL => + state <= WAIT_FOR_DATA; + + when WAIT_FOR_DATA => + if spi_datavalid = '1' then + state <= READY; + channel <= channel + 1; + end if; + end case; + end if; + end process p_fsm; + + -- Updates the internal registers when a new data is available + p_data : process(reset, clk) + begin + if reset = '1' then + for i in 0 to NUM_CHANNELS - 1 loop + data_reg(i) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + if state = WAIT_FOR_DATA and spi_datavalid = '1' then + data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data; + end if; + end if; + end process p_data; + + spi_start <= '1' when state = INIT_READ_CHANNEL else '0'; + spi_channel <= std_logic_vector(channel); + + -- Interface with the Avalon Switch Fabric + p_avalon_read : process(reset, clk) + begin + if reset = '1' then + readdata <= (others => '0'); + elsif rising_edge(clk) then + if read = '1' then + readdata <= data_reg(to_integer(unsigned(address))); + end if; + end if; + end process p_avalon_read; + +end architecture; diff --git a/cs309-psoc/lab_4_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl b/cs309-psoc/lab_4_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl new file mode 100644 index 0000000..757514d --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl @@ -0,0 +1,137 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 18:14:06 CET 2017 +# DO NOT MODIFY + + +# +# mcp3204 "mcp3204" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.18:14:06 +# 4-Channel 12-Bit A/D Converter with SPI Serial Interface +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module mcp3204 +# +set_module_property DESCRIPTION "4-Channel 12-Bit A/D Converter with SPI Serial Interface" +set_module_property NAME mcp3204 +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Joystick +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME mcp3204 +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL mcp3204 +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file mcp3204.vhd VHDL PATH mcp3204.vhd TOP_LEVEL_FILE +add_fileset_file mcp3204_spi.vhd VHDL PATH mcp3204_spi.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end CS_N cs_n Output 1 +add_interface_port conduit_end MOSI mosi Output 1 +add_interface_port conduit_end MISO miso Input 1 +add_interface_port conduit_end SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_4_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd b/cs309-psoc/lab_4_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd new file mode 100644 index 0000000..f5e072e --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd @@ -0,0 +1,87 @@ +-- ############################################################################# +-- mcp3204_spi.vhd +-- =============== +-- MCP3204 SPI interface. +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Author : () +-- Revision : 1 +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mcp3204_spi is + port( + -- 50 MHz + clk : in std_logic; + reset : in std_logic; + busy : out std_logic; + start : in std_logic; + channel : in std_logic_vector(1 downto 0); + data_valid : out std_logic; + data : out std_logic_vector(11 downto 0); + + -- 1 MHz + SCLK : out std_logic; + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); +end mcp3204_spi; + +architecture rtl of mcp3204_spi is + signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24 + signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz + signal reg_rising_edge_sclk : std_logic := '0'; + signal reg_falling_edge_sclk : std_logic := '0'; + + signal reg_sclk : std_logic := '0'; + +begin + clk_divider_generation : process(clk, reset) + begin + if reset = '1' then + reg_clk_divider_counter <= (others => '0'); + elsif rising_edge(clk) then + reg_clk_divider_counter <= reg_clk_divider_counter + 1; + reg_spi_en <= '0'; + reg_rising_edge_sclk <= '0'; + reg_falling_edge_sclk <= '0'; + + if reg_clk_divider_counter = 24 then + reg_clk_divider_counter <= (others => '0'); + reg_spi_en <= '1'; + + if reg_sclk = '0' then + reg_rising_edge_sclk <= '1'; + elsif reg_sclk = '1' then + reg_falling_edge_sclk <= '1'; + end if; + end if; + end if; + end process; + + SCLK_generation : process(clk, reset) + begin + if reset = '1' then + reg_sclk <= '0'; + elsif rising_edge(clk) then + if reg_spi_en = '1' then + reg_sclk <= not reg_sclk; + end if; + end if; + end process; + + STATE_LOGIC : process(clk, reset) + begin + -- TODO: complete this process + if reset = '1' then + elsif rising_edge(clk) then + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_4_0/hw/hdl/joysticks/tb/tb_mcp3204.vhd b/cs309-psoc/lab_4_0/hw/hdl/joysticks/tb/tb_mcp3204.vhd new file mode 100644 index 0000000..229f69d --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/joysticks/tb/tb_mcp3204.vhd @@ -0,0 +1,105 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; +use osvvm.RandomPkg.all; + +entity tb_mcp3204 is +end entity; + +architecture rtl of tb_mcp3204 is + constant CLK_PERIOD : time := 20 ns; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal sim_finished : boolean := false; + + -- mcp3204 ----------------------------------------------------------------- + signal address : std_logic_vector(1 downto 0) := (others => '0'); + signal read : std_logic := '0'; + signal readdata : std_logic_vector(31 downto 0) := (others => '0'); + signal CS_N : std_logic := '0'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '0'; + signal SCLK : std_logic := '0'; + +begin + duv : entity work.mcp3204 + port map( + clk => clk, + reset => reset, + address => address, + read => read, + readdata => readdata, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO, + SCLK => SCLK + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_finished; + + MISO_generation : process + variable rand_gen : RandomPType; + variable rint : integer; + begin + rand_gen.InitSeed(rand_gen'instance_name); + rand_gen.SetRandomParm(UNIFORM); + + while true loop + if not sim_finished then + wait until falling_edge(SCLK); + rint := rand_gen.RandInt(0, 1); + + if rint = 0 then + MISO <= '0'; + else + MISO <= '1'; + end if; + else + wait; + end if; + end loop; + + end process MISO_generation; + + sim : process + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + reset <= '1'; + + wait for CLK_PERIOD / 2; + reset <= '0'; + end procedure async_reset; + + procedure read_register(constant channel_number : natural range 0 to 3) is + begin + wait until falling_edge(clk); + address <= std_logic_vector(to_unsigned(channel_number, address'length)); + read <= '1'; + + wait until falling_edge(clk); + address <= (others => '0'); + read <= '0'; + + wait until falling_edge(clk); + end procedure; + + begin + async_reset; + + wait for 10000 * CLK_PERIOD; + + for i in 0 to 3 loop + read_register(i); + end loop; + + sim_finished <= true; + wait; + end process sim; +end architecture rtl; + + + diff --git a/cs309-psoc/lab_4_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd b/cs309-psoc/lab_4_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd new file mode 100644 index 0000000..1bb61d2 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd @@ -0,0 +1,103 @@ +-- ############################################################################# +-- tb_mcp3204_spi.vhd +-- ================== +-- Testbench for MCP3204 SPI interface. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 1 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_mcp3204_spi is +end entity; + +architecture rtl of tb_mcp3204_spi is + constant CLK_PERIOD : time := 20 ns; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal sim_finished : boolean := false; + + -- mcp3204_spi ------------------------------------------------------------ + signal busy : std_logic := '0'; + signal start : std_logic := '0'; + signal channel : std_logic_vector(1 downto 0) := (others => '0'); + signal data_valid : std_logic := '0'; + signal data : std_logic_vector(11 downto 0) := (others => '0'); + signal SCLK : std_logic := '0'; + signal CS_N : std_logic := '1'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '0'; + +begin + duv : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => busy, + start => start, + channel => channel, + data_valid => data_valid, + data => data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_finished; + + sim : process + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + reset <= '1'; + + wait for CLK_PERIOD / 2; + reset <= '0'; + end procedure async_reset; + + procedure spi_transfer(constant channel_number : natural range 0 to 3) is + begin + if busy = '1' then + wait until busy = '0'; + + else + wait until falling_edge(clk); + start <= '1'; + channel <= std_logic_vector(to_unsigned(channel_number, channel'length)); + + wait until falling_edge(clk); + start <= '0'; + channel <= (others => '0'); + + wait until rising_edge(data_valid); + wait until falling_edge(busy); + end if; + end procedure spi_transfer; + + begin + async_reset; + + MISO <= '1'; + spi_transfer(0); + + MISO <= '0'; + spi_transfer(1); + + MISO <= '1'; + spi_transfer(2); + + MISO <= '0'; + spi_transfer(3); + + sim_finished <= true; + wait; + end process sim; +end architecture rtl; + + diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd new file mode 100644 index 0000000..9769bb8 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd @@ -0,0 +1,139 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.utils.all; + +entity avalon_st_spi_master is + generic( + INPUT_CLK_FREQ : integer := 50000000; + SPI_SCLK_FREQ : integer := 10000000; + CPOL : integer := 1; + CPHA : integer := 1 + ); + port( + -- Input clock + clk : in std_logic; + + -- Reset + reset : in std_logic; + spi_cs_n : in std_logic; + -- Sink Avalon ST Interface + mosi_sink_data : in std_logic_vector(7 downto 0); + mosi_sink_valid : in std_logic; + mosi_sink_ready : out std_logic; + + -- Source Avalon ST Interface + miso_src_data : out std_logic_vector(7 downto 0); + miso_src_valid : out std_logic; + + -- SPI Master signals + SCLK : out std_logic; + MISO : in std_logic; + MOSI : out std_logic; + CS_n : out std_logic + ); +end avalon_st_spi_master; + +architecture rtl of avalon_st_spi_master is + constant SCLK_PRESCALER_MAX : integer := INPUT_CLK_FREQ / SPI_SCLK_FREQ / 2; + signal sclk_prescaler : unsigned(bitlength(SCLK_PRESCALER_MAX) downto 0); + signal sclk_toggle : std_logic; + + signal new_sink_buffer, cur_sink_buffer : std_logic_vector(mosi_sink_data'range); + signal new_sink_buffer_busy, cur_sink_buffer_busy : std_logic; + + signal miso_src_buffer : std_logic_vector(7 downto 0); + + signal spi_done, i_sclk : std_logic; + signal spi_bit_index : unsigned(2 downto 0); +begin + CS_n <= spi_cs_n; + + p_sclk_prescaler : process(clk, reset) is + begin + if reset = '1' then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + elsif rising_edge(clk) then + if sclk_prescaler = SCLK_PRESCALER_MAX then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + else + sclk_prescaler <= sclk_prescaler + 1; + end if; + end if; + end process p_sclk_prescaler; + sclk_toggle <= '1' when sclk_prescaler = SCLK_PRESCALER_MAX else '0'; + + p_avalon_st_sink : process(clk, reset) is + begin + if reset = '1' then + new_sink_buffer_busy <= '0'; + new_sink_buffer <= (others => '0'); + elsif rising_edge(clk) then + if mosi_sink_valid = '1' then + if new_sink_buffer_busy = '0' and cur_sink_buffer_busy = '1' then + new_sink_buffer <= mosi_sink_data; + new_sink_buffer_busy <= '1'; + end if; + elsif new_sink_buffer_busy = '1' and cur_sink_buffer_busy = '0' then + new_sink_buffer_busy <= '0'; + end if; + end if; + end process p_avalon_st_sink; + mosi_sink_ready <= not new_sink_buffer_busy; + + p_cur_buffer : process(clk, reset) is + begin + if reset = '1' then + cur_sink_buffer <= (others => '0'); + cur_sink_buffer_busy <= '0'; + elsif rising_edge(clk) then + if mosi_sink_valid = '1' and cur_sink_buffer_busy = '0' then + cur_sink_buffer <= mosi_sink_data; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '0' and new_sink_buffer_busy = '1' then + cur_sink_buffer <= new_sink_buffer; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '1' and spi_done = '1' then + cur_sink_buffer_busy <= '0'; + end if; + end if; + end process p_cur_buffer; + + p_spi : process(clk, reset) is + begin + if reset = '1' then + spi_done <= '0'; + i_sclk <= to_unsigned(CPOL, 1)(0); + spi_bit_index <= "000"; + MOSI <= '0'; + miso_src_data <= (others => '0'); + miso_src_valid <= '0'; + miso_src_buffer <= (others => '0'); + + elsif rising_edge(clk) then + spi_done <= '0'; + miso_src_valid <= '0'; + if cur_sink_buffer_busy = '1' and sclk_toggle = '1' then + if i_sclk /= to_unsigned(CPHA, 1)(0) then + if spi_bit_index = "111" then + spi_done <= '1'; + spi_bit_index <= "000"; + miso_src_valid <= '1'; + miso_src_data <= miso_src_buffer(7 downto 1) & MISO; + else + MOSI <= cur_sink_buffer(7 - to_integer(spi_bit_index)); + miso_src_buffer(7 - to_integer(spi_bit_index)) <= MISO; + spi_bit_index <= spi_bit_index + 1; + + end if; + + end if; + + i_sclk <= not i_sclk; + + end if; + end if; + end process p_spi; + SCLK <= i_sclk; + +end rtl; diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/byte2pix.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/byte2pix.vhd new file mode 100644 index 0000000..b888ba9 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/byte2pix.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------- +-- Title : Byte stream to pixel converter for the Lepton Camera +-- Project : PrSoC +------------------------------------------------------------------------------- +-- File : byte2pix.vhd +-- Author : Philemon Orphee Favrod +-- Company : +-- Created : 2016-03-21 +-- Last update: 2017-03-19 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: Converts a byte stream to a 14-bit pixel stream. +------------------------------------------------------------------------------- +-- Copyright (c) 2016 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2016-03-21 1.0 pofavrod Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity byte2pix is + port( + clk, reset : in std_logic; + byte_data : in std_logic_vector(7 downto 0); + byte_valid : in std_logic; + byte_sof : in std_logic; + byte_eof : in std_logic; + pix_data : out std_logic_vector(13 downto 0); + pix_valid : out std_logic; + pix_sof : out std_logic; + pix_eof : out std_logic); + +end byte2pix; + +architecture rtl of byte2pix is + signal last_sof : std_logic; + signal msb : std_logic_vector(5 downto 0); + signal cnt : std_logic; -- used to skip msb sampling every other time +begin + process(clk, reset) + begin + if reset = '1' then + msb <= (others => '0'); + cnt <= '0'; + last_sof <= '0'; + elsif rising_edge(clk) then + if byte_valid = '1' then + if cnt = '0' then + msb <= byte_data(5 downto 0); + last_sof <= byte_sof; + end if; + cnt <= not cnt; + end if; + end if; + end process; + + process(clk, reset) + begin + if reset = '1' then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + elsif rising_edge(clk) then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + + if byte_valid = '1' then + if cnt = '1' then + pix_data <= msb & byte_data; + pix_valid <= '1'; + pix_sof <= last_sof; + pix_eof <= byte_eof; + end if; + end if; + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd new file mode 100644 index 0000000..d4b4812 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd @@ -0,0 +1,192 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: dual_ported_ram.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +entity dual_ported_ram is + port( + clock : in std_logic := '1'; + data : in std_logic_vector(15 downto 0); + rdaddress : in std_logic_vector(12 downto 0); + wraddress : in std_logic_vector(12 downto 0); + wren : in std_logic := '0'; + q : out std_logic_vector(15 downto 0) + ); +end dual_ported_ram; + +architecture SYN of dual_ported_ram is + signal sub_wire0 : std_logic_vector(15 downto 0); + +begin + q <= sub_wire0(15 downto 0); + + altsyncram_component : altsyncram + generic map( + address_aclr_b => "NONE", + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 8192, + numwords_b => 8192, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "CLOCK0", + power_up_uninitialized => "FALSE", + read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => 13, + widthad_b => 13, + width_a => 16, + width_b => 16, + width_byteena_a => 1 + ) + port map( + address_a => wraddress, + address_b => rdaddress, + clock0 => clock, + data_a => data, + wren_a => wren, + q_b => sub_wire0 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]" +-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 +-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton.vhd new file mode 100644 index 0000000..82678ba --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton.vhd @@ -0,0 +1,288 @@ +-- Lepton Avalon Memory-Mapped Slave Interface +-- Author: Philémon Favrod (philemon.favrod@epfl.ch) +-- Modified by: Sahand Kashani-Akhavan (sahand.kashani-akhavan@epfl.ch) +-- Revision: 2 + +-- Register map +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 0 | COMMAND | WO | Command | +-- | | | | - Writing 1 starts capturing a frame & resets the | +-- | | | | ERROR bit (bit 1) in the STATUS register. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 1 | STATUS | RO | Status | +-- | | | | - Bit 0: 0 --> no capture in progress. | +-- | | | | 1 --> capture in progress. | +-- | | | | - Bit 1: 0 --> previous capture successful. | +-- | | | | 1 --> error during previous capture. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 2 | MIN | RO | Minimum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 3 | MAX | RO | Maximum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4 | SUM_LSB | RO | Sum of all pixels in frame (low 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 5 | SUM_MSB | RO | Sum of all pixels in frame (high 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 6 | ROW_IDX | RO | Current line being captured (1 <= ROW_IDX <= 60). | +-- | | | | Available for debugging purposes. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 7 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8 - 4807 | RAW BUFFER | RO | View into RAW pixel buffer. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4808 - 8191 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8192 - 12991 | ADJUSTED BUFFER | RO | View into adjusted (scaled) pixel buffer. | +-- | | | | Values are scaled between MIN and MAX. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 12992 - 16383 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton is + port( + clk : in std_logic; + reset : in std_logic; + address : in std_logic_vector(13 downto 0); + readdata : out std_logic_vector(15 downto 0); + writedata : in std_logic_vector(15 downto 0); + read : in std_logic; + write : in std_logic; + + SCLK : out std_logic; + CSn : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); + +end lepton; + +architecture rtl of lepton is + signal spi_cs_n : std_logic; + signal spi_mosi_data : std_logic_vector(7 downto 0); + signal spi_mosi_valid : std_logic; + signal spi_mosi_ready : std_logic; + signal spi_miso_data : std_logic_vector(7 downto 0); + signal spi_miso_valid : std_logic; + signal lepton_manager_start : std_logic; + signal lepton_manager_error : std_logic; + signal byte_data : std_logic_vector(7 downto 0); + signal byte_valid : std_logic; + signal byte_sof : std_logic; + signal byte_eof : std_logic; + signal pix_data : std_logic_vector(13 downto 0); + signal pix_valid : std_logic; + signal pix_sof : std_logic; + signal pix_eof : std_logic; + signal stat_min : std_logic_vector(13 downto 0); + signal stat_max : std_logic_vector(13 downto 0); + signal stat_sum : std_logic_vector(26 downto 0); + signal stat_valid : std_logic; + signal ram_data : std_logic_vector(15 downto 0); + signal ram_wren : std_logic; + signal ram_wraddress : std_logic_vector(12 downto 0); + signal ram_rdaddress : std_logic_vector(12 downto 0); + signal ram_q : std_logic_vector(15 downto 0); + signal row_idx : std_logic_vector(5 downto 0); + signal raw_pixel : std_logic_vector(13 downto 0); + signal raw_max : std_logic_vector(13 downto 0); + signal raw_min : std_logic_vector(13 downto 0); + signal raw_sum : std_logic_vector(26 downto 0); + signal adjusted_pixel : std_logic_vector(13 downto 0); + + constant COMMAND_REG_OFFSET : std_logic_vector(address'range) := "00000000000000"; + constant STATUS_REG_OFFSET : std_logic_vector(address'range) := "00000000000001"; + constant MIN_REG_OFFSET : std_logic_vector(address'range) := "00000000000010"; + constant MAX_REG_OFFSET : std_logic_vector(address'range) := "00000000000011"; + constant SUM_LSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000100"; + constant SUM_MSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000101"; + constant ROW_IDX_REG_OFFSET : std_logic_vector(address'range) := "00000000000110"; + constant BUFFER_REG_OFFSET : unsigned(address'range) := "00000000001000"; + constant ADJUSTED_BUFFER_REG_OFFSET : unsigned(address'range) := "10000000000000"; + + constant IMAGE_SIZE : integer := 80 * 60; + constant BUFFER_REG_LIMIT : unsigned(address'range) := unsigned(BUFFER_REG_OFFSET) + IMAGE_SIZE; + + constant ADJUSTED_BUFFER_LIMIT : unsigned(address'range) := unsigned(ADJUSTED_BUFFER_REG_OFFSET) + IMAGE_SIZE; + + signal max_reg : std_logic_vector(stat_max'range); + signal min_reg : std_logic_vector(stat_min'range); + signal sum_reg : std_logic_vector(stat_sum'range); + signal error_reg : std_logic; + +begin + spi_controller0 : entity work.avalon_st_spi_master + port map( + clk => clk, + reset => reset, + spi_cs_n => spi_cs_n, + mosi_sink_data => spi_mosi_data, + mosi_sink_valid => spi_mosi_valid, + mosi_sink_ready => spi_mosi_ready, + miso_src_data => spi_miso_data, + miso_src_valid => spi_miso_valid, + SCLK => SCLK, + MISO => MISO, + MOSI => MOSI, + CS_n => CSn + ); + + lepton_manager0 : entity work.lepton_manager + port map( + clk => clk, + reset => reset, + spi_miso_sink_data => spi_miso_data, + spi_miso_sink_valid => spi_miso_valid, + spi_mosi_src_data => spi_mosi_data, + spi_mosi_src_valid => spi_mosi_valid, + spi_mosi_src_ready => spi_mosi_ready, + lepton_out_data => byte_data, + lepton_out_valid => byte_valid, + lepton_out_sof => byte_sof, + lepton_out_eof => byte_eof, + row_idx => row_idx, + error => lepton_manager_error, + start => lepton_manager_start, + spi_cs_n => spi_cs_n + ); + + byte2pix0 : entity work.byte2pix + port map( + clk => clk, + reset => reset, + byte_data => byte_data, + byte_valid => byte_valid, + byte_sof => byte_sof, + byte_eof => byte_eof, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof + ); + + lepton_stats0 : entity work.lepton_stats + port map( + reset => reset, + clk => clk, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + stat_min => stat_min, + stat_max => stat_max, + stat_sum => stat_sum, + stat_valid => stat_valid + ); + + ram_writer0 : entity work.ram_writer + port map( + clk => clk, + reset => reset, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + ram_data => ram_data, + ram_wren => ram_wren, + ram_wraddress => ram_wraddress + ); + + dual_ported_ram0 : entity work.dual_ported_ram + port map( + clock => clk, + data => ram_data, + rdaddress => ram_rdaddress, + wraddress => ram_wraddress, + wren => ram_wren, + q => ram_q + ); + + level_adjuster0 : entity work.level_adjuster + port map( + clk => clk, + raw_pixel => ram_q(13 downto 0), + raw_max => max_reg, + raw_min => min_reg, + raw_sum => sum_reg, + adjusted_pixel => adjusted_pixel + ); + + p_lepton_start : process(clk, reset) + begin + if reset = '1' then + lepton_manager_start <= '0'; + error_reg <= '0'; + elsif rising_edge(clk) then + if write = '1' and address = COMMAND_REG_OFFSET then + lepton_manager_start <= writedata(0); + error_reg <= '0'; + elsif pix_eof = '1' then + lepton_manager_start <= '0'; + elsif lepton_manager_error = '1' then + error_reg <= '1'; + end if; + end if; + end process p_lepton_start; + + p_stat_reg : process(clk, reset) + begin + if reset = '1' then + min_reg <= (others => '0'); + max_reg <= (others => '0'); + sum_reg <= (others => '0'); + elsif rising_edge(clk) then + if stat_valid = '1' then + min_reg <= stat_min; + max_reg <= stat_max; + sum_reg <= stat_sum; + end if; + end if; + end process p_stat_reg; + + p_read : process(clk, reset) + begin + if reset = '1' then + readdata <= (others => '0'); + ram_rdaddress <= (others => '0'); + elsif rising_edge(clk) then + readdata <= (others => '0'); + if read = '1' then + case address is + when STATUS_REG_OFFSET => + readdata(1) <= error_reg; + readdata(0) <= lepton_manager_start; + + when MIN_REG_OFFSET => + readdata <= "00" & min_reg; + + when MAX_REG_OFFSET => + readdata <= "00" & max_reg; + + when SUM_MSB_REG_OFFSET => + readdata <= "00000" & sum_reg(26 downto 16); + + when SUM_LSB_REG_OFFSET => + readdata <= sum_reg(15 downto 0); + + when ROW_IDX_REG_OFFSET => + readdata(5 downto 0) <= row_idx; + + when others => + if unsigned(address) >= BUFFER_REG_OFFSET and unsigned(address) < BUFFER_REG_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= ram_q; + elsif unsigned(address) >= ADJUSTED_BUFFER_REG_OFFSET and unsigned(address) < ADJUSTED_BUFFER_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - ADJUSTED_BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= "00" & adjusted_pixel; + end if; + end case; + end if; + end if; + end process p_read; + +end rtl; diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton_hw.tcl b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton_hw.tcl new file mode 100644 index 0000000..d62e01b --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton_hw.tcl @@ -0,0 +1,148 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 19:05:24 CET 2017 +# DO NOT MODIFY + + +# +# lepton "lepton" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.19:05:24 +# IR Camera 80x60 +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module lepton +# +set_module_property DESCRIPTION "IR Camera 80x60" +set_module_property NAME lepton +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Camera +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME lepton +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL lepton +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file avalon_st_spi_master.vhd VHDL PATH avalon_st_spi_master.vhd +add_fileset_file byte2pix.vhd VHDL PATH byte2pix.vhd +add_fileset_file dual_ported_ram.vhd VHDL PATH dual_ported_ram.vhd +add_fileset_file lepton.vhd VHDL PATH lepton.vhd TOP_LEVEL_FILE +add_fileset_file lepton_manager.vhd VHDL PATH lepton_manager.vhd +add_fileset_file lepton_stats.vhd VHDL PATH lepton_stats.vhd +add_fileset_file ram_writer.vhd VHDL PATH ram_writer.vhd +add_fileset_file utils.vhd VHDL PATH utils.vhd +add_fileset_file level_adjuster.vhd VHDL PATH level_adjuster.vhd +add_fileset_file lpm_divider.vhd VHDL PATH lpm_divider.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitStates 9 +set_interface_property avalon_slave_0 readWaitTime 9 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 14 +add_interface_port avalon_slave_0 readdata readdata Output 16 +add_interface_port avalon_slave_0 writedata writedata Input 16 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point spi +# +add_interface spi conduit end +set_interface_property spi associatedClock clock +set_interface_property spi associatedReset "" +set_interface_property spi ENABLED true +set_interface_property spi EXPORT_OF "" +set_interface_property spi PORT_NAME_MAP "" +set_interface_property spi CMSIS_SVD_VARIABLES "" +set_interface_property spi SVD_ADDRESS_GROUP "" + +add_interface_port spi CSn cs_n Output 1 +add_interface_port spi MISO miso Input 1 +add_interface_port spi MOSI mosi Output 1 +add_interface_port spi SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton_manager.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton_manager.vhd new file mode 100644 index 0000000..1580be1 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton_manager.vhd @@ -0,0 +1,235 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_manager is + generic( + INPUT_CLK_FREQ : integer := 50000000); + port( + clk : in std_logic := '0'; + reset : in std_logic := '0'; + + -- Avalon ST Sink to receive SPI data + spi_miso_sink_data : in std_logic_vector(7 downto 0); + spi_miso_sink_valid : in std_logic; + + -- Avalon ST Source to send SPI data + spi_mosi_src_data : out std_logic_vector(7 downto 0); + spi_mosi_src_valid : out std_logic; + spi_mosi_src_ready : in std_logic := '0'; + + -- Filtered output to retransmit cleaned data (without the discard packets, see Lepton Datasheet on page 31) + -- lepton_out_data is valid on rising edge when lepton_src_valid = '1' + lepton_out_data : out std_logic_vector(7 downto 0); + lepton_out_valid : out std_logic; + lepton_out_sof : out std_logic; + lepton_out_eof : out std_logic; + + -- Some status + row_idx : out std_logic_vector(5 downto 0); + error : out std_logic; + + -- Avalon MM Slave interface for configuration + start : in std_logic; + + -- The SPI Chip Select (Active low !) + spi_cs_n : out std_logic := '0'); +end entity lepton_manager; + +architecture rtl of lepton_manager is + type state_t is (Idle, CSn, ReadHeader, ReadPayload, DiscardPayload, WaitBeforeIdle); + signal state, next_state : state_t; + + signal header_3_last_nibbles : std_logic_vector(11 downto 0); + + constant CLOCK_TICKS_PER_37_MS : integer := 37 * (INPUT_CLK_FREQ / 1e3); -- the timeout delay for a frame + constant CLOCK_TICKS_PER_200_MS : integer := 200 * (INPUT_CLK_FREQ / 1e3); + constant CLOCK_TICKS_PER_200_NS : integer := (200 * (INPUT_CLK_FREQ / 1e6)) / 1e3; + constant BYTES_PER_HEADER : integer := 4; + constant BYTES_PER_PAYLOAD : integer := 160; + + constant NUMBER_OF_LINES_PER_FRAME : positive := 60; + signal counter, counter_max : integer range 1 to CLOCK_TICKS_PER_200_MS; + signal line_counter : integer range 1 to NUMBER_OF_LINES_PER_FRAME; + signal timeout_counter : integer range 1 to CLOCK_TICKS_PER_37_MS; + signal counter_enabled : boolean; + signal waited_long_enough : boolean; + signal header_end, payload_end : boolean; +begin + + -- purpose: register for state + p_fsm : process(clk, reset) + begin + if reset = '1' then + state <= Idle; + elsif rising_edge(clk) then + state <= next_state; + end if; + end process p_fsm; + + -- purpose: compute the next state + p_nsl : process(header_3_last_nibbles, header_end, payload_end, start, spi_miso_sink_valid, state, waited_long_enough, line_counter) + begin + next_state <= state; + + case state is + when Idle => + if waited_long_enough and start = '1' then + next_state <= CSn; + end if; + + when CSn => + if waited_long_enough then + next_state <= ReadHeader; + end if; + + when ReadHeader => + if header_end then + if header_3_last_nibbles(11 downto 8) = X"F" then + next_state <= DiscardPayload; + else + next_state <= ReadPayload; + end if; + end if; + + when DiscardPayload | ReadPayload => + if payload_end then + next_state <= ReadHeader; + + if line_counter = NUMBER_OF_LINES_PER_FRAME then + next_state <= WaitBeforeIdle; + end if; + end if; + + when WaitBeforeIdle => + if spi_miso_sink_valid = '1' then + next_state <= Idle; + end if; + + end case; + end process p_nsl; + + p_counter : process(clk, reset) + begin + if reset = '1' then + counter <= 1; + line_counter <= 1; + elsif rising_edge(clk) then + if counter = counter_max and counter_enabled then + counter <= 1; + + if state = ReadPayload then + if line_counter = NUMBER_OF_LINES_PER_FRAME then + line_counter <= 1; + else + line_counter <= line_counter + 1; + end if; + end if; + + elsif counter_enabled then + counter <= counter + 1; + end if; + end if; + end process p_counter; + + p_error : process(clk, reset) + begin + if reset = '1' then + error <= '0'; + timeout_counter <= 1; + elsif rising_edge(clk) then + if state /= ReadHeader and state /= ReadPayload and state /= ReadHeader then + timeout_counter <= 1; + error <= '0'; + else + if timeout_counter = CLOCK_TICKS_PER_37_MS then + error <= '1'; + else + timeout_counter <= timeout_counter + 1; + end if; + end if; + if state = ReadPayload and header_3_last_nibbles /= std_logic_vector(to_unsigned(line_counter - 1, header_3_last_nibbles'length)) then + error <= '1'; + end if; + end if; + end process p_error; + + -- purpose: wire the datapath + p_datapath : process(counter, counter_enabled, counter_max, line_counter, spi_miso_sink_data, spi_miso_sink_valid, spi_mosi_src_ready, state) + variable counter_ended : boolean; + + begin + counter_max <= 1; + counter_enabled <= true; + waited_long_enough <= false; + lepton_out_data <= (others => '0'); + lepton_out_valid <= '0'; + lepton_out_sof <= '0'; + lepton_out_eof <= '0'; + spi_mosi_src_valid <= '0'; + spi_mosi_src_data <= (others => '0'); + spi_cs_n <= '0'; + header_end <= false; + payload_end <= false; + + counter_ended := (counter = counter_max and counter_enabled); + + case state is + when Idle => + counter_max <= CLOCK_TICKS_PER_200_MS; + waited_long_enough <= counter_ended; + spi_cs_n <= '1'; + + when CSn => + counter_max <= CLOCK_TICKS_PER_200_NS; + waited_long_enough <= counter_ended; + + when ReadHeader => + counter_max <= BYTES_PER_HEADER; + counter_enabled <= spi_miso_sink_valid = '1'; + header_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when ReadPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + lepton_out_data <= spi_miso_sink_data; + lepton_out_valid <= spi_miso_sink_valid; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + if spi_miso_sink_valid = '1' then + if counter = 1 and counter_enabled and line_counter = 1 then + lepton_out_sof <= '1'; + elsif counter_ended and line_counter = NUMBER_OF_LINES_PER_FRAME then + lepton_out_eof <= '1'; + end if; + end if; + + when DiscardPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when others => null; + end case; + end process p_datapath; + + p_capture_header : process(clk, reset) + begin + if reset = '1' then + header_3_last_nibbles <= X"000"; + elsif rising_edge(clk) then + if state = ReadHeader and spi_miso_sink_valid = '1' then + if counter = 1 then + header_3_last_nibbles(11 downto 8) <= spi_miso_sink_data(3 downto 0); + elsif counter = 2 then + header_3_last_nibbles(7 downto 0) <= spi_miso_sink_data; + end if; + end if; + end if; + end process p_capture_header; + + row_idx <= std_logic_vector(to_unsigned(line_counter, row_idx'length)); + +end architecture rtl; diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton_stats.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton_stats.vhd new file mode 100644 index 0000000..4b5cc91 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lepton_stats.vhd @@ -0,0 +1,78 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_stats is + port( + clk : in std_logic; + reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + stat_min : out std_logic_vector(13 downto 0); + stat_max : out std_logic_vector(13 downto 0); + stat_sum : out std_logic_vector(26 downto 0); + stat_valid : out std_logic); +end lepton_stats; + +architecture rtl of lepton_stats is + + -- The accumulated sum, min and max of the pixel values + signal curr_min : unsigned(13 downto 0); + signal curr_max : unsigned(13 downto 0); + signal curr_sum : unsigned(26 downto 0); + + -- The next value of the registers + signal next_min : unsigned(13 downto 0); + signal next_max : unsigned(13 downto 0); + signal next_sum : unsigned(26 downto 0); + +begin + + -- This is the synchronous transition logic + transition_logic : process(clk, reset) + begin + if reset = '1' then + curr_sum <= (others => '0'); + curr_min <= (others => '0'); + curr_max <= (others => '0'); + elsif rising_edge(clk) then + curr_min <= next_min; + curr_max <= next_max; + curr_sum <= next_sum; + end if; + end process; + + -- This is the combinatorial transition logic + next_min <= + curr_min when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_min when unsigned(pix_data) >= curr_min else + unsigned(pix_data); + + next_max <= + curr_max when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_max when unsigned(pix_data) <= curr_max else + unsigned(pix_data); + + next_sum <= + curr_sum when pix_valid = '0' else + unsigned((26 downto 14 => '0') & pix_data) when pix_sof = '1' else + curr_sum + unsigned((26 downto 14 => '0') & pix_data); + + -- This is the synchronous output logic + output_logic : process(clk, reset) + begin + if rising_edge(clk) then + stat_valid <= pix_eof; + end if; + end process; + + -- This is the combinatorial output logic + stat_min <= std_logic_vector(curr_min); + stat_max <= std_logic_vector(curr_max); + stat_sum <= std_logic_vector(curr_sum); + +end rtl; diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/level_adjuster.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/level_adjuster.vhd new file mode 100644 index 0000000..6b3053d --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/level_adjuster.vhd @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity level_adjuster is + port( + clk : in std_logic; + raw_pixel : in std_logic_vector(13 downto 0); + raw_max : in std_logic_vector(13 downto 0); + raw_min : in std_logic_vector(13 downto 0); + raw_sum : in std_logic_vector(26 downto 0); + adjusted_pixel : out std_logic_vector(13 downto 0)); +end level_adjuster; + +architecture rtl of level_adjuster is + component lpm_divider + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0)); + end component; + + -- Intermediate signals needed by the divider + signal numer : std_logic_vector(27 downto 0); + signal denom : std_logic_vector(13 downto 0); + signal quot : std_logic_vector(27 downto 0); + +begin + + -- Computation of the intermediate signals + numer <= std_logic_vector((13 downto 0 => '1') * (unsigned(raw_pixel) - unsigned(raw_min))); + denom <= std_logic_vector(unsigned(raw_max) - unsigned(raw_min)); + + -- We compute the remaineder of (x - min) / (max - min) + divider : lpm_divider port map( + clock => clk, + numer => numer, + denom => denom, + quotient => quot, + remain => open + ); + + -- And we only keep the LSB of the quotient (we know the MSB must be 0) + adjusted_pixel <= + (adjusted_pixel'range => '0') when denom = (denom'range => '0') else + quot(13 downto 0); + +end rtl; diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lpm_divider.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lpm_divider.vhd new file mode 100644 index 0000000..f8de4a6 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/lpm_divider.vhd @@ -0,0 +1,133 @@ +-- megafunction wizard: %LPM_DIVIDE% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_DIVIDE + +-- ============================================================ +-- File Name: lpm_divider.vhd +-- Megafunction Name(s): +-- LPM_DIVIDE +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library lpm; +use lpm.all; + +entity lpm_divider is + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); +end lpm_divider; + +architecture SYN of lpm_divider is + signal sub_wire0 : std_logic_vector(27 downto 0); + signal sub_wire1 : std_logic_vector(13 downto 0); + + component lpm_divide + generic( + lpm_drepresentation : string; + lpm_hint : string; + lpm_nrepresentation : string; + lpm_pipeline : natural; + lpm_type : string; + lpm_widthd : natural; + lpm_widthn : natural + ); + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); + end component; + +begin + quotient <= sub_wire0(27 downto 0); + remain <= sub_wire1(13 downto 0); + + LPM_DIVIDE_component : LPM_DIVIDE + generic map( + lpm_drepresentation => "UNSIGNED", + lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE", + lpm_nrepresentation => "UNSIGNED", + lpm_pipeline => 5, + lpm_type => "LPM_DIVIDE", + lpm_widthd => 14, + lpm_widthn => 28 + ) + port map( + clock => clock, + denom => denom, + numer => numer, + quotient => sub_wire0, + remain => sub_wire1 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" +-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1" +-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" +-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" +-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "14" +-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "28" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: denom 0 0 14 0 INPUT NODEFVAL "denom[13..0]" +-- Retrieval info: USED_PORT: numer 0 0 28 0 INPUT NODEFVAL "numer[27..0]" +-- Retrieval info: USED_PORT: quotient 0 0 28 0 OUTPUT NODEFVAL "quotient[27..0]" +-- Retrieval info: USED_PORT: remain 0 0 14 0 OUTPUT NODEFVAL "remain[13..0]" +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @denom 0 0 14 0 denom 0 0 14 0 +-- Retrieval info: CONNECT: @numer 0 0 28 0 numer 0 0 28 0 +-- Retrieval info: CONNECT: quotient 0 0 28 0 @quotient 0 0 28 0 +-- Retrieval info: CONNECT: remain 0 0 14 0 @remain 0 0 14 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/ram_writer.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/ram_writer.vhd new file mode 100644 index 0000000..8912cdb --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/ram_writer.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram_writer is + port( + clk, reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + ram_data : out std_logic_vector(15 downto 0); + ram_wren : out std_logic; + ram_wraddress : out std_logic_vector(12 downto 0)); + +end ram_writer; + +architecture rtl of ram_writer is + signal wraddress_counter : unsigned(ram_wraddress'range); +begin + p_address_gen : process(clk, reset) + begin + if reset = '1' then + wraddress_counter <= (others => '0'); + elsif rising_edge(clk) then + if pix_eof = '1' then + wraddress_counter <= (others => '0'); + elsif pix_valid = '1' then + wraddress_counter <= wraddress_counter + 1; + end if; + end if; + end process p_address_gen; + + ram_data <= "00" & pix_data; + ram_wren <= pix_valid; + ram_wraddress <= std_logic_vector(wraddress_counter); + +end rtl; diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/utils.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/utils.vhd new file mode 100644 index 0000000..83105ad --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/hdl/utils.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package utils is + function bitlength(number : positive) return positive; + +end package utils; + +package body utils is + + -- purpose: returns the minimum # of bits needed to represent the input number + function bitlength(number : positive) return positive is + variable acc : positive := 1; + variable i : natural := 0; + begin + while True loop + if acc > number then + return i; + end if; + + acc := acc * 2; + i := i + 1; + end loop; + end function bitlength; + +end package body utils; diff --git a/cs309-psoc/lab_4_0/hw/hdl/lepton/tb/lepton_tb.vhd b/cs309-psoc/lab_4_0/hw/hdl/lepton/tb/lepton_tb.vhd new file mode 100644 index 0000000..f134613 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/lepton/tb/lepton_tb.vhd @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity lepton_tb is +end lepton_tb; + +architecture tb of lepton_tb is + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal address : std_logic_vector(13 downto 0) := (others => '0'); + signal readdata : std_logic_vector(15 downto 0) := (others => '0'); + signal writedata : std_logic_vector(15 downto 0) := (others => '0'); + signal read : std_logic := '0'; + signal write : std_logic := '0'; + signal SCLK : std_logic := '0'; + signal CSn : std_logic := '0'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '1'; + + constant CLK_PERIOD : time := 20 ns; + + signal sim_ended : boolean := false; + +begin + dut : entity work.lepton + port map( + clk => clk, + reset => reset, + address => address, + readdata => readdata, + writedata => writedata, + read => read, + write => write, + SCLK => SCLK, + CSn => CSn, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_ended else '0'; + + miso_gen : process + variable seed1, seed2 : positive; + variable rand : real; + begin + if sim_ended then + wait; + else + uniform(seed1, seed2, rand); + wait until rising_edge(SCLK); + MISO <= to_unsigned(integer(rand), 1)(0); + + end if; + end process; + + stimuli : process + begin + reset <= '1'; + write <= '0'; + + wait for 2 * CLK_PERIOD; + reset <= '0'; + + wait for CLK_PERIOD; + write <= '1'; + writedata(0) <= '1'; + wait for CLK_PERIOD; + write <= '0'; + + wait for 17 ms; + sim_ended <= true; + wait; + end process; + +end tb; diff --git a/cs309-psoc/lab_4_0/hw/hdl/pantilt/hdl/pwm.vhd b/cs309-psoc/lab_4_0/hw/hdl/pantilt/hdl/pwm.vhd new file mode 100644 index 0000000..1b5cdc3 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/pantilt/hdl/pwm.vhd @@ -0,0 +1,42 @@ +-- ############################################################################# +-- pwm.vhd +-- ======= +-- PWM memory-mapped Avalon slave interface. +-- +-- Author : () +-- Author : () +-- Revision : +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity pwm is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + write : in std_logic; + readdata : out std_logic_vector(31 downto 0); + writedata : in std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + pwm_out : out std_logic + ); +end pwm; + +architecture rtl of pwm is + +begin + +end architecture rtl; diff --git a/cs309-psoc/lab_4_0/hw/hdl/pantilt/hdl/pwm_constants.vhd b/cs309-psoc/lab_4_0/hw/hdl/pantilt/hdl/pwm_constants.vhd new file mode 100644 index 0000000..bfff03b --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/pantilt/hdl/pwm_constants.vhd @@ -0,0 +1,61 @@ +-- ############################################################################# +-- pwm_constants.vhd +-- ================= +-- This package contains constants used in the PWM design files. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pwm_constants is + -- Register map + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | RegNo | Name | Access | Description | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW period to apply to the | + -- | | | | next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT period of the | + -- | | | | ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to | + -- | | | | the next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT duty cycle of | + -- | | | | the ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.| + -- | | | | Writing 1 to this register starts the PWM. | + -- | | | | | + -- | | | | >> Reading this register always returns 0. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00"; + constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01"; + constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10"; + + -- Default values of registers after reset (BEFORE writing START to the CTRL + -- register with a new configuration) + constant DEFAULT_PERIOD : natural := 4; + constant DEFAULT_DUTY_CYCLE : natural := 2; +end package pwm_constants; + +package body pwm_constants is + +end package body pwm_constants; diff --git a/cs309-psoc/lab_4_0/hw/hdl/pantilt/hdl/pwm_hw.tcl b/cs309-psoc/lab_4_0/hw/hdl/pantilt/hdl/pwm_hw.tcl new file mode 100644 index 0000000..df7d92a --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/pantilt/hdl/pwm_hw.tcl @@ -0,0 +1,135 @@ +# TCL File Generated by Component Editor 16.0 +# Tue Feb 28 12:18:00 CET 2017 +# DO NOT MODIFY + + +# +# pwm "pwm" v1.0 +# 2017.02.28.12:18:00 +# Pan-tilt +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module pwm +# +set_module_property DESCRIPTION Pan-tilt +set_module_property NAME pwm +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Pan-tilt +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME pwm +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE +add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +add_interface_port avalon_slave_0 writedata writedata Input 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end pwm_out pwm Output 1 diff --git a/cs309-psoc/lab_4_0/hw/hdl/pantilt/tb/tb_pwm.vhd b/cs309-psoc/lab_4_0/hw/hdl/pantilt/tb/tb_pwm.vhd new file mode 100644 index 0000000..ff2dee7 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/hdl/pantilt/tb/tb_pwm.vhd @@ -0,0 +1,205 @@ +-- ############################################################################# +-- tb_pwm.vhd +-- ========== +-- Testbench for PWM memory-mapped Avalon slave interface. +-- +-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity tb_pwm is +end entity; + +architecture rtl of tb_pwm is + + -- 50 MHz clock + constant CLK_PERIOD : time := 20 ns; + + -- Signal used to end simulator when we finished submitting our test cases + signal sim_finished : boolean := false; + + -- PWM PORTS + signal clk : std_logic; + signal reset : std_logic; + signal address : std_logic_vector(1 downto 0); + signal read : std_logic; + signal write : std_logic; + signal readdata : std_logic_vector(31 downto 0); + signal writedata : std_logic_vector(31 downto 0); + signal pwm_out : std_logic; + + -- Values of registers we are going to use to configure the PWM unit + constant CONFIG_PERIOD : natural := 100; + constant CONFIG_DUTY_CYCLE : natural := 20; + constant CONFIG_CTRL_START : natural := 1; + constant CONFIG_CTRL_STOP : natural := 0; + +begin + + -- Instantiate DUT + dut : entity work.pwm + port map( + clk => clk, + reset => reset, + address => address, + read => read, + write => write, + readdata => readdata, + writedata => writedata, + pwm_out => pwm_out + ); + + -- Generate clk signal + clk_generation : process + begin + if not sim_finished then + clk <= '1'; + wait for CLK_PERIOD / 2; + clk <= '0'; + wait for CLK_PERIOD / 2; + else + wait; + end if; + end process clk_generation; + + -- Test PWM + simulation : process + + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + + reset <= '1'; + wait for CLK_PERIOD / 2; + + reset <= '0'; + wait for CLK_PERIOD / 4; + end procedure async_reset; + + procedure write_register(constant ofst : in std_logic_vector(1 downto 0); + constant val : in natural) is + begin + wait until rising_edge(clk); + + address <= ofst; + write <= '1'; + writedata <= std_logic_vector(to_unsigned(val, writedata'length)); + wait until rising_edge(clk); + + address <= (others => '0'); + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + end procedure write_register; + + procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is + begin + wait until rising_edge(clk); + + address <= ofst; + read <= '1'; + -- The read has a 1 cycle wait-state, so we need to keep the read + -- signal high for 2 clock cycles. + wait until rising_edge(clk); + wait until rising_edge(clk); + + address <= (others => '0'); + read <= '0'; + wait until rising_edge(clk); + end procedure read_register; + + procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0); + constant expected_val : in natural) is + begin + read_register(ofst); + + case ofst is + when REG_PERIOD_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected PERIOD: " & + "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "PERIOD_expected = " & integer'image(expected_val) + severity error; + + when REG_DUTY_CYCLE_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected DUTY_CYCLE: " & + "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "DUTY_CYCLE_expected = " & integer'image(expected_val) + severity error; + + when REG_CTRL_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected CTRL: " & + "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "CTRL_expected = " & integer'image(expected_val) + severity error; + + when others => + null; + end case; + end procedure read_register_check; + + begin + + -- Default values + reset <= '0'; + address <= (others => '0'); + read <= '0'; + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + + -- Reset the circuit + async_reset; + + -- Write desired configuration to PWM Avalon-MM slave. + write_register(REG_PERIOD_OFST, CONFIG_PERIOD); + write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + + -- Read back configuration from PWM Avalon-MM slave. Note that we have + -- not started the PWM unit yet, so the new configuration must not be + -- read back at this point (as per the register map). + read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Start PWM + write_register(REG_CTRL_OFST, CONFIG_CTRL_START); + + -- Wait until PWM pulses for the first time after we sent START. + wait until rising_edge(pwm_out); + + -- Read back configuration from PWM Avalon-MM slave. Now that we have + -- started the PWM unit, we should be able to read back the + -- configuration we wrote (as per the register map). + read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Wait for 2 PWM periods to finish + wait for 2 * CLK_PERIOD * CONFIG_PERIOD; + + -- Stop PWM. + write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP); + + -- Wait for PWM period to finish + wait for 1 * CLK_PERIOD * CONFIG_PERIOD; + + -- Instruct "clk_generation" process to halt execution. + sim_finished <= true; + + -- Make this process wait indefinitely (it will never re-execute from + -- its beginning again). + wait; + end process simulation; +end architecture rtl; + diff --git a/cs309-psoc/lab_4_0/hw/quartus/ip/components.ipx b/cs309-psoc/lab_4_0/hw/quartus/ip/components.ipx new file mode 100644 index 0000000..efff046 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/quartus/ip/components.ipx @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_4_0/hw/quartus/lab_4_0.qpf b/cs309-psoc/lab_4_0/hw/quartus/lab_4_0.qpf new file mode 100644 index 0000000..c2f3aba --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/quartus/lab_4_0.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition +# Date created = 11:03:02 February 05, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.1" +DATE = "11:03:02 February 05, 2016" + +# Revisions + +PROJECT_REVISION = "lab_4_0" diff --git a/cs309-psoc/lab_4_0/hw/quartus/lab_4_0.qsf b/cs309-psoc/lab_4_0/hw/quartus/lab_4_0.qsf new file mode 100644 index 0000000..0f92d41 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/quartus/lab_4_0.qsf @@ -0,0 +1,1017 @@ +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 + +set_global_assignment -name SMART_RECOMPILE OFF +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level + +set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +set_global_assignment -name QIP_FILE soc_system/synthesis/soc_system.qip +set_global_assignment -name SDC_FILE lab_4_0.sdc + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA4U23C6 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO Extention OV7670 CAMERA +#============================================================ +set_location_assignment PIN_AE15 -to CAM_D[0] +set_location_assignment PIN_AE15 -to CAM_D_0 +set_location_assignment PIN_AF17 -to CAM_D[1] +set_location_assignment PIN_AF17 -to CAM_D_1 +set_location_assignment PIN_AH8 -to CAM_D[2] +set_location_assignment PIN_AH8 -to CAM_D_2 +set_location_assignment PIN_AG8 -to CAM_D[3] +set_location_assignment PIN_AG8 -to CAM_D_3 +set_location_assignment PIN_U13 -to CAM_D[4] +set_location_assignment PIN_U13 -to CAM_D_4 +set_location_assignment PIN_U14 -to CAM_D[5] +set_location_assignment PIN_U14 -to CAM_D_5 +set_location_assignment PIN_AG9 -to CAM_D[6] +set_location_assignment PIN_AG9 -to CAM_D_6 +set_location_assignment PIN_AG10 -to CAM_D[7] +set_location_assignment PIN_AG10 -to CAM_D_7 +set_location_assignment PIN_AF13 -to CAM_D[8] +set_location_assignment PIN_AF13 -to CAM_D_8 +set_location_assignment PIN_AG13 -to CAM_D[9] +set_location_assignment PIN_AG13 -to CAM_D_9 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9 + +#============================================================ +# Arduino Extension LEPTON CAMERA THERMAL CAM_TH +#============================================================ +set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N +set_location_assignment PIN_AG16 -to CAM_TH_MOSI +set_location_assignment PIN_AH11 -to CAM_TH_MISO +set_location_assignment PIN_AH12 -to CAM_TH_CLK +set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA +set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL + +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#============================================================ +# HPS +#============================================================ +set_location_assignment PIN_C6 -to HPS_CONV_USB_N +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0] +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0 +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1] +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1 +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2] +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2 +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3] +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3 +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4] +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4 +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5] +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5 +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6] +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6 +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7] +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7 +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8] +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8 +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9] +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9 +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10] +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10 +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11] +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11 +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12] +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12 +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13] +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13 +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14] +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14 +set_location_assignment PIN_A27 -to HPS_DDR3_BA[0] +set_location_assignment PIN_A27 -to HPS_DDR3_BA_0 +set_location_assignment PIN_H25 -to HPS_DDR3_BA[1] +set_location_assignment PIN_H25 -to HPS_DDR3_BA_1 +set_location_assignment PIN_G25 -to HPS_DDR3_BA[2] +set_location_assignment PIN_G25 -to HPS_DDR3_BA_2 +set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N +set_location_assignment PIN_L28 -to HPS_DDR3_CKE +set_location_assignment PIN_N20 -to HPS_DDR3_CK_N +set_location_assignment PIN_N21 -to HPS_DDR3_CK_P +set_location_assignment PIN_L21 -to HPS_DDR3_CS_N +set_location_assignment PIN_G28 -to HPS_DDR3_DM[0] +set_location_assignment PIN_G28 -to HPS_DDR3_DM_0 +set_location_assignment PIN_P28 -to HPS_DDR3_DM[1] +set_location_assignment PIN_P28 -to HPS_DDR3_DM_1 +set_location_assignment PIN_W28 -to HPS_DDR3_DM[2] +set_location_assignment PIN_W28 -to HPS_DDR3_DM_2 +set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3] +set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3 +set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0] +set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0 +set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1] +set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1 +set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2] +set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2 +set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3] +set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3 +set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4] +set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4 +set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5] +set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5 +set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6] +set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6 +set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7] +set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7 +set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8] +set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8 +set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9] +set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9 +set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10] +set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10 +set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11] +set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11 +set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12] +set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12 +set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13] +set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13 +set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14] +set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14 +set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15] +set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15 +set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16] +set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16 +set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17] +set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17 +set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18] +set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18 +set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19] +set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19 +set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20] +set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20 +set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21] +set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21 +set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22] +set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22 +set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23] +set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23 +set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24] +set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24 +set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25] +set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25 +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26] +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26 +set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27] +set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27 +set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28] +set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28 +set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29] +set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29 +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30] +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30 +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31] +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31 +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0] +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0 +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1] +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1 +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2] +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2 +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3] +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3 +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0] +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0 +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1] +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1 +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2] +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2 +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3] +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3 +set_location_assignment PIN_D28 -to HPS_DDR3_ODT +set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N +set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N +set_location_assignment PIN_D25 -to HPS_DDR3_RZQ +set_location_assignment PIN_E25 -to HPS_DDR3_WE_N +set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK +set_location_assignment PIN_B14 -to HPS_ENET_INT_N +set_location_assignment PIN_A13 -to HPS_ENET_MDC +set_location_assignment PIN_E16 -to HPS_ENET_MDIO +set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0] +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0 +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1] +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1 +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2] +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2 +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3] +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3 +set_location_assignment PIN_J13 -to HPS_ENET_RX_DV +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0] +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0 +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1] +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1 +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2] +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2 +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3] +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3 +set_location_assignment PIN_A12 -to HPS_ENET_TX_EN +set_location_assignment PIN_A17 -to HPS_GSENSOR_INT +set_location_assignment PIN_C18 -to HPS_I2C0_SCLK +set_location_assignment PIN_A19 -to HPS_I2C0_SDAT +set_location_assignment PIN_K18 -to HPS_I2C1_SCLK +set_location_assignment PIN_A21 -to HPS_I2C1_SDAT +set_location_assignment PIN_J18 -to HPS_KEY_N +set_location_assignment PIN_A20 -to HPS_LED +set_location_assignment PIN_H13 -to HPS_LTC_GPIO +set_location_assignment PIN_B8 -to HPS_SD_CLK +set_location_assignment PIN_D14 -to HPS_SD_CMD +set_location_assignment PIN_C13 -to HPS_SD_DATA[0] +set_location_assignment PIN_C13 -to HPS_SD_DATA_0 +set_location_assignment PIN_B6 -to HPS_SD_DATA[1] +set_location_assignment PIN_B6 -to HPS_SD_DATA_1 +set_location_assignment PIN_B11 -to HPS_SD_DATA[2] +set_location_assignment PIN_B11 -to HPS_SD_DATA_2 +set_location_assignment PIN_B9 -to HPS_SD_DATA[3] +set_location_assignment PIN_B9 -to HPS_SD_DATA_3 +set_location_assignment PIN_C19 -to HPS_SPIM_CLK +set_location_assignment PIN_B19 -to HPS_SPIM_MISO +set_location_assignment PIN_B16 -to HPS_SPIM_MOSI +set_location_assignment PIN_C16 -to HPS_SPIM_SS +set_location_assignment PIN_A22 -to HPS_UART_RX +set_location_assignment PIN_B21 -to HPS_UART_TX +set_location_assignment PIN_G4 -to HPS_USB_CLKOUT +set_location_assignment PIN_C10 -to HPS_USB_DATA[0] +set_location_assignment PIN_C10 -to HPS_USB_DATA_0 +set_location_assignment PIN_F5 -to HPS_USB_DATA[1] +set_location_assignment PIN_F5 -to HPS_USB_DATA_1 +set_location_assignment PIN_C9 -to HPS_USB_DATA[2] +set_location_assignment PIN_C9 -to HPS_USB_DATA_2 +set_location_assignment PIN_C4 -to HPS_USB_DATA[3] +set_location_assignment PIN_C4 -to HPS_USB_DATA_3 +set_location_assignment PIN_C8 -to HPS_USB_DATA[4] +set_location_assignment PIN_C8 -to HPS_USB_DATA_4 +set_location_assignment PIN_D4 -to HPS_USB_DATA[5] +set_location_assignment PIN_D4 -to HPS_USB_DATA_5 +set_location_assignment PIN_C7 -to HPS_USB_DATA[6] +set_location_assignment PIN_C7 -to HPS_USB_DATA_6 +set_location_assignment PIN_F4 -to HPS_USB_DATA[7] +set_location_assignment PIN_F4 -to HPS_USB_DATA_7 +set_location_assignment PIN_E5 -to HPS_USB_DIR +set_location_assignment PIN_D5 -to HPS_USB_NXT +set_location_assignment PIN_C5 -to HPS_USB_STP + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY_N +#============================================================ +set_location_assignment PIN_AH17 -to KEY_N[0] +set_location_assignment PIN_AH17 -to KEY_N_0 +set_location_assignment PIN_AH16 -to KEY_N[1] +set_location_assignment PIN_AH16 -to KEY_N_1 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_W15 -to LED_0 +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_AA24 -to LED_1 +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V16 -to LED_2 +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_V15 -to LED_3 +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AF26 -to LED_4 +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_AE26 -to LED_5 +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_Y16 -to LED_6 +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_AA23 -to LED_7 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7 + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_L10 -to SW[0] +set_location_assignment PIN_L10 -to SW_0 +set_location_assignment PIN_L9 -to SW[1] +set_location_assignment PIN_L9 -to SW_1 +set_location_assignment PIN_H6 -to SW[2] +set_location_assignment PIN_H6 -to SW_2 +set_location_assignment PIN_H5 -to SW[3] +set_location_assignment PIN_H5 -to SW_3 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3 + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_V12 -to PIO_INT_N +set_location_assignment PIN_AE11 -to PIO_SCL +set_location_assignment PIN_AE12 -to PIO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA + +set_location_assignment PIN_AF7 -to PIR_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT + +set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA +set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL +set_location_assignment PIN_T11 -to CAM_SYS_CLK +set_location_assignment PIN_AG6 -to CAM_LV +set_location_assignment PIN_AH2 -to CAM_PIX_CLK +set_location_assignment PIN_AE4 -to CAM_FV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV + +set_location_assignment PIN_Y8 -to PAL_VD_HSO +set_location_assignment PIN_AB4 -to PAL_VD_VSO +set_location_assignment PIN_AG5 -to PAL_VD_VD[0] +set_location_assignment PIN_AG5 -to PAL_VD_VD_0 +set_location_assignment PIN_AH5 -to PAL_VD_VD[1] +set_location_assignment PIN_AH5 -to PAL_VD_VD_1 +set_location_assignment PIN_AH6 -to PAL_VD_VD[2] +set_location_assignment PIN_AH6 -to PAL_VD_VD_2 +set_location_assignment PIN_T8 -to PAL_VD_VD[3] +set_location_assignment PIN_T8 -to PAL_VD_VD_3 +set_location_assignment PIN_T12 -to PAL_VD_VD[4] +set_location_assignment PIN_T12 -to PAL_VD_VD_4 +set_location_assignment PIN_Y5 -to PAL_VD_VD[5] +set_location_assignment PIN_Y5 -to PAL_VD_VD_5 +set_location_assignment PIN_Y4 -to PAL_VD_VD[6] +set_location_assignment PIN_Y4 -to PAL_VD_VD_6 +set_location_assignment PIN_W8 -to PAL_VD_VD[7] +set_location_assignment PIN_W8 -to PAL_VD_VD_7 +set_location_assignment PIN_AH4 -to PAL_VD_CLKO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO + +set_location_assignment PIN_AH3 -to SERVO_0 +set_location_assignment PIN_AF4 -to SERVO_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1 + +set_location_assignment PIN_AD12 -to J0_SPI_CLK +set_location_assignment PIN_AD11 -to J0_SPI_MISO +set_location_assignment PIN_AF9 -to J0_SPI_CS_N +set_location_assignment PIN_AD10 -to J0_SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI + +set_location_assignment PIN_AF5 -to FROM_ESP_TXD +set_location_assignment PIN_T13 -to TO_ESP_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD + +set_location_assignment PIN_AE7 -to SPI_MISO +set_location_assignment PIN_AF6 -to SPI_ENA_N +set_location_assignment PIN_AE8 -to SPI_CLK +set_location_assignment PIN_AE9 -to SPI_MOSI +set_location_assignment PIN_AF10 -to SPI_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT + +set_location_assignment PIN_AF11 -to LED_BGR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_AA15 -to RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N + +set_location_assignment PIN_AG28 -to TS_SCL +set_location_assignment PIN_AH27 -to TS_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA + +set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N +set_location_assignment PIN_AG26 -to LCD_DE +set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN + +set_location_assignment PIN_AH24 -to BLT_TXD +set_location_assignment PIN_AE22 -to BLT_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD + +set_location_assignment PIN_AG20 -to BOARD_ID +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID + +set_location_assignment PIN_AF21 -to VIDEO_HSYNC +set_location_assignment PIN_AG19 -to VIDEO_VSYNC +set_location_assignment PIN_AF20 -to VIDEO_CLK +set_location_assignment PIN_AG23 -to VIDEO_B[0] +set_location_assignment PIN_AG23 -to VIDEO_B_0 +set_location_assignment PIN_AH23 -to VIDEO_B[1] +set_location_assignment PIN_AH23 -to VIDEO_B_1 +set_location_assignment PIN_AF25 -to VIDEO_B[2] +set_location_assignment PIN_AF25 -to VIDEO_B_2 +set_location_assignment PIN_AG24 -to VIDEO_B[3] +set_location_assignment PIN_AG24 -to VIDEO_B_3 +set_location_assignment PIN_AA19 -to VIDEO_B[4] +set_location_assignment PIN_AA19 -to VIDEO_B_4 +set_location_assignment PIN_AH26 -to VIDEO_B[5] +set_location_assignment PIN_AH26 -to VIDEO_B_5 +set_location_assignment PIN_AG18 -to VIDEO_B[6] +set_location_assignment PIN_AG18 -to VIDEO_B_6 +set_location_assignment PIN_AC23 -to VIDEO_B[7] +set_location_assignment PIN_AC23 -to VIDEO_B_7 +set_location_assignment PIN_AH22 -to VIDEO_G[0] +set_location_assignment PIN_AH22 -to VIDEO_G_0 +set_location_assignment PIN_AF22 -to VIDEO_G[1] +set_location_assignment PIN_AF22 -to VIDEO_G_1 +set_location_assignment PIN_AD20 -to VIDEO_G[2] +set_location_assignment PIN_AD20 -to VIDEO_G_2 +set_location_assignment PIN_AE24 -to VIDEO_G[3] +set_location_assignment PIN_AE24 -to VIDEO_G_3 +set_location_assignment PIN_AE20 -to VIDEO_G[4] +set_location_assignment PIN_AE20 -to VIDEO_G_4 +set_location_assignment PIN_AD19 -to VIDEO_G[5] +set_location_assignment PIN_AD19 -to VIDEO_G_5 +set_location_assignment PIN_AF18 -to VIDEO_G[6] +set_location_assignment PIN_AF18 -to VIDEO_G_6 +set_location_assignment PIN_AE19 -to VIDEO_G[7] +set_location_assignment PIN_AE19 -to VIDEO_G_7 +set_location_assignment PIN_AC22 -to VIDEO_R[0] +set_location_assignment PIN_AC22 -to VIDEO_R_0 +set_location_assignment PIN_AA18 -to VIDEO_R[1] +set_location_assignment PIN_AA18 -to VIDEO_R_1 +set_location_assignment PIN_AE23 -to VIDEO_R[2] +set_location_assignment PIN_AE23 -to VIDEO_R_2 +set_location_assignment PIN_AD23 -to VIDEO_R[3] +set_location_assignment PIN_AD23 -to VIDEO_R_3 +set_location_assignment PIN_AH18 -to VIDEO_R[4] +set_location_assignment PIN_AH18 -to VIDEO_R_4 +set_location_assignment PIN_AG21 -to VIDEO_R[5] +set_location_assignment PIN_AG21 -to VIDEO_R_5 +set_location_assignment PIN_AH21 -to VIDEO_R[6] +set_location_assignment PIN_AH21 -to VIDEO_R_6 +set_location_assignment PIN_AH19 -to VIDEO_R[7] +set_location_assignment PIN_AH19 -to VIDEO_R_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7 + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_P -tag __hps_sdram_p0 +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_P -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_N -tag __hps_sdram_p0 +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[0] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[10] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[11] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[12] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[13] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[14] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[1] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[2] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[3] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[4] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[5] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[6] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[7] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[8] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[9] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[0] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[1] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[2] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CAS_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CKE -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CS_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ODT -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RAS_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_WE_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RESET_N -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[10] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[11] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[12] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[13] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[14] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[4] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[5] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[6] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[7] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[8] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[9] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CAS_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CKE -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CS_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ODT -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RAS_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_WE_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RESET_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_P -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_N -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -tag __hps_sdram_p0 +set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0 +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0 +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON +set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name ECO_REGENERATE_REPORT ON diff --git a/cs309-psoc/lab_4_0/hw/quartus/lab_4_0.sdc b/cs309-psoc/lab_4_0/hw/quartus/lab_4_0.sdc new file mode 100644 index 0000000..16a41f3 --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/quartus/lab_4_0.sdc @@ -0,0 +1,6 @@ +create_clock -period 20 [get_ports FPGA_CLK1_50] +create_clock -period 20 [get_ports FPGA_CLK2_50] +create_clock -period 20 [get_ports FPGA_CLK3_50] + +derive_pll_clocks +derive_clock_uncertainty diff --git a/cs309-psoc/lab_4_0/hw/quartus/soc_system.qsys b/cs309-psoc/lab_4_0/hw/quartus/soc_system.qsys new file mode 100644 index 0000000..869db4c --- /dev/null +++ b/cs309-psoc/lab_4_0/hw/quartus/soc_system.qsys @@ -0,0 +1,1197 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,Yes,Yes,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + 0x000000000000000000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Create an adjpllin signal to connect with an upstream PLL + + + + + + + + + + + + + + + + + + + + + + + + Automatic Switchover + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_4_0/lab_4_0.pdf b/cs309-psoc/lab_4_0/lab_4_0.pdf new file mode 100644 index 0000000..70c6a39 Binary files /dev/null and b/cs309-psoc/lab_4_0/lab_4_0.pdf differ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/app.c b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/app.c new file mode 100644 index 0000000..2794add --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/app.c @@ -0,0 +1,6 @@ +#include + +int main(void) { + /* TODO : complete this function with your application */ + return EXIT_SUCCESS; +} diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/batman_320x240.jpg b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/batman_320x240.jpg new file mode 100644 index 0000000..d5c2252 Binary files /dev/null and b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/batman_320x240.jpg differ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/batman_480x272.jpg b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/batman_480x272.jpg new file mode 100644 index 0000000..eae4bad Binary files /dev/null and b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/batman_480x272.jpg differ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/fb_multiple_buffering_example.c b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/fb_multiple_buffering_example.c new file mode 100644 index 0000000..32d1847 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/fb_multiple_buffering_example.c @@ -0,0 +1,84 @@ +/** + * @author Philemon Favrod + * @brief Example of ping-pong buffering using the framebuffer. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct fb_fix_screeninfo fix_info; +struct fb_var_screeninfo var_info; +uint32_t *frame_buffer; +int num_buffers; +int num_pixels_per_buffer; +int fb_fd; + +inline uint32_t make_color(uint8_t red, uint8_t green, uint8_t blue) +{ + uint32_t r = red << var_info.red.offset; + uint32_t g = green << var_info.green.offset; + uint32_t b = blue << var_info.blue.offset; + return r | g | b; +} + +int main(void) +{ + fb_fd = open("/dev/fb0", O_RDWR); + assert(fb_fd >= 0); + + // Get screen information + int ret = ioctl(fb_fd, FBIOGET_FSCREENINFO, &fix_info); + assert(ret >= 0); + + ret = ioctl(fb_fd, FBIOGET_VSCREENINFO, &var_info); + assert(ret >= 0); + + // Map the frame buffer in user memory + frame_buffer = mmap(NULL, var_info.yres_virtual * fix_info.line_length, PROT_READ | PROT_WRITE, MAP_SHARED, fb_fd, 0); + assert(frame_buffer != MAP_FAILED); + + // Reminder: with prsoc_fbdev driver the number of buffer can be changed in the device tree + num_buffers = (var_info.yres_virtual * var_info.xres_virtual) / (var_info.xres * var_info.yres); + num_pixels_per_buffer = var_info.yres * var_info.xres; + + int buffer_idx; + for (buffer_idx = 0; buffer_idx < num_buffers; ++buffer_idx) { + + // Compute the color of the buffer + // Buffers 0, 3, 6, ... will be red + // Buffers 1, 4, 7, ... will be green + // Buffers 2, 5, 8, ... will be blue + uint32_t color = make_color(0xff, 0, 0); + if (buffer_idx % 3 == 1) { + color = make_color(0, 0xff, 0); + } else if (buffer_idx % 3 == 2) { + color = make_color(0, 0, 0xff); + } + + int pixel_idx; + for (pixel_idx = buffer_idx * num_pixels_per_buffer; pixel_idx < (buffer_idx + 1) * num_pixels_per_buffer; ++pixel_idx) { + frame_buffer[pixel_idx] = color; + } + } + + while (1) { + int i; + + for (i = 0; i < num_buffers; ++i) { + var_info.yoffset = i * var_info.yres; + ret = ioctl(fb_fd, FBIOPAN_DISPLAY, &var_info); + assert(ret >= 0); + + usleep(3000000); + } + } + + + return 0; +} diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/fbv b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/fbv new file mode 100755 index 0000000..d8f27bc Binary files /dev/null and b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/displays/fbv differ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/iorw.h b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/iorw.h new file mode 100644 index 0000000..67b35a6 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/iorw.h @@ -0,0 +1,24 @@ +#ifndef __IORW_H__ +#define __IORW_H__ + +#ifdef __nios2_arch__ + #include + + #define io_write_8(base, ofst, data) (IOWR_8DIRECT((base), (ofst), (data))) + #define io_write_16(base, ofst, data) (IOWR_16DIRECT((base), (ofst), (data))) + #define io_write_32(base, ofst, data) (IOWR_32DIRECT((base), (ofst), (data))) + #define io_read_8(base, ofst) (IORD_8DIRECT((base), (ofst))) + #define io_read_16(base, ofst) (IORD_16DIRECT((base), (ofst))) + #define io_read_32(base, ofst) (IORD_32DIRECT((base), (ofst))) +#else + #include + + #define io_write_8(base, ofst, data) (alt_write_byte((uintptr_t) (base) + (ofst), (data))) + #define io_write_16(base, ofst, data) (alt_write_hword((uintptr_t) (base) + (ofst), (data))) + #define io_write_32(base, ofst, data) (alt_write_word((uintptr_t) (base) + (ofst), (data))) + #define io_read_8(base, ofst) (alt_read_byte((uintptr_t) (base) + (ofst))) + #define io_read_16(base, ofst) (alt_read_hword((uintptr_t) (base) + (ofst))) + #define io_read_32(base, ofst) (alt_read_word((uintptr_t) (base) + (ofst))) +#endif + +#endif \ No newline at end of file diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/joysticks.c b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/joysticks.c new file mode 100644 index 0000000..a84c8d4 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/joysticks.c @@ -0,0 +1,79 @@ +#include "joysticks.h" + +#define JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL (0) +#define JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL (1) +#define JOYSTICK_LEFT_VRY_MCP3204_CHANNEL (2) +#define JOYSTICK_LEFT_VRX_MCP3204_CHANNEL (3) + +/** + * joysticks_inst + * + * Instantiate a joysticks device structure. + * + * @param base Base address of the MCP3204 component connected to the joysticks. + */ +joysticks_dev joysticks_inst(void *mcp3204_base) { + joysticks_dev dev; + dev.mcp3204 = mcp3204_inst((void *) mcp3204_base); + + return dev; +} + +/** + * joysticks_init + * + * Initializes the joysticks device. + * + * @param dev joysticks device structure. + */ +void joysticks_init(joysticks_dev *dev) { + mcp3204_init(&(dev->mcp3204)); +} + +/** + * joysticks_read_left_vertical + * + * Returns the vertical position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204, JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL); +} + +/** + * joysticks_read_left_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204, JOYSTICK_LEFT_VRX_MCP3204_CHANNEL); +} + +/** + * joysticks_read_right_vertical + * + * Returns the vertical position of the right joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204, JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL); +} + +/** + * joysticks_read_right_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204, JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL); +} diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/joysticks.h b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/joysticks.h new file mode 100644 index 0000000..ac9c383 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/joysticks.h @@ -0,0 +1,27 @@ +#ifndef __JOYSTICKS_H__ +#define __JOYSTICKS_H__ + +#include "mcp3204/mcp3204.h" + +/* joysticks device structure */ +typedef struct joysticks_dev { + mcp3204_dev mcp3204; /* MCP3204 device handle */ +} joysticks_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define JOYSTICKS_MIN_VALUE (MCP3204_MIN_VALUE) +#define JOYSTICKS_MAX_VALUE (MCP3204_MAX_VALUE) + +joysticks_dev joysticks_inst(void *mcp3204_base); + +void joysticks_init(joysticks_dev *dev); + +uint32_t joysticks_read_left_vertical(joysticks_dev *dev); +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev); +uint32_t joysticks_read_right_vertical(joysticks_dev *dev); +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev); + +#endif /* __JOYSTICKS_H__ */ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/mcp3204/mcp3204.c b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/mcp3204/mcp3204.c new file mode 100644 index 0000000..1210e31 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/mcp3204/mcp3204.c @@ -0,0 +1,44 @@ +#include "mcp3204.h" +#include "iorw.h" + +#define MCP3204_NUM_CHANNELS (4) + +/** + * mcp3204_inst + * + * Instantiate a mcp3204 device structure. + * + * @param base Base address of the component. + */ +mcp3204_dev mcp3204_inst(void *base) { + mcp3204_dev dev; + dev.base = base; + + return dev; +} + +/** + * mcp3204_init + * + * Initializes the mcp3204 device. + * + * @param dev mcp3204 device structure. + */ +void mcp3204_init(mcp3204_dev *dev) { + return; +} + +/** + * mcp3204_read + * + * Reads the register corresponding to the supplied channel parameter. + * + * @param dev mcp3204 device structure. + * @param channel channel to be read + */ +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) { + if (channel >= 4) + return 0; + + return io_read_32(dev->base, channel * 4); +} diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/mcp3204/mcp3204.h b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/mcp3204/mcp3204.h new file mode 100644 index 0000000..3b2b2e6 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/mcp3204/mcp3204.h @@ -0,0 +1,23 @@ +#ifndef __MCP3204_H__ +#define __MCP3204_H__ + +#include + +/* mcp3204 device structure */ +typedef struct mcp3204_dev { + void *base; /* Base address of component */ +} mcp3204_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define MCP3204_MIN_VALUE (0) +#define MCP3204_MAX_VALUE (4095) + +mcp3204_dev mcp3204_inst(void *base); + +void mcp3204_init(mcp3204_dev *dev); +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel); + +#endif /* __MCP3204_H__ */ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/mcp3204/mcp3204_regs.h b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/mcp3204/mcp3204_regs.h new file mode 100644 index 0000000..b1c78cd --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/joysticks/mcp3204/mcp3204_regs.h @@ -0,0 +1,9 @@ +#ifndef __MCP3204_REGS_H__ +#define __MCP3204_REGS_H__ + +#define MCP3204_CHANNEL_0_OFST (0 * 4) /* RO */ +#define MCP3204_CHANNEL_1_OFST (1 * 4) /* RO */ +#define MCP3204_CHANNEL_2_OFST (2 * 4) /* RO */ +#define MCP3204_CHANNEL_3_OFST (3 * 4) /* RO */ + +#endif /* __MCP3204_REGS_H__ */ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/lepton/lepton.c b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/lepton/lepton.c new file mode 100644 index 0000000..64cfcf1 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/lepton/lepton.c @@ -0,0 +1,117 @@ +#include +#include +#include +#include + +#include "lepton_regs.h" +#include "lepton.h" +#include "iorw.h" + +/** + * lepton_inst + * + * Instantiate a lepton device structure. + * + * @param base Base address of the component. + */ +lepton_dev lepton_inst(void *base) { + lepton_dev dev; + dev.base = base; + + return dev; +} + +/** + * lepton_init + * + * Initializes the lepton device. + * + * @param dev lepton device structure. + */ +void lepton_init(lepton_dev *dev) { + return; +} + +/** + * lepton_start_capture + * + * Instructs the device to start the frame capture process. + * + * @param dev lepton device structure. + */ +void lepton_start_capture(lepton_dev *dev) { + io_write_16(dev->base, LEPTON_REGS_COMMAND_OFST, 0x1); +} + +/** + * lepton_error_check + * + * @abstract Check for errors at the device level. + * @param dev lepton device structure. + * @return true if there was an error, and false otherwise. + */ +bool lepton_error_check(lepton_dev *dev) { + return (io_read_16(dev->base, LEPTON_REGS_STATUS_OFST) & 0x2) != 0; +} + +/** + * lepton_wait_until_eof + * + * Waits until the frame being captured has been fully received and saved in the + * internal memory. + * + * @param dev lepton device structure. + */ +void lepton_wait_until_eof(lepton_dev *dev) { + while (io_read_16(dev->base, LEPTON_REGS_STATUS_OFST) & 0x1); +} + +/** + * lepton_save_capture + * + * Saves the captured frame on the host filesystem under the supplied filename. + * The frame will be saved in PGM format. + * + * @param dev lepton device structure. + * @param adjusted Setting this parameter to false will cause RAW sensor data to + * be written to the file. + * Setting this parameter to true will cause a preprocessed image + * (with a stretched dynamic range) to be saved to the file. + * + * @param fname the output file name. + */ +void lepton_save_capture(lepton_dev *dev, bool adjusted, FILE* file) { + assert(file); + + const uint8_t num_rows = 60; + const uint8_t num_cols = 80; + + uint16_t offset = LEPTON_REGS_RAW_BUFFER_OFST; + uint16_t max_value = io_read_16(dev->base, LEPTON_REGS_MAX_OFST); + if (adjusted) { + offset = LEPTON_REGS_ADJUSTED_BUFFER_OFST; + max_value = 0x3fff; + } + + /* Write PGM header */ + fprintf(file, "P2\n%" PRIu8 " %" PRIu8 "\n%" PRIu16, num_cols, num_rows, max_value); + + /* Write body */ + uint8_t row = 0; + for (row = 0; row < num_rows; ++row) { + fprintf(file, "\n"); + + uint8_t col = 0; + for (col = 0; col < num_cols; ++col) { + if (col > 0) { + fprintf(file, " "); + } + + uint16_t current_ofst = offset + (row * num_cols + col) * sizeof(uint16_t); + uint16_t pix_value = io_read_16(dev->base, current_ofst); + fprintf(file, "%" PRIu16, pix_value); + } + } + + assert(!fclose(file)); +} diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/lepton/lepton.h b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/lepton/lepton.h new file mode 100644 index 0000000..b642abb --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/lepton/lepton.h @@ -0,0 +1,23 @@ +#ifndef __LEPTON_H__ +#define __LEPTON_H__ + +#include + +/* lepton device structure */ +typedef struct { + void *base; /* Base address of the component */ +} lepton_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +lepton_dev lepton_inst(void *base); + +void lepton_init(lepton_dev *dev); +void lepton_start_capture(lepton_dev *dev); +void lepton_wait_until_eof(lepton_dev *dev); +bool lepton_error_check(lepton_dev *dev); +void lepton_save_capture(lepton_dev *dev, bool adjusted, FILE* file); + +#endif /* __LEPTON_H__ */ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/lepton/lepton_regs.h b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/lepton/lepton_regs.h new file mode 100644 index 0000000..db24244 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/lepton/lepton_regs.h @@ -0,0 +1,25 @@ +#ifndef __LEPTON_REGS_H__ +#define __LEPTON_REGS_H__ + +/* Register offsets */ +#define LEPTON_REGS_COMMAND_OFST ( 0 * 2) /* WO */ +#define LEPTON_REGS_STATUS_OFST ( 1 * 2) /* RO */ +#define LEPTON_REGS_MIN_OFST ( 2 * 2) /* RO */ +#define LEPTON_REGS_MAX_OFST ( 3 * 2) /* RO */ +#define LEPTON_REGS_SUM_LSB_OFST ( 4 * 2) /* RO */ +#define LEPTON_REGS_SUM_MSB_OFST ( 5 * 2) /* RO */ +#define LEPTON_REGS_ROW_IDX_OFST ( 6 * 2) /* RO */ +#define LEPTON_REGS_RAW_BUFFER_OFST ( 8 * 2) /* RO */ +#define LEPTON_REGS_ADJUSTED_BUFFER_OFST (8192 * 2) /* RO */ + +/* Command register */ +#define LEPTON_COMMAND_START (0x0001) + +/* Status register */ +#define LEPTON_STATUS_CAPTURE_IN_PROGRESS_MASK (1 << 0) +#define LEPTON_STATUS_ERROR_MASK (1 << 1) + +#define LEPTON_REGS_BUFFER_NUM_PIXELS (80 * 60) +#define LEPTON_REGS_BUFFER_BYTELENGTH (LEPTON_REGS_BUFFER_NUM_PIXELS * 2) + +#endif /* __LEPTON_REGS_H__ */ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pantilt.c b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pantilt.c new file mode 100644 index 0000000..d9c4c72 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pantilt.c @@ -0,0 +1,109 @@ +#include "pantilt.h" + +/** + * pantilt_inst + * + * Instantiate a pantilt device structure. + * + * @param pwm_v_base Base address of the vertical PWM component. + * @param pwm_h_base Base address of the horizontal PWM component. + */ +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) { + pantilt_dev dev; + dev.pwm_v = pwm_inst(pwm_v_base); + dev.pwm_h = pwm_inst(pwm_h_base); + + return dev; +} + +/** + * pantilt_init + * + * Initializes the pantilt device. + * + * @param dev pantilt device structure. + */ +void pantilt_init(pantilt_dev *dev) { + pwm_init(&(dev->pwm_v)); + pwm_init(&(dev->pwm_h)); +} + +/** + * pantilt_configure_vertical + * + * Configure the vertical PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_v), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_configure_horizontal + * + * Configure the horizontal PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_h), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_start_vertical + * + * Starts the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_vertical(pantilt_dev *dev) { + pwm_start(&(dev->pwm_v)); +} + +/** + * pantilt_start_horizontal + * + * Starts the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_horizontal(pantilt_dev *dev) { + pwm_start(&(dev->pwm_h)); +} + +/** + * pantilt_stop_vertical + * + * Stops the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_vertical(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_v)); +} + +/** + * pantilt_stop_horizontal + * + * Stops the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_horizontal(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_h)); +} diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pantilt.h b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pantilt.h new file mode 100644 index 0000000..1f17500 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pantilt.h @@ -0,0 +1,39 @@ +#ifndef __PANTILT_H__ +#define __PANTILT_H__ + +#include "pwm/pwm.h" + +/* joysticks device structure */ +typedef struct pantilt_dev { + pwm_dev pwm_v; /* Vertical PWM device handle */ + pwm_dev pwm_h; /* Horizontal PWM device handle */ +} pantilt_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz + +#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms + +/* Vertical servo */ +#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms +#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms + +/* Horizontal servo */ +#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms +#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms + +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base); + +void pantilt_init(pantilt_dev *dev); + +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_start_vertical(pantilt_dev *dev); +void pantilt_start_horizontal(pantilt_dev *dev); +void pantilt_stop_vertical(pantilt_dev *dev); +void pantilt_stop_horizontal(pantilt_dev *dev); + +#endif /* __PANTILT_H__ */ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pwm/pwm.c b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pwm/pwm.c new file mode 100644 index 0000000..39fa34d --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pwm/pwm.c @@ -0,0 +1,68 @@ +#include "pwm.h" +#include "pwm_regs.h" +#include "iorw.h" + +#define MICROSEC_TO_CLK(time, freq) ((time) * ((freq) / 1000000)) + +/** + * pwm_inst + * + * Instantiate a pwm device structure. + * + * @param base Base address of the component. + */ +pwm_dev pwm_inst(void *base) { + pwm_dev dev; + + dev.base = base; + + return dev; +} + +/** + * pwm_init + * + * Initializes the pwm device. This function stops the controller. + * + * @param dev pwm device structure. + */ +void pwm_init(pwm_dev *dev) { + pwm_stop(dev); +} + +/** + * pwm_configure + * + * Configure pwm component. + * + * @param dev pwm device structure. + * @param duty_cycle pwm duty cycle in us. + * @param period pwm period in us. + * @param module_frequency frequency at which the component is clocked. + */ +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) { + io_write_32(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency)); + io_write_32(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency)); +} + +/** + * pwm_start + * + * Starts the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_start(pwm_dev *dev) { + io_write_32(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} + +/** + * pwm_stop + * + * Stops the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_stop(pwm_dev *dev) { + io_write_32(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pwm/pwm.h b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pwm/pwm.h new file mode 100644 index 0000000..e2987f4 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pwm/pwm.h @@ -0,0 +1,21 @@ +#ifndef __PWM_H__ +#define __PWM_H__ + +#include + +/* pwm device structure */ +typedef struct pwm_dev { + void *base; /* Base address of component */ +} pwm_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ +pwm_dev pwm_inst(void *base); + +void pwm_init(pwm_dev *dev); +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency); +void pwm_start(pwm_dev *dev); +void pwm_stop(pwm_dev *dev); + +#endif /* __PWM_H__ */ diff --git a/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pwm/pwm_regs.h b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pwm/pwm_regs.h new file mode 100644 index 0000000..488583d --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/application/lab_4_0/pantilt/pwm/pwm_regs.h @@ -0,0 +1,11 @@ +#ifndef __PWM_REGS_H__ +#define __PWM_REGS_H__ + +#define PWM_PERIOD_OFST (0 * 4) /* RW */ +#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */ +#define PWM_CTRL_OFST (2 * 4) /* WO */ + +#define PWM_CTRL_STOP_MASK (0) +#define PWM_CTRL_START_MASK (1) + +#endif /* __PWM_REGS_H__ */ diff --git a/cs309-psoc/lab_4_0/sw/hps/linux/device_tree/socfpga_cyclone5_de0_sockit_prsoc.dts b/cs309-psoc/lab_4_0/sw/hps/linux/device_tree/socfpga_cyclone5_de0_sockit_prsoc.dts new file mode 100644 index 0000000..f6e5d4a --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/linux/device_tree/socfpga_cyclone5_de0_sockit_prsoc.dts @@ -0,0 +1,37 @@ +#include "socfpga_cyclone5_de0_sockit.dts" +#include +#include + +#define VGA_SEQUENCER_REG_CSR 0x00 +#define VGA_SEQUENCER_REG_HBP 0x04 +#define VGA_SEQUENCER_REG_HFP 0x08 +#define VGA_SEQUENCER_REG_VBP 0x0c +#define VGA_SEQUENCER_REG_VFP 0x10 +#define VGA_SEQUENCER_REG_HDATA 0x14 +#define VGA_SEQUENCER_REG_VDATA 0x18 +#define VGA_SEQUENCER_REG_HSYNC 0x1c +#define VGA_SEQUENCER_REG_VSYNC 0x20 + +/ { + soc { + display { + compatible = "prsoc,display"; + reg = <0xff200080 0x40 /* Frame manager
*/ + 0xff200000 0x80>; /* VGA sequencer
*/ + interrupts = ; + prsoc,screen-width = <480>; + prsoc,screen-height = <272>; + prsoc,buffer-width = <480>; + prsoc,buffer-height = <544>; // -> 2 buffers + prsoc,reg-init = , + , + , + , + , + , + , + , + ; + }; + }; +}; diff --git a/cs309-psoc/lab_4_0/sw/hps/linux/driver/fbdev/Makefile b/cs309-psoc/lab_4_0/sw/hps/linux/driver/fbdev/Makefile new file mode 100644 index 0000000..275fdda --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/linux/driver/fbdev/Makefile @@ -0,0 +1,9 @@ +obj-m += prsoc_fbdev.o + +KERNEL_SOURCE_PATH='../../source/' + +all: + make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -C $(KERNEL_SOURCE_PATH) M=$(PWD) modules + +clean: + make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -C $(KERNEL_SOURCE_PATH) clean diff --git a/cs309-psoc/lab_4_0/sw/hps/linux/driver/fbdev/prsoc_fbdev.c b/cs309-psoc/lab_4_0/sw/hps/linux/driver/fbdev/prsoc_fbdev.c new file mode 100644 index 0000000..29675da --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/linux/driver/fbdev/prsoc_fbdev.c @@ -0,0 +1,416 @@ +/* + * @file prsoc_vga_fbdev + * @author Philemon Favrod + * @date 18 May 2016 + * @brief The framebuffer Linux driver for the PrSoC extension board. + * + * This file is divided in two sections. The first contains the framebuffer + * driver code. The second contains the boilerplate code to create the + * device associated with the framebuffer. The latter allow us to use + * much less error-prone APIs (devm_* or dmam_*). + * + * More precisely, the LCD is viewed as a platform device, i.e. a device + * that is directly addressable from the CPU. Platform device are loaded + * based on their compatible string (here "prsoc,display"). In other words, + * once this driver is known to the kernel (c.f. insmod), the kernel will + * call its associated probe function if its associated compatible string + * is present in a device node (= an element of the device tree). + * + * In our case, the probe function is prsoc_display_platform_probe that you + * can find at the end of this file. Its main role is to allocate the resources + * based on what the device tree says. It uses the so-called managed API to + * do so. This API has the advantage of letting the kernel do the clean up based on + * whether or not the driver is loaded. It makes the code more readable. + * At the end of the probe function, the framebuffer is registered. + * + * For more information about this, here is a collection of resources that + * might be helpful: + * - https://www.kernel.org/doc/Documentation/driver-model/platform.txt + * - + * + * Revisions: + * 5/18/2016 Created (only for simple VGA) + * 5/28/2016 Adapted for TFT043 + * 5/28/2016 Extended with mmap support + * 6/15/2016 Extend configurability from DT + panning + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Offsets of the framebuffer manager's registers. */ +#define FM_REG_FRAME_START_ADDRESS 0x00 +#define FM_REG_FRAME_PIX_PER_LINE 0x04 +#define FM_REG_FRAME_NUM_LINES 0x08 +#define FM_REG_FRAME_EOL_BYTE_OFST 0x0C +#define FM_REG_CONTROL 0x10 +#define FM_REG_BURST_COUNT 0x14 + + +#define FM_CONTROL_ENABLE_DMA_MASK (1UL << 0) +#define FM_CONTROL_ENABLE_IRQ_MASK (1UL << 2) +#define FM_CONTROL_ACKNOWLEDGE_IRQ_MASK (1UL << 4) + + +/* Enclose the driver data. */ +struct prsoc_display_drvdata { + uint8_t *fm_regs; /* a pointer to the frame manager's regs */ + uint8_t *lcd_int_regs; /* a pointer to the LCD interface's regs */ + + uint32_t *front_buffer; /* a dmable frame buffer */ + unsigned long front_buffer_phys; /* physical address of the frame buffer */ + int irq; +}; + +#define FM_WR(DRVDATA, REG, VAL) \ + iowrite32((VAL), (DRVDATA)->fm_regs + (REG)) +#define LCD_INTERFACE_WR(DRVDATA, REG, VAL) \ + iowrite32((VAL), (DRVDATA)->lcd_int_regs + (REG)) + +/* Framebuffer driver */ + +/* ISR called at the end of each frame. Called at the beginning + * of the vertical back porch, i.e. as soon as possible to avoid + * tearing effect. */ +static irqreturn_t vsync_isr(int irq, void *data) +{ + /*printk("IRQ received.\n");*/ + + //int i; + struct prsoc_display_drvdata *drvdata = data; + + /* Acknowledge the IRQ */ + FM_WR(drvdata, FM_REG_CONTROL, FM_CONTROL_ACKNOWLEDGE_IRQ_MASK); + + return IRQ_HANDLED; +} + +/* Defaults screen parameters */ +static struct fb_fix_screeninfo prsocfb_fix_defaults = { + .id = "prsocfb", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_DIRECTCOLOR, + .accel = FB_ACCEL_NONE, + .ypanstep = 1 // support y panning +}; + +static struct fb_var_screeninfo prsocfb_var_defaults = { + .bits_per_pixel = 32, + .red = { .offset = 16, .length = 8 }, + .green = { .offset = 8, .length = 8 }, + .blue = { .offset = 0, .length = 8 } +}; + +uint32_t pseudo_palette[16]; +static int prsocfb_setcoloreg(unsigned regno, unsigned red, + unsigned green, unsigned blue, + unsigned transp, struct fb_info *info) +{ + if (regno >= 16) + return -EINVAL; + + red *= 0xff; + green *= 0xff; + blue *= 0xff; + + red /= 0xffff; + green /= 0xffff; + blue /= 0xffff; + + pseudo_palette[regno] = (red << 16) | (green << 8) | blue; + return 0; +} + +int prsocfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct prsoc_display_drvdata *drvdata = (struct prsoc_display_drvdata *)info->par; + uint32_t byte_offset; + + if ((var->yoffset + var->yres > var->yres_virtual) || + (var->xoffset + var->xres > var->xres_virtual)) + { + return -EINVAL; + } + + byte_offset = (var->yoffset * info->fix.line_length) + + (var->xoffset * (var->bits_per_pixel / 8)); + + FM_WR(drvdata, FM_REG_FRAME_START_ADDRESS, drvdata->front_buffer_phys + byte_offset); + + return 0; +} + + +/* purpose: mmap the front buffer. */ +static int prsocfb_mmap(struct fb_info *info, + struct vm_area_struct *vma) +{ + struct prsoc_display_drvdata *drvdata = (struct prsoc_display_drvdata *)info->par; + unsigned long start = vma->vm_start; + unsigned long size = vma->vm_end - vma->vm_start; + unsigned long screen_size = info->var.xres_virtual * info->var.yres_virtual * sizeof(uint32_t); + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + unsigned long pfn = -1; + void * pos = phys_to_virt(drvdata->front_buffer_phys) + offset; + + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); // non cachable page + vma->vm_flags |= VM_IO; + + /* Compute the screen size in PAGE_SIZE. */ + screen_size += PAGE_SIZE - 1; + screen_size >>= PAGE_SHIFT; + screen_size <<= PAGE_SHIFT; + + /* Make sure that it maps only the back buffer */ + if (offset + size > screen_size) { + printk(KERN_ERR "prsocfb: trying to mmap too much memory. %lu %lu %lu\n", + offset, size, screen_size); + return -EINVAL; + } + + while (size > 0) { + /* Extract the page number of the current position + * in the buffer. */ + pfn = virt_to_pfn(pos); + + /* Map it in the user virtual memory. */ + if (remap_pfn_range(vma, start, pfn, PAGE_SIZE, vma->vm_page_prot)) { + printk(KERN_ERR "prsocfb: remap_pfn_range failed\n"); + return -EAGAIN; + } + + start += PAGE_SIZE; + pos += PAGE_SIZE; + + if (size > PAGE_SIZE) + size -= PAGE_SIZE; + else + size = 0; + } + + return 0; +} + +static struct fb_ops prsocfb_ops = { + .owner = THIS_MODULE, + .fb_setcolreg = prsocfb_setcoloreg, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_mmap = prsocfb_mmap, + .fb_pan_display = prsocfb_pan_display +}; + +/* Platform driver */ + +/* Informs the kernel of the corresponding compatible string. */ +static const struct of_device_id prsoc_display_device_ids[] = { + { .compatible = "prsoc,display" }, + { } +}; +MODULE_DEVICE_TABLE(of, prsoc_display_device_ids); + +/* To understand Device tree parsing, see: + * - http://xillybus.com/tutorials/device-tree-zynq-4 + * - http://xillybus.com/tutorials/device-tree-zynq-5 + */ +#define EXTRACT_INT_FROM_DT_OR_FAIL(NP, PROP) ({ \ + const void *property = of_get_property((NP), (PROP), NULL); \ + if (!property) { \ + printk(KERN_ERR "no '" PROP "' in the device tree."); \ + return -EINVAL; \ + } \ + be32_to_cpup(property); \ +}) + +/* Apply configuration from device tree. */ +static int configure_from_dt( + struct platform_device *pdev, + struct prsoc_display_drvdata *drvdata, + struct fb_fix_screeninfo *fix_screeninfo, + struct fb_var_screeninfo *var_screeninfo) +{ + struct resource *rsrc; + int err, i; + + const __be32 *properties; + int len; + + /* Extract a pointer to the device node. */ + struct device_node *np = pdev->dev.of_node; + dma_addr_t phys; + + /* Get the width and height properties. */ + uint32_t screen_width = EXTRACT_INT_FROM_DT_OR_FAIL(np, "prsoc,screen-width"); + uint32_t screen_height = EXTRACT_INT_FROM_DT_OR_FAIL(np, "prsoc,screen-height"); + uint32_t buffer_width = EXTRACT_INT_FROM_DT_OR_FAIL(np, "prsoc,buffer-width"); + uint32_t buffer_height = EXTRACT_INT_FROM_DT_OR_FAIL(np, "prsoc,buffer-height"); + + printk(KERN_INFO "According to the device tree, the screen is %ux%u and the buffer is %ux%u.", + screen_width, screen_height, buffer_width, buffer_height); + + /* Maps the addresses of the registers of the framebuffer manager. */ + rsrc = platform_get_resource(pdev, IORESOURCE_MEM, 0); + drvdata->fm_regs = devm_ioremap_resource(&pdev->dev, rsrc); + if (IS_ERR(drvdata->fm_regs)) + return PTR_ERR(drvdata->fm_regs); + + printk(KERN_INFO "Framebuffer manager regs @ 0x%x-0x%x\n", + rsrc->start, rsrc->end); + + /* Maps the addresses of the video interface. */ + rsrc = platform_get_resource(pdev, IORESOURCE_MEM, 1); + drvdata->lcd_int_regs = devm_ioremap_resource(&pdev->dev, rsrc); + if (IS_ERR(drvdata->lcd_int_regs)) + return PTR_ERR(drvdata->lcd_int_regs); + + printk(KERN_INFO "Interface regs @ 0x%x-0x%x\n", rsrc->start, + rsrc->end); + + /* Register the ISR for vertical blanking notification. */ + drvdata->irq = platform_get_irq(pdev, 0); + err = devm_request_irq( + &pdev->dev, drvdata->irq, + (irq_handler_t) vsync_isr, + 0, "prsoc-fbdev", drvdata); + if (err) { + printk(KERN_ERR "couldn't register ISR. Is 'interrupts' " \ + "field in the device tree?\n"); + return -ENXIO; + } + + /* Set the screeninfo to default values */ + *fix_screeninfo = prsocfb_fix_defaults; + *var_screeninfo = prsocfb_var_defaults; + + /* Set the size properties */ + var_screeninfo->xres = screen_width; + var_screeninfo->yres = screen_height; + var_screeninfo->xres_virtual = buffer_width; + var_screeninfo->yres_virtual = buffer_height; + fix_screeninfo->line_length = screen_width * sizeof(uint32_t); + + /* Allocate DMAble frame buffer. */ + drvdata->front_buffer = dmam_alloc_coherent( + &pdev->dev, + buffer_width * buffer_height * sizeof(uint32_t), + &phys, + GFP_KERNEL); + + if (!drvdata->front_buffer) { + printk(KERN_ERR "prsoc_fbdev: couldn't allocate a dmable buffer.\n"); + return -ENOMEM; + } + + drvdata->front_buffer_phys = (unsigned long)phys; + printk(KERN_INFO "DMABLE BUFFER @ 0x%lx\n", drvdata->front_buffer_phys); + + /* Parse the reg-init sequence */ + properties = of_get_property(pdev->dev.of_node, "prsoc,reg-init", &len); + + if (!properties) { + printk(KERN_INFO "no 'prsoc,reg-init' property found in Device Tree.\n"); + return 0; // reg-init is optional + } + + len /= sizeof(__be32); + + if (len % 2 != 0) { + printk(KERN_ERR "'prsoc,reg-init' in Device Tree should have format , , ...\n"); + return -EINVAL; + } + + printk(KERN_INFO "Initialize registers as specified in Device Tree:\n"); + for (i = 0; i < len; i += 2) { + uint32_t offset = be32_to_cpup(properties + i); + uint32_t value = be32_to_cpup(properties + i + 1); + LCD_INTERFACE_WR(drvdata, offset, value); + printk(KERN_INFO "\tWrite 0x%x at offset 0x%x\n", value, offset); + } + + return 0; +} + +/* + * The following method is called when the driver is loaded. + * It collects information from the device tree. + */ +static int +prsoc_display_platform_probe(struct platform_device *pdev) +{ + struct prsoc_display_drvdata *drvdata; + struct fb_info *info; + + /* Defensive programming: let's make sure this is the right device. */ + if (!of_match_device(prsoc_display_device_ids, &pdev->dev)) + return -EINVAL; + + /* Allocate the framebuffer. */ + info = framebuffer_alloc(sizeof(struct prsoc_display_drvdata), &pdev->dev); + if (!info) { + return -ENOMEM; + } + + /* Extract the allocated driver data structure. */ + drvdata = (struct prsoc_display_drvdata *)info->par; + + platform_set_drvdata(pdev, drvdata); + + printk(KERN_INFO "Configure from Device Tree.\n"); + configure_from_dt(pdev, drvdata, &info->fix, &info->var); + + printk(KERN_INFO "Initialize the Frame Manager.\n"); + FM_WR(drvdata, FM_REG_FRAME_START_ADDRESS, drvdata->front_buffer_phys); + FM_WR(drvdata, FM_REG_FRAME_PIX_PER_LINE, info->var.xres); + FM_WR(drvdata, FM_REG_FRAME_NUM_LINES, info->var.yres); + FM_WR(drvdata, FM_REG_FRAME_EOL_BYTE_OFST, 0); + FM_WR(drvdata, FM_REG_BURST_COUNT, 4); + FM_WR(drvdata, FM_REG_CONTROL, FM_CONTROL_ENABLE_DMA_MASK); + + /* Enable IRQ */ + // FM_WR(drvdata, FM_REG_CONTROL, FM_CONTROL_ENABLE_IRQ_MASK); + + /* Configure the framebuffer */ + info->screen_base = (void *)drvdata->front_buffer; + info->screen_size = info->var.xres * info->var.yres * sizeof(uint32_t); + info->fbops = &prsocfb_ops; + info->pseudo_palette = pseudo_palette; + info->flags = FBINFO_DEFAULT; + + if (fb_alloc_cmap(&info->cmap, 256, 0)) + return -ENOMEM; + + return register_framebuffer(info); +} + +int prsoc_display_platform_remove(struct platform_device *pdev) +{ + struct prsoc_display_drvdata *drvdata = platform_get_drvdata(pdev); + struct fb_info *info = container_of((void *)drvdata, struct fb_info, par); + + unregister_framebuffer(info); + fb_dealloc_cmap(&info->cmap); + framebuffer_release(info); + + return 0; +} + +static struct platform_driver prsoc_display_pdriver = { + .probe = prsoc_display_platform_probe, + .driver = { + .name = "PrSoC displays", + .owner = THIS_MODULE, + .of_match_table = prsoc_display_device_ids, + }, +}; + +MODULE_LICENSE("GPL"); +module_platform_driver(prsoc_display_pdriver); \ No newline at end of file diff --git a/cs309-psoc/lab_4_0/sw/hps/linux/rootfs/config_post_install.sh b/cs309-psoc/lab_4_0/sw/hps/linux/rootfs/config_post_install.sh new file mode 100755 index 0000000..33fd8db --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/linux/rootfs/config_post_install.sh @@ -0,0 +1,23 @@ +#!/bin/bash -x + +# apt sources +# uncomment the "deb" lines (no need to uncomment "deb src" lines) + +# Edit the “/etc/apt/sources.list” file to configure the package manager. This +# file contains a list of mirrors that the package manager queries. By default, +# this file has all fields commented out, so the package manager will not have +# access to any mirrors. The following command uncomments all commented out +# lines starting with "deb". These contain the mirrors we are interested in. +sudo perl -pi -e 's/^#+\s+(deb\s+http)/$1/g' "/etc/apt/sources.list" + +# When writing our linux applications, we want to use ARM DS-5’s remote +# debugging feature to automatically transfer our binaries to the target device +# and to start a debugging session. The remote debugging feature requires an SSH +# server and a remote gdb server to be available on the target. These are easy +# to install as we have a package manager available +sudo apt update +sudo apt -y install ssh gdbserver + +# Allow root SSH login with password (needed so we can use ARM DS-5 for remote +# debugging) +sudo perl -pi -e 's/^(PermitRootLogin) without-password$/$1 yes/g' "/etc/ssh/sshd_config" diff --git a/cs309-psoc/lab_4_0/sw/hps/linux/rootfs/config_system.sh b/cs309-psoc/lab_4_0/sw/hps/linux/rootfs/config_system.sh new file mode 100755 index 0000000..24e5ed7 --- /dev/null +++ b/cs309-psoc/lab_4_0/sw/hps/linux/rootfs/config_system.sh @@ -0,0 +1,94 @@ +#!/bin/bash -x + +# Configure the locale to have proper language support. +localedef -i en_US -c -f UTF-8 en_US.UTF-8 +dpkg-reconfigure locales + +# Configure the timezone. +echo "Europe/Zurich" > "/etc/timezone" +dpkg-reconfigure -f noninteractive tzdata + +# Set the machine’s hostname. +echo "DE0-Nano-SoC" > "/etc/hostname" +tee "/etc/hosts" >"/dev/null" < "/dev/null" < "/dev/null" < "/dev/null" < "/dev/null" < "${uboot_script_file}" +################################################################################ +echo --- Resetting Env variables --- + +# reset environment variables to default +env default -a + +echo --- Setting Env variables --- + +# Set the kernel image +setenv bootimage $(basename ${sdcard_fat32_zImage_file}); + +# address to which the device tree will be loaded +setenv fdtaddr 0x00000100 + +# Set the devicetree image +setenv fdtimage $(basename ${sdcard_fat32_dtb_file}); + +# set kernel boot arguments, then boot the kernel +setenv mmcboot 'setenv bootargs mem=${linux_kernel_mem_arg} console=ttyS0,115200 root=\${mmcroot} rw rootwait; \ +bootz \${loadaddr} - \${fdtaddr}'; + +# load linux kernel image and device tree to memory +setenv mmcload 'mmc rescan; \ +\${mmcloadcmd} mmc 0:\${mmcloadpart} \${loadaddr} \${bootimage}; \ +\${mmcloadcmd} mmc 0:\${mmcloadpart} \${fdtaddr} \${fdtimage}' + +# command to be executed to read from sdcard +setenv mmcloadcmd fatload + +# sdcard fat32 partition number +setenv mmcloadpart ${sdcard_partition_number_fat32} + +# sdcard ext3 identifier +setenv mmcroot /dev/mmcblk0p${sdcard_partition_number_ext3} + +# standard input/output +setenv stderr serial +setenv stdin serial +setenv stdout serial + +# save environment to sdcard (not needed, but useful to avoid CRC errors on a new sdcard) +saveenv + +################################################################################ +echo --- Programming FPGA --- + +# load rbf from FAT partition into memory +fatload mmc 0:1 \${fpgadata} $(basename ${sdcard_fat32_rbf_file}); + +# program FPGA +fpga load 0 \${fpgadata} \${filesize}; + +# enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges +bridge enable; + +################################################################################ +echo --- Booting Linux --- + +# load linux kernel image and device tree to memory +run mmcload; + +# set kernel boot arguments, then boot the kernel +run mmcboot; +EOF + + # compile uboot script to binary form + mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "${quartus_project_name}" -d "${uboot_script_file}" "${sdcard_fat32_uboot_scr_file}" + + # copy artifacts to associated sdcard directory + cp "${uboot_img_file}" "${sdcard_fat32_uboot_img_file}" + + # change working directory back to script directory + popd +} + +# compile_linux() ############################################################## +compile_linux() { + # if linux source tree doesn't exist, then download it + if [ ! -d "${linux_src_dir}" ]; then + git clone "${linux_src_git_repo}" "${linux_src_dir}" + fi + + # change working directory to linux source tree directory + pushd "${linux_src_dir}" + + # compile for the ARM architecture + export ARCH=arm + + # use cross compiler instead of standard x86 version of gcc + export CROSS_COMPILE=arm-linux-gnueabihf- + + # clean up source tree + make distclean + + # checkout the following commit (tested and working): + git checkout "${linux_src_git_checkout_commit}" + + # configure kernel for socfpga architecture + make "${linux_src_make_config_file}" + + # compile zImage + make -j4 zImage + + # compile device tree + make -j4 "$(basename "${linux_dtb_file}")" + + # copy artifacts to associated sdcard directory + cp "${linux_zImage_file}" "${sdcard_fat32_zImage_file}" + cp "${linux_dtb_file}" "${sdcard_fat32_dtb_file}" + + # change working directory back to script directory + popd +} + +# create_rootfs() ############################################################## +create_rootfs() { + # if rootfs tarball doesn't exist, then download it + if [ ! -f "${rootfs_src_tgz_file}" ]; then + wget "${rootfs_src_tgz_link}" -O "${rootfs_src_tgz_file}" + fi + + # delete old artifacts + sudo rm -rf "${rootfs_chroot_dir}" \ + "${sdcard_ext3_rootfs_tgz_file}" + + # create dir to extract rootfs + mkdir -p "${rootfs_chroot_dir}" + + # extract ubuntu core rootfs + pushd "${rootfs_chroot_dir}" + sudo tar -xzpf "${rootfs_src_tgz_file}" + popd + + # copy chroot SYSTEM configuration script to chroot directory + sudo cp "${rootfs_system_config_script_file}" "${rootfs_chroot_dir}" + + # edit chroot environment's /etc/rc.local to execute the rootfs + # configuration script + sudo tee "${rootfs_chroot_dir}/etc/rc.local" > "/dev/null" < 4095 t a2 (2048 is default first sector) + # n p 1 +32M t 1 b (4096 is default first sector) + # n p 2 +512M t 2 83 (69632 is default first sector) + # w + # result + # Device Boot Start End Sectors Size Id Type + # /dev/sdb1 4096 69631 65536 32M b W95 FAT32 + # /dev/sdb2 69632 1118207 1048576 512M 83 Linux + # /dev/sdb3 2048 4095 2048 1M a2 unknown + # note that you can choose any size for the FAT32 and Linux partitions, + # but the a2 partition must be 1M. + + # automatically partitioning the sdcard + # wipe partition table + sudo dd if="/dev/zero" of="${sdcard_dev}" bs=512 count=1 + + # create partitions + # no need to specify the partition number for the first invocation of + # the "t" command in fdisk, because there is only 1 partition at this + # point + echo -e "n\np\n3\n\n4095\nt\na2\nn\np\n1\n\n+${sdcard_partition_size_fat32}\nt\n1\nb\nn\np\n2\n\n+${sdcard_partition_size_linux}\nt\n2\n83\nw\nq\n" | sudo fdisk "${sdcard_dev}" + + # create filesystems + sudo mkfs.vfat "${sdcard_dev_fat32}" + sudo mkfs.ext3 -F "${sdcard_dev_ext3}" +} + +# write_sdcard() ############################################################### +write_sdcard() { + # create mount point for sdcard + mkdir -p "${sdcard_dev_fat32_mount_point}" + mkdir -p "${sdcard_dev_ext3_mount_point}" + + # mount sdcard partitions + sudo mount "${sdcard_dev_fat32}" "${sdcard_dev_fat32_mount_point}" + sudo mount "${sdcard_dev_ext3}" "${sdcard_dev_ext3_mount_point}" + + # preloader + sudo dd if="${sdcard_a2_preloader_bin_file}" of="${sdcard_dev_a2}" bs=64K seek=0 + + # fpga .rbf, uboot .img, uboot .scr, linux zImage, linux .dtb + sudo cp "${sdcard_fat32_dir}"/* "${sdcard_dev_fat32_mount_point}" + + # linux rootfs + pushd "${sdcard_dev_ext3_mount_point}" + sudo tar -xzf "${sdcard_ext3_rootfs_tgz_file}" + popd + + # flush write buffers to target + sudo sync + + # unmount sdcard partitions + sudo umount "${sdcard_dev_fat32_mount_point}" + sudo umount "${sdcard_dev_ext3_mount_point}" + + # delete mount points for sdcard + rm -rf "${sdcard_dev_fat32_mount_point}" + rm -rf "${sdcard_dev_ext3_mount_point}" +} + +# Script execution ############################################################# + +# Report script line number on any error (non-zero exit code). +trap 'echo "Error on line ${LINENO}" 1>&2' ERR +set -e + +# Create sdcard output directories +mkdir -p "${sdcard_a2_dir}" +mkdir -p "${sdcard_fat32_dir}" + +compile_quartus_project +compile_preloader +compile_uboot +compile_linux +create_rootfs + +# Write sdcard if it exists +if [ -z "${sdcard_dev}" ]; then + echo "sdcard argument not provided => no sdcard written." + +elif [ -b "${sdcard_dev}" ]; then + partition_sdcard + write_sdcard +fi + +# Make sure MSEL = 000000 diff --git a/cs309-psoc/lab_4_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd b/cs309-psoc/lab_4_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd new file mode 100644 index 0000000..ff7fc2a --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd @@ -0,0 +1,330 @@ +-- ############################################################################# +-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +-- +-- BOARD : PrSoC extension board for DE0-Nano-SoC +-- Author : Florian Depraz based on Sahand Kashani-Akhavan work +-- Revision : 1.1 +-- Creation date : 06/02/2016 +-- +-- Syntax Rule : GROUP_NAME_N[bit] +-- +-- GROUP : specify a particular interface (ex: SDR_) +-- NAME : signal name (ex: CONFIG, D, ...) +-- bit : signal index +-- _N : to specify an active-low signal +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; + +entity DE0_Nano_SoC_PrSoC_extn_board_top_level is + port( + ------------------------------- + -- Comment ALL unused ports. -- + ------------------------------- + + -- CLOCK + FPGA_CLK1_50 : in std_logic; + -- FPGA_CLK2_50 : in std_logic; + -- FPGA_CLK3_50 : in std_logic; + + -- KEY on DE0 Nano SoC + KEY_N : in std_logic_vector(1 downto 0); + + -- LEDs on DE0 Nano SoC + -- LED : out std_logic_vector(7 downto 0); + + -- SWITCHES on DE0 Nano SoC + -- SW : in std_logic_vector(3 downto 0); + + -- Servomotors pwm + SERVO_0 : out std_logic; + SERVO_1 : out std_logic; + + -- ADC Joysticks + J0_SPI_CS_n : out std_logic; + J0_SPI_MOSI : out std_logic; + J0_SPI_MISO : in std_logic; + J0_SPI_CLK : out std_logic; + + -- Lepton + CAM_TH_SPI_CS_N : out std_logic; + CAM_TH_MISO : in std_logic; + CAM_TH_MOSI : out std_logic; + CAM_TH_CLK : out std_logic; + + -- PCA9637 + -- PIO_SCL : inout std_logic; + -- PIO_SDA : inout std_logic; + -- PIO_INT_N : in std_logic; + -- RESET_N : out std_logic; + + -- OV7670 + -- CAM_D : in std_logic_vector(9 downto 0); + -- CAM_PIX_CLK : in std_logic; + -- CAM_LV : in std_logic; + -- CAM_FV : in std_logic; + -- CAM_SYS_CLK : out std_logic; + + -- VGA and LCD shared signals + -- VIDEO_CLK : out std_logic; + -- VIDEO_VSYNC : out std_logic; + -- VIDEO_HSYNC : out std_logic; + -- VIDEO_B : out std_logic_vector(7 downto 0); + -- VIDEO_G : out std_logic_vector(7 downto 0); + -- VIDEO_R : out std_logic_vector(7 downto 0); + + -- LCD Specific signals + -- LCD_DE : out std_logic; + -- LCD_PIN_DAV_N : ? ?? std_logic; + -- LCD_DISPLAY_EN : out std_logic; + -- SPI_MISO : in std_logic; + -- SPI_ENA_N : out std_logic; + -- SPI_CLK : out std_logic; + -- SPI_MOSI : out std_logic; + -- SPI_DAT : inout std_logic; + + -- I2C TOUCH SCREEN + -- TS_SCL : inout std_logic; + -- TS_SDA : inout std_logic; + + -- BLUETOOTH (BLE) + -- BLT_TXD : in std_logic; + -- BLT_RXD : out std_logic; + + -- I2C For VGA, PAL and OV7670 cameras + -- CAM_PAL_VGA_SDA : inout std_logic; + -- CAM_PAL_VGA_SCL : inout std_logic; + + -- ONE WIRE + -- BOARD_ID : inout std_logic; + + -- PAL Camera + -- PAL_VD_VD : in std_logic_vector(7 downto 0); + -- PAL_VD_VSO : in std_logic; + -- PAL_VD_HSO : in std_logic; + -- PAL_VD_CLKO : in std_logic; + -- PAL_PWDN : out std_logic; + + -- WIFI + -- FROM_ESP_TXD : in std_logic; + -- TO_ESP_RXD : out std_logic; + + -- LED RGB + -- LED_BGR : out std_logic; + + -- HPS + HPS_CONV_USB_N : inout std_logic; + HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); + HPS_DDR3_BA : out std_logic_vector(2 downto 0); + HPS_DDR3_CAS_N : out std_logic; + HPS_DDR3_CK_N : out std_logic; + HPS_DDR3_CK_P : out std_logic; + HPS_DDR3_CKE : out std_logic; + HPS_DDR3_CS_N : out std_logic; + HPS_DDR3_DM : out std_logic_vector(3 downto 0); + HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); + HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); + HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); + HPS_DDR3_ODT : out std_logic; + HPS_DDR3_RAS_N : out std_logic; + HPS_DDR3_RESET_N : out std_logic; + HPS_DDR3_RZQ : in std_logic; + HPS_DDR3_WE_N : out std_logic; + HPS_ENET_GTX_CLK : out std_logic; + HPS_ENET_INT_N : inout std_logic; + HPS_ENET_MDC : out std_logic; + HPS_ENET_MDIO : inout std_logic; + HPS_ENET_RX_CLK : in std_logic; + HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); + HPS_ENET_RX_DV : in std_logic; + HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); + HPS_ENET_TX_EN : out std_logic; + HPS_GSENSOR_INT : inout std_logic; + HPS_I2C0_SCLK : inout std_logic; + HPS_I2C0_SDAT : inout std_logic; + HPS_I2C1_SCLK : inout std_logic; + HPS_I2C1_SDAT : inout std_logic; + HPS_KEY_N : inout std_logic; + -- HPS_LED : inout std_logic; + HPS_LTC_GPIO : inout std_logic; + HPS_SD_CLK : out std_logic; + HPS_SD_CMD : inout std_logic; + HPS_SD_DATA : inout std_logic_vector(3 downto 0); + HPS_SPIM_CLK : out std_logic; + HPS_SPIM_MISO : in std_logic; + HPS_SPIM_MOSI : out std_logic; + HPS_SPIM_SS : inout std_logic; + HPS_UART_RX : in std_logic; + HPS_UART_TX : out std_logic; + HPS_USB_CLKOUT : in std_logic; + HPS_USB_DATA : inout std_logic_vector(7 downto 0); + HPS_USB_DIR : in std_logic; + HPS_USB_NXT : in std_logic; + HPS_USB_STP : out std_logic + ); +end entity DE0_Nano_SoC_PrSoC_extn_board_top_level; + +architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is + component soc_system is + port ( + clk_clk : in std_logic := 'X'; -- clk + hps_0_ddr_mem_a : out std_logic_vector(14 downto 0); -- mem_a + hps_0_ddr_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba + hps_0_ddr_mem_ck : out std_logic; -- mem_ck + hps_0_ddr_mem_ck_n : out std_logic; -- mem_ck_n + hps_0_ddr_mem_cke : out std_logic; -- mem_cke + hps_0_ddr_mem_cs_n : out std_logic; -- mem_cs_n + hps_0_ddr_mem_ras_n : out std_logic; -- mem_ras_n + hps_0_ddr_mem_cas_n : out std_logic; -- mem_cas_n + hps_0_ddr_mem_we_n : out std_logic; -- mem_we_n + hps_0_ddr_mem_reset_n : out std_logic; -- mem_reset_n + hps_0_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq + hps_0_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs + hps_0_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n + hps_0_ddr_mem_odt : out std_logic; -- mem_odt + hps_0_ddr_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm + hps_0_ddr_oct_rzqin : in std_logic := 'X'; -- oct_rzqin + hps_0_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK + hps_0_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0 + hps_0_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1 + hps_0_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2 + hps_0_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3 + hps_0_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0 + hps_0_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO + hps_0_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC + hps_0_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL + hps_0_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL + hps_0_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK + hps_0_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1 + hps_0_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2 + hps_0_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3 + hps_0_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD + hps_0_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0 + hps_0_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1 + hps_0_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK + hps_0_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2 + hps_0_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3 + hps_0_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0 + hps_0_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1 + hps_0_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2 + hps_0_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3 + hps_0_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4 + hps_0_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5 + hps_0_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6 + hps_0_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7 + hps_0_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK + hps_0_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP + hps_0_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR + hps_0_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT + hps_0_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK + hps_0_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI + hps_0_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO + hps_0_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0 + hps_0_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX + hps_0_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX + hps_0_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA + hps_0_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL + hps_0_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA + hps_0_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL + hps_0_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09 + hps_0_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35 + hps_0_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40 + hps_0_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54 + hps_0_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61 + lepton_0_spi_cs_n : out std_logic; -- cs_n + lepton_0_spi_miso : in std_logic := 'X'; -- miso + lepton_0_spi_mosi : out std_logic; -- mosi + lepton_0_spi_sclk : out std_logic; -- sclk + mcp3204_0_conduit_end_cs_n : out std_logic; -- cs_n + mcp3204_0_conduit_end_mosi : out std_logic; -- mosi + mcp3204_0_conduit_end_miso : in std_logic := 'X'; -- miso + mcp3204_0_conduit_end_sclk : out std_logic; -- sclk + pwm_0_conduit_end_pwm : out std_logic; -- pwm + pwm_1_conduit_end_pwm : out std_logic; -- pwm + reset_reset_n : in std_logic := 'X' -- reset_n + ); + end component soc_system; + + + begin + u0 : component soc_system + port map ( + clk_clk => FPGA_CLK1_50, -- clk.clk + hps_0_ddr_mem_a => HPS_DDR3_ADDR, -- hps_0_ddr.mem_a + hps_0_ddr_mem_ba => HPS_DDR3_BA, -- .mem_ba + hps_0_ddr_mem_ck => HPS_DDR3_CK_P, -- .mem_ck + hps_0_ddr_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n + hps_0_ddr_mem_cke => HPS_DDR3_CKE, -- .mem_cke + hps_0_ddr_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n + hps_0_ddr_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n + hps_0_ddr_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n + hps_0_ddr_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n + hps_0_ddr_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n + hps_0_ddr_mem_dq => HPS_DDR3_DQ, -- .mem_dq + hps_0_ddr_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs + hps_0_ddr_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n + hps_0_ddr_mem_odt => HPS_DDR3_ODT, -- .mem_odt + hps_0_ddr_mem_dm => HPS_DDR3_DM, -- .mem_dm + hps_0_ddr_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin + hps_0_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK, -- hps_0_io.hps_io_emac1_inst_TX_CLK + hps_0_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0), -- .hps_io_emac1_inst_TXD0 + hps_0_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1), -- .hps_io_emac1_inst_TXD1 + hps_0_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), -- .hps_io_emac1_inst_TXD2 + hps_0_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), -- .hps_io_emac1_inst_TXD3 + hps_0_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), -- .hps_io_emac1_inst_RXD0 + hps_0_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO, -- .hps_io_emac1_inst_MDIO + hps_0_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC, -- .hps_io_emac1_inst_MDC + hps_0_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV, -- .hps_io_emac1_inst_RX_CTL + hps_0_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN, -- .hps_io_emac1_inst_TX_CTL + hps_0_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK, -- .hps_io_emac1_inst_RX_CLK + hps_0_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), -- .hps_io_emac1_inst_RXD1 + hps_0_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), -- .hps_io_emac1_inst_RXD2 + hps_0_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), -- .hps_io_emac1_inst_RXD3 + hps_0_io_hps_io_sdio_inst_CMD => HPS_SD_CMD, -- .hps_io_sdio_inst_CMD + hps_0_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), -- .hps_io_sdio_inst_D0 + hps_0_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), -- .hps_io_sdio_inst_D1 + hps_0_io_hps_io_sdio_inst_CLK => HPS_SD_CLK, -- .hps_io_sdio_inst_CLK + hps_0_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), -- .hps_io_sdio_inst_D2 + hps_0_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), -- .hps_io_sdio_inst_D3 + hps_0_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), -- .hps_io_usb1_inst_D0 + hps_0_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), -- .hps_io_usb1_inst_D1 + hps_0_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), -- .hps_io_usb1_inst_D2 + hps_0_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), -- .hps_io_usb1_inst_D3 + hps_0_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), -- .hps_io_usb1_inst_D4 + hps_0_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), -- .hps_io_usb1_inst_D5 + hps_0_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), -- .hps_io_usb1_inst_D6 + hps_0_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), -- .hps_io_usb1_inst_D7 + hps_0_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT, -- .hps_io_usb1_inst_CLK + hps_0_io_hps_io_usb1_inst_STP => HPS_USB_STP, -- .hps_io_usb1_inst_STP + hps_0_io_hps_io_usb1_inst_DIR => HPS_USB_DIR, -- .hps_io_usb1_inst_DIR + hps_0_io_hps_io_usb1_inst_NXT => HPS_USB_NXT, -- .hps_io_usb1_inst_NXT + hps_0_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK, -- .hps_io_spim1_inst_CLK + hps_0_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI, -- .hps_io_spim1_inst_MOSI + hps_0_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO, -- .hps_io_spim1_inst_MISO + hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS, -- .hps_io_spim1_inst_SS0 + hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX, -- .hps_io_uart0_inst_RX + hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX, -- .hps_io_uart0_inst_TX + hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C0_SDAT, -- .hps_io_i2c0_inst_SDA + hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C0_SCLK, -- .hps_io_i2c0_inst_SCL + hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C1_SDAT, -- .hps_io_i2c1_inst_SDA + hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C1_SCLK, -- .hps_io_i2c1_inst_SCL + hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N, -- .hps_io_gpio_inst_GPIO09 + hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N, -- .hps_io_gpio_inst_GPIO35 + hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO, -- .hps_io_gpio_inst_GPIO40 + hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N, -- .hps_io_gpio_inst_GPIO54 + hps_0_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT, -- .hps_io_gpio_inst_GPIO61 + lepton_0_spi_cs_n => CAM_TH_SPI_CS_N, -- lepton_0_spi.cs_n + lepton_0_spi_miso => CAM_TH_MISO, -- .miso + lepton_0_spi_mosi => CAM_TH_MOSI, -- .mosi + lepton_0_spi_sclk => CAM_TH_CLK, -- .sclk + mcp3204_0_conduit_end_cs_n => J0_SPI_CS_n, -- mcp3204_0_conduit_end.cs_n + mcp3204_0_conduit_end_mosi => J0_SPI_MOSI, -- .mosi + mcp3204_0_conduit_end_miso => J0_SPI_MISO, -- .miso + mcp3204_0_conduit_end_sclk => J0_SPI_CLK, -- .sclk + pwm_0_conduit_end_pwm => SERVO_0, -- pwm_0_conduit_end.pwm + pwm_1_conduit_end_pwm => SERVO_1, -- pwm_1_conduit_end.pwm + reset_reset_n => KEY_N(0) -- reset.reset_n + ); + +end; diff --git a/cs309-psoc/lab_4_1/hw/hdl/joysticks/hdl/mcp3204.vhd b/cs309-psoc/lab_4_1/hw/hdl/joysticks/hdl/mcp3204.vhd new file mode 100644 index 0000000..af0aafb --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/joysticks/hdl/mcp3204.vhd @@ -0,0 +1,138 @@ +-- ############################################################################# +-- mcp3204.vhd +-- =========== +-- MCP3204 Avalon-MM slave interface. +-- +-- Register map +-- +-------+-----------+--------+------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +-------+-----------+--------+------------------------------------+ +-- | 0 | CHANNEL_0 | RO | 12-bit digital value of channel 0. | +-- +-------+-----------+--------+------------------------------------+ +-- | 1 | CHANNEL_1 | RO | 12-bit digital value of channel 1. | +-- +-------+-----------+--------+------------------------------------+ +-- | 2 | CHANNEL_2 | RO | 12-bit digital value of channel 2. | +-- +-------+-----------+--------+------------------------------------+ +-- | 3 | CHANNEL_3 | RO | 12-bit digital value of channel 3. | +-- +-------+-----------+--------+------------------------------------+ +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity mcp3204 is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + readdata : out std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic; + SCLK : out std_logic + ); +end entity; + +architecture arch of mcp3204 is + constant NUM_CHANNELS : positive := 4; + constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS)))); + + type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range); + signal data_reg : data_array; + + signal spi_busy, spi_start, spi_datavalid : std_logic; + signal spi_channel : std_logic_vector(1 downto 0); + signal spi_data : std_logic_vector(11 downto 0); + + type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA); + signal state : state_t; + + signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0); + +begin + SPI : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => spi_busy, + start => spi_start, + channel => spi_channel, + data_valid => spi_datavalid, + data => spi_data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + -- FSM that dictates which channel is being read. The state of the component + -- should be thought as the pair (state, channel) + p_fsm : process(reset, clk) + begin + if reset = '1' then + state <= READY; + channel <= (others => '0'); + elsif rising_edge(clk) then + case state is + when READY => + if spi_busy = '0' then + state <= INIT_READ_CHANNEL; + end if; + + when INIT_READ_CHANNEL => + state <= WAIT_FOR_DATA; + + when WAIT_FOR_DATA => + if spi_datavalid = '1' then + state <= READY; + channel <= channel + 1; + end if; + end case; + end if; + end process p_fsm; + + -- Updates the internal registers when a new data is available + p_data : process(reset, clk) + begin + if reset = '1' then + for i in 0 to NUM_CHANNELS - 1 loop + data_reg(i) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + if state = WAIT_FOR_DATA and spi_datavalid = '1' then + data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data; + end if; + end if; + end process p_data; + + spi_start <= '1' when state = INIT_READ_CHANNEL else '0'; + spi_channel <= std_logic_vector(channel); + + -- Interface with the Avalon Switch Fabric + p_avalon_read : process(reset, clk) + begin + if reset = '1' then + readdata <= (others => '0'); + elsif rising_edge(clk) then + if read = '1' then + readdata <= data_reg(to_integer(unsigned(address))); + end if; + end if; + end process p_avalon_read; + +end architecture; diff --git a/cs309-psoc/lab_4_1/hw/hdl/joysticks/hdl/mcp3204_hw.tcl b/cs309-psoc/lab_4_1/hw/hdl/joysticks/hdl/mcp3204_hw.tcl new file mode 100644 index 0000000..757514d --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/joysticks/hdl/mcp3204_hw.tcl @@ -0,0 +1,137 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 18:14:06 CET 2017 +# DO NOT MODIFY + + +# +# mcp3204 "mcp3204" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.18:14:06 +# 4-Channel 12-Bit A/D Converter with SPI Serial Interface +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module mcp3204 +# +set_module_property DESCRIPTION "4-Channel 12-Bit A/D Converter with SPI Serial Interface" +set_module_property NAME mcp3204 +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Joystick +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME mcp3204 +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL mcp3204 +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file mcp3204.vhd VHDL PATH mcp3204.vhd TOP_LEVEL_FILE +add_fileset_file mcp3204_spi.vhd VHDL PATH mcp3204_spi.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end CS_N cs_n Output 1 +add_interface_port conduit_end MOSI mosi Output 1 +add_interface_port conduit_end MISO miso Input 1 +add_interface_port conduit_end SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_4_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd b/cs309-psoc/lab_4_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd new file mode 100644 index 0000000..f5e072e --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd @@ -0,0 +1,87 @@ +-- ############################################################################# +-- mcp3204_spi.vhd +-- =============== +-- MCP3204 SPI interface. +-- +-- Author : Philémon Favrod [philemon.favrod@epfl.ch] +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Author : () +-- Revision : 1 +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mcp3204_spi is + port( + -- 50 MHz + clk : in std_logic; + reset : in std_logic; + busy : out std_logic; + start : in std_logic; + channel : in std_logic_vector(1 downto 0); + data_valid : out std_logic; + data : out std_logic_vector(11 downto 0); + + -- 1 MHz + SCLK : out std_logic; + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); +end mcp3204_spi; + +architecture rtl of mcp3204_spi is + signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24 + signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz + signal reg_rising_edge_sclk : std_logic := '0'; + signal reg_falling_edge_sclk : std_logic := '0'; + + signal reg_sclk : std_logic := '0'; + +begin + clk_divider_generation : process(clk, reset) + begin + if reset = '1' then + reg_clk_divider_counter <= (others => '0'); + elsif rising_edge(clk) then + reg_clk_divider_counter <= reg_clk_divider_counter + 1; + reg_spi_en <= '0'; + reg_rising_edge_sclk <= '0'; + reg_falling_edge_sclk <= '0'; + + if reg_clk_divider_counter = 24 then + reg_clk_divider_counter <= (others => '0'); + reg_spi_en <= '1'; + + if reg_sclk = '0' then + reg_rising_edge_sclk <= '1'; + elsif reg_sclk = '1' then + reg_falling_edge_sclk <= '1'; + end if; + end if; + end if; + end process; + + SCLK_generation : process(clk, reset) + begin + if reset = '1' then + reg_sclk <= '0'; + elsif rising_edge(clk) then + if reg_spi_en = '1' then + reg_sclk <= not reg_sclk; + end if; + end if; + end process; + + STATE_LOGIC : process(clk, reset) + begin + -- TODO: complete this process + if reset = '1' then + elsif rising_edge(clk) then + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_4_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd b/cs309-psoc/lab_4_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd new file mode 100644 index 0000000..1bb61d2 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd @@ -0,0 +1,103 @@ +-- ############################################################################# +-- tb_mcp3204_spi.vhd +-- ================== +-- Testbench for MCP3204 SPI interface. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 1 +-- Last modified : 2018-03-06 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_mcp3204_spi is +end entity; + +architecture rtl of tb_mcp3204_spi is + constant CLK_PERIOD : time := 20 ns; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal sim_finished : boolean := false; + + -- mcp3204_spi ------------------------------------------------------------ + signal busy : std_logic := '0'; + signal start : std_logic := '0'; + signal channel : std_logic_vector(1 downto 0) := (others => '0'); + signal data_valid : std_logic := '0'; + signal data : std_logic_vector(11 downto 0) := (others => '0'); + signal SCLK : std_logic := '0'; + signal CS_N : std_logic := '1'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '0'; + +begin + duv : entity work.mcp3204_spi + port map( + clk => clk, + reset => reset, + busy => busy, + start => start, + channel => channel, + data_valid => data_valid, + data => data, + SCLK => SCLK, + CS_N => CS_N, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_finished; + + sim : process + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + reset <= '1'; + + wait for CLK_PERIOD / 2; + reset <= '0'; + end procedure async_reset; + + procedure spi_transfer(constant channel_number : natural range 0 to 3) is + begin + if busy = '1' then + wait until busy = '0'; + + else + wait until falling_edge(clk); + start <= '1'; + channel <= std_logic_vector(to_unsigned(channel_number, channel'length)); + + wait until falling_edge(clk); + start <= '0'; + channel <= (others => '0'); + + wait until rising_edge(data_valid); + wait until falling_edge(busy); + end if; + end procedure spi_transfer; + + begin + async_reset; + + MISO <= '1'; + spi_transfer(0); + + MISO <= '0'; + spi_transfer(1); + + MISO <= '1'; + spi_transfer(2); + + MISO <= '0'; + spi_transfer(3); + + sim_finished <= true; + wait; + end process sim; +end architecture rtl; + + diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd new file mode 100644 index 0000000..9769bb8 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd @@ -0,0 +1,139 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.utils.all; + +entity avalon_st_spi_master is + generic( + INPUT_CLK_FREQ : integer := 50000000; + SPI_SCLK_FREQ : integer := 10000000; + CPOL : integer := 1; + CPHA : integer := 1 + ); + port( + -- Input clock + clk : in std_logic; + + -- Reset + reset : in std_logic; + spi_cs_n : in std_logic; + -- Sink Avalon ST Interface + mosi_sink_data : in std_logic_vector(7 downto 0); + mosi_sink_valid : in std_logic; + mosi_sink_ready : out std_logic; + + -- Source Avalon ST Interface + miso_src_data : out std_logic_vector(7 downto 0); + miso_src_valid : out std_logic; + + -- SPI Master signals + SCLK : out std_logic; + MISO : in std_logic; + MOSI : out std_logic; + CS_n : out std_logic + ); +end avalon_st_spi_master; + +architecture rtl of avalon_st_spi_master is + constant SCLK_PRESCALER_MAX : integer := INPUT_CLK_FREQ / SPI_SCLK_FREQ / 2; + signal sclk_prescaler : unsigned(bitlength(SCLK_PRESCALER_MAX) downto 0); + signal sclk_toggle : std_logic; + + signal new_sink_buffer, cur_sink_buffer : std_logic_vector(mosi_sink_data'range); + signal new_sink_buffer_busy, cur_sink_buffer_busy : std_logic; + + signal miso_src_buffer : std_logic_vector(7 downto 0); + + signal spi_done, i_sclk : std_logic; + signal spi_bit_index : unsigned(2 downto 0); +begin + CS_n <= spi_cs_n; + + p_sclk_prescaler : process(clk, reset) is + begin + if reset = '1' then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + elsif rising_edge(clk) then + if sclk_prescaler = SCLK_PRESCALER_MAX then + sclk_prescaler <= to_unsigned(1, sclk_prescaler'length); + else + sclk_prescaler <= sclk_prescaler + 1; + end if; + end if; + end process p_sclk_prescaler; + sclk_toggle <= '1' when sclk_prescaler = SCLK_PRESCALER_MAX else '0'; + + p_avalon_st_sink : process(clk, reset) is + begin + if reset = '1' then + new_sink_buffer_busy <= '0'; + new_sink_buffer <= (others => '0'); + elsif rising_edge(clk) then + if mosi_sink_valid = '1' then + if new_sink_buffer_busy = '0' and cur_sink_buffer_busy = '1' then + new_sink_buffer <= mosi_sink_data; + new_sink_buffer_busy <= '1'; + end if; + elsif new_sink_buffer_busy = '1' and cur_sink_buffer_busy = '0' then + new_sink_buffer_busy <= '0'; + end if; + end if; + end process p_avalon_st_sink; + mosi_sink_ready <= not new_sink_buffer_busy; + + p_cur_buffer : process(clk, reset) is + begin + if reset = '1' then + cur_sink_buffer <= (others => '0'); + cur_sink_buffer_busy <= '0'; + elsif rising_edge(clk) then + if mosi_sink_valid = '1' and cur_sink_buffer_busy = '0' then + cur_sink_buffer <= mosi_sink_data; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '0' and new_sink_buffer_busy = '1' then + cur_sink_buffer <= new_sink_buffer; + cur_sink_buffer_busy <= '1'; + elsif cur_sink_buffer_busy = '1' and spi_done = '1' then + cur_sink_buffer_busy <= '0'; + end if; + end if; + end process p_cur_buffer; + + p_spi : process(clk, reset) is + begin + if reset = '1' then + spi_done <= '0'; + i_sclk <= to_unsigned(CPOL, 1)(0); + spi_bit_index <= "000"; + MOSI <= '0'; + miso_src_data <= (others => '0'); + miso_src_valid <= '0'; + miso_src_buffer <= (others => '0'); + + elsif rising_edge(clk) then + spi_done <= '0'; + miso_src_valid <= '0'; + if cur_sink_buffer_busy = '1' and sclk_toggle = '1' then + if i_sclk /= to_unsigned(CPHA, 1)(0) then + if spi_bit_index = "111" then + spi_done <= '1'; + spi_bit_index <= "000"; + miso_src_valid <= '1'; + miso_src_data <= miso_src_buffer(7 downto 1) & MISO; + else + MOSI <= cur_sink_buffer(7 - to_integer(spi_bit_index)); + miso_src_buffer(7 - to_integer(spi_bit_index)) <= MISO; + spi_bit_index <= spi_bit_index + 1; + + end if; + + end if; + + i_sclk <= not i_sclk; + + end if; + end if; + end process p_spi; + SCLK <= i_sclk; + +end rtl; diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/byte2pix.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/byte2pix.vhd new file mode 100644 index 0000000..b888ba9 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/byte2pix.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------- +-- Title : Byte stream to pixel converter for the Lepton Camera +-- Project : PrSoC +------------------------------------------------------------------------------- +-- File : byte2pix.vhd +-- Author : Philemon Orphee Favrod +-- Company : +-- Created : 2016-03-21 +-- Last update: 2017-03-19 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: Converts a byte stream to a 14-bit pixel stream. +------------------------------------------------------------------------------- +-- Copyright (c) 2016 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2016-03-21 1.0 pofavrod Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity byte2pix is + port( + clk, reset : in std_logic; + byte_data : in std_logic_vector(7 downto 0); + byte_valid : in std_logic; + byte_sof : in std_logic; + byte_eof : in std_logic; + pix_data : out std_logic_vector(13 downto 0); + pix_valid : out std_logic; + pix_sof : out std_logic; + pix_eof : out std_logic); + +end byte2pix; + +architecture rtl of byte2pix is + signal last_sof : std_logic; + signal msb : std_logic_vector(5 downto 0); + signal cnt : std_logic; -- used to skip msb sampling every other time +begin + process(clk, reset) + begin + if reset = '1' then + msb <= (others => '0'); + cnt <= '0'; + last_sof <= '0'; + elsif rising_edge(clk) then + if byte_valid = '1' then + if cnt = '0' then + msb <= byte_data(5 downto 0); + last_sof <= byte_sof; + end if; + cnt <= not cnt; + end if; + end if; + end process; + + process(clk, reset) + begin + if reset = '1' then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + elsif rising_edge(clk) then + pix_data <= (others => '0'); + pix_valid <= '0'; + pix_sof <= '0'; + pix_eof <= '0'; + + if byte_valid = '1' then + if cnt = '1' then + pix_data <= msb & byte_data; + pix_valid <= '1'; + pix_sof <= last_sof; + pix_eof <= byte_eof; + end if; + end if; + end if; + end process; + +end architecture rtl; diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd new file mode 100644 index 0000000..d4b4812 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd @@ -0,0 +1,192 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: dual_ported_ram.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +entity dual_ported_ram is + port( + clock : in std_logic := '1'; + data : in std_logic_vector(15 downto 0); + rdaddress : in std_logic_vector(12 downto 0); + wraddress : in std_logic_vector(12 downto 0); + wren : in std_logic := '0'; + q : out std_logic_vector(15 downto 0) + ); +end dual_ported_ram; + +architecture SYN of dual_ported_ram is + signal sub_wire0 : std_logic_vector(15 downto 0); + +begin + q <= sub_wire0(15 downto 0); + + altsyncram_component : altsyncram + generic map( + address_aclr_b => "NONE", + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 8192, + numwords_b => 8192, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "CLOCK0", + power_up_uninitialized => "FALSE", + read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => 13, + widthad_b => 13, + width_a => 16, + width_b => 16, + width_byteena_a => 1 + ) + port map( + address_a => wraddress, + address_b => rdaddress, + clock0 => clock, + data_a => data, + wren_a => wren, + q_b => sub_wire0 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]" +-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 +-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton.vhd new file mode 100644 index 0000000..82678ba --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton.vhd @@ -0,0 +1,288 @@ +-- Lepton Avalon Memory-Mapped Slave Interface +-- Author: Philémon Favrod (philemon.favrod@epfl.ch) +-- Modified by: Sahand Kashani-Akhavan (sahand.kashani-akhavan@epfl.ch) +-- Revision: 2 + +-- Register map +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | RegNo | Name | Access | Description | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 0 | COMMAND | WO | Command | +-- | | | | - Writing 1 starts capturing a frame & resets the | +-- | | | | ERROR bit (bit 1) in the STATUS register. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 1 | STATUS | RO | Status | +-- | | | | - Bit 0: 0 --> no capture in progress. | +-- | | | | 1 --> capture in progress. | +-- | | | | - Bit 1: 0 --> previous capture successful. | +-- | | | | 1 --> error during previous capture. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 2 | MIN | RO | Minimum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 3 | MAX | RO | Maximum pixel value in frame. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4 | SUM_LSB | RO | Sum of all pixels in frame (low 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 5 | SUM_MSB | RO | Sum of all pixels in frame (high 16 bits). | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 6 | ROW_IDX | RO | Current line being captured (1 <= ROW_IDX <= 60). | +-- | | | | Available for debugging purposes. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 7 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8 - 4807 | RAW BUFFER | RO | View into RAW pixel buffer. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 4808 - 8191 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 8192 - 12991 | ADJUSTED BUFFER | RO | View into adjusted (scaled) pixel buffer. | +-- | | | | Values are scaled between MIN and MAX. | +-- +---------------+-----------------+--------+---------------------------------------------------+ +-- | 12992 - 16383 | RESERVED | - | Reserved | +-- +---------------+-----------------+--------+---------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton is + port( + clk : in std_logic; + reset : in std_logic; + address : in std_logic_vector(13 downto 0); + readdata : out std_logic_vector(15 downto 0); + writedata : in std_logic_vector(15 downto 0); + read : in std_logic; + write : in std_logic; + + SCLK : out std_logic; + CSn : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); + +end lepton; + +architecture rtl of lepton is + signal spi_cs_n : std_logic; + signal spi_mosi_data : std_logic_vector(7 downto 0); + signal spi_mosi_valid : std_logic; + signal spi_mosi_ready : std_logic; + signal spi_miso_data : std_logic_vector(7 downto 0); + signal spi_miso_valid : std_logic; + signal lepton_manager_start : std_logic; + signal lepton_manager_error : std_logic; + signal byte_data : std_logic_vector(7 downto 0); + signal byte_valid : std_logic; + signal byte_sof : std_logic; + signal byte_eof : std_logic; + signal pix_data : std_logic_vector(13 downto 0); + signal pix_valid : std_logic; + signal pix_sof : std_logic; + signal pix_eof : std_logic; + signal stat_min : std_logic_vector(13 downto 0); + signal stat_max : std_logic_vector(13 downto 0); + signal stat_sum : std_logic_vector(26 downto 0); + signal stat_valid : std_logic; + signal ram_data : std_logic_vector(15 downto 0); + signal ram_wren : std_logic; + signal ram_wraddress : std_logic_vector(12 downto 0); + signal ram_rdaddress : std_logic_vector(12 downto 0); + signal ram_q : std_logic_vector(15 downto 0); + signal row_idx : std_logic_vector(5 downto 0); + signal raw_pixel : std_logic_vector(13 downto 0); + signal raw_max : std_logic_vector(13 downto 0); + signal raw_min : std_logic_vector(13 downto 0); + signal raw_sum : std_logic_vector(26 downto 0); + signal adjusted_pixel : std_logic_vector(13 downto 0); + + constant COMMAND_REG_OFFSET : std_logic_vector(address'range) := "00000000000000"; + constant STATUS_REG_OFFSET : std_logic_vector(address'range) := "00000000000001"; + constant MIN_REG_OFFSET : std_logic_vector(address'range) := "00000000000010"; + constant MAX_REG_OFFSET : std_logic_vector(address'range) := "00000000000011"; + constant SUM_LSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000100"; + constant SUM_MSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000101"; + constant ROW_IDX_REG_OFFSET : std_logic_vector(address'range) := "00000000000110"; + constant BUFFER_REG_OFFSET : unsigned(address'range) := "00000000001000"; + constant ADJUSTED_BUFFER_REG_OFFSET : unsigned(address'range) := "10000000000000"; + + constant IMAGE_SIZE : integer := 80 * 60; + constant BUFFER_REG_LIMIT : unsigned(address'range) := unsigned(BUFFER_REG_OFFSET) + IMAGE_SIZE; + + constant ADJUSTED_BUFFER_LIMIT : unsigned(address'range) := unsigned(ADJUSTED_BUFFER_REG_OFFSET) + IMAGE_SIZE; + + signal max_reg : std_logic_vector(stat_max'range); + signal min_reg : std_logic_vector(stat_min'range); + signal sum_reg : std_logic_vector(stat_sum'range); + signal error_reg : std_logic; + +begin + spi_controller0 : entity work.avalon_st_spi_master + port map( + clk => clk, + reset => reset, + spi_cs_n => spi_cs_n, + mosi_sink_data => spi_mosi_data, + mosi_sink_valid => spi_mosi_valid, + mosi_sink_ready => spi_mosi_ready, + miso_src_data => spi_miso_data, + miso_src_valid => spi_miso_valid, + SCLK => SCLK, + MISO => MISO, + MOSI => MOSI, + CS_n => CSn + ); + + lepton_manager0 : entity work.lepton_manager + port map( + clk => clk, + reset => reset, + spi_miso_sink_data => spi_miso_data, + spi_miso_sink_valid => spi_miso_valid, + spi_mosi_src_data => spi_mosi_data, + spi_mosi_src_valid => spi_mosi_valid, + spi_mosi_src_ready => spi_mosi_ready, + lepton_out_data => byte_data, + lepton_out_valid => byte_valid, + lepton_out_sof => byte_sof, + lepton_out_eof => byte_eof, + row_idx => row_idx, + error => lepton_manager_error, + start => lepton_manager_start, + spi_cs_n => spi_cs_n + ); + + byte2pix0 : entity work.byte2pix + port map( + clk => clk, + reset => reset, + byte_data => byte_data, + byte_valid => byte_valid, + byte_sof => byte_sof, + byte_eof => byte_eof, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof + ); + + lepton_stats0 : entity work.lepton_stats + port map( + reset => reset, + clk => clk, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + stat_min => stat_min, + stat_max => stat_max, + stat_sum => stat_sum, + stat_valid => stat_valid + ); + + ram_writer0 : entity work.ram_writer + port map( + clk => clk, + reset => reset, + pix_data => pix_data, + pix_valid => pix_valid, + pix_sof => pix_sof, + pix_eof => pix_eof, + ram_data => ram_data, + ram_wren => ram_wren, + ram_wraddress => ram_wraddress + ); + + dual_ported_ram0 : entity work.dual_ported_ram + port map( + clock => clk, + data => ram_data, + rdaddress => ram_rdaddress, + wraddress => ram_wraddress, + wren => ram_wren, + q => ram_q + ); + + level_adjuster0 : entity work.level_adjuster + port map( + clk => clk, + raw_pixel => ram_q(13 downto 0), + raw_max => max_reg, + raw_min => min_reg, + raw_sum => sum_reg, + adjusted_pixel => adjusted_pixel + ); + + p_lepton_start : process(clk, reset) + begin + if reset = '1' then + lepton_manager_start <= '0'; + error_reg <= '0'; + elsif rising_edge(clk) then + if write = '1' and address = COMMAND_REG_OFFSET then + lepton_manager_start <= writedata(0); + error_reg <= '0'; + elsif pix_eof = '1' then + lepton_manager_start <= '0'; + elsif lepton_manager_error = '1' then + error_reg <= '1'; + end if; + end if; + end process p_lepton_start; + + p_stat_reg : process(clk, reset) + begin + if reset = '1' then + min_reg <= (others => '0'); + max_reg <= (others => '0'); + sum_reg <= (others => '0'); + elsif rising_edge(clk) then + if stat_valid = '1' then + min_reg <= stat_min; + max_reg <= stat_max; + sum_reg <= stat_sum; + end if; + end if; + end process p_stat_reg; + + p_read : process(clk, reset) + begin + if reset = '1' then + readdata <= (others => '0'); + ram_rdaddress <= (others => '0'); + elsif rising_edge(clk) then + readdata <= (others => '0'); + if read = '1' then + case address is + when STATUS_REG_OFFSET => + readdata(1) <= error_reg; + readdata(0) <= lepton_manager_start; + + when MIN_REG_OFFSET => + readdata <= "00" & min_reg; + + when MAX_REG_OFFSET => + readdata <= "00" & max_reg; + + when SUM_MSB_REG_OFFSET => + readdata <= "00000" & sum_reg(26 downto 16); + + when SUM_LSB_REG_OFFSET => + readdata <= sum_reg(15 downto 0); + + when ROW_IDX_REG_OFFSET => + readdata(5 downto 0) <= row_idx; + + when others => + if unsigned(address) >= BUFFER_REG_OFFSET and unsigned(address) < BUFFER_REG_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= ram_q; + elsif unsigned(address) >= ADJUSTED_BUFFER_REG_OFFSET and unsigned(address) < ADJUSTED_BUFFER_LIMIT then + ram_rdaddress <= std_logic_vector(resize(unsigned(address) - ADJUSTED_BUFFER_REG_OFFSET, ram_rdaddress'length)); + readdata <= "00" & adjusted_pixel; + end if; + end case; + end if; + end if; + end process p_read; + +end rtl; diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton_hw.tcl b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton_hw.tcl new file mode 100644 index 0000000..d62e01b --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton_hw.tcl @@ -0,0 +1,148 @@ +# TCL File Generated by Component Editor 16.0 +# Sun Feb 05 19:05:24 CET 2017 +# DO NOT MODIFY + + +# +# lepton "lepton" v1.0 +# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.19:05:24 +# IR Camera 80x60 +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module lepton +# +set_module_property DESCRIPTION "IR Camera 80x60" +set_module_property NAME lepton +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Camera +set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan" +set_module_property DISPLAY_NAME lepton +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL lepton +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file avalon_st_spi_master.vhd VHDL PATH avalon_st_spi_master.vhd +add_fileset_file byte2pix.vhd VHDL PATH byte2pix.vhd +add_fileset_file dual_ported_ram.vhd VHDL PATH dual_ported_ram.vhd +add_fileset_file lepton.vhd VHDL PATH lepton.vhd TOP_LEVEL_FILE +add_fileset_file lepton_manager.vhd VHDL PATH lepton_manager.vhd +add_fileset_file lepton_stats.vhd VHDL PATH lepton_stats.vhd +add_fileset_file ram_writer.vhd VHDL PATH ram_writer.vhd +add_fileset_file utils.vhd VHDL PATH utils.vhd +add_fileset_file level_adjuster.vhd VHDL PATH level_adjuster.vhd +add_fileset_file lpm_divider.vhd VHDL PATH lpm_divider.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitStates 9 +set_interface_property avalon_slave_0 readWaitTime 9 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 14 +add_interface_port avalon_slave_0 readdata readdata Output 16 +add_interface_port avalon_slave_0 writedata writedata Input 16 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point spi +# +add_interface spi conduit end +set_interface_property spi associatedClock clock +set_interface_property spi associatedReset "" +set_interface_property spi ENABLED true +set_interface_property spi EXPORT_OF "" +set_interface_property spi PORT_NAME_MAP "" +set_interface_property spi CMSIS_SVD_VARIABLES "" +set_interface_property spi SVD_ADDRESS_GROUP "" + +add_interface_port spi CSn cs_n Output 1 +add_interface_port spi MISO miso Input 1 +add_interface_port spi MOSI mosi Output 1 +add_interface_port spi SCLK sclk Output 1 + diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton_manager.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton_manager.vhd new file mode 100644 index 0000000..1580be1 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton_manager.vhd @@ -0,0 +1,235 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_manager is + generic( + INPUT_CLK_FREQ : integer := 50000000); + port( + clk : in std_logic := '0'; + reset : in std_logic := '0'; + + -- Avalon ST Sink to receive SPI data + spi_miso_sink_data : in std_logic_vector(7 downto 0); + spi_miso_sink_valid : in std_logic; + + -- Avalon ST Source to send SPI data + spi_mosi_src_data : out std_logic_vector(7 downto 0); + spi_mosi_src_valid : out std_logic; + spi_mosi_src_ready : in std_logic := '0'; + + -- Filtered output to retransmit cleaned data (without the discard packets, see Lepton Datasheet on page 31) + -- lepton_out_data is valid on rising edge when lepton_src_valid = '1' + lepton_out_data : out std_logic_vector(7 downto 0); + lepton_out_valid : out std_logic; + lepton_out_sof : out std_logic; + lepton_out_eof : out std_logic; + + -- Some status + row_idx : out std_logic_vector(5 downto 0); + error : out std_logic; + + -- Avalon MM Slave interface for configuration + start : in std_logic; + + -- The SPI Chip Select (Active low !) + spi_cs_n : out std_logic := '0'); +end entity lepton_manager; + +architecture rtl of lepton_manager is + type state_t is (Idle, CSn, ReadHeader, ReadPayload, DiscardPayload, WaitBeforeIdle); + signal state, next_state : state_t; + + signal header_3_last_nibbles : std_logic_vector(11 downto 0); + + constant CLOCK_TICKS_PER_37_MS : integer := 37 * (INPUT_CLK_FREQ / 1e3); -- the timeout delay for a frame + constant CLOCK_TICKS_PER_200_MS : integer := 200 * (INPUT_CLK_FREQ / 1e3); + constant CLOCK_TICKS_PER_200_NS : integer := (200 * (INPUT_CLK_FREQ / 1e6)) / 1e3; + constant BYTES_PER_HEADER : integer := 4; + constant BYTES_PER_PAYLOAD : integer := 160; + + constant NUMBER_OF_LINES_PER_FRAME : positive := 60; + signal counter, counter_max : integer range 1 to CLOCK_TICKS_PER_200_MS; + signal line_counter : integer range 1 to NUMBER_OF_LINES_PER_FRAME; + signal timeout_counter : integer range 1 to CLOCK_TICKS_PER_37_MS; + signal counter_enabled : boolean; + signal waited_long_enough : boolean; + signal header_end, payload_end : boolean; +begin + + -- purpose: register for state + p_fsm : process(clk, reset) + begin + if reset = '1' then + state <= Idle; + elsif rising_edge(clk) then + state <= next_state; + end if; + end process p_fsm; + + -- purpose: compute the next state + p_nsl : process(header_3_last_nibbles, header_end, payload_end, start, spi_miso_sink_valid, state, waited_long_enough, line_counter) + begin + next_state <= state; + + case state is + when Idle => + if waited_long_enough and start = '1' then + next_state <= CSn; + end if; + + when CSn => + if waited_long_enough then + next_state <= ReadHeader; + end if; + + when ReadHeader => + if header_end then + if header_3_last_nibbles(11 downto 8) = X"F" then + next_state <= DiscardPayload; + else + next_state <= ReadPayload; + end if; + end if; + + when DiscardPayload | ReadPayload => + if payload_end then + next_state <= ReadHeader; + + if line_counter = NUMBER_OF_LINES_PER_FRAME then + next_state <= WaitBeforeIdle; + end if; + end if; + + when WaitBeforeIdle => + if spi_miso_sink_valid = '1' then + next_state <= Idle; + end if; + + end case; + end process p_nsl; + + p_counter : process(clk, reset) + begin + if reset = '1' then + counter <= 1; + line_counter <= 1; + elsif rising_edge(clk) then + if counter = counter_max and counter_enabled then + counter <= 1; + + if state = ReadPayload then + if line_counter = NUMBER_OF_LINES_PER_FRAME then + line_counter <= 1; + else + line_counter <= line_counter + 1; + end if; + end if; + + elsif counter_enabled then + counter <= counter + 1; + end if; + end if; + end process p_counter; + + p_error : process(clk, reset) + begin + if reset = '1' then + error <= '0'; + timeout_counter <= 1; + elsif rising_edge(clk) then + if state /= ReadHeader and state /= ReadPayload and state /= ReadHeader then + timeout_counter <= 1; + error <= '0'; + else + if timeout_counter = CLOCK_TICKS_PER_37_MS then + error <= '1'; + else + timeout_counter <= timeout_counter + 1; + end if; + end if; + if state = ReadPayload and header_3_last_nibbles /= std_logic_vector(to_unsigned(line_counter - 1, header_3_last_nibbles'length)) then + error <= '1'; + end if; + end if; + end process p_error; + + -- purpose: wire the datapath + p_datapath : process(counter, counter_enabled, counter_max, line_counter, spi_miso_sink_data, spi_miso_sink_valid, spi_mosi_src_ready, state) + variable counter_ended : boolean; + + begin + counter_max <= 1; + counter_enabled <= true; + waited_long_enough <= false; + lepton_out_data <= (others => '0'); + lepton_out_valid <= '0'; + lepton_out_sof <= '0'; + lepton_out_eof <= '0'; + spi_mosi_src_valid <= '0'; + spi_mosi_src_data <= (others => '0'); + spi_cs_n <= '0'; + header_end <= false; + payload_end <= false; + + counter_ended := (counter = counter_max and counter_enabled); + + case state is + when Idle => + counter_max <= CLOCK_TICKS_PER_200_MS; + waited_long_enough <= counter_ended; + spi_cs_n <= '1'; + + when CSn => + counter_max <= CLOCK_TICKS_PER_200_NS; + waited_long_enough <= counter_ended; + + when ReadHeader => + counter_max <= BYTES_PER_HEADER; + counter_enabled <= spi_miso_sink_valid = '1'; + header_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when ReadPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + lepton_out_data <= spi_miso_sink_data; + lepton_out_valid <= spi_miso_sink_valid; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + if spi_miso_sink_valid = '1' then + if counter = 1 and counter_enabled and line_counter = 1 then + lepton_out_sof <= '1'; + elsif counter_ended and line_counter = NUMBER_OF_LINES_PER_FRAME then + lepton_out_eof <= '1'; + end if; + end if; + + when DiscardPayload => + counter_max <= BYTES_PER_PAYLOAD; + counter_enabled <= spi_miso_sink_valid = '1'; + payload_end <= counter_ended; + spi_mosi_src_valid <= spi_mosi_src_ready; + + when others => null; + end case; + end process p_datapath; + + p_capture_header : process(clk, reset) + begin + if reset = '1' then + header_3_last_nibbles <= X"000"; + elsif rising_edge(clk) then + if state = ReadHeader and spi_miso_sink_valid = '1' then + if counter = 1 then + header_3_last_nibbles(11 downto 8) <= spi_miso_sink_data(3 downto 0); + elsif counter = 2 then + header_3_last_nibbles(7 downto 0) <= spi_miso_sink_data; + end if; + end if; + end if; + end process p_capture_header; + + row_idx <= std_logic_vector(to_unsigned(line_counter, row_idx'length)); + +end architecture rtl; diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton_stats.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton_stats.vhd new file mode 100644 index 0000000..4b5cc91 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lepton_stats.vhd @@ -0,0 +1,78 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_stats is + port( + clk : in std_logic; + reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + stat_min : out std_logic_vector(13 downto 0); + stat_max : out std_logic_vector(13 downto 0); + stat_sum : out std_logic_vector(26 downto 0); + stat_valid : out std_logic); +end lepton_stats; + +architecture rtl of lepton_stats is + + -- The accumulated sum, min and max of the pixel values + signal curr_min : unsigned(13 downto 0); + signal curr_max : unsigned(13 downto 0); + signal curr_sum : unsigned(26 downto 0); + + -- The next value of the registers + signal next_min : unsigned(13 downto 0); + signal next_max : unsigned(13 downto 0); + signal next_sum : unsigned(26 downto 0); + +begin + + -- This is the synchronous transition logic + transition_logic : process(clk, reset) + begin + if reset = '1' then + curr_sum <= (others => '0'); + curr_min <= (others => '0'); + curr_max <= (others => '0'); + elsif rising_edge(clk) then + curr_min <= next_min; + curr_max <= next_max; + curr_sum <= next_sum; + end if; + end process; + + -- This is the combinatorial transition logic + next_min <= + curr_min when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_min when unsigned(pix_data) >= curr_min else + unsigned(pix_data); + + next_max <= + curr_max when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_max when unsigned(pix_data) <= curr_max else + unsigned(pix_data); + + next_sum <= + curr_sum when pix_valid = '0' else + unsigned((26 downto 14 => '0') & pix_data) when pix_sof = '1' else + curr_sum + unsigned((26 downto 14 => '0') & pix_data); + + -- This is the synchronous output logic + output_logic : process(clk, reset) + begin + if rising_edge(clk) then + stat_valid <= pix_eof; + end if; + end process; + + -- This is the combinatorial output logic + stat_min <= std_logic_vector(curr_min); + stat_max <= std_logic_vector(curr_max); + stat_sum <= std_logic_vector(curr_sum); + +end rtl; diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/level_adjuster.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/level_adjuster.vhd new file mode 100644 index 0000000..6b3053d --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/level_adjuster.vhd @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity level_adjuster is + port( + clk : in std_logic; + raw_pixel : in std_logic_vector(13 downto 0); + raw_max : in std_logic_vector(13 downto 0); + raw_min : in std_logic_vector(13 downto 0); + raw_sum : in std_logic_vector(26 downto 0); + adjusted_pixel : out std_logic_vector(13 downto 0)); +end level_adjuster; + +architecture rtl of level_adjuster is + component lpm_divider + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0)); + end component; + + -- Intermediate signals needed by the divider + signal numer : std_logic_vector(27 downto 0); + signal denom : std_logic_vector(13 downto 0); + signal quot : std_logic_vector(27 downto 0); + +begin + + -- Computation of the intermediate signals + numer <= std_logic_vector((13 downto 0 => '1') * (unsigned(raw_pixel) - unsigned(raw_min))); + denom <= std_logic_vector(unsigned(raw_max) - unsigned(raw_min)); + + -- We compute the remaineder of (x - min) / (max - min) + divider : lpm_divider port map( + clock => clk, + numer => numer, + denom => denom, + quotient => quot, + remain => open + ); + + -- And we only keep the LSB of the quotient (we know the MSB must be 0) + adjusted_pixel <= + (adjusted_pixel'range => '0') when denom = (denom'range => '0') else + quot(13 downto 0); + +end rtl; diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lpm_divider.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lpm_divider.vhd new file mode 100644 index 0000000..f8de4a6 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/lpm_divider.vhd @@ -0,0 +1,133 @@ +-- megafunction wizard: %LPM_DIVIDE% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_DIVIDE + +-- ============================================================ +-- File Name: lpm_divider.vhd +-- Megafunction Name(s): +-- LPM_DIVIDE +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other +--applicable license agreement, including, without limitation, +--that your use is for the sole purpose of programming logic +--devices manufactured by Altera and sold by Altera or its +--authorized distributors. Please refer to the applicable +--agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; + +library lpm; +use lpm.all; + +entity lpm_divider is + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); +end lpm_divider; + +architecture SYN of lpm_divider is + signal sub_wire0 : std_logic_vector(27 downto 0); + signal sub_wire1 : std_logic_vector(13 downto 0); + + component lpm_divide + generic( + lpm_drepresentation : string; + lpm_hint : string; + lpm_nrepresentation : string; + lpm_pipeline : natural; + lpm_type : string; + lpm_widthd : natural; + lpm_widthn : natural + ); + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0) + ); + end component; + +begin + quotient <= sub_wire0(27 downto 0); + remain <= sub_wire1(13 downto 0); + + LPM_DIVIDE_component : LPM_DIVIDE + generic map( + lpm_drepresentation => "UNSIGNED", + lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE", + lpm_nrepresentation => "UNSIGNED", + lpm_pipeline => 5, + lpm_type => "LPM_DIVIDE", + lpm_widthd => 14, + lpm_widthn => 28 + ) + port map( + clock => clock, + denom => denom, + numer => numer, + quotient => sub_wire0, + remain => sub_wire1 + ); + +end SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" +-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1" +-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" +-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" +-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "14" +-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "28" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: denom 0 0 14 0 INPUT NODEFVAL "denom[13..0]" +-- Retrieval info: USED_PORT: numer 0 0 28 0 INPUT NODEFVAL "numer[27..0]" +-- Retrieval info: USED_PORT: quotient 0 0 28 0 OUTPUT NODEFVAL "quotient[27..0]" +-- Retrieval info: USED_PORT: remain 0 0 14 0 OUTPUT NODEFVAL "remain[13..0]" +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @denom 0 0 14 0 denom 0 0 14 0 +-- Retrieval info: CONNECT: @numer 0 0 28 0 numer 0 0 28 0 +-- Retrieval info: CONNECT: quotient 0 0 28 0 @quotient 0 0 28 0 +-- Retrieval info: CONNECT: remain 0 0 14 0 @remain 0 0 14 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/ram_writer.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/ram_writer.vhd new file mode 100644 index 0000000..8912cdb --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/ram_writer.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram_writer is + port( + clk, reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + ram_data : out std_logic_vector(15 downto 0); + ram_wren : out std_logic; + ram_wraddress : out std_logic_vector(12 downto 0)); + +end ram_writer; + +architecture rtl of ram_writer is + signal wraddress_counter : unsigned(ram_wraddress'range); +begin + p_address_gen : process(clk, reset) + begin + if reset = '1' then + wraddress_counter <= (others => '0'); + elsif rising_edge(clk) then + if pix_eof = '1' then + wraddress_counter <= (others => '0'); + elsif pix_valid = '1' then + wraddress_counter <= wraddress_counter + 1; + end if; + end if; + end process p_address_gen; + + ram_data <= "00" & pix_data; + ram_wren <= pix_valid; + ram_wraddress <= std_logic_vector(wraddress_counter); + +end rtl; diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/utils.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/utils.vhd new file mode 100644 index 0000000..83105ad --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/hdl/utils.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package utils is + function bitlength(number : positive) return positive; + +end package utils; + +package body utils is + + -- purpose: returns the minimum # of bits needed to represent the input number + function bitlength(number : positive) return positive is + variable acc : positive := 1; + variable i : natural := 0; + begin + while True loop + if acc > number then + return i; + end if; + + acc := acc * 2; + i := i + 1; + end loop; + end function bitlength; + +end package body utils; diff --git a/cs309-psoc/lab_4_1/hw/hdl/lepton/tb/lepton_tb.vhd b/cs309-psoc/lab_4_1/hw/hdl/lepton/tb/lepton_tb.vhd new file mode 100644 index 0000000..f134613 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/lepton/tb/lepton_tb.vhd @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity lepton_tb is +end lepton_tb; + +architecture tb of lepton_tb is + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal address : std_logic_vector(13 downto 0) := (others => '0'); + signal readdata : std_logic_vector(15 downto 0) := (others => '0'); + signal writedata : std_logic_vector(15 downto 0) := (others => '0'); + signal read : std_logic := '0'; + signal write : std_logic := '0'; + signal SCLK : std_logic := '0'; + signal CSn : std_logic := '0'; + signal MOSI : std_logic := '0'; + signal MISO : std_logic := '1'; + + constant CLK_PERIOD : time := 20 ns; + + signal sim_ended : boolean := false; + +begin + dut : entity work.lepton + port map( + clk => clk, + reset => reset, + address => address, + readdata => readdata, + writedata => writedata, + read => read, + write => write, + SCLK => SCLK, + CSn => CSn, + MOSI => MOSI, + MISO => MISO + ); + + clk <= not clk after CLK_PERIOD / 2 when not sim_ended else '0'; + + miso_gen : process + variable seed1, seed2 : positive; + variable rand : real; + begin + if sim_ended then + wait; + else + uniform(seed1, seed2, rand); + wait until rising_edge(SCLK); + MISO <= to_unsigned(integer(rand), 1)(0); + + end if; + end process; + + stimuli : process + begin + reset <= '1'; + write <= '0'; + + wait for 2 * CLK_PERIOD; + reset <= '0'; + + wait for CLK_PERIOD; + write <= '1'; + writedata(0) <= '1'; + wait for CLK_PERIOD; + write <= '0'; + + wait for 17 ms; + sim_ended <= true; + wait; + end process; + +end tb; diff --git a/cs309-psoc/lab_4_1/hw/hdl/pantilt/hdl/pwm.vhd b/cs309-psoc/lab_4_1/hw/hdl/pantilt/hdl/pwm.vhd new file mode 100644 index 0000000..1b5cdc3 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/pantilt/hdl/pwm.vhd @@ -0,0 +1,42 @@ +-- ############################################################################# +-- pwm.vhd +-- ======= +-- PWM memory-mapped Avalon slave interface. +-- +-- Author : () +-- Author : () +-- Revision : +-- Last modified : +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity pwm is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + write : in std_logic; + readdata : out std_logic_vector(31 downto 0); + writedata : in std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + pwm_out : out std_logic + ); +end pwm; + +architecture rtl of pwm is + +begin + +end architecture rtl; diff --git a/cs309-psoc/lab_4_1/hw/hdl/pantilt/hdl/pwm_constants.vhd b/cs309-psoc/lab_4_1/hw/hdl/pantilt/hdl/pwm_constants.vhd new file mode 100644 index 0000000..bfff03b --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/pantilt/hdl/pwm_constants.vhd @@ -0,0 +1,61 @@ +-- ############################################################################# +-- pwm_constants.vhd +-- ================= +-- This package contains constants used in the PWM design files. +-- +-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pwm_constants is + -- Register map + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | RegNo | Name | Access | Description | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW period to apply to the | + -- | | | | next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT period of the | + -- | | | | ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] | + -- | | | | | + -- | | | | This value can be read/written while the unit is in the middle of an ongoing | + -- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an | + -- | | | | ongoing pulse, so we adopt the following semantics for this register: | + -- | | | | | + -- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to | + -- | | | | the next pulse. | + -- | | | | | + -- | | | | >> READING a value from this register indicates the CURRENT duty cycle of | + -- | | | | the ongoing pulse. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + -- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.| + -- | | | | Writing 1 to this register starts the PWM. | + -- | | | | | + -- | | | | >> Reading this register always returns 0. | + -- +--------+------------+--------+------------------------------------------------------------------------------+ + constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00"; + constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01"; + constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10"; + + -- Default values of registers after reset (BEFORE writing START to the CTRL + -- register with a new configuration) + constant DEFAULT_PERIOD : natural := 4; + constant DEFAULT_DUTY_CYCLE : natural := 2; +end package pwm_constants; + +package body pwm_constants is + +end package body pwm_constants; diff --git a/cs309-psoc/lab_4_1/hw/hdl/pantilt/hdl/pwm_hw.tcl b/cs309-psoc/lab_4_1/hw/hdl/pantilt/hdl/pwm_hw.tcl new file mode 100644 index 0000000..df7d92a --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/pantilt/hdl/pwm_hw.tcl @@ -0,0 +1,135 @@ +# TCL File Generated by Component Editor 16.0 +# Tue Feb 28 12:18:00 CET 2017 +# DO NOT MODIFY + + +# +# pwm "pwm" v1.0 +# 2017.02.28.12:18:00 +# Pan-tilt +# + +# +# request TCL package from ACDS 16.0 +# +package require -exact qsys 16.0 + + +# +# module pwm +# +set_module_property DESCRIPTION Pan-tilt +set_module_property NAME pwm +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Pan-tilt +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME pwm +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE +add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 address address Input 2 +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +add_interface_port avalon_slave_0 readdata readdata Output 32 +add_interface_port avalon_slave_0 writedata writedata Input 32 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end pwm_out pwm Output 1 diff --git a/cs309-psoc/lab_4_1/hw/hdl/pantilt/tb/tb_pwm.vhd b/cs309-psoc/lab_4_1/hw/hdl/pantilt/tb/tb_pwm.vhd new file mode 100644 index 0000000..ff2dee7 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/hdl/pantilt/tb/tb_pwm.vhd @@ -0,0 +1,205 @@ +-- ############################################################################# +-- tb_pwm.vhd +-- ========== +-- Testbench for PWM memory-mapped Avalon slave interface. +-- +-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch] +-- Revision : 2 +-- Last modified : 2018-02-28 +-- ############################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity tb_pwm is +end entity; + +architecture rtl of tb_pwm is + + -- 50 MHz clock + constant CLK_PERIOD : time := 20 ns; + + -- Signal used to end simulator when we finished submitting our test cases + signal sim_finished : boolean := false; + + -- PWM PORTS + signal clk : std_logic; + signal reset : std_logic; + signal address : std_logic_vector(1 downto 0); + signal read : std_logic; + signal write : std_logic; + signal readdata : std_logic_vector(31 downto 0); + signal writedata : std_logic_vector(31 downto 0); + signal pwm_out : std_logic; + + -- Values of registers we are going to use to configure the PWM unit + constant CONFIG_PERIOD : natural := 100; + constant CONFIG_DUTY_CYCLE : natural := 20; + constant CONFIG_CTRL_START : natural := 1; + constant CONFIG_CTRL_STOP : natural := 0; + +begin + + -- Instantiate DUT + dut : entity work.pwm + port map( + clk => clk, + reset => reset, + address => address, + read => read, + write => write, + readdata => readdata, + writedata => writedata, + pwm_out => pwm_out + ); + + -- Generate clk signal + clk_generation : process + begin + if not sim_finished then + clk <= '1'; + wait for CLK_PERIOD / 2; + clk <= '0'; + wait for CLK_PERIOD / 2; + else + wait; + end if; + end process clk_generation; + + -- Test PWM + simulation : process + + procedure async_reset is + begin + wait until rising_edge(clk); + wait for CLK_PERIOD / 4; + + reset <= '1'; + wait for CLK_PERIOD / 2; + + reset <= '0'; + wait for CLK_PERIOD / 4; + end procedure async_reset; + + procedure write_register(constant ofst : in std_logic_vector(1 downto 0); + constant val : in natural) is + begin + wait until rising_edge(clk); + + address <= ofst; + write <= '1'; + writedata <= std_logic_vector(to_unsigned(val, writedata'length)); + wait until rising_edge(clk); + + address <= (others => '0'); + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + end procedure write_register; + + procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is + begin + wait until rising_edge(clk); + + address <= ofst; + read <= '1'; + -- The read has a 1 cycle wait-state, so we need to keep the read + -- signal high for 2 clock cycles. + wait until rising_edge(clk); + wait until rising_edge(clk); + + address <= (others => '0'); + read <= '0'; + wait until rising_edge(clk); + end procedure read_register; + + procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0); + constant expected_val : in natural) is + begin + read_register(ofst); + + case ofst is + when REG_PERIOD_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected PERIOD: " & + "PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "PERIOD_expected = " & integer'image(expected_val) + severity error; + + when REG_DUTY_CYCLE_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected DUTY_CYCLE: " & + "DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "DUTY_CYCLE_expected = " & integer'image(expected_val) + severity error; + + when REG_CTRL_OFST => + assert to_integer(unsigned(readdata)) = expected_val + report "Unexpected CTRL: " & + "CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " & + "CTRL_expected = " & integer'image(expected_val) + severity error; + + when others => + null; + end case; + end procedure read_register_check; + + begin + + -- Default values + reset <= '0'; + address <= (others => '0'); + read <= '0'; + write <= '0'; + writedata <= (others => '0'); + wait until rising_edge(clk); + + -- Reset the circuit + async_reset; + + -- Write desired configuration to PWM Avalon-MM slave. + write_register(REG_PERIOD_OFST, CONFIG_PERIOD); + write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + + -- Read back configuration from PWM Avalon-MM slave. Note that we have + -- not started the PWM unit yet, so the new configuration must not be + -- read back at this point (as per the register map). + read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Start PWM + write_register(REG_CTRL_OFST, CONFIG_CTRL_START); + + -- Wait until PWM pulses for the first time after we sent START. + wait until rising_edge(pwm_out); + + -- Read back configuration from PWM Avalon-MM slave. Now that we have + -- started the PWM unit, we should be able to read back the + -- configuration we wrote (as per the register map). + read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD); + read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE); + read_register_check(REG_CTRL_OFST, 0); + + -- Wait for 2 PWM periods to finish + wait for 2 * CLK_PERIOD * CONFIG_PERIOD; + + -- Stop PWM. + write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP); + + -- Wait for PWM period to finish + wait for 1 * CLK_PERIOD * CONFIG_PERIOD; + + -- Instruct "clk_generation" process to halt execution. + sim_finished <= true; + + -- Make this process wait indefinitely (it will never re-execute from + -- its beginning again). + wait; + end process simulation; +end architecture rtl; + diff --git a/cs309-psoc/lab_4_1/hw/quartus/ip/components.ipx b/cs309-psoc/lab_4_1/hw/quartus/ip/components.ipx new file mode 100644 index 0000000..7536257 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/quartus/ip/components.ipx @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_4_1/hw/quartus/lab_4_1.qpf b/cs309-psoc/lab_4_1/hw/quartus/lab_4_1.qpf new file mode 100644 index 0000000..5e77870 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/quartus/lab_4_1.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition +# Date created = 11:03:02 February 05, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.1" +DATE = "11:03:02 February 05, 2016" + +# Revisions + +PROJECT_REVISION = "lab_4_1" diff --git a/cs309-psoc/lab_4_1/hw/quartus/lab_4_1.qsf b/cs309-psoc/lab_4_1/hw/quartus/lab_4_1.qsf new file mode 100644 index 0000000..0ecba8a --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/quartus/lab_4_1.qsf @@ -0,0 +1,1379 @@ +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" + +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA4U23C6 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO Extention OV7670 CAMERA +#============================================================ +set_location_assignment PIN_AE15 -to CAM_D[0] +set_location_assignment PIN_AE15 -to CAM_D_0 +set_location_assignment PIN_AF17 -to CAM_D[1] +set_location_assignment PIN_AF17 -to CAM_D_1 +set_location_assignment PIN_AH8 -to CAM_D[2] +set_location_assignment PIN_AH8 -to CAM_D_2 +set_location_assignment PIN_AG8 -to CAM_D[3] +set_location_assignment PIN_AG8 -to CAM_D_3 +set_location_assignment PIN_U13 -to CAM_D[4] +set_location_assignment PIN_U13 -to CAM_D_4 +set_location_assignment PIN_U14 -to CAM_D[5] +set_location_assignment PIN_U14 -to CAM_D_5 +set_location_assignment PIN_AG9 -to CAM_D[6] +set_location_assignment PIN_AG9 -to CAM_D_6 +set_location_assignment PIN_AG10 -to CAM_D[7] +set_location_assignment PIN_AG10 -to CAM_D_7 +set_location_assignment PIN_AF13 -to CAM_D[8] +set_location_assignment PIN_AF13 -to CAM_D_8 +set_location_assignment PIN_AG13 -to CAM_D[9] +set_location_assignment PIN_AG13 -to CAM_D_9 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9 + +#============================================================ +# Arduino Extension LEPTON CAMERA THERMAL CAM_TH +#============================================================ +set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N +set_location_assignment PIN_AG16 -to CAM_TH_MOSI +set_location_assignment PIN_AH11 -to CAM_TH_MISO +set_location_assignment PIN_AH12 -to CAM_TH_CLK +set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA +set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL + +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#============================================================ +# HPS +#============================================================ +set_location_assignment PIN_C6 -to HPS_CONV_USB_N +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0] +set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0 +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1] +set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1 +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2] +set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2 +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3] +set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3 +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4] +set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4 +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5] +set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5 +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6] +set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6 +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7] +set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7 +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8] +set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8 +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9] +set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9 +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10] +set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10 +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11] +set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11 +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12] +set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12 +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13] +set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13 +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14] +set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14 +set_location_assignment PIN_A27 -to HPS_DDR3_BA[0] +set_location_assignment PIN_A27 -to HPS_DDR3_BA_0 +set_location_assignment PIN_H25 -to HPS_DDR3_BA[1] +set_location_assignment PIN_H25 -to HPS_DDR3_BA_1 +set_location_assignment PIN_G25 -to HPS_DDR3_BA[2] +set_location_assignment PIN_G25 -to HPS_DDR3_BA_2 +set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N +set_location_assignment PIN_L28 -to HPS_DDR3_CKE +set_location_assignment PIN_N20 -to HPS_DDR3_CK_N +set_location_assignment PIN_N21 -to HPS_DDR3_CK_P +set_location_assignment PIN_L21 -to HPS_DDR3_CS_N +set_location_assignment PIN_G28 -to HPS_DDR3_DM[0] +set_location_assignment PIN_G28 -to HPS_DDR3_DM_0 +set_location_assignment PIN_P28 -to HPS_DDR3_DM[1] +set_location_assignment PIN_P28 -to HPS_DDR3_DM_1 +set_location_assignment PIN_W28 -to HPS_DDR3_DM[2] +set_location_assignment PIN_W28 -to HPS_DDR3_DM_2 +set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3] +set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3 +set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0] +set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0 +set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1] +set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1 +set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2] +set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2 +set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3] +set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3 +set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4] +set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4 +set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5] +set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5 +set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6] +set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6 +set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7] +set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7 +set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8] +set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8 +set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9] +set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9 +set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10] +set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10 +set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11] +set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11 +set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12] +set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12 +set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13] +set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13 +set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14] +set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14 +set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15] +set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15 +set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16] +set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16 +set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17] +set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17 +set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18] +set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18 +set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19] +set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19 +set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20] +set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20 +set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21] +set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21 +set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22] +set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22 +set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23] +set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23 +set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24] +set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24 +set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25] +set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25 +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26] +set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26 +set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27] +set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27 +set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28] +set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28 +set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29] +set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29 +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30] +set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30 +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31] +set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31 +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0] +set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0 +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1] +set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1 +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2] +set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2 +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3] +set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3 +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0] +set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0 +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1] +set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1 +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2] +set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2 +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3] +set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3 +set_location_assignment PIN_D28 -to HPS_DDR3_ODT +set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N +set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N +set_location_assignment PIN_D25 -to HPS_DDR3_RZQ +set_location_assignment PIN_E25 -to HPS_DDR3_WE_N +set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK +set_location_assignment PIN_B14 -to HPS_ENET_INT_N +set_location_assignment PIN_A13 -to HPS_ENET_MDC +set_location_assignment PIN_E16 -to HPS_ENET_MDIO +set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0] +set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0 +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1] +set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1 +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2] +set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2 +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3] +set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3 +set_location_assignment PIN_J13 -to HPS_ENET_RX_DV +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0] +set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0 +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1] +set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1 +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2] +set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2 +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3] +set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3 +set_location_assignment PIN_A12 -to HPS_ENET_TX_EN +set_location_assignment PIN_A17 -to HPS_GSENSOR_INT +set_location_assignment PIN_C18 -to HPS_I2C0_SCLK +set_location_assignment PIN_A19 -to HPS_I2C0_SDAT +set_location_assignment PIN_K18 -to HPS_I2C1_SCLK +set_location_assignment PIN_A21 -to HPS_I2C1_SDAT +set_location_assignment PIN_J18 -to HPS_KEY_N +set_location_assignment PIN_A20 -to HPS_LED +set_location_assignment PIN_H13 -to HPS_LTC_GPIO +set_location_assignment PIN_B8 -to HPS_SD_CLK +set_location_assignment PIN_D14 -to HPS_SD_CMD +set_location_assignment PIN_C13 -to HPS_SD_DATA[0] +set_location_assignment PIN_C13 -to HPS_SD_DATA_0 +set_location_assignment PIN_B6 -to HPS_SD_DATA[1] +set_location_assignment PIN_B6 -to HPS_SD_DATA_1 +set_location_assignment PIN_B11 -to HPS_SD_DATA[2] +set_location_assignment PIN_B11 -to HPS_SD_DATA_2 +set_location_assignment PIN_B9 -to HPS_SD_DATA[3] +set_location_assignment PIN_B9 -to HPS_SD_DATA_3 +set_location_assignment PIN_C19 -to HPS_SPIM_CLK +set_location_assignment PIN_B19 -to HPS_SPIM_MISO +set_location_assignment PIN_B16 -to HPS_SPIM_MOSI +set_location_assignment PIN_C16 -to HPS_SPIM_SS +set_location_assignment PIN_A22 -to HPS_UART_RX +set_location_assignment PIN_B21 -to HPS_UART_TX +set_location_assignment PIN_G4 -to HPS_USB_CLKOUT +set_location_assignment PIN_C10 -to HPS_USB_DATA[0] +set_location_assignment PIN_C10 -to HPS_USB_DATA_0 +set_location_assignment PIN_F5 -to HPS_USB_DATA[1] +set_location_assignment PIN_F5 -to HPS_USB_DATA_1 +set_location_assignment PIN_C9 -to HPS_USB_DATA[2] +set_location_assignment PIN_C9 -to HPS_USB_DATA_2 +set_location_assignment PIN_C4 -to HPS_USB_DATA[3] +set_location_assignment PIN_C4 -to HPS_USB_DATA_3 +set_location_assignment PIN_C8 -to HPS_USB_DATA[4] +set_location_assignment PIN_C8 -to HPS_USB_DATA_4 +set_location_assignment PIN_D4 -to HPS_USB_DATA[5] +set_location_assignment PIN_D4 -to HPS_USB_DATA_5 +set_location_assignment PIN_C7 -to HPS_USB_DATA[6] +set_location_assignment PIN_C7 -to HPS_USB_DATA_6 +set_location_assignment PIN_F4 -to HPS_USB_DATA[7] +set_location_assignment PIN_F4 -to HPS_USB_DATA_7 +set_location_assignment PIN_E5 -to HPS_USB_DIR +set_location_assignment PIN_D5 -to HPS_USB_NXT +set_location_assignment PIN_C5 -to HPS_USB_STP + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY_N +#============================================================ +set_location_assignment PIN_AH17 -to KEY_N[0] +set_location_assignment PIN_AH17 -to KEY_N_0 +set_location_assignment PIN_AH16 -to KEY_N[1] +set_location_assignment PIN_AH16 -to KEY_N_1 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_W15 -to LED_0 +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_AA24 -to LED_1 +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V16 -to LED_2 +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_V15 -to LED_3 +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AF26 -to LED_4 +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_AE26 -to LED_5 +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_Y16 -to LED_6 +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_AA23 -to LED_7 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7 + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_L10 -to SW[0] +set_location_assignment PIN_L10 -to SW_0 +set_location_assignment PIN_L9 -to SW[1] +set_location_assignment PIN_L9 -to SW_1 +set_location_assignment PIN_H6 -to SW[2] +set_location_assignment PIN_H6 -to SW_2 +set_location_assignment PIN_H5 -to SW[3] +set_location_assignment PIN_H5 -to SW_3 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3 + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_V12 -to PIO_INT_N +set_location_assignment PIN_AE11 -to PIO_SCL +set_location_assignment PIN_AE12 -to PIO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA + +set_location_assignment PIN_AF7 -to PIR_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT + +set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA +set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL +set_location_assignment PIN_T11 -to CAM_SYS_CLK +set_location_assignment PIN_AG6 -to CAM_LV +set_location_assignment PIN_AH2 -to CAM_PIX_CLK +set_location_assignment PIN_AE4 -to CAM_FV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV + +set_location_assignment PIN_Y8 -to PAL_VD_HSO +set_location_assignment PIN_AB4 -to PAL_VD_VSO +set_location_assignment PIN_AG5 -to PAL_VD_VD[0] +set_location_assignment PIN_AG5 -to PAL_VD_VD_0 +set_location_assignment PIN_AH5 -to PAL_VD_VD[1] +set_location_assignment PIN_AH5 -to PAL_VD_VD_1 +set_location_assignment PIN_AH6 -to PAL_VD_VD[2] +set_location_assignment PIN_AH6 -to PAL_VD_VD_2 +set_location_assignment PIN_T8 -to PAL_VD_VD[3] +set_location_assignment PIN_T8 -to PAL_VD_VD_3 +set_location_assignment PIN_T12 -to PAL_VD_VD[4] +set_location_assignment PIN_T12 -to PAL_VD_VD_4 +set_location_assignment PIN_Y5 -to PAL_VD_VD[5] +set_location_assignment PIN_Y5 -to PAL_VD_VD_5 +set_location_assignment PIN_Y4 -to PAL_VD_VD[6] +set_location_assignment PIN_Y4 -to PAL_VD_VD_6 +set_location_assignment PIN_W8 -to PAL_VD_VD[7] +set_location_assignment PIN_W8 -to PAL_VD_VD_7 +set_location_assignment PIN_AH4 -to PAL_VD_CLKO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO + +set_location_assignment PIN_AH3 -to SERVO_0 +set_location_assignment PIN_AF4 -to SERVO_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1 + +set_location_assignment PIN_AD12 -to J0_SPI_CLK +set_location_assignment PIN_AD11 -to J0_SPI_MISO +set_location_assignment PIN_AF9 -to J0_SPI_CS_N +set_location_assignment PIN_AD10 -to J0_SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI + +set_location_assignment PIN_AF5 -to FROM_ESP_TXD +set_location_assignment PIN_T13 -to TO_ESP_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD + +set_location_assignment PIN_AE7 -to SPI_MISO +set_location_assignment PIN_AF6 -to SPI_ENA_N +set_location_assignment PIN_AE8 -to SPI_CLK +set_location_assignment PIN_AE9 -to SPI_MOSI +set_location_assignment PIN_AF10 -to SPI_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT + +set_location_assignment PIN_AF11 -to LED_BGR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_AA15 -to RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N + +set_location_assignment PIN_AG28 -to TS_SCL +set_location_assignment PIN_AH27 -to TS_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA + +set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N +set_location_assignment PIN_AG26 -to LCD_DE +set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN + +set_location_assignment PIN_AH24 -to BLT_TXD +set_location_assignment PIN_AE22 -to BLT_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD + +set_location_assignment PIN_AG20 -to BOARD_ID +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID + +set_location_assignment PIN_AF21 -to VIDEO_HSYNC +set_location_assignment PIN_AG19 -to VIDEO_VSYNC +set_location_assignment PIN_AF20 -to VIDEO_CLK +set_location_assignment PIN_AG23 -to VIDEO_B[0] +set_location_assignment PIN_AG23 -to VIDEO_B_0 +set_location_assignment PIN_AH23 -to VIDEO_B[1] +set_location_assignment PIN_AH23 -to VIDEO_B_1 +set_location_assignment PIN_AF25 -to VIDEO_B[2] +set_location_assignment PIN_AF25 -to VIDEO_B_2 +set_location_assignment PIN_AG24 -to VIDEO_B[3] +set_location_assignment PIN_AG24 -to VIDEO_B_3 +set_location_assignment PIN_AA19 -to VIDEO_B[4] +set_location_assignment PIN_AA19 -to VIDEO_B_4 +set_location_assignment PIN_AH26 -to VIDEO_B[5] +set_location_assignment PIN_AH26 -to VIDEO_B_5 +set_location_assignment PIN_AG18 -to VIDEO_B[6] +set_location_assignment PIN_AG18 -to VIDEO_B_6 +set_location_assignment PIN_AC23 -to VIDEO_B[7] +set_location_assignment PIN_AC23 -to VIDEO_B_7 +set_location_assignment PIN_AH22 -to VIDEO_G[0] +set_location_assignment PIN_AH22 -to VIDEO_G_0 +set_location_assignment PIN_AF22 -to VIDEO_G[1] +set_location_assignment PIN_AF22 -to VIDEO_G_1 +set_location_assignment PIN_AD20 -to VIDEO_G[2] +set_location_assignment PIN_AD20 -to VIDEO_G_2 +set_location_assignment PIN_AE24 -to VIDEO_G[3] +set_location_assignment PIN_AE24 -to VIDEO_G_3 +set_location_assignment PIN_AE20 -to VIDEO_G[4] +set_location_assignment PIN_AE20 -to VIDEO_G_4 +set_location_assignment PIN_AD19 -to VIDEO_G[5] +set_location_assignment PIN_AD19 -to VIDEO_G_5 +set_location_assignment PIN_AF18 -to VIDEO_G[6] +set_location_assignment PIN_AF18 -to VIDEO_G_6 +set_location_assignment PIN_AE19 -to VIDEO_G[7] +set_location_assignment PIN_AE19 -to VIDEO_G_7 +set_location_assignment PIN_AC22 -to VIDEO_R[0] +set_location_assignment PIN_AC22 -to VIDEO_R_0 +set_location_assignment PIN_AA18 -to VIDEO_R[1] +set_location_assignment PIN_AA18 -to VIDEO_R_1 +set_location_assignment PIN_AE23 -to VIDEO_R[2] +set_location_assignment PIN_AE23 -to VIDEO_R_2 +set_location_assignment PIN_AD23 -to VIDEO_R[3] +set_location_assignment PIN_AD23 -to VIDEO_R_3 +set_location_assignment PIN_AH18 -to VIDEO_R[4] +set_location_assignment PIN_AH18 -to VIDEO_R_4 +set_location_assignment PIN_AG21 -to VIDEO_R[5] +set_location_assignment PIN_AG21 -to VIDEO_R_5 +set_location_assignment PIN_AH21 -to VIDEO_R[6] +set_location_assignment PIN_AH21 -to VIDEO_R_6 +set_location_assignment PIN_AH19 -to VIDEO_R[7] +set_location_assignment PIN_AH19 -to VIDEO_R_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7 + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_AG13 -to ARDUINO_IO[0] +set_location_assignment PIN_AG13 -to ARDUINO_IO_0 +set_location_assignment PIN_AF13 -to ARDUINO_IO[1] +set_location_assignment PIN_AF13 -to ARDUINO_IO_1 +set_location_assignment PIN_AG10 -to ARDUINO_IO[2] +set_location_assignment PIN_AG10 -to ARDUINO_IO_2 +set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +set_location_assignment PIN_AG9 -to ARDUINO_IO_3 +set_location_assignment PIN_U14 -to ARDUINO_IO[4] +set_location_assignment PIN_U14 -to ARDUINO_IO_4 +set_location_assignment PIN_U13 -to ARDUINO_IO[5] +set_location_assignment PIN_U13 -to ARDUINO_IO_5 +set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +set_location_assignment PIN_AG8 -to ARDUINO_IO_6 +set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +set_location_assignment PIN_AH8 -to ARDUINO_IO_7 +set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +set_location_assignment PIN_AF17 -to ARDUINO_IO_8 +set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +set_location_assignment PIN_AE15 -to ARDUINO_IO_9 +set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +set_location_assignment PIN_AF15 -to ARDUINO_IO_10 +set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +set_location_assignment PIN_AG16 -to ARDUINO_IO_11 +set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +set_location_assignment PIN_AH11 -to ARDUINO_IO_12 +set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +set_location_assignment PIN_AH12 -to ARDUINO_IO_13 +set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +set_location_assignment PIN_AH9 -to ARDUINO_IO_14 +set_location_assignment PIN_AG11 -to ARDUINO_IO[15] +set_location_assignment PIN_AG11 -to ARDUINO_IO_15 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_9 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_11 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_12 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_13 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_14 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_15 +set_location_assignment PIN_V12 -to GPIO_0[0] +set_location_assignment PIN_V12 -to GPIO_0_0 +set_location_assignment PIN_AF7 -to GPIO_0[1] +set_location_assignment PIN_AF7 -to GPIO_0_1 +set_location_assignment PIN_W12 -to GPIO_0[2] +set_location_assignment PIN_W12 -to GPIO_0_2 +set_location_assignment PIN_AF8 -to GPIO_0[3] +set_location_assignment PIN_AF8 -to GPIO_0_3 +set_location_assignment PIN_Y8 -to GPIO_0[4] +set_location_assignment PIN_Y8 -to GPIO_0_4 +set_location_assignment PIN_AB4 -to GPIO_0[5] +set_location_assignment PIN_AB4 -to GPIO_0_5 +set_location_assignment PIN_W8 -to GPIO_0[6] +set_location_assignment PIN_W8 -to GPIO_0_6 +set_location_assignment PIN_Y4 -to GPIO_0[7] +set_location_assignment PIN_Y4 -to GPIO_0_7 +set_location_assignment PIN_Y5 -to GPIO_0[8] +set_location_assignment PIN_Y5 -to GPIO_0_8 +set_location_assignment PIN_U11 -to GPIO_0[9] +set_location_assignment PIN_U11 -to GPIO_0_9 +set_location_assignment PIN_T8 -to GPIO_0[10] +set_location_assignment PIN_T8 -to GPIO_0_10 +set_location_assignment PIN_T12 -to GPIO_0[11] +set_location_assignment PIN_T12 -to GPIO_0_11 +set_location_assignment PIN_AH5 -to GPIO_0[12] +set_location_assignment PIN_AH5 -to GPIO_0_12 +set_location_assignment PIN_AH6 -to GPIO_0[13] +set_location_assignment PIN_AH6 -to GPIO_0_13 +set_location_assignment PIN_AH4 -to GPIO_0[14] +set_location_assignment PIN_AH4 -to GPIO_0_14 +set_location_assignment PIN_AG5 -to GPIO_0[15] +set_location_assignment PIN_AG5 -to GPIO_0_15 +set_location_assignment PIN_AH3 -to GPIO_0[16] +set_location_assignment PIN_AH3 -to GPIO_0_16 +set_location_assignment PIN_AH2 -to GPIO_0[17] +set_location_assignment PIN_AH2 -to GPIO_0_17 +set_location_assignment PIN_AF4 -to GPIO_0[18] +set_location_assignment PIN_AF4 -to GPIO_0_18 +set_location_assignment PIN_AG6 -to GPIO_0[19] +set_location_assignment PIN_AG6 -to GPIO_0_19 +set_location_assignment PIN_AF5 -to GPIO_0[20] +set_location_assignment PIN_AF5 -to GPIO_0_20 +set_location_assignment PIN_AE4 -to GPIO_0[21] +set_location_assignment PIN_AE4 -to GPIO_0_21 +set_location_assignment PIN_T13 -to GPIO_0[22] +set_location_assignment PIN_T13 -to GPIO_0_22 +set_location_assignment PIN_T11 -to GPIO_0[23] +set_location_assignment PIN_T11 -to GPIO_0_23 +set_location_assignment PIN_AE7 -to GPIO_0[24] +set_location_assignment PIN_AE7 -to GPIO_0_24 +set_location_assignment PIN_AF6 -to GPIO_0[25] +set_location_assignment PIN_AF6 -to GPIO_0_25 +set_location_assignment PIN_AF9 -to GPIO_0[26] +set_location_assignment PIN_AF9 -to GPIO_0_26 +set_location_assignment PIN_AE8 -to GPIO_0[27] +set_location_assignment PIN_AE8 -to GPIO_0_27 +set_location_assignment PIN_AD10 -to GPIO_0[28] +set_location_assignment PIN_AD10 -to GPIO_0_28 +set_location_assignment PIN_AE9 -to GPIO_0[29] +set_location_assignment PIN_AE9 -to GPIO_0_29 +set_location_assignment PIN_AD11 -to GPIO_0[30] +set_location_assignment PIN_AD11 -to GPIO_0_30 +set_location_assignment PIN_AF10 -to GPIO_0[31] +set_location_assignment PIN_AF10 -to GPIO_0_31 +set_location_assignment PIN_AD12 -to GPIO_0[32] +set_location_assignment PIN_AD12 -to GPIO_0_32 +set_location_assignment PIN_AE11 -to GPIO_0[33] +set_location_assignment PIN_AE11 -to GPIO_0_33 +set_location_assignment PIN_AF11 -to GPIO_0[34] +set_location_assignment PIN_AF11 -to GPIO_0_34 +set_location_assignment PIN_AE12 -to GPIO_0[35] +set_location_assignment PIN_AE12 -to GPIO_0_35 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_9 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_11 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_12 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_13 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_14 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_15 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_16 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_17 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_18 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_19 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_20 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_21 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_22 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_23 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_24 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_26 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_28 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_29 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_30 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_31 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_32 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_33 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_34 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_35 +set_location_assignment PIN_Y15 -to GPIO_1[0] +set_location_assignment PIN_Y15 -to GPIO_1_0 +set_location_assignment PIN_AG28 -to GPIO_1[1] +set_location_assignment PIN_AG28 -to GPIO_1_1 +set_location_assignment PIN_AA15 -to GPIO_1[2] +set_location_assignment PIN_AA15 -to GPIO_1_2 +set_location_assignment PIN_AH27 -to GPIO_1[3] +set_location_assignment PIN_AH27 -to GPIO_1_3 +set_location_assignment PIN_AG26 -to GPIO_1[4] +set_location_assignment PIN_AG26 -to GPIO_1_4 +set_location_assignment PIN_AH24 -to GPIO_1[5] +set_location_assignment PIN_AH24 -to GPIO_1_5 +set_location_assignment PIN_AF23 -to GPIO_1[6] +set_location_assignment PIN_AF23 -to GPIO_1_6 +set_location_assignment PIN_AE22 -to GPIO_1[7] +set_location_assignment PIN_AE22 -to GPIO_1_7 +set_location_assignment PIN_AF21 -to GPIO_1[8] +set_location_assignment PIN_AF21 -to GPIO_1_8 +set_location_assignment PIN_AG20 -to GPIO_1[9] +set_location_assignment PIN_AG20 -to GPIO_1_9 +set_location_assignment PIN_AG19 -to GPIO_1[10] +set_location_assignment PIN_AG19 -to GPIO_1_10 +set_location_assignment PIN_AF20 -to GPIO_1[11] +set_location_assignment PIN_AF20 -to GPIO_1_11 +set_location_assignment PIN_AC23 -to GPIO_1[12] +set_location_assignment PIN_AC23 -to GPIO_1_12 +set_location_assignment PIN_AG18 -to GPIO_1[13] +set_location_assignment PIN_AG18 -to GPIO_1_13 +set_location_assignment PIN_AH26 -to GPIO_1[14] +set_location_assignment PIN_AH26 -to GPIO_1_14 +set_location_assignment PIN_AA19 -to GPIO_1[15] +set_location_assignment PIN_AA19 -to GPIO_1_15 +set_location_assignment PIN_AG24 -to GPIO_1[16] +set_location_assignment PIN_AG24 -to GPIO_1_16 +set_location_assignment PIN_AF25 -to GPIO_1[17] +set_location_assignment PIN_AF25 -to GPIO_1_17 +set_location_assignment PIN_AH23 -to GPIO_1[18] +set_location_assignment PIN_AH23 -to GPIO_1_18 +set_location_assignment PIN_AG23 -to GPIO_1[19] +set_location_assignment PIN_AG23 -to GPIO_1_19 +set_location_assignment PIN_AE19 -to GPIO_1[20] +set_location_assignment PIN_AE19 -to GPIO_1_20 +set_location_assignment PIN_AF18 -to GPIO_1[21] +set_location_assignment PIN_AF18 -to GPIO_1_21 +set_location_assignment PIN_AD19 -to GPIO_1[22] +set_location_assignment PIN_AD19 -to GPIO_1_22 +set_location_assignment PIN_AE20 -to GPIO_1[23] +set_location_assignment PIN_AE20 -to GPIO_1_23 +set_location_assignment PIN_AE24 -to GPIO_1[24] +set_location_assignment PIN_AE24 -to GPIO_1_24 +set_location_assignment PIN_AD20 -to GPIO_1[25] +set_location_assignment PIN_AD20 -to GPIO_1_25 +set_location_assignment PIN_AF22 -to GPIO_1[26] +set_location_assignment PIN_AF22 -to GPIO_1_26 +set_location_assignment PIN_AH22 -to GPIO_1[27] +set_location_assignment PIN_AH22 -to GPIO_1_27 +set_location_assignment PIN_AH19 -to GPIO_1[28] +set_location_assignment PIN_AH19 -to GPIO_1_28 +set_location_assignment PIN_AH21 -to GPIO_1[29] +set_location_assignment PIN_AH21 -to GPIO_1_29 +set_location_assignment PIN_AG21 -to GPIO_1[30] +set_location_assignment PIN_AG21 -to GPIO_1_30 +set_location_assignment PIN_AH18 -to GPIO_1[31] +set_location_assignment PIN_AH18 -to GPIO_1_31 +set_location_assignment PIN_AD23 -to GPIO_1[32] +set_location_assignment PIN_AD23 -to GPIO_1_32 +set_location_assignment PIN_AE23 -to GPIO_1[33] +set_location_assignment PIN_AE23 -to GPIO_1_33 +set_location_assignment PIN_AA18 -to GPIO_1[34] +set_location_assignment PIN_AA18 -to GPIO_1_34 +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AC22 -to GPIO_1_35 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_9 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_11 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_12 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_13 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_14 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_15 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_16 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_17 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_18 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_19 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_20 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_21 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_22 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_23 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_24 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_26 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_28 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_29 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_30 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_31 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_32 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_33 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_34 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_35 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name QSYS_FILE soc_system.qsys +set_global_assignment -name SOURCE_FILE soc_system/soc_system.cmp +set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd +set_global_assignment -name SDC_FILE lab_4_1.sdc +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_P -tag __hps_sdram_p0 +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_P -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_N -tag __hps_sdram_p0 +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[0] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[10] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[11] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[12] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[13] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[14] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[1] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[2] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[3] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[4] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[5] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[6] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[7] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[8] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[9] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[0] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[1] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[2] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CAS_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CKE -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CS_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ODT -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RAS_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_WE_N -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RESET_N -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[10] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[11] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[12] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[13] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[14] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[4] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[5] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[6] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[7] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[8] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[9] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CAS_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CKE -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CS_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ODT -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RAS_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_WE_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RESET_N -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_P -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_N -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -tag __hps_sdram_p0 +set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to u0|hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0 +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to u0|hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0 +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON +set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name ECO_REGENERATE_REPORT ON +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON \ No newline at end of file diff --git a/cs309-psoc/lab_4_1/hw/quartus/lab_4_1.sdc b/cs309-psoc/lab_4_1/hw/quartus/lab_4_1.sdc new file mode 100644 index 0000000..16a41f3 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/quartus/lab_4_1.sdc @@ -0,0 +1,6 @@ +create_clock -period 20 [get_ports FPGA_CLK1_50] +create_clock -period 20 [get_ports FPGA_CLK2_50] +create_clock -period 20 [get_ports FPGA_CLK3_50] + +derive_pll_clocks +derive_clock_uncertainty diff --git a/cs309-psoc/lab_4_1/hw/quartus/soc_system.qsys b/cs309-psoc/lab_4_1/hw/quartus/soc_system.qsys new file mode 100644 index 0000000..43919a2 --- /dev/null +++ b/cs309-psoc/lab_4_1/hw/quartus/soc_system.qsys @@ -0,0 +1,915 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + 0x000000000000000000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cs309-psoc/lab_4_1/lab_3_1.pdf b/cs309-psoc/lab_4_1/lab_3_1.pdf new file mode 100644 index 0000000..ebb19ef Binary files /dev/null and b/cs309-psoc/lab_4_1/lab_3_1.pdf differ diff --git a/cs309-psoc/lab_4_1/sw/hps/application/client-sfml/Makefile b/cs309-psoc/lab_4_1/sw/hps/application/client-sfml/Makefile new file mode 100644 index 0000000..b0eec66 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/client-sfml/Makefile @@ -0,0 +1,14 @@ + +CC=g++ +LDLIBS=`pkg-config --libs sfml-graphics sfml-window sfml-network` + +all: main + +main.o: main.cpp +main: main.o + +run: + @./main + +clean: + rm -f main.o main diff --git a/cs309-psoc/lab_4_1/sw/hps/application/client-sfml/main.cpp b/cs309-psoc/lab_4_1/sw/hps/application/client-sfml/main.cpp new file mode 100644 index 0000000..f94fe2a --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/client-sfml/main.cpp @@ -0,0 +1,120 @@ + +#include +#include +#include +#include +using namespace std; + +#define IMAGE_WIDTH 80 +#define IMAGE_HEIGHT 60 +#define SCALE_FACTOR 10 +#define UPDATE_INTERVAL IMAGE_HEIGHT + +#define SERVER_PORT 25700 +#define BUFFER_SIZE (4 + IMAGE_WIDTH * 2) +#define HANDSHAKE_TIMEOUT 2000 + +void updateLine(uint8_t* buffer, uint32_t lineIndex, uint16_t* line); +void bernsteinRGB(uint8_t* rgba, double t); +void sendHandshake(sf::UdpSocket& socket, sf::IpAddress address, unsigned short port); + +int main(int argc, char* argv[]) { + if (argc != 2) { + cout << "Invalid usage of client. You should pass the address of the server." << endl; + return -1; + } + + // We create the window to which we render the image + sf::RenderWindow window(sf::VideoMode(IMAGE_WIDTH * SCALE_FACTOR, IMAGE_HEIGHT * SCALE_FACTOR), "Thermalizer", sf::Style::Close); + + // The intermediate buffer in which the image is received before being sent to the GPU + uint8_t buffer[IMAGE_HEIGHT * IMAGE_WIDTH * 4]; // RGBA = 4 bytes per pixel + size_t lastRefresh = 0; // the number of lines since the last refresh + uint32_t lineIndex = 0; // the index of the last line that was received + + // The texture to which the image will be drawn + sf::Texture texture; + texture.create(IMAGE_WIDTH, IMAGE_HEIGHT); + sf::Sprite sprite; + sprite.setTexture(texture); + sprite.setScale(SCALE_FACTOR, SCALE_FACTOR); + + // The buffer in which the packet for the lines are received + char lineBuffer[BUFFER_SIZE]; + size_t received; + sf::IpAddress serverAddress(argv[1]), senderAddress; + unsigned short serverPort = SERVER_PORT, senderPort; + + // Create the UDP socket + cout << "Creating and binding a UDP socket..." << endl; + sf::UdpSocket socket; + sf::SocketSelector selector; + if (socket.bind(sf::UdpSocket::AnyPort) != sf::Socket::Done) { + cout << "Couldn't bind socket on port " << socket.getLocalPort() << endl; + return -1; + } + + cout << "UDP Socket successfully bound." << endl; + sendHandshake(socket, serverAddress, serverPort); + selector.add(socket); + + while (window.isOpen()) { + sf::Event event; + while (window.pollEvent(event)) { + // If the user requested the window to be closed + if (event.type == sf::Event::Closed || + (event.type == sf::Event::KeyPressed && event.key.code == sf::Keyboard::Q)) { + // Inform the server about the client stopping + socket.send(nullptr, 0, serverAddress, serverPort); + window.close(); + } + } + + if (selector.wait(sf::milliseconds(500))) { + // If a packet was received, we update the intermediate buffer + socket.receive(lineBuffer, BUFFER_SIZE, received, senderAddress, senderPort); + lineIndex = *((uint32_t*) lineBuffer); + updateLine(buffer, lineIndex, (uint16_t*) (lineBuffer + sizeof(uint32_t))); + lastRefresh++; + } else { + // If no packet was received in a while, we re-send a handshake to try to reconnect + sendHandshake(socket, serverAddress, serverPort); + } + + // We refresh the image every once in a while, so that if there is packet loss on the last + // line the screen is still updated. + if (lastRefresh == UPDATE_INTERVAL || lineIndex == IMAGE_HEIGHT - 1) { + // If enough packets were received, we update the texture + lastRefresh = 0; + texture.update(buffer); + + // And draw it to the screen + window.clear(); + window.draw(sprite); + window.display(); + } + + } +} + +// Updates the line of the buffer with the packet that arrived +void updateLine(uint8_t* buffer, uint32_t lineIndex, uint16_t* line) { + uint8_t* lineBuffer = buffer + lineIndex * IMAGE_WIDTH * 4; + + for (size_t x = 0; x < IMAGE_WIDTH; x++) + bernsteinRGB(lineBuffer + x * 4, (double) line[x] / 0x3FFF); +} + +// Performs the color interpolation using Bernstein polynomials +void bernsteinRGB(uint8_t* rgba, double t) { + rgba[0] = (9 * (1 - t) * t * t * t) * 255; + rgba[1] = (15 * (1 - t) * (1 - t) * t * t) * 255; + rgba[2] = (9 * (1 - t) * (1 - t) * (1 - t) * t) * 255; + rgba[3] = 255; +} + +// Sends a handshake to the server +void sendHandshake(sf::UdpSocket& socket, sf::IpAddress address, unsigned short port) { + cout << "Sending a handshake to the server..." << endl; + socket.send(nullptr, 0, address, port); +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/client/Makefile b/cs309-psoc/lab_4_1/sw/hps/application/client/Makefile new file mode 100644 index 0000000..f8bae50 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/client/Makefile @@ -0,0 +1,5 @@ +LDLIBS= -lcaca +CFLAGS= -Wall + +main: main.o +main.o: main.c diff --git a/cs309-psoc/lab_4_1/sw/hps/application/client/main.c b/cs309-psoc/lab_4_1/sw/hps/application/client/main.c new file mode 100644 index 0000000..e374ad6 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/client/main.c @@ -0,0 +1,216 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define ERR -1 +#define NO_ERR 0 + +#define M_REQUIRE(cond_, mess_, ...) \ + do{ \ + if(!(cond_)){ \ + fprintf(stderr, mess_, ##__VA_ARGS__); \ + return ERR; \ + } \ + }while(0); + +#define M_REQUIRE_NO_ERR(v, mess_, ...)\ + M_REQUIRE(v==NO_ERR, mess_, ##__VA_ARGS__) + +#define M_REQUIRE_NO_NULL(v, mess_, ...)\ + M_REQUIRE(v!=NULL, mess_, ##__VA_ARGS__) + +#define MAX(a,b) ((a)>(b)?(a):(b)) +#define MIN(a,b) ((a)<(b)?(a):(b)) + +#define DEFAULT_PORT 25700 + +#define IM_WIDTH 80 +#define IM_HEIGHT 60 +#define IM_BPP 16 +#define IM_TOTAL IM_WIDTH*IM_HEIGHT + +#define PCKT_SIZE (IM_WIDTH*sizeof(pix_t)+sizeof(uint32_t)) + +#define PX_MAX_V 0x3FFF + +#define IM_MR 0xFF00 +#define IM_MG 0x0000 +#define IM_MB 0x00FF +#define IM_MA 0x0000 + +#define IM_5B 0x1F + +#define REF_DIV 1 + + +typedef uint16_t pix_t; +typedef struct sockaddr_in saddr_t; + +/*=================================================================================================*/ + + +pix_t IMG_IN[IM_TOTAL] = {0}; +caca_canvas_t* cv = NULL; +caca_display_t* dp = NULL; +caca_dither_t* dither; +int ww = 0, wh = 0; +uint64_t msg_cnt = 0; +uint8_t refresh = 0; + +char event = 0; + +/*=================================================================================================*/ + +int setup_caca(){ + cv = caca_create_canvas(IM_WIDTH,IM_HEIGHT); + M_REQUIRE_NO_NULL(cv, "Error: Unable to create caca canvas\n"); + dp = caca_create_display(cv); + M_REQUIRE_NO_NULL(dp, "Error: Unable to create caca canvas\n"); + caca_set_display_title(dp,"CACA HEAT VIEWER"); + ww = caca_get_canvas_width(cv); + wh = caca_get_canvas_height(cv); + + #ifdef COLORING_RB + dither = caca_create_dither(IM_BPP,IM_WIDTH,IM_HEIGHT,IM_WIDTH*sizeof(pix_t),IM_MR,IM_MG,IM_MB,IM_MA); + #else + dither = caca_create_dither(IM_BPP,IM_WIDTH,IM_HEIGHT,IM_WIDTH*sizeof(pix_t),IM_5B<<10,IM_5B<<5,IM_5B,IM_MA); + #endif + + caca_refresh_display(dp); + return NO_ERR; +} + +int clear_caca(){ + caca_free_display(dp); + caca_free_canvas(cv); + return NO_ERR; +} + +int get_server_addr(const char* ip, const uint16_t port, struct sockaddr_in* const p_server_addr){ + assert(p_server_addr != NULL); + + struct sockaddr_in server_addr = {0}; + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(port); + if(ip == NULL){ + server_addr.sin_addr.s_addr = htonl(INADDR_ANY); + }else{ + M_REQUIRE(inet_aton(ip, &server_addr.sin_addr)== 1, "Error: Unable to set server adress (IP)\n"); + } + *p_server_addr = server_addr; + return NO_ERR; +} + +int bind_server(const int socket, const uint16_t port){ + struct sockaddr_in server_addr; + M_REQUIRE_NO_ERR(get_server_addr(NULL, port, &server_addr), "Error: Unable to get server adress\n"); + M_REQUIRE_NO_ERR(bind(socket, (const struct sockaddr*) &server_addr, sizeof(server_addr)), " Error: Unable to bind socket\n"); + return NO_ERR; +} + +pix_t bernstein_rgb(float f){ + uint8_t r = (9*(1-f) *f *f *f)*IM_5B; + uint8_t g = (15*(1-f) *(1-f) *f *f)*IM_5B; + uint8_t b = (9*(1-f) *(1-f) *(1-f) *f)*IM_5B; + return r<<10 | g<<5 | b; +} + +pix_t custom_rb(float f){ + uint8_t r = f*0xFF ; + uint8_t b = (1-f)*0xFF; + return r<<8 | b; +} + +void adjust_row(uint32_t row){ + for(size_t i = 0; i < IM_WIDTH; ++i){ + #ifdef COLORING_RB + IMG_IN[row*IM_WIDTH+i] = custom_rb((float)IMG_IN[row*IM_WIDTH+i]/PX_MAX_V); + #else + IMG_IN[row*IM_WIDTH+i] = bernstein_rgb((float)IMG_IN[row*IM_WIDTH+i]/PX_MAX_V); + #endif + } +} + +int handle_message(ssize_t in_msg_len, uint8_t* in_msg){ + M_REQUIRE_NO_NULL(in_msg,"Error: input message is null\n"); + M_REQUIRE(in_msg_len >=0, "Error: server message timeout\n"); + M_REQUIRE(in_msg_len == PCKT_SIZE, "Error: message with wrong length (%zu)\n",in_msg_len); + + uint32_t row = (uint32_t) in_msg[0]; + if(row < IM_HEIGHT){ + memcpy(IMG_IN + row*IM_WIDTH, in_msg + sizeof(uint32_t), IM_WIDTH*sizeof(pix_t)); + adjust_row(row); + } + if(row == IM_HEIGHT-1){ + refresh = 1; + } + + return NO_ERR; +} + +int main (int argc, char** argv){ + M_REQUIRE(argc==2,"Invalid usage of client. You should pass the address of the server.\n"); + + fprintf(stderr, "Starting Caca\n"); + M_REQUIRE_NO_ERR(setup_caca(),"Error: Creating Caca\n"); + memset(IMG_IN,0,IM_TOTAL*sizeof(pix_t)); + M_REQUIRE_NO_ERR(caca_dither_bitmap(cv,0,0,IM_WIDTH,IM_HEIGHT,dither,IMG_IN), "Error: Unable to draw\n"); + caca_refresh_display(dp); + fprintf(stderr, "Started CACA HEAT VIEWER successfully\n"); + + fprintf(stderr, "Starting Network\n"); + int32_t s = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + M_REQUIRE(s > 0, "Error: Unable to open socket\n"); + M_REQUIRE_NO_ERR(bind_server(s, 0), "Error: Unable to bind socket\n"); + saddr_t srv_addr; + M_REQUIRE_NO_ERR(get_server_addr(argv[1], DEFAULT_PORT, &srv_addr), "Error: Unable to get server adress\n"); + fprintf(stderr, "Started Network\n"); + + fprintf(stderr, "Sending poke to server...\n"); + char e = 0; + M_REQUIRE(sendto(s,&e,0,0,(struct sockaddr *)&srv_addr,sizeof(srv_addr))==0, " Error: Unable to send message to server\n"); + fprintf(stderr, "Sent poke successfully\n"); + uint8_t quit = 0; + while(!feof(stdin) && !ferror(stdin) && !quit){ + caca_event_t ev; + if(caca_get_event(dp, CACA_EVENT_RESIZE | CACA_EVENT_QUIT | CACA_EVENT_KEY_PRESS, &ev, 0)){ + if(caca_get_event_type(&ev) == CACA_EVENT_RESIZE){ + caca_set_canvas_size(cv,IM_WIDTH,IM_HEIGHT); + }else if(caca_get_event_type(&ev) & CACA_EVENT_QUIT){ + quit = 1; + }else { + switch(caca_get_event_key_ch(&ev)){ + case 'Q': + case 'q': + quit=1; + break; + default: + break; + } + } + } + uint8_t in_msg[PCKT_SIZE] = {0}; + ssize_t in_msg_len = recv(s, in_msg, PCKT_SIZE, 0); + M_REQUIRE_NO_ERR(handle_message(in_msg_len, in_msg), "Error: Couldn't handle message\n"); + ++msg_cnt; + if (msg_cnt%(IM_HEIGHT/REF_DIV)==0 || refresh){ + refresh = 0; + msg_cnt = 0; + M_REQUIRE_NO_ERR(caca_dither_bitmap(cv,0,0,IM_WIDTH,IM_HEIGHT,dither,IMG_IN), "Error: Unable to draw\n"); + caca_refresh_display(dp); + } + } + M_REQUIRE(sendto(s,&e,0,0,(struct sockaddr *)&srv_addr,sizeof(srv_addr))==0, " Error: Unable to send message to server\n"); + M_REQUIRE_NO_ERR(clear_caca(),"Error: Clearing Caca\n" ); + close(s); + + return NO_ERR; +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/hps_soc_system.h b/cs309-psoc/lab_4_1/sw/hps/application/hps_soc_system.h new file mode 100644 index 0000000..6d58999 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/hps_soc_system.h @@ -0,0 +1,67 @@ +#ifndef _ALTERA_HPS_SOC_SYSTEM_H_ +#define _ALTERA_HPS_SOC_SYSTEM_H_ + +/* + * This file was automatically generated by the swinfo2header utility. + * + * Created from SOPC Builder system 'soc_system' in + * file 'hw/quartus/soc_system.sopcinfo'. + */ + +/* + * This file contains macros for module 'hps_0' and devices + * connected to the following master: + * h2f_lw_axi_master + * + * Do not include this header file and another header file created for a + * different module or master group at the same time. + * Doing so may result in duplicate macro names. + * Instead, use the system header file which has macros with unique names. + */ + +/* + * Macros for device 'lepton_0', class 'lepton' + * The macros are prefixed with 'LEPTON_0_'. + * The prefix is the slave descriptor. + */ +#define LEPTON_0_COMPONENT_TYPE lepton +#define LEPTON_0_COMPONENT_NAME lepton_0 +#define LEPTON_0_BASE 0x40000 +#define LEPTON_0_SPAN 32768 +#define LEPTON_0_END 0x47fff + +/* + * Macros for device 'mcp3204_0', class 'mcp3204' + * The macros are prefixed with 'MCP3204_0_'. + * The prefix is the slave descriptor. + */ +#define MCP3204_0_COMPONENT_TYPE mcp3204 +#define MCP3204_0_COMPONENT_NAME mcp3204_0 +#define MCP3204_0_BASE 0x49000 +#define MCP3204_0_SPAN 16 +#define MCP3204_0_END 0x4900f + +/* + * Macros for device 'pwm_1', class 'pwm' + * The macros are prefixed with 'PWM_1_'. + * The prefix is the slave descriptor. + */ +#define PWM_1_COMPONENT_TYPE pwm +#define PWM_1_COMPONENT_NAME pwm_1 +#define PWM_1_BASE 0x49010 +#define PWM_1_SPAN 16 +#define PWM_1_END 0x4901f + +/* + * Macros for device 'pwm_0', class 'pwm' + * The macros are prefixed with 'PWM_0_'. + * The prefix is the slave descriptor. + */ +#define PWM_0_COMPONENT_TYPE pwm +#define PWM_0_COMPONENT_NAME pwm_0 +#define PWM_0_BASE 0x49020 +#define PWM_0_SPAN 16 +#define PWM_0_END 0x4902f + + +#endif /* _ALTERA_HPS_SOC_SYSTEM_H_ */ diff --git a/cs309-psoc/lab_4_1/sw/hps/application/iorw.h b/cs309-psoc/lab_4_1/sw/hps/application/iorw.h new file mode 100644 index 0000000..074ef00 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/iorw.h @@ -0,0 +1,24 @@ +#ifndef __IORW_H__ +#define __IORW_H__ + +#if defined(__nios2_arch__) // For the soft-core Nios processor + #include + + #define io_write_8(base, ofst, data) (IOWR_8DIRECT((base), (ofst), (data))) + #define io_write_16(base, ofst, data) (IOWR_16DIRECT((base), (ofst), (data))) + #define io_write_32(base, ofst, data) (IOWR_32DIRECT((base), (ofst), (data))) + #define io_read_8(base, ofst) (IORD_8DIRECT((base), (ofst))) + #define io_read_16(base, ofst) (IORD_16DIRECT((base), (ofst))) + #define io_read_32(base, ofst) (IORD_32DIRECT((base), (ofst))) +#else // For the hard-core ARM Cortex A9 processor + #include + + #define io_write_8(base, ofst, data) (alt_write_byte((uintptr_t) (base) + (ofst), (data))) + #define io_write_16(base, ofst, data) (alt_write_hword((uintptr_t) (base) + (ofst), (data))) + #define io_write_32(base, ofst, data) (alt_write_word((uintptr_t) (base) + (ofst), (data))) + #define io_read_8(base, ofst) (alt_read_byte((uintptr_t) (base) + (ofst))) + #define io_read_16(base, ofst) (alt_read_hword((uintptr_t) (base) + (ofst))) + #define io_read_32(base, ofst) (alt_read_word((uintptr_t) (base) + (ofst))) +#endif + +#endif diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/Makefile b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/Makefile new file mode 100644 index 0000000..ea9013c --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/Makefile @@ -0,0 +1,9 @@ + +all: app +clean: + rm -rf *.o + rm -f app + +server.o: server.c server.h +app.o: app.c server.h +app: app.o server.o diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/app.c b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/app.c new file mode 100644 index 0000000..ad91429 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/app.c @@ -0,0 +1,125 @@ +#include "hps_soc_system.h" +#include "lepton/lepton.h" +#include "server.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** The port on which the server is available */ +#define SERVER_PORT 25700 + +int main(int argc, char* argv[]) { + // Copy the old terminal configuration to restore it later + struct termios orig_term_attr, new_term_attr; + tcgetattr(fileno(stdin), &orig_term_attr); + memcpy(&new_term_attr, &orig_term_attr, sizeof(struct termios)); + + + // Set the input to non-canonical mode, so that the keypresses are instantaneously recorded + new_term_attr.c_lflag &= ~(ECHO | ICANON); + new_term_attr.c_cc[VTIME] = 0; + new_term_attr.c_cc[VMIN] = 0; + tcsetattr(fileno(stdin), TCSANOW, &new_term_attr); + + // Open the physical memory through the filesystem + int mem_fd = open("/dev/mem", O_SYNC | O_RDWR); + if(mem_fd == -1){ + fprintf(stderr, "Failed to open /dev/mem. Exiting. Consider running this program with root privileges.\n"); + tcsetattr(fileno(stdin), TCSANOW, &orig_term_attr); + return -1; + } + + // Map the physical memory into the virtual address space + size_t length = ALT_LWFPGASLVS_UB_ADDR - ALT_LWFPGASLVS_LB_ADDR + 1; + size_t offset = ALT_LWFPGASLVS_OFST; + void* mapped = mmap(NULL, length, PROT_READ | PROT_WRITE, MAP_SHARED, mem_fd, offset); + if (mapped == MAP_FAILED){ + fprintf(stderr, "Failed to map physical memory into virtual address space. Exiting.\n"); + close(mem_fd); + tcsetattr(fileno(stdin), TCSANOW, &orig_term_attr); + return -1; + } + + // Initialize the lepton device with the mapped memory + lepton_dev lepton = lepton_inst(mapped + LEPTON_0_BASE); + lepton_init(&lepton); + + // Create the socket + printf("Creating and binding a UDP socket on port %d...\n", SERVER_PORT); + int socket = create_upd_socket(SERVER_PORT); + if (socket == -1) { + fprintf(stderr, "Failed to create the UDP socket. Exiting.\n"); + close(mem_fd); + munmap(mapped, length); + tcsetattr(fileno(stdin), TCSANOW, &orig_term_attr); + return EXIT_FAILURE; + } + + printf("Socket successfully bound.\n"); + printf("Press 'q' to stop the server.\n"); + + while (1) { + // Wait for a client to connect + printf("Waiting for a new client to connect...\n"); + struct sockaddr_in client_addr, sender_addr; + int event; + + do { + // Wait for either a packet or the user quiting + event = wait_for_event(socket, &client_addr, -1); + } while (event == NO_EVENT); + + if (event == QUIT_EVENT) { + printf("Stopping the server...\n"); + munmap(mapped, length); + close(mem_fd); + close(socket); + tcsetattr(fileno(stdin), TCSANOW, &orig_term_attr); + return EXIT_SUCCESS; + } + + // Inform the user about the connection + char addr_string[INET_ADDRSTRLEN]; + inet_ntop(AF_INET, &client_addr.sin_addr, addr_string, INET_ADDRSTRLEN); + printf("Connected to client at address %s:%d.\n", addr_string, client_addr.sin_port); + + // We continuously send the stream to the client until stopping is requested + do { + do { + lepton_start_capture(&lepton); + lepton_wait_until_eof(&lepton); + } while (lepton_error_check(&lepton)); + + uint16_t* image = lepton_get_image(&lepton, true); + send_image(socket, image, &client_addr); + + event = wait_for_event(socket, &sender_addr, 0); + if (event == PACKET_EVENT && + (sender_addr.sin_addr.s_addr != client_addr.sin_addr.s_addr + || sender_addr.sin_port != client_addr.sin_port)) + event = NO_EVENT; + } while (event == NO_EVENT); + + // Stop the server if the user wants to + if (event == QUIT_EVENT) { + printf("Stopping the server...\n"); + munmap(mapped, length); + close(mem_fd); + close(socket); + tcsetattr(fileno(stdin), TCSANOW, &orig_term_attr); + return EXIT_SUCCESS; + } + + printf("The client disconnected.\n"); + } + + return EXIT_SUCCESS; +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/joysticks.c b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/joysticks.c new file mode 100644 index 0000000..a84c8d4 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/joysticks.c @@ -0,0 +1,79 @@ +#include "joysticks.h" + +#define JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL (0) +#define JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL (1) +#define JOYSTICK_LEFT_VRY_MCP3204_CHANNEL (2) +#define JOYSTICK_LEFT_VRX_MCP3204_CHANNEL (3) + +/** + * joysticks_inst + * + * Instantiate a joysticks device structure. + * + * @param base Base address of the MCP3204 component connected to the joysticks. + */ +joysticks_dev joysticks_inst(void *mcp3204_base) { + joysticks_dev dev; + dev.mcp3204 = mcp3204_inst((void *) mcp3204_base); + + return dev; +} + +/** + * joysticks_init + * + * Initializes the joysticks device. + * + * @param dev joysticks device structure. + */ +void joysticks_init(joysticks_dev *dev) { + mcp3204_init(&(dev->mcp3204)); +} + +/** + * joysticks_read_left_vertical + * + * Returns the vertical position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204, JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL); +} + +/** + * joysticks_read_left_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204, JOYSTICK_LEFT_VRX_MCP3204_CHANNEL); +} + +/** + * joysticks_read_right_vertical + * + * Returns the vertical position of the right joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204, JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL); +} + +/** + * joysticks_read_right_horizontal + * + * Returns the horizontal position of the left joystick. Return value ranges + * between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE. + * + * @param dev joysticks device structure. + */ +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204, JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL); +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/joysticks.h b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/joysticks.h new file mode 100644 index 0000000..ac9c383 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/joysticks.h @@ -0,0 +1,27 @@ +#ifndef __JOYSTICKS_H__ +#define __JOYSTICKS_H__ + +#include "mcp3204/mcp3204.h" + +/* joysticks device structure */ +typedef struct joysticks_dev { + mcp3204_dev mcp3204; /* MCP3204 device handle */ +} joysticks_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define JOYSTICKS_MIN_VALUE (MCP3204_MIN_VALUE) +#define JOYSTICKS_MAX_VALUE (MCP3204_MAX_VALUE) + +joysticks_dev joysticks_inst(void *mcp3204_base); + +void joysticks_init(joysticks_dev *dev); + +uint32_t joysticks_read_left_vertical(joysticks_dev *dev); +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev); +uint32_t joysticks_read_right_vertical(joysticks_dev *dev); +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev); + +#endif /* __JOYSTICKS_H__ */ diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/mcp3204/mcp3204.c b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/mcp3204/mcp3204.c new file mode 100644 index 0000000..1210e31 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/mcp3204/mcp3204.c @@ -0,0 +1,44 @@ +#include "mcp3204.h" +#include "iorw.h" + +#define MCP3204_NUM_CHANNELS (4) + +/** + * mcp3204_inst + * + * Instantiate a mcp3204 device structure. + * + * @param base Base address of the component. + */ +mcp3204_dev mcp3204_inst(void *base) { + mcp3204_dev dev; + dev.base = base; + + return dev; +} + +/** + * mcp3204_init + * + * Initializes the mcp3204 device. + * + * @param dev mcp3204 device structure. + */ +void mcp3204_init(mcp3204_dev *dev) { + return; +} + +/** + * mcp3204_read + * + * Reads the register corresponding to the supplied channel parameter. + * + * @param dev mcp3204 device structure. + * @param channel channel to be read + */ +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) { + if (channel >= 4) + return 0; + + return io_read_32(dev->base, channel * 4); +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/mcp3204/mcp3204.h b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/mcp3204/mcp3204.h new file mode 100644 index 0000000..3b2b2e6 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/mcp3204/mcp3204.h @@ -0,0 +1,23 @@ +#ifndef __MCP3204_H__ +#define __MCP3204_H__ + +#include + +/* mcp3204 device structure */ +typedef struct mcp3204_dev { + void *base; /* Base address of component */ +} mcp3204_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define MCP3204_MIN_VALUE (0) +#define MCP3204_MAX_VALUE (4095) + +mcp3204_dev mcp3204_inst(void *base); + +void mcp3204_init(mcp3204_dev *dev); +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel); + +#endif /* __MCP3204_H__ */ diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/mcp3204/mcp3204_regs.h b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/mcp3204/mcp3204_regs.h new file mode 100644 index 0000000..b1c78cd --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/joysticks/mcp3204/mcp3204_regs.h @@ -0,0 +1,9 @@ +#ifndef __MCP3204_REGS_H__ +#define __MCP3204_REGS_H__ + +#define MCP3204_CHANNEL_0_OFST (0 * 4) /* RO */ +#define MCP3204_CHANNEL_1_OFST (1 * 4) /* RO */ +#define MCP3204_CHANNEL_2_OFST (2 * 4) /* RO */ +#define MCP3204_CHANNEL_3_OFST (3 * 4) /* RO */ + +#endif /* __MCP3204_REGS_H__ */ diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/lepton/lepton.c b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/lepton/lepton.c new file mode 100644 index 0000000..aa68efd --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/lepton/lepton.c @@ -0,0 +1,122 @@ +#include +#include +#include +#include + +#include "lepton_regs.h" +#include "lepton.h" +#include "iorw.h" + +/** + * lepton_inst + * + * Instantiate a lepton device structure. + * + * @param base Base address of the component. + */ +lepton_dev lepton_inst(void *base) { + lepton_dev dev; + dev.base = base; + + return dev; +} + +/** + * lepton_init + * + * Initializes the lepton device. + * + * @param dev lepton device structure. + */ +void lepton_init(lepton_dev *dev) { + return; +} + +/** + * lepton_start_capture + * + * Instructs the device to start the frame capture process. + * + * @param dev lepton device structure. + */ +void lepton_start_capture(lepton_dev *dev) { + io_write_16(dev->base, LEPTON_REGS_COMMAND_OFST, 0x1); +} + +/** + * lepton_error_check + * + * @abstract Check for errors at the device level. + * @param dev lepton device structure. + * @return true if there was an error, and false otherwise. + */ +bool lepton_error_check(lepton_dev *dev) { + return (io_read_16(dev->base, LEPTON_REGS_STATUS_OFST) & 0x2) != 0; +} + +/** + * lepton_wait_until_eof + * + * Waits until the frame being captured has been fully received and saved in the + * internal memory. + * + * @param dev lepton device structure. + */ +void lepton_wait_until_eof(lepton_dev *dev) { + while (io_read_16(dev->base, LEPTON_REGS_STATUS_OFST) & 0x1); +} + +/** + * lepton_save_capture + * + * Saves the captured frame on the host filesystem under the supplied filename. + * The frame will be saved in PGM format. + * + * @param dev lepton device structure. + * @param adjusted Setting this parameter to false will cause RAW sensor data to + * be written to the file. + * Setting this parameter to true will cause a preprocessed image + * (with a stretched dynamic range) to be saved to the file. + * + * @param fname the output file name. + */ +void lepton_save_capture(lepton_dev *dev, bool adjusted, FILE* file) { + assert(file); + + const uint8_t num_rows = 60; + const uint8_t num_cols = 80; + + uint16_t offset = LEPTON_REGS_RAW_BUFFER_OFST; + uint16_t max_value = io_read_16(dev->base, LEPTON_REGS_MAX_OFST); + if (adjusted) { + offset = LEPTON_REGS_ADJUSTED_BUFFER_OFST; + max_value = 0x3fff; + } + + /* Write PGM header */ + fprintf(file, "P2\n%" PRIu8 " %" PRIu8 "\n%" PRIu16, num_cols, num_rows, max_value); + + /* Write body */ + uint8_t row = 0; + for (row = 0; row < num_rows; ++row) { + fprintf(file, "\n"); + + uint8_t col = 0; + for (col = 0; col < num_cols; ++col) { + if (col > 0) { + fprintf(file, " "); + } + + uint16_t current_ofst = offset + (row * num_cols + col) * sizeof(uint16_t); + uint16_t pix_value = io_read_16(dev->base, current_ofst); + fprintf(file, "%" PRIu16, pix_value); + } + } + + assert(!fclose(file)); +} + +uint16_t* lepton_get_image(lepton_dev *dev, bool adjusted) { + size_t offset = adjusted ? LEPTON_REGS_ADJUSTED_BUFFER_OFST : LEPTON_REGS_RAW_BUFFER_OFST; + return (uint16_t*) ((uint8_t*) dev->base + offset); +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/lepton/lepton.h b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/lepton/lepton.h new file mode 100644 index 0000000..b266828 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/lepton/lepton.h @@ -0,0 +1,26 @@ +#ifndef __LEPTON_H__ +#define __LEPTON_H__ + +#include +#include +#include + +/* lepton device structure */ +typedef struct { + void *base; /* Base address of the component */ +} lepton_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +lepton_dev lepton_inst(void *base); + +void lepton_init(lepton_dev *dev); +void lepton_start_capture(lepton_dev *dev); +void lepton_wait_until_eof(lepton_dev *dev); +bool lepton_error_check(lepton_dev *dev); +void lepton_save_capture(lepton_dev *dev, bool adjusted, FILE* file); +uint16_t* lepton_get_image(lepton_dev *dev, bool adjusted); + +#endif /* __LEPTON_H__ */ diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/lepton/lepton_regs.h b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/lepton/lepton_regs.h new file mode 100644 index 0000000..db24244 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/lepton/lepton_regs.h @@ -0,0 +1,25 @@ +#ifndef __LEPTON_REGS_H__ +#define __LEPTON_REGS_H__ + +/* Register offsets */ +#define LEPTON_REGS_COMMAND_OFST ( 0 * 2) /* WO */ +#define LEPTON_REGS_STATUS_OFST ( 1 * 2) /* RO */ +#define LEPTON_REGS_MIN_OFST ( 2 * 2) /* RO */ +#define LEPTON_REGS_MAX_OFST ( 3 * 2) /* RO */ +#define LEPTON_REGS_SUM_LSB_OFST ( 4 * 2) /* RO */ +#define LEPTON_REGS_SUM_MSB_OFST ( 5 * 2) /* RO */ +#define LEPTON_REGS_ROW_IDX_OFST ( 6 * 2) /* RO */ +#define LEPTON_REGS_RAW_BUFFER_OFST ( 8 * 2) /* RO */ +#define LEPTON_REGS_ADJUSTED_BUFFER_OFST (8192 * 2) /* RO */ + +/* Command register */ +#define LEPTON_COMMAND_START (0x0001) + +/* Status register */ +#define LEPTON_STATUS_CAPTURE_IN_PROGRESS_MASK (1 << 0) +#define LEPTON_STATUS_ERROR_MASK (1 << 1) + +#define LEPTON_REGS_BUFFER_NUM_PIXELS (80 * 60) +#define LEPTON_REGS_BUFFER_BYTELENGTH (LEPTON_REGS_BUFFER_NUM_PIXELS * 2) + +#endif /* __LEPTON_REGS_H__ */ diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pantilt.c b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pantilt.c new file mode 100644 index 0000000..d9c4c72 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pantilt.c @@ -0,0 +1,109 @@ +#include "pantilt.h" + +/** + * pantilt_inst + * + * Instantiate a pantilt device structure. + * + * @param pwm_v_base Base address of the vertical PWM component. + * @param pwm_h_base Base address of the horizontal PWM component. + */ +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) { + pantilt_dev dev; + dev.pwm_v = pwm_inst(pwm_v_base); + dev.pwm_h = pwm_inst(pwm_h_base); + + return dev; +} + +/** + * pantilt_init + * + * Initializes the pantilt device. + * + * @param dev pantilt device structure. + */ +void pantilt_init(pantilt_dev *dev) { + pwm_init(&(dev->pwm_v)); + pwm_init(&(dev->pwm_h)); +} + +/** + * pantilt_configure_vertical + * + * Configure the vertical PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_v), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_configure_horizontal + * + * Configure the horizontal PWM component. + * + * @param dev pantilt device structure. + * @param duty_cycle pwm duty cycle in us. + */ +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) { + // Need to compensate for inverted servo rotation. + duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US; + + pwm_configure(&(dev->pwm_h), + duty_cycle, + PANTILT_PWM_PERIOD_US, + PANTILT_PWM_CLOCK_FREQ_HZ); +} + +/** + * pantilt_start_vertical + * + * Starts the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_vertical(pantilt_dev *dev) { + pwm_start(&(dev->pwm_v)); +} + +/** + * pantilt_start_horizontal + * + * Starts the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_start_horizontal(pantilt_dev *dev) { + pwm_start(&(dev->pwm_h)); +} + +/** + * pantilt_stop_vertical + * + * Stops the vertical pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_vertical(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_v)); +} + +/** + * pantilt_stop_horizontal + * + * Stops the horizontal pwm controller. + * + * @param dev pantilt device structure. + */ +void pantilt_stop_horizontal(pantilt_dev *dev) { + pwm_stop(&(dev->pwm_h)); +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pantilt.h b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pantilt.h new file mode 100644 index 0000000..1f17500 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pantilt.h @@ -0,0 +1,39 @@ +#ifndef __PANTILT_H__ +#define __PANTILT_H__ + +#include "pwm/pwm.h" + +/* joysticks device structure */ +typedef struct pantilt_dev { + pwm_dev pwm_v; /* Vertical PWM device handle */ + pwm_dev pwm_h; /* Horizontal PWM device handle */ +} pantilt_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ + +#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz + +#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms + +/* Vertical servo */ +#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms +#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms + +/* Horizontal servo */ +#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms +#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms + +pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base); + +void pantilt_init(pantilt_dev *dev); + +void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle); +void pantilt_start_vertical(pantilt_dev *dev); +void pantilt_start_horizontal(pantilt_dev *dev); +void pantilt_stop_vertical(pantilt_dev *dev); +void pantilt_stop_horizontal(pantilt_dev *dev); + +#endif /* __PANTILT_H__ */ diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pwm/pwm.c b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pwm/pwm.c new file mode 100644 index 0000000..39fa34d --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pwm/pwm.c @@ -0,0 +1,68 @@ +#include "pwm.h" +#include "pwm_regs.h" +#include "iorw.h" + +#define MICROSEC_TO_CLK(time, freq) ((time) * ((freq) / 1000000)) + +/** + * pwm_inst + * + * Instantiate a pwm device structure. + * + * @param base Base address of the component. + */ +pwm_dev pwm_inst(void *base) { + pwm_dev dev; + + dev.base = base; + + return dev; +} + +/** + * pwm_init + * + * Initializes the pwm device. This function stops the controller. + * + * @param dev pwm device structure. + */ +void pwm_init(pwm_dev *dev) { + pwm_stop(dev); +} + +/** + * pwm_configure + * + * Configure pwm component. + * + * @param dev pwm device structure. + * @param duty_cycle pwm duty cycle in us. + * @param period pwm period in us. + * @param module_frequency frequency at which the component is clocked. + */ +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) { + io_write_32(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency)); + io_write_32(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency)); +} + +/** + * pwm_start + * + * Starts the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_start(pwm_dev *dev) { + io_write_32(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} + +/** + * pwm_stop + * + * Stops the pwm controller. + * + * @param dev pwm device structure. + */ +void pwm_stop(pwm_dev *dev) { + io_write_32(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pwm/pwm.h b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pwm/pwm.h new file mode 100644 index 0000000..e2987f4 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pwm/pwm.h @@ -0,0 +1,21 @@ +#ifndef __PWM_H__ +#define __PWM_H__ + +#include + +/* pwm device structure */ +typedef struct pwm_dev { + void *base; /* Base address of component */ +} pwm_dev; + +/******************************************************************************* + * Public API + ******************************************************************************/ +pwm_dev pwm_inst(void *base); + +void pwm_init(pwm_dev *dev); +void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency); +void pwm_start(pwm_dev *dev); +void pwm_stop(pwm_dev *dev); + +#endif /* __PWM_H__ */ diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pwm/pwm_regs.h b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pwm/pwm_regs.h new file mode 100644 index 0000000..488583d --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/pantilt/pwm/pwm_regs.h @@ -0,0 +1,11 @@ +#ifndef __PWM_REGS_H__ +#define __PWM_REGS_H__ + +#define PWM_PERIOD_OFST (0 * 4) /* RW */ +#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */ +#define PWM_CTRL_OFST (2 * 4) /* WO */ + +#define PWM_CTRL_STOP_MASK (0) +#define PWM_CTRL_START_MASK (1) + +#endif /* __PWM_REGS_H__ */ diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/server.c b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/server.c new file mode 100644 index 0000000..0ee854c --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/server.c @@ -0,0 +1,79 @@ +#include "server.h" +#include // for socket +#include // for AF_INET +#include // for sockaddr_in +#include // for htonl +#include // for uint16_t +#include // for close +#include // for memcpy +#include // for poll + +#define ROW_SIZE (IMG_WIDTH * sizeof(uint16_t)) + +int create_upd_socket(uint16_t port) { + int sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + + if (sock == -1) + return -1; + + struct sockaddr_in addr; + addr.sin_family = AF_INET; + addr.sin_port = htons(port); + addr.sin_addr.s_addr = htonl(INADDR_ANY); + + if (bind(sock, (const struct sockaddr*) &addr, sizeof(addr))) { + close(sock); + return -1; + } + + return sock; +} + +int wait_for_event(int socket, struct sockaddr_in* addr, int timeout) { + char c = 0; + struct pollfd fds[2]; + + // Wait for a packet + fds[0].fd = socket; + fds[0].events = POLLIN; + fds[0].revents = 0; + + // Wait for a command line input + fds[1].fd = STDIN_FILENO; + fds[1].events = POLLIN; + fds[1].revents = 0; + + // Wait for the two file descriptors in parallel + int ret = poll(fds, 2, timeout); + + if (ret <= 0) // error or timeout + return NO_EVENT; + + if (fds[1].revents & POLLIN) { + read(STDIN_FILENO, &c, 1); + + if (c == 'q') + return QUIT_EVENT; + } + + if (fds[0].revents & POLLIN) { + socklen_t addr_len = sizeof(struct sockaddr_in); + recvfrom(socket, &c, 1, 0, (struct sockaddr*) addr, &addr_len); + return PACKET_EVENT; + } + + return NO_EVENT; +} + +void send_image(int socket, uint16_t* img, const struct sockaddr_in* addr) { + // This buffer is used to hold the packet for a row + char row_buffer[sizeof(uint32_t) + ROW_SIZE]; + + // We send the rows one by one + uint8_t i = 0; + for (i = 0; i < IMG_HEIGHT; i++) { + *((uint32_t*) row_buffer) = i; // The first bytes of the packet contain the row index + memcpy(row_buffer + sizeof(uint32_t), img + i * IMG_WIDTH, ROW_SIZE); // The rest contains the actual row + sendto(socket, row_buffer, sizeof(uint32_t) + ROW_SIZE, 0, (const struct sockaddr*) addr, sizeof(*addr)); + } +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/server.h b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/server.h new file mode 100644 index 0000000..82671b8 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/lab_4_1/server.h @@ -0,0 +1,32 @@ +#ifndef __SERVER_H__ +#define __SERVER_H__ + +#include +#include + +/** Image definitions - needs to move to another file later */ +#define IMG_WIDTH 80 +#define IMG_HEIGHT 60 +#define IMG_SIZE (IMG_WIDTH * IMG_HEIGHT) + +/** + * Creates and binds a socket on the given port, using the UDP protocol. + * If an error occured, -1 is returned, otherwise the socket is returned. + */ +int create_upd_socket(in_port_t port); + +/** + * Polls the given socket for a message, and check if the user wants to quit by pressing q + * in the console. Returns what happened in the form of an integer. + */ +#define NO_EVENT 0 +#define QUIT_EVENT 1 +#define PACKET_EVENT 2 +int wait_for_event(int socket, struct sockaddr_in* addr, int timeout); + +/** + * Sends the entire image over udp, row by row, through the given socket. + */ +void send_image(int socket, uint16_t* img, const struct sockaddr_in* addr); + +#endif diff --git a/cs309-psoc/lab_4_1/sw/hps/application/mock_server/Makefile b/cs309-psoc/lab_4_1/sw/hps/application/mock_server/Makefile new file mode 100644 index 0000000..ea9013c --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/mock_server/Makefile @@ -0,0 +1,9 @@ + +all: app +clean: + rm -rf *.o + rm -f app + +server.o: server.c server.h +app.o: app.c server.h +app: app.o server.o diff --git a/cs309-psoc/lab_4_1/sw/hps/application/mock_server/app.c b/cs309-psoc/lab_4_1/sw/hps/application/mock_server/app.c new file mode 100644 index 0000000..2fe7db3 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/mock_server/app.c @@ -0,0 +1,94 @@ +#include "server.h" +#include +#include +#include +#include +#include +#include + +/** The port on which the server is available */ +#define SERVER_PORT 25700 + +// Creates a moving fake image +void generate_image(uint16_t* img, size_t t); + +int main(int argc, char* argv[]) { + + // Set the input to non-canonical mode, so that the keypresses are instantaneously recorded + struct termios term_attr; + tcgetattr(fileno(stdin), &term_attr); + term_attr.c_lflag &= ~(ECHO | ICANON); + term_attr.c_cc[VTIME] = 0; + term_attr.c_cc[VMIN] = 0; + tcsetattr(fileno(stdin), TCSANOW, &term_attr); + + // This is the image that will be sent + uint16_t img[IMG_WIDTH * IMG_HEIGHT]; + size_t t = 0; + + // Create the socket + printf("Creating and binding a UDP socket on port %d...\n", SERVER_PORT); + int socket = create_upd_socket(SERVER_PORT); + if (socket == -1) { + fprintf(stderr, "Failed to create the UDP socket. Exiting.\n"); + return EXIT_FAILURE; + } + + printf("Socket successfully bound.\n"); + printf("Press 'q' to stop the server.\n"); + + while (1) { + // Wait for a client to connect + printf("Waiting for a new client to connect...\n"); + struct sockaddr_in client_addr, sender_addr; + int event; + + do { + // Wait for either a packet or the user quiting + event = wait_for_event(socket, &client_addr, -1); + } while (event == NO_EVENT); + + if (event == QUIT_EVENT) { + printf("Stopping the server...\n"); + close(socket); + return EXIT_SUCCESS; + } + + // Inform the user about the connection + char addr_string[INET_ADDRSTRLEN]; + inet_ntop(AF_INET, &client_addr.sin_addr, addr_string, INET_ADDRSTRLEN); + printf("Connected to client at address %s:%d.\n", addr_string, client_addr.sin_port); + + // We continuously send the stream to the client until stopping is requested + do { + generate_image(img, t++); + send_image(socket, img, &client_addr); + event = wait_for_event(socket, &sender_addr, 100); + + if (event == PACKET_EVENT && + (sender_addr.sin_addr.s_addr != client_addr.sin_addr.s_addr + || sender_addr.sin_port != client_addr.sin_port)) + event = NO_EVENT; + } while (event == NO_EVENT); + + // Stop the server if the user wants to + if (event == QUIT_EVENT) { + printf("Stopping the server...\n"); + close(socket); + return EXIT_SUCCESS; + } + + printf("The client disconnected.\n"); + } + + return EXIT_SUCCESS; +} + +void generate_image(uint16_t* img, size_t t) { + for (size_t x = 0; x < IMG_WIDTH; x++) { + uint16_t val = ((x + t) % IMG_WIDTH) * 0x3FFF / IMG_WIDTH; + + for (size_t y = 0; y < IMG_HEIGHT; y++) + img[y * IMG_WIDTH + x] = val; + } +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/mock_server/server.c b/cs309-psoc/lab_4_1/sw/hps/application/mock_server/server.c new file mode 100644 index 0000000..0ee854c --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/mock_server/server.c @@ -0,0 +1,79 @@ +#include "server.h" +#include // for socket +#include // for AF_INET +#include // for sockaddr_in +#include // for htonl +#include // for uint16_t +#include // for close +#include // for memcpy +#include // for poll + +#define ROW_SIZE (IMG_WIDTH * sizeof(uint16_t)) + +int create_upd_socket(uint16_t port) { + int sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + + if (sock == -1) + return -1; + + struct sockaddr_in addr; + addr.sin_family = AF_INET; + addr.sin_port = htons(port); + addr.sin_addr.s_addr = htonl(INADDR_ANY); + + if (bind(sock, (const struct sockaddr*) &addr, sizeof(addr))) { + close(sock); + return -1; + } + + return sock; +} + +int wait_for_event(int socket, struct sockaddr_in* addr, int timeout) { + char c = 0; + struct pollfd fds[2]; + + // Wait for a packet + fds[0].fd = socket; + fds[0].events = POLLIN; + fds[0].revents = 0; + + // Wait for a command line input + fds[1].fd = STDIN_FILENO; + fds[1].events = POLLIN; + fds[1].revents = 0; + + // Wait for the two file descriptors in parallel + int ret = poll(fds, 2, timeout); + + if (ret <= 0) // error or timeout + return NO_EVENT; + + if (fds[1].revents & POLLIN) { + read(STDIN_FILENO, &c, 1); + + if (c == 'q') + return QUIT_EVENT; + } + + if (fds[0].revents & POLLIN) { + socklen_t addr_len = sizeof(struct sockaddr_in); + recvfrom(socket, &c, 1, 0, (struct sockaddr*) addr, &addr_len); + return PACKET_EVENT; + } + + return NO_EVENT; +} + +void send_image(int socket, uint16_t* img, const struct sockaddr_in* addr) { + // This buffer is used to hold the packet for a row + char row_buffer[sizeof(uint32_t) + ROW_SIZE]; + + // We send the rows one by one + uint8_t i = 0; + for (i = 0; i < IMG_HEIGHT; i++) { + *((uint32_t*) row_buffer) = i; // The first bytes of the packet contain the row index + memcpy(row_buffer + sizeof(uint32_t), img + i * IMG_WIDTH, ROW_SIZE); // The rest contains the actual row + sendto(socket, row_buffer, sizeof(uint32_t) + ROW_SIZE, 0, (const struct sockaddr*) addr, sizeof(*addr)); + } +} diff --git a/cs309-psoc/lab_4_1/sw/hps/application/mock_server/server.h b/cs309-psoc/lab_4_1/sw/hps/application/mock_server/server.h new file mode 100644 index 0000000..82671b8 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/application/mock_server/server.h @@ -0,0 +1,32 @@ +#ifndef __SERVER_H__ +#define __SERVER_H__ + +#include +#include + +/** Image definitions - needs to move to another file later */ +#define IMG_WIDTH 80 +#define IMG_HEIGHT 60 +#define IMG_SIZE (IMG_WIDTH * IMG_HEIGHT) + +/** + * Creates and binds a socket on the given port, using the UDP protocol. + * If an error occured, -1 is returned, otherwise the socket is returned. + */ +int create_upd_socket(in_port_t port); + +/** + * Polls the given socket for a message, and check if the user wants to quit by pressing q + * in the console. Returns what happened in the form of an integer. + */ +#define NO_EVENT 0 +#define QUIT_EVENT 1 +#define PACKET_EVENT 2 +int wait_for_event(int socket, struct sockaddr_in* addr, int timeout); + +/** + * Sends the entire image over udp, row by row, through the given socket. + */ +void send_image(int socket, uint16_t* img, const struct sockaddr_in* addr); + +#endif diff --git a/cs309-psoc/lab_4_1/sw/hps/linux/rootfs/config_post_install.sh b/cs309-psoc/lab_4_1/sw/hps/linux/rootfs/config_post_install.sh new file mode 100755 index 0000000..1ccae61 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/linux/rootfs/config_post_install.sh @@ -0,0 +1,22 @@ +#!/bin/bash -x +# apt sources +# uncomment the "deb" lines (no need to uncomment "deb src" lines) + +# Edit the “/etc/apt/sources.list” file to configure the package manager. This +# file contains a list of mirrors that the package manager queries. By default, +# this file has all fields commented out, so the package manager will not have +# access to any mirrors. The following command uncomments all commented out +# lines starting with "deb". These contain the mirrors we are interested in. +sudo perl -pi -e 's/^#+\s+(deb\s+http)/$1/g' "/etc/apt/sources.list" + +# When writing our linux applications, we want to use ARM DS-5’s remote +# debugging feature to automatically transfer our binaries to the target device +# and to start a debugging session. The remote debugging feature requires an SSH +# server and a remote gdb server to be available on the target. These are easy +# to install as we have a package manager available +sudo apt update +sudo apt -y install ssh gdbserver + +# Allow root SSH login with password (needed so we can use ARM DS-5 for remote +# debugging) +sudo perl -pi -e 's/^(PermitRootLogin) without-password$/$1 yes/g' "/etc/ssh/sshd_config" diff --git a/cs309-psoc/lab_4_1/sw/hps/linux/rootfs/config_system.sh b/cs309-psoc/lab_4_1/sw/hps/linux/rootfs/config_system.sh new file mode 100755 index 0000000..e0c89b8 --- /dev/null +++ b/cs309-psoc/lab_4_1/sw/hps/linux/rootfs/config_system.sh @@ -0,0 +1,74 @@ +#!/bin/bash -x +# Configure the locale to have proper language support. +localedef -i en_US -c -f UTF-8 en_US.UTF-8 +dpkg-reconfigure locales +# Configure the timezone. +echo "Europe/Zurich" > "/etc/timezone" +dpkg-reconfigure -f noninteractive tzdata +# Set the machine’s hostname. +echo "DE0-Nano-SoC" > "/etc/hostname" +tee "/etc/hosts" >"/dev/null" < "/dev/null" < "/dev/null" < "/dev/null" < "/dev/null" <base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency)); + IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency)); +} + +void pwm_start(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK); +} + +void pwm_stop(pwm_dev *dev) { + IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK); +} +\end{minted} +\captionof{listing}{Le code écrit dans pwm.c\label{code:pwm.c}} + +\begin{minted}[breaklines]{VHDL} +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pwm_constants.all; + +entity pwm is + port( + -- Avalon Clock interface + clk : in std_logic; + + -- Avalon Reset interface + reset : in std_logic; + + -- Avalon-MM Slave interface + address : in std_logic_vector(1 downto 0); + read : in std_logic; + write : in std_logic; + readdata : out std_logic_vector(31 downto 0); + writedata : in std_logic_vector(31 downto 0); + + -- Avalon Conduit interface + pwm_out : out std_logic + ); +end pwm; + +architecture rtl of pwm is + + -- The period of the current and next PWM cycle + signal reg_next_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length); + signal reg_current_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length); + + -- The duty cycle of the current and next PWM cycle + signal reg_next_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length); + signal reg_current_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length); + + -- The status of the current and next PWM cycle + signal reg_prev_ctrl : std_logic := '0'; + signal reg_current_ctrl : std_logic := '0'; + + -- The internal counter of the PWN + signal reg_counter : unsigned(writedata'range) := to_unsigned(0, writedata'length); + +begin + + --Avalon-MM slave write + process(clk, reset) + begin + if reset = '1' then + reg_next_period <= to_unsigned(DEFAULT_PERIOD, writedata'length); + reg_next_dutycycle <= to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length); + reg_current_ctrl <= '0'; + elsif rising_edge(clk) then + if write = '1' then + case address is + when REG_PERIOD_OFST => + if unsigned(writedata) >= to_unsigned(2, writedata'length) then + reg_next_period <= unsigned(writedata); + end if; + when REG_DUTY_CYCLE_OFST => + if (unsigned(writedata) >= to_unsigned(1, writedata'length)) and + (unsigned(writedata) <= reg_next_period) then + reg_next_dutycycle <= unsigned(writedata); + end if; + when REG_CTRL_OFST => + reg_current_ctrl <= writedata(0); + when others => null; + end case; + end if; + end if; + end process; + + + --Avalon-MM slave read + process(clk, reset) + begin + if rising_edge(clk) then + if read = '1' then + case address is + when REG_PERIOD_OFST => + readdata <= std_logic_vector(reg_current_period); + when REG_DUTY_CYCLE_OFST => + readdata <= std_logic_vector(reg_current_dutycycle); + when others => + readdata <= (others => '0'); + end case; + end if; + end if; + end process; + + -- Internal synchronous logic + process(clk, reset) + begin + if reset = '1' then + reg_counter <= to_unsigned(0, writedata'length); + reg_prev_ctrl <= '0'; + elsif rising_edge(clk) then + if ((reg_prev_ctrl = '0') and (reg_current_ctrl = '1')) or + (reg_counter = reg_current_period - 1) then + reg_current_period <= reg_next_period; + reg_current_dutycycle <= reg_next_dutycycle; + reg_counter <= to_unsigned(0, writedata'length); + elsif (reg_current_ctrl = '1') then + reg_counter <= reg_counter + 1; + end if; + reg_prev_ctrl <= reg_current_ctrl; + end if; + end process; + + -- Avalon Conduit interface + process(clk, reset) + begin + if rising_edge(clk) then + + if (reg_counter < reg_current_dutycycle) and (reg_current_ctrl = '1') then + pwm_out <= '1'; + else + pwm_out <= '0'; + end if; + end if; + end process; + +end architecture rtl; +\end{minted} +\captionof{listing}{Le code écrit dans pwm.vhd\label{code:pwm.vhd}} + +\begin{minted}[breaklines]{VHDL} +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mcp3204_spi is + port( + -- 50 MHz + clk : in std_logic; + reset : in std_logic; + busy : out std_logic; + start : in std_logic; + channel : in std_logic_vector(1 downto 0); + data_valid : out std_logic; + data : out std_logic_vector(11 downto 0); + + -- 1 MHz + SCLK : out std_logic; + CS_N : out std_logic; + MOSI : out std_logic; + MISO : in std_logic + ); +end mcp3204_spi; + +architecture rtl of mcp3204_spi is + -- The signals that drive the clock divider + signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24 + signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz + signal reg_rising_edge_sclk : std_logic := '0'; + signal reg_falling_edge_sclk : std_logic := '0'; + signal reg_sclk : std_logic := '0'; + + -- The state related to the FSM + type state_type is (IDL, SYN, SND_S, SND_SGL, SND_D, WT, RCV_NB, RCV_D, WB); + signal reg_state, next_state : state_type := IDL; + signal reg_bit_idx : unsigned(3 downto 0) := (others => '0'); + signal reg_channel : unsigned(1 downto 0); + + -- The register that holds the transmitted data + signal reg_data : unsigned(11 downto 0) := (others => '0'); + +begin + clk_divider_generation : process(clk, reset) + begin + if reset = '1' then + reg_clk_divider_counter <= (others => '0'); + elsif rising_edge(clk) then + reg_clk_divider_counter <= reg_clk_divider_counter + 1; + reg_spi_en <= '0'; + reg_rising_edge_sclk <= '0'; + reg_falling_edge_sclk <= '0'; + + if reg_clk_divider_counter = 24 then + reg_clk_divider_counter <= (others => '0'); + reg_spi_en <= '1'; + + if reg_sclk = '0' then + reg_rising_edge_sclk <= '1'; + elsif reg_sclk = '1' then + reg_falling_edge_sclk <= '1'; + end if; + end if; + end if; + end process; + + SCLK_generation : process(clk, reset) + begin + if reset = '1' then + reg_sclk <= '0'; + elsif rising_edge(clk) then + if reg_spi_en = '1' then + reg_sclk <= not reg_sclk; + end if; + end if; + end process; + + STATE_LOGIC : process(clk, reset) + begin + if reset = '1' then + reg_state <= IDL; + reg_bit_idx <= (others => '0'); + elsif rising_edge(clk) then + reg_state <= next_state; + + case reg_state is + when IDL => + if next_state = SYN then + reg_channel <= unsigned(channel); + end if; + when SND_SGL => + if next_state = SND_D then + reg_bit_idx <= to_unsigned(2, reg_bit_idx'length); + end if; + when RCV_NB => + if next_state = RCV_D then + reg_bit_idx <= to_unsigned(11, reg_bit_idx'length); + end if; + when SND_D | RCV_D => + if reg_falling_edge_sclk = '1' then + reg_bit_idx <= reg_bit_idx - 1; + end if; + when others => + null; + end case; + end if; + end process; + + -- This is the combinatory logic to compute the next state + next_state <= + SYN when reg_state = IDL and start = '1' else + SND_S when reg_state = SYN and reg_falling_edge_sclk = '1' else + SND_SGL when reg_state = SND_S and reg_falling_edge_sclk = '1' else + SND_D when reg_state = SND_SGL and reg_falling_edge_sclk = '1' else + WT when reg_state = SND_D and reg_falling_edge_sclk = '1' and reg_bit_idx = 0 else + RCV_NB when reg_state = WT and reg_falling_edge_sclk = '1' else + RCV_D when reg_state = RCV_NB and reg_falling_edge_sclk = '1' else + WB when reg_state = RCV_D and reg_falling_edge_sclk = '1' and reg_bit_idx = 0 else + IDL when reg_state = WB else + reg_state; + + -- This process reads the bits sent from the ADC + ADC_READ : process(clk, reset) + begin + if reset = '1' then + reg_data <= (others => '0'); + elsif rising_edge(clk) then + if reg_state = RCV_D and reg_rising_edge_sclk = '1' then + reg_data(to_integer(reg_bit_idx)) <= MISO; + end if; + end if; + end process; + + -- This is the combinatory logic to the ADC converter + SCLK <= reg_sclk; + CS_N <= '1' when reg_state = IDL or reg_state = SYN or reg_state = WB else '0'; + MOSI <= + '1' when reg_state = SND_S or reg_state = SND_SGL else + '0' when reg_state = SND_D and reg_bit_idx = 2 else + reg_channel(to_integer(reg_bit_idx)) when reg_state = SND_D else + '0'; + + -- This is the combinatory logic to the SPI manager + busy <= '0' when reg_state = IDL else + '1'; + data_valid <= '1' when reg_state = WB else + '0'; + data <= std_logic_vector(reg_data) when reg_state = WB else + (others => '0'); + +end architecture rtl; +\end{minted} +\captionof{listing}{Le code écrit dans mcp3204_spi.vhd\label{code:mcp3204_spi.vhd}} + +\begin{minted}[breaklines]{C} +uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) { + return channel < 4 ? IORD_32DIRECT(dev->base, channel * 4) : 0; +} +\end{minted} +\captionof{listing}{Le code écrit dans mcp3204.c\label{code:mcp3204.c}} + +\begin{minted}[breaklines]{C} +uint32_t joysticks_read_left_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,LV_CHANNEL); +} + +uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204,LH_CHANNEL); +} + +uint32_t joysticks_read_right_vertical(joysticks_dev *dev) { + return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,RV_CHANNEL); +} + +uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) { + return mcp3204_read(&dev->mcp3204,RH_CHANNEL); +} +\end{minted} +\captionof{listing}{Le code écrit dans joysticks.c\label{code:joysticks.c}} + +\begin{minted}[breaklines]{C} +uint32_t interpolate(uint32_t input, + uint32_t input_lower_bound, + uint32_t input_upper_bound, + uint32_t output_lower_bound, + uint32_t output_upper_bound) { +return (input - input_lower_bound) * (output_upper_bound - output_lower_bound) / (input_upper_bound - input_lower_bound) + output_lower_bound; +} +\end{minted} +\captionof{listing}{Le code écrit dans app.c\label{code:app.c}} + +\end{document} diff --git a/cs309-psoc/report_2/horizontal.png b/cs309-psoc/report_2/horizontal.png new file mode 100644 index 0000000..b160158 Binary files /dev/null and b/cs309-psoc/report_2/horizontal.png differ diff --git a/cs309-psoc/report_2/output_bottles.png b/cs309-psoc/report_2/output_bottles.png new file mode 100644 index 0000000..554d735 Binary files /dev/null and b/cs309-psoc/report_2/output_bottles.png differ diff --git a/cs309-psoc/report_2/output_computer.png b/cs309-psoc/report_2/output_computer.png new file mode 100644 index 0000000..c9510c8 Binary files /dev/null and b/cs309-psoc/report_2/output_computer.png differ diff --git a/cs309-psoc/report_2/output_face.png b/cs309-psoc/report_2/output_face.png new file mode 100644 index 0000000..3b5df72 Binary files /dev/null and b/cs309-psoc/report_2/output_face.png differ diff --git a/cs309-psoc/report_2/qsys_1.png b/cs309-psoc/report_2/qsys_1.png new file mode 100644 index 0000000..acfaeaa Binary files /dev/null and b/cs309-psoc/report_2/qsys_1.png differ diff --git a/cs309-psoc/report_2/report.pdf b/cs309-psoc/report_2/report.pdf new file mode 100644 index 0000000..1632526 Binary files /dev/null and b/cs309-psoc/report_2/report.pdf differ diff --git a/cs309-psoc/report_2/report.tex b/cs309-psoc/report_2/report.tex new file mode 100644 index 0000000..e065952 --- /dev/null +++ b/cs309-psoc/report_2/report.tex @@ -0,0 +1,238 @@ +\documentclass[12pt]{article} +\usepackage[margin=2cm]{geometry} +\usepackage[utf8]{inputenc} +\usepackage{hyperref} +\usepackage{graphicx}\documentclass[12pt]{article} +\usepackage[margin=2cm]{geometry} +\usepackage[utf8]{inputenc} +\usepackage{hyperref} +\usepackage{graphicx} +\usepackage{minted} +\usepackage{caption} + +\title{Laboratory 2 report} +\author{Cédric Hölzl \and Antoine Brunner} +\date{March 2020} + +\begin{document} +\maketitle + +\section{VHDL system design} +In the first part of the laboratory, we had to implement the statistic computations, the level adjuster in VHDL. + +For the statistics computation, we didn't do anything incredible ;). In the component, there are three registers: one for the maximum, one for the minimum, and one for the sum. Those registers are updated with the value from \emph{pix\_data} when the signal \emph{valid} is 1. They are reset when the signal \emph{pix\_sof} is 1, so that the statistics for the new frame can be computed. + +The level adjuster was just a matter of finding a formula that does what we want. The component takes as input a 14-bit value that is in the range $[raw\_min, raw\_max]$, and we would like to remap those values to the full range $[0, 2^{14}-1]$. If we were able to use floating point arithmetic, what we would do the following: +\[x \mapsto \frac{x - min}{max - min} \cdot (2^{14} - 1)\] + +That is, we would first divide $x - min$ by $max - min$ to have a value between 0 and 1. Then, we would multiply that by $2^{14} - 1$ to get the result. But since we are using integer arithmetic, we cannot perform the first division in this way. The trick is to first multiply by $2^{14} - 1$, which results in a 27-bit value, and then make an integer division by $max - min$. + +Once we realized that little trick, the rest was a matter of translating it to VHDL, which was fairly easy, since we had already been given the division component. + +\section{C application design} +As for the first lab, the C wasn't too extensive, we used IORD/IOWR to interact with the right registers (or bits) for the different function: in one case writing a value, in another one checking a bit and the last one looping while a bit is 1. We also completed the main loop of the application, with it working as follows: While no error occurs capture and wait. + +\section{QSys system integration} +The second part of the lab consisted of connecting all the hardware component together using \emph{QSys}. We didn't encounter any major problems in that part. Some small issues that we had was that we were setting wrong directions for some signals, but that wasn't really hard to fix. +Note that we used the automatic memory mapping from QSys to let him decide where our components were mapped in memory. The memory mapping was then exported to the software part through the file system.h. Figure~\ref{fig:memory_mapping} shows how that mapping was chosen by QSys and exported to the file \emph{system.h}. + +\begin{figure}[H] +\centering +\includegraphics[width=\textwidth]{qsys_1.png} +\includegraphics[width=\textwidth]{horizontal.png} +\caption{At the top, the QSys editor. At the bottom, the \emph{system.h} file that was automatically generated. It can be seen that the memory mapping was taken by QSys.} +\label{fig:memory_mapping} +\end{figure} + +Another problem that we had was that we forgot to instantiate the components of the system in the VHDL entity that \emph{QSys} generated, because we initialy thought it was also done automaticly. + +\section*{Results} +In this section we just present a few images that we captured using the thermal camera, in Figure~\ref{fig:thermal_images} + +\begin{figure}[H] +\centering +\includegraphics{output_face.png} +\includegraphics{output_bottles.png} +\includegraphics{output_computer.png} +\caption{The images that we captured using the thermal camera. From left to right: Face with glasses, Glass Bottles, Inside a Computer with CPU and GPU (where we can see on the left a column of chokes and capacitors and on the right a crystal both of them being a major source of heat. We can also see on the bottom right an SSD).} +\label{fig:thermal_images} +\end{figure} + +\newpage +\section{Appendix: Code} +In this appendix, we have put the code that implements what was described in the previous sections, if you prefer to read from the PDF. In order not to make the report too long, we have only included the changes that we made, not the full files. + +\begin{minted}[breaklines]{VHDL} +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity lepton_stats is + port( + clk : in std_logic; + reset : in std_logic; + pix_data : in std_logic_vector(13 downto 0); + pix_valid : in std_logic; + pix_sof : in std_logic; + pix_eof : in std_logic; + stat_min : out std_logic_vector(13 downto 0); + stat_max : out std_logic_vector(13 downto 0); + stat_sum : out std_logic_vector(26 downto 0); + stat_valid : out std_logic); +end lepton_stats; + +architecture rtl of lepton_stats is + + -- The accumulated sum, min and max of the pixel values + signal curr_min : unsigned(13 downto 0); + signal curr_max : unsigned(13 downto 0); + signal curr_sum : unsigned(26 downto 0); + + -- The next value of the registers + signal next_min : unsigned(13 downto 0); + signal next_max : unsigned(13 downto 0); + signal next_sum : unsigned(26 downto 0); + +begin + + -- This is the synchronous transition logic + transition_logic : process(clk, reset) + begin + if reset = '1' then + curr_sum <= (others => '0'); + curr_min <= (others => '0'); + curr_max <= (others => '0'); + elsif rising_edge(clk) then + curr_min <= next_min; + curr_max <= next_max; + curr_sum <= next_sum; + end if; + end process; + + -- This is the combinatorial transition logic + next_min <= + curr_min when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_min when unsigned(pix_data) >= curr_min else + unsigned(pix_data); + + next_max <= + curr_max when pix_valid = '0' else + unsigned(pix_data) when pix_sof = '1' else + curr_max when unsigned(pix_data) <= curr_max else + unsigned(pix_data); + + next_sum <= + curr_sum when pix_valid = '0' else + unsigned((26 downto 14 => '0') & pix_data) when pix_sof = '1' else + curr_sum + unsigned((26 downto 14 => '0') & pix_data); + + -- This is the synchronous output logic + output_logic : process(clk, reset) + begin + if rising_edge(clk) then + stat_valid <= pix_eof; + end if; + end process; + + -- This is the combinatorial output logic + stat_min <= std_logic_vector(curr_min); + stat_max <= std_logic_vector(curr_max); + stat_sum <= std_logic_vector(curr_sum); + +end rtl; +\end{minted} +\captionof{listing}{ + The code written in lepton\_stats.vhd + \label{code:lepton_stats.vhd} +} + + +\begin{minted}[breaklines]{VHDL} +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity level_adjuster is + port( + clk : in std_logic; + raw_pixel : in std_logic_vector(13 downto 0); + raw_max : in std_logic_vector(13 downto 0); + raw_min : in std_logic_vector(13 downto 0); + raw_sum : in std_logic_vector(26 downto 0); + adjusted_pixel : out std_logic_vector(13 downto 0)); +end level_adjuster; + +architecture rtl of level_adjuster is + component lpm_divider + port( + clock : in std_logic; + denom : in std_logic_vector(13 downto 0); + numer : in std_logic_vector(27 downto 0); + quotient : out std_logic_vector(27 downto 0); + remain : out std_logic_vector(13 downto 0)); + end component; + + -- Intermediate signals needed by the divider + signal numer : std_logic_vector(27 downto 0); + signal denom : std_logic_vector(13 downto 0); + signal quot : std_logic_vector(27 downto 0); + +begin + + -- Computation of the intermediate signals + numer <= std_logic_vector((13 downto 0 => '1') * (unsigned(raw_pixel) - unsigned(raw_min))); + denom <= std_logic_vector(unsigned(raw_max) - unsigned(raw_min)); + + -- We compute the remaineder of (x - min) / (max - min) + divider : lpm_divider port map( + clock => clk, + numer => numer, + denom => denom, + quotient => quot, + remain => open + ); + + -- And we only keep the LSB of the quotient (we know the MSB must be 0) + adjusted_pixel <= + (adjusted_pixel'range => '0') when denom = (denom'range => '0') else + quot(13 downto 0); + +end rtl; +\end{minted} +\captionof{listing}{ + The code written in level\_adjuster.vhd + \label{code:level_adjuster.vhd} +} + +\begin{minted}[breaklines]{C} + do{ + lepton_start_capture(&lepton); + lepton_wait_until_eof(&lepton); +}while(lepton_error_check(&lepton)); +\end{minted} +\captionof{listing}{ + The code written in app.c + \label{code:app.c} +} + +\begin{minted}[breaklines]{C} +void lepton_start_capture(lepton_dev *dev) { + IOWR_16DIRECT(dev->base, LEPTON_REGS_COMMAND_OFST, 0x1); +} + +bool lepton_error_check(lepton_dev *dev) { + return (IORD_16DIRECT(dev->base, LEPTON_REGS_STATUS_OFST) & 0x2) != 0; +} + +void lepton_wait_until_eof(lepton_dev *dev) { + while(IORD_16DIRECT(dev->base, LEPTON_REGS_STATUS_OFST) & 0x1); +} +\end{minted} +\captionof{listing}{ + The code written in lepton.c + \label{code:lepton.c} +} + +\end{document} + diff --git a/cs309-psoc/report_2/systemh.png b/cs309-psoc/report_2/systemh.png new file mode 100644 index 0000000..3b23f9a Binary files /dev/null and b/cs309-psoc/report_2/systemh.png differ diff --git a/cs309-psoc/report_3/HPS_PERIF.PNG b/cs309-psoc/report_3/HPS_PERIF.PNG new file mode 100644 index 0000000..0fe1c1f Binary files /dev/null and b/cs309-psoc/report_3/HPS_PERIF.PNG differ diff --git a/cs309-psoc/report_3/QSYS.PNG b/cs309-psoc/report_3/QSYS.PNG new file mode 100644 index 0000000..da98bd0 Binary files /dev/null and b/cs309-psoc/report_3/QSYS.PNG differ diff --git a/cs309-psoc/report_3/report.pdf b/cs309-psoc/report_3/report.pdf new file mode 100644 index 0000000..8798312 Binary files /dev/null and b/cs309-psoc/report_3/report.pdf differ diff --git a/cs309-psoc/report_3/report.tex b/cs309-psoc/report_3/report.tex new file mode 100644 index 0000000..e2e37da --- /dev/null +++ b/cs309-psoc/report_3/report.tex @@ -0,0 +1,64 @@ +\documentclass[12pt]{article} +\usepackage[margin=2cm]{geometry} +\usepackage[utf8]{inputenc} +\usepackage{hyperref} +\usepackage{graphicx} +\usepackage[margin=2cm]{geometry} +\usepackage[utf8]{inputenc} +\usepackage{hyperref} +\usepackage{graphicx} +\usepackage{minted} +\usepackage{caption} + +\title{Laboratory 3 report} +\author{Cédric Hölzl \and Antoine Brunner} +\date{May 2020} + +\begin{document} +\maketitle + +\section{Introduction} +The goal of this laboratory was to build a complete Linux system on a DE0-nano-SoC - a hybrid board consisting of a FPGA and an ARM dual-core HPS. Building a Linux system tailored to a specific hardware architecture is not an easy task, and there were a lot of steps involved before succeeding with that. First, we had to use the QSys platform designer to configure the hardware properly. Then, we had to use Altera's BSP editor to generate a boot loader tailored to the hardware configuration. After that, we had to compile the Linux OS and flash it to an SD card, along with the pre-loader and the boot loader. Finally, we could boot the system, and log onto it using a minicom terminal and after configuring the wired interface via SSH from a remote device. + +\section{Configuring the hardware using QSys} +In this part, we had to configure the hardware for the Linux system. While the Linux system can run on an ARM processor, we still had to configure the FPGA part, because the goal was to reuse some hardware interfaces from previous labs. That is, we want to configure the joysticks and the thermal camera so that they can be used by the HPS. Figure~\ref{fig:qsys} shows how we configured the system with the joysticks, the thermal camera and the ARM processor. + +\begin{figure}[H] +\centering +\includegraphics[width=\textwidth]{QSYS.PNG} +\caption{Overall view of the system} +\label{fig:qsys} +\end{figure} + +As a side note, since the HPS would run a Linux OS, accessing the memory mapped peripherals cannot be done in the virtual address space of the processes. Several solutions exists, such as creating a driver, or probably simpler, using \emph{mmap} to map physical pages into the virtual address space. That was not the concern of the lab, but it is worth mentioning it, because that's a problem we will face in the next laboratory. + +An error that we made while using QSys was that we didn't understand what the \emph{peripheral multiplexer} tab was doing. Due to that misunderstanding, we did not select the pins that system needed, and couldn't boot the system correctly. After an explanation by an assistant, we finally understood how that pin multiplexer works, and we could fix the mistake that we had made. + +Other than that, we also had to instantiate the system in the top-level VHD file, by making the right pin assignments for all the components, and get the design to compile. We also had some problems at this stage. Initialy we left some pins unassigned by mistake, causing the fitter to fail, but that was easily fixed. + +\section{Compiling the system} +To compile the system on the board, we still had a long way. We had to generate the pre-loader using the BSP editor. After that, we downloaded Alteras's U-boot, configured it for the ARM processor and compiled it. The last piece of the puzzle was to download Ubuntu 14, compile it, and configure it by creating scripts that would run at the first start. + +Although we have not succeeded initialy in doing those steps by ourselves, we didn't encounter any major problems in those steps, thanks to the Soc-FPGA Design Guide. + +The final step was to put all the generated files in the right partitions of the SD card, so that the system could properly boot: the pre-loader to the A2 partition, the boot loader to the FAT32 partition and the Linux file system to the EXT3 partition. + +We were already familiar with creating partitions and moving data to certain partitions using the command line, so we managed to do this step without major difficulties. + +\section{Problems encountered} +Of course, it would have been to easy if everything went correctly... We didn't manage to boot our system from the first time because of a very dumb mistake. At least, we have learnt something from that mistake. + +The mistake that we did is that we forgot to enable the GPIO pins in the QSys platform designer, meaning that the multiple ports (SD, Ethernet, ...) would never be properly connected to the processor. Figure~\ref{fig:pin_multiplexer} shows the interface on which we should have selected the right pins. That was the reason why we could not see anything in the Minicom terminal when the system was supposed to be booting. That mistake came from the fact that we didn't understand the QSys interface very well, nor the utility of the pin multiplexer. After an explanation from one of the assistants we have now understood what this interface is useful for, and we managed to fix the problem pretty easily. + +\begin{figure}[H] +\centering +\includegraphics[width=\textwidth]{HPS_PERIF.PNG} +\caption{The peripherals multiplexer view} +\label{fig:pin_multiplexer} +\end{figure} + +\section{Conclusion} +As a conclusion, we think that this lab was a lot about following the guide, which sometimes didn't help us understand what we were doing. This in part the reason why we have made that mistake. Fortunately, it allowed us to question what we had done, and to learn what we were doing wrong. We had to restart the instruction from the beginning (having had a corruption issue with the VM), so the second time we started to remember a lot better what to do, allowing us to complete it quickly without issues. + +\end{document} + diff --git a/cs309-psoc/report_4/bernstein-curves.png b/cs309-psoc/report_4/bernstein-curves.png new file mode 100644 index 0000000..6ee589d Binary files /dev/null and b/cs309-psoc/report_4/bernstein-curves.png differ diff --git a/cs309-psoc/report_4/bernstein-range.png b/cs309-psoc/report_4/bernstein-range.png new file mode 100644 index 0000000..bc363eb Binary files /dev/null and b/cs309-psoc/report_4/bernstein-range.png differ diff --git a/cs309-psoc/report_4/caca-hand.png b/cs309-psoc/report_4/caca-hand.png new file mode 100644 index 0000000..1d3cb05 Binary files /dev/null and b/cs309-psoc/report_4/caca-hand.png differ diff --git a/cs309-psoc/report_4/caca-hot.png b/cs309-psoc/report_4/caca-hot.png new file mode 100644 index 0000000..ad92d0d Binary files /dev/null and b/cs309-psoc/report_4/caca-hot.png differ diff --git a/cs309-psoc/report_4/caca-human.png b/cs309-psoc/report_4/caca-human.png new file mode 100644 index 0000000..b275950 Binary files /dev/null and b/cs309-psoc/report_4/caca-human.png differ diff --git a/cs309-psoc/report_4/caca-pc.png b/cs309-psoc/report_4/caca-pc.png new file mode 100644 index 0000000..ee5b28d Binary files /dev/null and b/cs309-psoc/report_4/caca-pc.png differ diff --git a/cs309-psoc/report_4/caca-stcc.png b/cs309-psoc/report_4/caca-stcc.png new file mode 100644 index 0000000..cb87edd Binary files /dev/null and b/cs309-psoc/report_4/caca-stcc.png differ diff --git a/cs309-psoc/report_4/caca-wet.png b/cs309-psoc/report_4/caca-wet.png new file mode 100644 index 0000000..1ce2e41 Binary files /dev/null and b/cs309-psoc/report_4/caca-wet.png differ diff --git a/cs309-psoc/report_4/lab4.zip b/cs309-psoc/report_4/lab4.zip new file mode 100644 index 0000000..22cd1d9 Binary files /dev/null and b/cs309-psoc/report_4/lab4.zip differ diff --git a/cs309-psoc/report_4/report.pdf b/cs309-psoc/report_4/report.pdf new file mode 100644 index 0000000..8febc08 Binary files /dev/null and b/cs309-psoc/report_4/report.pdf differ diff --git a/cs309-psoc/report_4/report.tex b/cs309-psoc/report_4/report.tex new file mode 100644 index 0000000..be32fc0 --- /dev/null +++ b/cs309-psoc/report_4/report.tex @@ -0,0 +1,134 @@ +\documentclass[12pt]{article} +\usepackage[margin=2cm]{geometry} +\usepackage[utf8]{inputenc} +\usepackage{graphicx} +\usepackage[margin=2cm]{geometry} +\usepackage[utf8]{inputenc} +\usepackage[colorlinks]{hyperref} +\usepackage{graphicx} +\usepackage{minted} +\usepackage{caption} +\usepackage{subfigure} +\usepackage{dirtree} + +\title{Laboratory 4 report} +\author{Cédric Hölzl \and Antoine Brunner} +\date{May 2020} + +\begin{document} +\maketitle + +\section{Introduction} +In this laboratory, we had to create our own project using the DE0-nano-SoC. We chose to build upon thermal camera from the second lab and create a server capable of streaming the image from the thermal camera to a client through the Ethernet interface available on the board. + +The server would run on the Linux OS on the hard-core ARM processor and would access the thermal camera through the interface that was created on the FPGA part of the board. This means that we had to find a way to access data captured by the thermal camera on the FPGA part from the Linux. + +\section{Thermal camera interface} +We have reused the lepton camera interface programmed in VHDL from lab 2. It already suited our needs, so we didn't need to change anything to it. However, it is still important to remember how the interface worked. The interface allows us to control the camera through memory mapped registers. For example, there are a \emph{COMMAND} and a \emph{STATUS} registers that allow to instruct the camera to start capturing a frame and check its error status. There are also two memory regions that allow to read the raw image, as it was captured, or the image adjusted between the minimum and maximum temperature. This means that if we have access to that memory, we can control the camera by just reading and writing to certain addresses. The challenge was to be able to access that memory from the ARM processor, and it will be discussed in the next sections. + +\section{Linux OS} +Since we needed to create a server, we needed to use the Ethernet interface. It would be possible to develop a baremetal application that uses the Ethernet interface, but it would be harder to implement. Instead, Linux provides us with drivers that allow to access it transparently through existing libraries. As we are programmers, we are lazy and don't want to reinvent the wheel, so that's why we chose to use Linux, instead of a baremetal application. In the previous lab, we have been able to boot Linux on our DE0-nano-SoC so we could reuse that configuration for this lab. As was said above, the challenge was to access the lepton camera interface from the Linux part. + +\section{Accessing the thermal camera from Linux} +The fact that there is a Linux system running on the ARM processor means that we cannot access the memory directly anymore. OS's virtualize the memory so that several processes can run simultaneously. While this architecture provides a great abstraction over the hardware, it also means that we cannot directly access the physical memory. But fortunately, there is a way to map physical memory onto virtual memory, through the \emph{mmap} function. + +\emph{mmap} allows to map a given file descriptor in a certain range of the virtual memory. On Linux systems, there is a special file \emph{/dev/mem} that represents the physical memory. Combining the two functionalities, we can first open that special file, and map it into the virtual memory. This gives us the ability to access arbitrary ranges of the physical memory from a Linux process. This approach has one drawback: opening \emph{/dev/mem} requires elevated privileges, so it means that our server needs to be run with \emph{sudo}. This is not such a big problem for us since we are the administrators of the Linux system, but it could cause some problems if a normal user wants to run our server. + +\section{Server-client protocol} +Now that we have a way to access the thermal camera images from a Linux process, we need to send it to the client. To do so, we can use the Linux socket programming libraries to set up a working server. We chose to send the image over UDP with one packet per line, along some metadata. The motivation behind that choice is that UDP hass less overhead than TCP (no handshakes,...) and that packet loss is not a major issue. Indeed if a packet containing a certain line is lost, we can simply display the line from the previous frame, and it is not going to be noticeable (at most it might have an effect similar to screen tearing). + +We will now explain our very simple server-client protocol. Once the server has created and bound a UDP socket, it then waits for a client to arrive. To start the communication to the server, a client has to send an empty (zero-length) packet to the server. Once the server received that packet, it starts sending the thermal image with one packet per line. Each packet first contains the index of the line, encoded in four bytes (for alignment purposes), and then contains the pixels of the line that take two bytes each. The client can send again a zero-length packet to the server to indicate that he wants to stop the connection. In that case, the server stops sending packets to that client and waits for the next client to connect. The server can also be stopped at any time by pressing on 'q'. + +\section{Clients} +Since both of us were familiar with different libraries for rendering images to the screen, we have decided to create two clients to visualize the thermal image. Cedric wanted to experiment with a library called CACA, while Antoine already had some experience with a library called SFML. + +\subsection{Refresh Logic} +While trying to reduce the performance impact of our software, we had some choices to make. Initialy, we refreshed the display for every line received. This however proved rather inefficient, updating the display 60 times for every frame, at 9 frames per seconds. Ideally, we would want to refresh the image every 60 lines, but with packet loss it might end up out of sync with the frames. We could add a frame counter to the packets but it will have the drawback that there is no way to detect missing packets. We made the choice in the end to refresh every 60 lines, resetting the counter when we receive the last line of any frame. This prevents the line counter from getting out of sync and guarantees that even with out of order packets and packet loss we still get a relatively good image. + +\subsection{Greyscale to RGB} +The values that are read from the thermal camera are encoded on 14 bits and represent the temperature between the minimum and the maximum (we sample the adjusted buffer). To visualize them, we could simply map them to a grey scale color. While it would be easy to implement, the result is not really intuitive, or at least not visually pleasant. To improve the image visualization we have used a slightly more complex mapping using Bernstein polynomials. Those polynomials are not related in any way to color mapping, but it turns out that they yield a perfect color mapping for temperature visualization, so we chose to use them. Figure~\ref{fig:bernstein} shows the red green and blue curves that the Bernstein polynomials give, as well as visualization of the resulting color range. + +\begin{figure} + \centering + \subfigure[The red, blue and green curves as the temperature varies]{\includegraphics[width=5cm]{bernstein-curves}} + \subfigure[The resulting color range]{\includegraphics[width=5cm]{bernstein-range}} + \caption{The Bernstein color mapping} + \label{fig:bernstein} +\end{figure} + +\subsection{CACA client} +CACA stands for \textbf{C}olor-\textbf{A}S\textbf{C}II-\textbf{A}rt. It is a library that is aimed to transform media such as images or video into colored ASCII frames in terminal environments. It uses NCurses, is relativly lightweight, and has options for image processing and more, making it an interesting tool for this project. We used standard C sockets to communicate with the server. We managed to optimize performance making our program use at most 1.5\% CPU while running. + +\subsection{SFML client} +SFML stands for \textbf{S}imple and \textbf{F}ast \textbf{M}ultimedia \textbf{L}ibrary. It is a cross-platform library that allows to build simple window applications and that also provides access to sockets. We have initially chosen to use asynchronous socket receiving in order not to block the interface while waiting for packets to arrive. While this was meant to make the application more responsive, it had the opposite effect. We noticed that the client was using 6 threads and almost 200\% of the CPU (two cores). We believe that the threads come from how SFML was implemented, and in particular from the asynchronous sockets. To try and optimize this, we switched back to synchronous socket receiving (meaning that the process can sleep while waiting for packets).We also tried to refresh the screen less often, which had a big effect on the performance. After those optimizations, the usage dropped from 200\% (2 cores) to around 2\%. + +\section{Gallery} +In this section, we show some images that we captured using the thermal camera and the two clients. Note that the images captured using the CACA client are stretched, because ASCII characters are not perfectly square in terminals, but are usually twice as high as they are wide. + +\begin{figure}[H] + \centering + \subfigure[CACA]{\includegraphics[width=5cm]{caca-hand}} + \subfigure[SFML]{\includegraphics[width=5cm]{sfml-hand}} + \caption{A hand holding a mouse} +\end{figure} +\begin{figure}[H] + \centering + \subfigure[CACA]{\includegraphics[width=5cm]{caca-hot}} + \subfigure[SFML]{\includegraphics[width=5cm]{sfml-hot}} + \caption{A mug and plastic cup holding boiling water} +\end{figure} +\begin{figure}[H] + \centering + \subfigure[CACA]{\includegraphics[width=5cm]{caca-human}} + \subfigure[SFML]{\includegraphics[width=5cm]{sfml-human}} + \caption{Cedric's face, with his glasses and microphone} +\end{figure} +\begin{figure}[H] + \centering + \subfigure[CACA]{\includegraphics[width=5cm]{caca-pc}} + \subfigure[SFML]{\includegraphics[width=5cm]{sfml-pc}} + \caption{Inside a water-cooled computer (top-left cpu, bottom right SSD)} +\end{figure} +\begin{figure}[H] + \centering + \subfigure[CACA]{\includegraphics[width=5cm]{caca-stcc}} + \subfigure[SFML]{\includegraphics[width=5cm]{sfml-stcc}} + \caption{The Swiss Tech Convention Center} +\end{figure} +\begin{figure}[H] + \centering + \subfigure[CACA]{\includegraphics[width=5cm]{caca-wet}} + \subfigure[SFML]{\includegraphics[width=5cm]{sfml-wet}} + \caption{Hand with wet fingers} +\end{figure} + +\section{Conclusion} +It was very interesting to work on a project were we have to write a system from the hardware to the software. It is not often that we get to program hardware interfaces, sockets, and window applications in the same project. Since a lot of the work had already been done in the previous labs, we didn't struggle too much with the hardware part, and we had a lot of time left to program the server and the clients. + +We also have multiple ideas of additions to extend our project. One would be to make use of the servos to control the infrared camera's pitch and yaw from the client. An other idea would be to transmit the real min/max temperatures so that the client knows what temperature the colors translate to. A final idea that we had would be to allow the server to send the stream to multiple clients, either using multicast or by keeping a list of connected clients. Of course, if we had more time, we would certainly tinker a bit more with that project, but unfortunately all things have an end. + +\newpage +\section{Appendix: archive structure} +Since we have used a lot of files for this project, we have decided not to include them in the report, so that it doesn't get absurdly long. We have included the files in which we implemented the server and the clients in the archive using the structure described just below. Note that we do not include VHDL files in the archive because we have taken the files from the second laboratory without modifying them. There are three main folders in the archive, where you can find the server and the two clients respectively. Note that in the server, we have mainly modified the files \emph{server.h}, \emph{server.c} and \emph{app.c}, but we include the other files for completeness. + +\dirtree{% + .1 {lab4.zip} . + .2 {CedricHoelzl\_AntoineBrunner\_lab4\_EmbeddedLinuxMiniProject.pdf} . + .2 {client-caca} . + .3 {main.cpp} . + .2 {client-sfml} . + .3 {main.cpp} . + .2 {server} . + .3 {lepton} . + .4 {lepton.h} . + .4 {lepton.c} . + .4 {lepton\_regs.h} . + .3 {hps\_soc\_system.h} . + .3 {iorw.h} . + .3 {server.h} . + .3 {server.c} . + .3 {app.c} . +} + +\end{document} + diff --git a/cs309-psoc/report_4/sfml-hand.png b/cs309-psoc/report_4/sfml-hand.png new file mode 100644 index 0000000..170a31e Binary files /dev/null and b/cs309-psoc/report_4/sfml-hand.png differ diff --git a/cs309-psoc/report_4/sfml-hot.png b/cs309-psoc/report_4/sfml-hot.png new file mode 100644 index 0000000..0e217ac Binary files /dev/null and b/cs309-psoc/report_4/sfml-hot.png differ diff --git a/cs309-psoc/report_4/sfml-human.png b/cs309-psoc/report_4/sfml-human.png new file mode 100644 index 0000000..450cc5f Binary files /dev/null and b/cs309-psoc/report_4/sfml-human.png differ diff --git a/cs309-psoc/report_4/sfml-pc.png b/cs309-psoc/report_4/sfml-pc.png new file mode 100644 index 0000000..ff04121 Binary files /dev/null and b/cs309-psoc/report_4/sfml-pc.png differ diff --git a/cs309-psoc/report_4/sfml-stcc.png b/cs309-psoc/report_4/sfml-stcc.png new file mode 100644 index 0000000..59a44a9 Binary files /dev/null and b/cs309-psoc/report_4/sfml-stcc.png differ diff --git a/cs309-psoc/report_4/sfml-wet.png b/cs309-psoc/report_4/sfml-wet.png new file mode 100644 index 0000000..cc83d80 Binary files /dev/null and b/cs309-psoc/report_4/sfml-wet.png differ