Disabled external gits

cs309-psoc/lab_4_0/hw/quartus/ip/components.ipx

@@ -0,0 +1,98 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<library>
+ <!--  date: 2017.05.14.23:41:43 -->
+ <!--  generated by: ip-make-ipx -->
+ <!--   -->
+ <!--     5 in ../../hdl/ -->
+ <!--   -->
+ <component
+   name="framebuffer_manager"
+   file="../../hdl/displays/framebuffer_manager/hdl/framebuffer_manager_hw.tcl"
+   displayName="framebuffer_manager"
+   version="1.0"
+   description=""
+   tags="AUTHORSHIP=Philemon Favrod /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=false"
+   categories="LCD"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+ <component
+   name="lepton"
+   file="../../hdl/lepton/hdl/lepton_hw.tcl"
+   displayName="lepton"
+   version="1.0"
+   description="IR Camera 80x60"
+   tags="AUTHORSHIP=Philemon Favrod &amp; Sahand Kashani-Akhavan /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
+   categories="Camera"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+ <component
+   name="mcp3204"
+   file="../../hdl/joysticks/hdl/mcp3204_hw.tcl"
+   displayName="mcp3204"
+   version="1.0"
+   description="4-Channel 12-Bit A/D Converter with SPI Serial Interface"
+   tags="AUTHORSHIP=Philemon Favrod &amp; Sahand Kashani-Akhavan /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
+   categories="Joystick"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+ <component
+   name="pwm"
+   file="../../hdl/pantilt/hdl/pwm_hw.tcl"
+   displayName="pwm"
+   version="1.0"
+   description="Pan-tilt"
+   tags="AUTHORSHIP= /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
+   categories="Pan-tilt"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+ <component
+   name="vga_sequencer"
+   file="../../hdl/displays/vga_sequencer/hdl/vga_sequencer_hw.tcl"
+   displayName="vga_sequencer"
+   version="1.0"
+   description=""
+   tags="AUTHORSHIP=Philemon Favrod /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=false"
+   categories="LCD"
+   factory="TclModuleFactory">
+  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
+  <tag2 key="COMPONENT_EDITABLE" value="true" />
+  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
+  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
+  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
+  <tag2 key="REPORT_HIERARCHY" value="false" />
+  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
+  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
+ </component>
+</library>

cs309-psoc/lab_4_0/hw/quartus/lab_4_0.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors.  Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+# Date created = 11:03:02  February 05, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "15.1"
+DATE = "11:03:02  February 05, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "lab_4_0"

cs309-psoc/lab_4_0/hw/quartus/lab_4_0.sdc

@@ -0,0 +1,6 @@
+create_clock -period 20 [get_ports FPGA_CLK1_50]
+create_clock -period 20 [get_ports FPGA_CLK2_50]
+create_clock -period 20 [get_ports FPGA_CLK3_50]
+
+derive_pll_clocks
+derive_clock_uncertainty