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choelzl
2022-04-07 18:54:11 +02:00
parent 15e7120d6d
commit 0fb3e365d4
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214
cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/dc_video_fifo.vhd Normal file
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-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: dc_video_fifo.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dc_video_fifo IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (95 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END dc_video_fifo;
ARCHITECTURE SYN OF dc_video_fifo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (95 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(23 DOWNTO 0);
rdempty <= sub_wire1;
wrusedw <= sub_wire2(8 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone V",
lpm_numwords => 256,
lpm_showahead => "ON",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 96,
lpm_widthu => 9,
lpm_widthu_r => 11,
lpm_width_r => 24,
overflow_checking => "ON",
rdsync_delaypipe => 5,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
aclr => aclr,
data => data,
rdclk => rdclk,
rdreq => rdreq,
wrclk => wrclk,
wrreq => wrreq,
q => sub_wire0,
rdempty => sub_wire1,
wrusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "256"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "96"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
-- Retrieval info: PRIVATE: output_width NUMERIC "24"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "96"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "11"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "24"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 96 0 INPUT NODEFVAL "data[95..0]"
-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 96 0 data 0 0 96 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dc_video_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dc_video_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dc_video_fifo.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dc_video_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dc_video_fifo_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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-------------------------------------------------------------------------------
-- Title : Frame Buffer Manager
-- Project : From FPGA to Linux: An embedded system exploration
-------------------------------------------------------------------------------
-- File : framebuffer_manager.vhd
-- Author : Philemon Orphee Favrod <philemon.favrod@epfl.ch>
-- Company :
-- Created : 2016-03-10
-- Last update: 2017-02-21
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: DMA-capable unit that manages reads to a framebuffer.
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-10 1.0 P. Favrod Created
-- 2016-04-25 1.1 P. Favrod Debuged
-- 2016-05-23 1.2 P. Favrod Increased bandwidth + fifo sync @ VFP
-- 2016-05-29 1.3 P. Favrod Added MSB to FIFO + removed wrfull
-------------------------------------------------------------------------------
-- Register Memory Mapping
-- +-------+--------+-----+-----+-----+-----+----+-----------+
-- | Regno | Access | B31 | ... | B10 | ... | B1 | B0 |
-- +-------+--------+-----+-----+-----+-----+----+-----------+
-- | 0 | R/W | FRAME_START_ADDRESS |
-- +-------+--------+----------------------------------------+
-- | 1 | R/W | FRAME_PIXEL_PER_LINE |
-- +-------+--------+----------------------------------------+
-- | 2 | R/W | FRAME_LINES_PER_FRAME |
-- +-------+--------+----------------------------------------+
-- | 3 | R/W | FRAME_EOL_BYTE_OFFSET |
-- +-------+--------+----------------------------------------+
-- | 4 | WO | COMMAND_REGISTER |
-- +-------+--------+---------------------------+------------+
-- | 5 | R/W | | FB_BURST_COUNT |
-- +-------+--------+-----------+----------------------------+
--
-- Command register:
-- [0] Enable DMA loop
-- [1] Disable DMA loop
-- [2] Enable interrupts
-- [3] Disable interrupts
-- [4] Acknowledge IRQ
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity framebuffer_manager is
port(
clk : in std_logic;
pixclk : in std_logic;
reset : in std_logic;
-- Avalon-MM Slave Interface
as_address : in std_logic_vector(3 downto 0);
as_read : in std_logic;
as_readdata : out std_logic_vector(31 downto 0);
as_write : in std_logic;
as_writedata : in std_logic_vector(31 downto 0);
-- Avalon-MM Master Interface
am_address : out std_logic_vector(31 downto 0);
am_waitrequest : in std_logic;
am_burstcount : out std_logic_vector(10 downto 0);
am_read : out std_logic;
am_readdata : in std_logic_vector(127 downto 0);
am_readdatavalid : in std_logic;
frame_sync : in std_logic;
-- Interrupt Sender Interface
irq : out std_logic;
-- Avalon-ST Source Interface
src_data : out std_logic_vector(23 downto 0);
src_valid : out std_logic;
src_ready : in std_logic);
end framebuffer_manager;
architecture rtl of framebuffer_manager is
constant MAX_BURST_COUNT : integer := 1024;
constant FRAME_START_ADDRESS_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(0, as_address'length));
constant FRAME_PIXEL_PER_LINE_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(1, as_address'length));
constant FRAME_LINES_PER_FRAME_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(2, as_address'length));
constant FRAME_EOL_BYTE_OFFSET_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(3, as_address'length));
constant FB_COMMAND_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(4, as_address'length));
constant FB_BURST_COUNT_REGNO : std_logic_vector(as_address'range) := std_logic_vector(to_unsigned(5, as_address'length));
signal start_address : integer;
signal current_address : integer;
signal pix_per_line, pix_per_line_copy : integer;
signal num_lines, num_lines_copy : integer;
signal eol_byte_offset, eol_byte_offset_copy : integer;
signal enabled : boolean;
signal burst_count, burst_count_copy : integer;
signal irq_enabled : boolean;
signal irq_acknowledged : boolean;
signal burst_counter : integer range 1 to MAX_BURST_COUNT;
signal pix_counter : integer;
signal line_counter : integer;
type state is (IDLE, MEMSTARTREAD, MEMRESTARTREAD, MEMREAD, FLUSHBURST, WAITSYNC);
signal current_state : state;
constant INTERNAL_FIFO_DEPTH : integer := 256;
signal fifo_clr : std_logic;
signal fifo_data_in : std_logic_vector(95 downto 0);
signal fifo_data_out : std_logic_vector(23 downto 0);
signal fifo_read : std_logic;
signal fifo_write : std_logic;
signal fifo_usedw : std_logic_vector(8 downto 0);
signal fifo_freew : integer range 0 to INTERNAL_FIFO_DEPTH;
signal fifo_empty : std_logic;
signal fifo_large_enough : boolean;
begin
dc_video_fifo_inst : entity work.dc_video_fifo port map (
aclr => fifo_clr,
data => fifo_data_in,
rdclk => pixclk,
rdreq => fifo_read,
wrclk => clk,
wrreq => fifo_write,
q => fifo_data_out,
rdempty => fifo_empty,
wrusedw => fifo_usedw);
fifo_write <= am_readdatavalid and not fifo_clr when current_state = MEMREAD else '0';
fifo_read <= src_ready and not fifo_empty;
fifo_clr <= '1' when current_state = IDLE else '0';
fifo_freew <= INTERNAL_FIFO_DEPTH - to_integer(unsigned(fifo_usedw));
fifo_large_enough <= fifo_freew >= burst_count_copy;
fifo_data_in <= am_readdata(119 downto 96) & am_readdata(87 downto 64) & am_readdata(55 downto 32) & am_readdata(23 downto 0);
src_data <= fifo_data_out when fifo_empty = '0' else X"ff0000";
src_valid <= not fifo_empty;
p_as_write : process (clk, reset)
begin
if reset = '1' then
start_address <= 0;
pix_per_line <= 0;
num_lines <= 0;
eol_byte_offset <= 0;
burst_count <= 4;
enabled <= false;
irq_enabled <= false;
irq_acknowledged <= false;
elsif rising_edge(clk) then
irq_acknowledged <= false;
if as_write = '1' then
case as_address is
when FRAME_START_ADDRESS_REGNO =>
start_address <= to_integer(unsigned(as_writedata));
when FRAME_PIXEL_PER_LINE_REGNO =>
pix_per_line <= to_integer(unsigned(as_writedata));
when FRAME_LINES_PER_FRAME_REGNO =>
num_lines <= to_integer(unsigned(as_writedata));
when FRAME_EOL_BYTE_OFFSET_REGNO =>
eol_byte_offset <= to_integer(unsigned(as_writedata));
when FB_COMMAND_REGNO =>
if as_writedata(0) = '1' then
enabled <= true;
end if;
if as_writedata(1) = '1' then
enabled <= false;
end if;
if as_writedata(2) = '1' then
irq_enabled <= true;
end if;
if as_writedata(3) = '1' then
irq_enabled <= false;
end if;
if as_writedata(4) = '1' then
irq_acknowledged <= true;
end if;
when FB_BURST_COUNT_REGNO =>
if unsigned(as_writedata) > MAX_BURST_COUNT then
burst_count <= MAX_BURST_COUNT;
else
burst_count <= to_integer(unsigned(as_writedata));
end if;
when others => null;
end case;
end if;
end if;
end process p_as_write;
p_as_read : process (clk, reset)
begin
if reset = '1' then
as_readdata <= (others => '0');
elsif rising_edge(clk) then
as_readdata <= (others => '0');
if as_read = '1' then
case as_address is
when FRAME_START_ADDRESS_REGNO =>
as_readdata <= std_logic_vector(to_unsigned(start_address, as_readdata'length));
when FRAME_PIXEL_PER_LINE_REGNO =>
as_readdata <= std_logic_vector(to_unsigned(pix_per_line, as_readdata'length));
when FRAME_LINES_PER_FRAME_REGNO =>
as_readdata <= std_logic_vector(to_unsigned(num_lines, as_readdata'length));
when FRAME_EOL_BYTE_OFFSET_REGNO =>
as_readdata <= std_logic_vector(to_unsigned(eol_byte_offset, as_readdata'length));
when FB_BURST_COUNT_REGNO =>
as_readdata <= std_logic_vector(to_unsigned(burst_count, as_readdata'length));
when others => null;
end case;
end if;
end if;
end process p_as_read;
p_fsm : process (clk, reset)
begin
if reset = '1' then
current_address <= 0;
pix_per_line_copy <= 0;
num_lines_copy <= 0;
eol_byte_offset_copy <= 0;
burst_count_copy <= 0;
burst_counter <= 1;
pix_counter <= 0;
line_counter <= 0;
current_state <= IDLE;
elsif rising_edge(clk) then
-- If the interrupts have been disabled or acknowledged
-- we deassert the interrupt request line.
if not irq_enabled or irq_acknowledged then
irq <= '0';
end if;
case current_state is
when IDLE =>
-- In IDLE state, wait for enabled to be high Then, save a copy of registers
-- in shadow registers and start reading memory.
if enabled then
current_address <= start_address;
pix_per_line_copy <= pix_per_line;
num_lines_copy <= num_lines;
eol_byte_offset_copy <= eol_byte_offset;
burst_count_copy <= burst_count;
current_state <= MEMSTARTREAD;
pix_counter <= 4 * burst_count; -- so that when pix_counter =
-- pix_per_line_copy we are done
line_counter <= 1;
end if;
-- wait state for the DC fifo signal to be updated
when MEMRESTARTREAD =>
current_state <= MEMSTARTREAD;
when MEMSTARTREAD =>
-- If there is room for a full burst in the FIFO and
-- no wait request on the bus, we start reading!
if fifo_large_enough and am_waitrequest = '0' then
burst_counter <= 1;
current_state <= MEMREAD;
end if;
when MEMREAD =>
-- If a valid data is received
if am_readdatavalid = '1' then
-- If in the middle of a burst, increment the burst counter
if burst_counter < burst_count_copy then
burst_counter <= burst_counter + 1;
else
-- If in the middle of a line, increment the pixel counter and the
-- address accordingly
if pix_counter < pix_per_line_copy then
pix_counter <= pix_counter + 4 * burst_count_copy;
current_address <= current_address + 16 * burst_count_copy;
current_state <= MEMRESTARTREAD;
-- If at the end of a line, increment the line counter and the
-- address accordingly. Reset pix_counter too!
elsif line_counter < num_lines_copy then
line_counter <= line_counter + 1;
pix_counter <= 4 * burst_count_copy;
current_address <= current_address + 16 * burst_count_copy + eol_byte_offset_copy;
current_state <= MEMRESTARTREAD;
-- If at the end of a frame, go back to WAITSYNC until blanking
else
current_state <= WAITSYNC;
-- End of frame => IRQ!
if irq_enabled then
irq <= '1';
end if;
end if;
end if;
end if;
if frame_sync = '1' then
current_state <= FLUSHBURST;
end if;
when FLUSHBURST =>
if burst_counter = burst_count_copy then
current_state <= IDLE;
elsif am_readdatavalid = '1' then
burst_counter <= burst_counter + 1;
end if;
when WAITSYNC =>
-- Wait for vertical blanking to occur to avoid filling the FIFO
-- just before it is cleared!
if frame_sync = '1' then
current_state <= IDLE;
end if;
when others => null;
end case;
end if;
end process p_fsm;
am_address <= std_logic_vector(to_unsigned(current_address, am_address'length));
am_read <= '1' when fifo_large_enough and current_state = MEMSTARTREAD else '0';
am_burstcount <= std_logic_vector(to_unsigned(burst_count_copy, am_burstcount'length));
end architecture;

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cs309-psoc/lab_4_0/hw/hdl/displays/framebuffer_manager/hdl/framebuffer_manager_hw.tcl Normal file
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# TCL File Generated by Component Editor 16.0
# Sun Feb 05 18:18:01 CET 2017
# DO NOT MODIFY
#
# framebuffer_manager "framebuffer_manager" v1.0
# 2017.02.05.18:18:01
#
#
#
# request TCL package from ACDS 16.0
#
package require -exact qsys 16.0
#
# module framebuffer_manager
#
set_module_property DESCRIPTION ""
set_module_property NAME framebuffer_manager
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP LCD
set_module_property AUTHOR "Philemon Favrod"
set_module_property DISPLAY_NAME framebuffer_manager
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL framebuffer_manager
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file framebuffer_manager.vhd VHDL PATH framebuffer_manager.vhd TOP_LEVEL_FILE
add_fileset_file dc_video_fifo.vhd VHDL PATH dc_video_fifo.vhd
#
# parameters
#
#
# module assignments
#
set_module_assignment embeddedsw.dts.compatible prsoc,framebuffer-manager
set_module_assignment embeddedsw.dts.group any
set_module_assignment embeddedsw.dts.vendor prsoc
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1
#
# connection point interrupt_sender
#
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint ""
set_interface_property interrupt_sender associatedClock clock
set_interface_property interrupt_sender associatedReset reset
set_interface_property interrupt_sender bridgedReceiverOffset ""
set_interface_property interrupt_sender bridgesToReceiver ""
set_interface_property interrupt_sender ENABLED true
set_interface_property interrupt_sender EXPORT_OF ""
set_interface_property interrupt_sender PORT_NAME_MAP ""
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
add_interface_port interrupt_sender irq irq Output 1
#
# connection point csr
#
add_interface csr avalon end
set_interface_property csr addressUnits WORDS
set_interface_property csr associatedClock clock
set_interface_property csr associatedReset reset
set_interface_property csr bitsPerSymbol 8
set_interface_property csr burstOnBurstBoundariesOnly false
set_interface_property csr burstcountUnits WORDS
set_interface_property csr explicitAddressSpan 0
set_interface_property csr holdTime 0
set_interface_property csr linewrapBursts false
set_interface_property csr maximumPendingReadTransactions 0
set_interface_property csr maximumPendingWriteTransactions 0
set_interface_property csr readLatency 0
set_interface_property csr readWaitTime 1
set_interface_property csr setupTime 0
set_interface_property csr timingUnits Cycles
set_interface_property csr writeWaitTime 0
set_interface_property csr ENABLED true
set_interface_property csr EXPORT_OF ""
set_interface_property csr PORT_NAME_MAP ""
set_interface_property csr CMSIS_SVD_VARIABLES ""
set_interface_property csr SVD_ADDRESS_GROUP ""
add_interface_port csr as_address address Input 4
add_interface_port csr as_read read Input 1
add_interface_port csr as_readdata readdata Output 32
add_interface_port csr as_write write Input 1
add_interface_port csr as_writedata writedata Input 32
set_interface_assignment csr embeddedsw.configuration.isFlash 0
set_interface_assignment csr embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment csr embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment csr embeddedsw.configuration.isPrintableDevice 0
#
# connection point dma
#
add_interface dma avalon start
set_interface_property dma addressUnits SYMBOLS
set_interface_property dma associatedClock clock
set_interface_property dma associatedReset reset
set_interface_property dma bitsPerSymbol 8
set_interface_property dma burstOnBurstBoundariesOnly false
set_interface_property dma burstcountUnits WORDS
set_interface_property dma doStreamReads false
set_interface_property dma doStreamWrites false
set_interface_property dma holdTime 0
set_interface_property dma linewrapBursts false
set_interface_property dma maximumPendingReadTransactions 0
set_interface_property dma maximumPendingWriteTransactions 0
set_interface_property dma readLatency 0
set_interface_property dma readWaitTime 1
set_interface_property dma setupTime 0
set_interface_property dma timingUnits Cycles
set_interface_property dma writeWaitTime 0
set_interface_property dma ENABLED true
set_interface_property dma EXPORT_OF ""
set_interface_property dma PORT_NAME_MAP ""
set_interface_property dma CMSIS_SVD_VARIABLES ""
set_interface_property dma SVD_ADDRESS_GROUP ""
add_interface_port dma am_address address Output 32
add_interface_port dma am_burstcount burstcount Output 11
add_interface_port dma am_read read Output 1
add_interface_port dma am_readdata readdata Input 128
add_interface_port dma am_readdatavalid readdatavalid Input 1
add_interface_port dma am_waitrequest waitrequest Input 1
#
# connection point video_out
#
add_interface video_out avalon_streaming start
set_interface_property video_out associatedClock pixclk
set_interface_property video_out associatedReset reset
set_interface_property video_out dataBitsPerSymbol 24
set_interface_property video_out errorDescriptor ""
set_interface_property video_out firstSymbolInHighOrderBits true
set_interface_property video_out maxChannel 0
set_interface_property video_out readyLatency 0
set_interface_property video_out ENABLED true
set_interface_property video_out EXPORT_OF ""
set_interface_property video_out PORT_NAME_MAP ""
set_interface_property video_out CMSIS_SVD_VARIABLES ""
set_interface_property video_out SVD_ADDRESS_GROUP ""
add_interface_port video_out src_data data Output 24
add_interface_port video_out src_valid valid Output 1
add_interface_port video_out src_ready ready Input 1
#
# connection point sync
#
add_interface sync conduit end
set_interface_property sync associatedClock clock
set_interface_property sync associatedReset ""
set_interface_property sync ENABLED true
set_interface_property sync EXPORT_OF ""
set_interface_property sync PORT_NAME_MAP ""
set_interface_property sync CMSIS_SVD_VARIABLES ""
set_interface_property sync SVD_ADDRESS_GROUP ""
add_interface_port sync frame_sync frame_sync Input 1
#
# connection point pixclk
#
add_interface pixclk clock end
set_interface_property pixclk clockRate 0
set_interface_property pixclk ENABLED true
set_interface_property pixclk EXPORT_OF ""
set_interface_property pixclk PORT_NAME_MAP ""
set_interface_property pixclk CMSIS_SVD_VARIABLES ""
set_interface_property pixclk SVD_ADDRESS_GROUP ""
add_interface_port pixclk pixclk clk Input 1

358
cs309-psoc/lab_4_0/hw/hdl/displays/vga_sequencer/hdl/vga_sequencer.vhd Normal file
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--+--------+------------+-------------------------------------------------------------------+
--| Offset | Name | Description |
--+--------+------------+-------------------------------------------------------------------+
--| 0x0 | CSR | [0] Enable/Disable |
--| 0x1 | HBP | [15..0] Horizontal Back Porch (in DCLK) |
--| 0x2 | HFP | [15..0] Horizontal Front Porch (in DCLK) |
--| 0x3 | VBP | [15..0] Vertical Back Porch (in # lines) |
--| 0x4 | VFP | [15..0] Vertical Front Porch (in # lines) |
--| 0x5 | HDATA | [15..0] Horizontal data (in DCLK) |
--| 0x6 | VDATA | [15..0] [15..0] Vertical data (in # lines) |
--| 0x7 | HSync | [15..0] HSync width (in DCLK) |
--| 0x8 | Vsync | [15..0] VSync width (in # lines) |
--+--------+------------+-------------------------------------------------------------------+
--
-- As usual, the horizontal timings are specified in number of data clock
-- cycles, and the vertical timings are specified in number of lines.
--
-- For naming conventions, please refer to the following diagram:
-- +----------------------------------------------------------------------------------------------+-----
-- | A | B | C | D | ...
-- +----------------------------------------------------------------------------------------------+-----
-- --+ +------------------------------------------------------------------------------------------+ +-
-- | | | |
-- +---+ +---+
--
-- A is the pulse width
-- B is the back porch
-- C is the valid data
-- D is the front porch
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_sequencer is
generic (
HBP_DEFAULT : positive := 12;
HFP_DEFAULT : positive := 18;
VBP_DEFAULT : positive := 8;
VFP_DEFAULT : positive := 20;
HDATA_DEFAULT : positive := 240;
VDATA_DEFAULT : positive := 320;
HSYNC_DEFAULT : positive := 2;
VSYNC_DEFAULT : positive := 7);
port (
pixclk : in std_logic; -- A copy of the pixclk from the PLL
clk : in std_logic; -- The clock of the bus
reset : in std_logic;
-- Avalon-MM CSR Interface
address : in std_logic_vector(4 downto 0);
read, write : in std_logic;
readdata : out std_logic_vector(31 downto 0);
writedata : in std_logic_vector(31 downto 0);
-- Avalon-ST sink Interface
sink_data : in std_logic_vector(23 downto 0);
sink_valid : in std_logic;
sink_ready : out std_logic;
-- TFT Interface
r : out std_logic_vector(7 downto 0);
g : out std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0);
hsync : out std_logic;
vsync : out std_logic;
de : out std_logic;
-- Indicates when we enter the front porch of the vertical sync.
-- Used to flush the FIFO and restart reading the frame in memory.
frame_sync : out std_logic);
end entity vga_sequencer;
architecture rtl of vga_sequencer is
-- Both counters should be able to count up to the addition of any four 16-bit numbers.
signal horizontal_counter, horizontal_max : unsigned(19 downto 0);
constant HORIZONTAL_COUNTER_RESET : unsigned(horizontal_counter'range) := to_unsigned(1, horizontal_counter'length);
signal vertical_counter, vertical_max : unsigned(19 downto 0);
constant VERTICAL_COUNTER_RESET : unsigned(horizontal_counter'range) := to_unsigned(1, horizontal_counter'length);
-- Registers
signal hbp, hfp, vbp, vfp, hdata_width, vdata_width, hsync_width, vsync_width : unsigned(15 downto 0);
signal enabled : boolean;
-- Output registers
signal i_r : std_logic_vector(7 downto 0);
signal i_g : std_logic_vector(7 downto 0);
signal i_b : std_logic_vector(7 downto 0);
signal i_hsync : std_logic;
signal i_vsync : std_logic;
signal i_de : std_logic;
-- couting becomes true whenever enabled is true and sink_valid='1'
signal counting : boolean;
constant CSR_REG_OFST : unsigned(address'range) := to_unsigned(0, address'length);
constant HBP_REG_OFST : unsigned(address'range) := to_unsigned(1, address'length);
constant HFP_REG_OFST : unsigned(address'range) := to_unsigned(2, address'length);
constant VBP_REG_OFST : unsigned(address'range) := to_unsigned(3, address'length);
constant VFP_REG_OFST : unsigned(address'range) := to_unsigned(4, address'length);
constant HDATA_REG_OFST : unsigned(address'range) := to_unsigned(5, address'length);
constant VDATA_REG_OFST : unsigned(address'range) := to_unsigned(6, address'length);
constant HSYNC_REG_OFST : unsigned(address'range) := to_unsigned(7, address'length);
constant VSYNC_REG_OFST : unsigned(address'range) := to_unsigned(8, address'length);
begin
p_csr_write : process (clk, reset)
begin
if reset = '1' then
enabled <= false;
hbp <= to_unsigned(HBP_DEFAULT, hbp'length);
hfp <= to_unsigned(HFP_DEFAULT, hfp'length);
vbp <= to_unsigned(VBP_DEFAULT, vbp'length);
vfp <= to_unsigned(VFP_DEFAULT, vfp'length);
hdata_width <= to_unsigned(HDATA_DEFAULT, hdata_width'length);
vdata_width <= to_unsigned(VDATA_DEFAULT, vdata_width'length);
hsync_width <= to_unsigned(HSYNC_DEFAULT, hsync_width'length);
vsync_width <= to_unsigned(VSYNC_DEFAULT, vsync_width'length);
elsif rising_edge(clk) then
if write = '1' then
case unsigned(address) is
-- Status
when CSR_REG_OFST =>
if writedata(0) = '1' then
enabled <= true;
else
enabled <= false;
end if;
-- HBP
when HBP_REG_OFST =>
hbp <= unsigned(writedata(15 downto 0));
-- HFP
when HFP_REG_OFST =>
hfp <= unsigned(writedata(15 downto 0));
-- VBP
when VBP_REG_OFST =>
vbp <= unsigned(writedata(15 downto 0));
-- VFP
when VFP_REG_OFST =>
vfp <= unsigned(writedata(15 downto 0));
-- HDATA
when HDATA_REG_OFST =>
hdata_width <= unsigned(writedata(15 downto 0));
-- VDATA
when VDATA_REG_OFST =>
vdata_width <= unsigned(writedata(15 downto 0));
-- HSYNC
when HSYNC_REG_OFST =>
hsync_width <= unsigned(writedata(15 downto 0));
-- VSYNC
when VSYNC_REG_OFST =>
vsync_width <= unsigned(writedata(15 downto 0));
when others => null;
end case;
end if;
end if;
end process p_csr_write;
p_csr_read : process (clk, reset)
begin
if reset = '1' then
readdata <= (others => '0');
elsif rising_edge(clk) then
readdata <= (others => '0');
if read = '1' then
case unsigned(address) is
-- Status
when CSR_REG_OFST =>
readdata <= (others => '0');
if enabled then
readdata(0) <= '1';
end if;
-- HBP
when HBP_REG_OFST =>
readdata(15 downto 0) <= std_logic_vector(hbp);
-- HFP
when HFP_REG_OFST =>
readdata(15 downto 0) <= std_logic_vector(hfp);
-- VBP
when VBP_REG_OFST =>
readdata(15 downto 0) <= std_logic_vector(vbp);
-- VFP
when VFP_REG_OFST =>
readdata(15 downto 0) <= std_logic_vector(vfp);
-- HDATA
when HDATA_REG_OFST =>
readdata(15 downto 0) <= std_logic_vector(hdata_width);
-- VDATA
when VDATA_REG_OFST =>
readdata(15 downto 0) <= std_logic_vector(vdata_width);
-- HSYNC
when HSYNC_REG_OFST =>
readdata(15 downto 0) <= std_logic_vector(hsync_width);
-- VSYNC
when VSYNC_REG_OFST =>
readdata(15 downto 0) <= std_logic_vector(vsync_width);
when others => null;
end case;
end if;
end if;
end process p_csr_read;
horizontal_max <=
resize(hsync_width, horizontal_max 'length) +
resize(hbp, horizontal_max'length) +
resize(hdata_width, horizontal_max'length) +
resize(hfp, horizontal_max'length);
vertical_max <=
resize(vsync_width, horizontal_max 'length) +
resize(vbp, horizontal_max'length) +
resize(vdata_width, horizontal_max'length) +
resize(vfp, horizontal_max'length);
p_cnt_trigger : process (pixclk, reset)
begin
if reset = '1' then
counting <= false;
elsif rising_edge(pixclk) then
if enabled and sink_valid = '1' then
counting <= true;
elsif not enabled then
counting <= false;
end if;
end if;
end process p_cnt_trigger;
p_horizontal_count : process (pixclk, reset)
begin
if reset = '1' then
horizontal_counter <= HORIZONTAL_COUNTER_RESET;
elsif rising_edge(pixclk) then
horizontal_counter <= HORIZONTAL_COUNTER_RESET;
if counting and horizontal_counter < horizontal_max then
horizontal_counter <= horizontal_counter + 1;
end if;
end if;
end process p_horizontal_count;
p_vertical_count : process (pixclk, reset)
begin
if reset = '1' then
vertical_counter <= VERTICAL_COUNTER_RESET;
elsif rising_edge(pixclk) then
if counting then
if horizontal_counter = horizontal_max then
if vertical_counter < vertical_max then
vertical_counter <= vertical_counter + 1;
else
vertical_counter <= VERTICAL_COUNTER_RESET;
end if;
end if;
else
vertical_counter <= VERTICAL_COUNTER_RESET;
end if;
end if;
end process p_vertical_count;
p_hsync_vsync_gen : process (counting, horizontal_counter, hsync_width,
vertical_counter, vsync_width)
begin
-- HSYNC generation
i_hsync <= '1';
if horizontal_counter <= hsync_width then
i_hsync <= '0';
end if;
-- VSYNC generation
i_vsync <= '1';
if vertical_counter <= vsync_width then
i_vsync <= '0';
end if;
if not counting then
i_vsync <= '1';
i_hsync <= '1';
end if;
end process p_hsync_vsync_gen;
p_rgb_out : process (hbp, hdata_width, horizontal_counter, hsync_width,
sink_data, vbp, vdata_width, vertical_counter,
vsync_width)
begin
i_r <= (others => '0');
i_g <= (others => '0');
i_b <= (others => '0');
i_de <= '0';
sink_ready <= '0';
frame_sync <= '0';
if
vertical_counter > (resize(vsync_width, vertical_counter'length) + resize(vbp, vertical_counter'length)) and
vertical_counter <= (resize(vsync_width, vertical_counter'length) + resize(vbp, vertical_counter'length) + resize(vdata_width, vertical_counter'length)) and
horizontal_counter > (resize(hsync_width, horizontal_counter'length) + resize(hbp, horizontal_counter'length)) and
horizontal_counter <= (resize(hsync_width, horizontal_counter'length) + resize(hbp, horizontal_counter'length) + resize(hdata_width, horizontal_counter'length))
then
i_de <= '1';
i_r <= sink_data(23 downto 16);
i_g <= sink_data(15 downto 8);
i_b <= sink_data(7 downto 0);
sink_ready <= '1';
end if;
if
vertical_counter > (resize(vsync_width, vertical_counter'length) + resize(vbp, vertical_counter'length) + resize(vdata_width, vertical_counter'length))
then
frame_sync <= '1';
end if;
end process p_rgb_out;
p_output_reg : process (pixclk, reset)
begin
if reset = '1' then
r <= (others => '0');
g <= (others => '0');
b <= (others => '0');
de <= '0';
hsync <= '1';
vsync <= '1';
elsif rising_edge(pixclk) then
de <= i_de;
r <= i_r;
g <= i_g;
b <= i_b;
vsync <= i_vsync;
hsync <= i_hsync;
end if;
end process;
end architecture rtl;

247
cs309-psoc/lab_4_0/hw/hdl/displays/vga_sequencer/hdl/vga_sequencer_hw.tcl Normal file
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# TCL File Generated by Component Editor 16.0
# Sun Feb 05 18:18:28 CET 2017
# DO NOT MODIFY
#
# vga_sequencer "vga_sequencer" v1.0
# 2017.02.05.18:18:28
#
#
#
# request TCL package from ACDS 16.0
#
package require -exact qsys 16.0
#
# module vga_sequencer
#
set_module_property DESCRIPTION ""
set_module_property NAME vga_sequencer
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP LCD
set_module_property AUTHOR "Philemon Favrod"
set_module_property DISPLAY_NAME vga_sequencer
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL vga_sequencer
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file vga_sequencer.vhd VHDL PATH vga_sequencer.vhd TOP_LEVEL_FILE
#
# parameters
#
add_parameter HBP_DEFAULT POSITIVE 12
set_parameter_property HBP_DEFAULT DEFAULT_VALUE 12
set_parameter_property HBP_DEFAULT DISPLAY_NAME HBP_DEFAULT
set_parameter_property HBP_DEFAULT TYPE POSITIVE
set_parameter_property HBP_DEFAULT UNITS None
set_parameter_property HBP_DEFAULT ALLOWED_RANGES 1:2147483647
set_parameter_property HBP_DEFAULT HDL_PARAMETER true
add_parameter HFP_DEFAULT POSITIVE 18
set_parameter_property HFP_DEFAULT DEFAULT_VALUE 18
set_parameter_property HFP_DEFAULT DISPLAY_NAME HFP_DEFAULT
set_parameter_property HFP_DEFAULT TYPE POSITIVE
set_parameter_property HFP_DEFAULT UNITS None
set_parameter_property HFP_DEFAULT ALLOWED_RANGES 1:2147483647
set_parameter_property HFP_DEFAULT HDL_PARAMETER true
add_parameter VBP_DEFAULT POSITIVE 8
set_parameter_property VBP_DEFAULT DEFAULT_VALUE 8
set_parameter_property VBP_DEFAULT DISPLAY_NAME VBP_DEFAULT
set_parameter_property VBP_DEFAULT TYPE POSITIVE
set_parameter_property VBP_DEFAULT UNITS None
set_parameter_property VBP_DEFAULT ALLOWED_RANGES 1:2147483647
set_parameter_property VBP_DEFAULT HDL_PARAMETER true
add_parameter VFP_DEFAULT POSITIVE 20
set_parameter_property VFP_DEFAULT DEFAULT_VALUE 20
set_parameter_property VFP_DEFAULT DISPLAY_NAME VFP_DEFAULT
set_parameter_property VFP_DEFAULT TYPE POSITIVE
set_parameter_property VFP_DEFAULT UNITS None
set_parameter_property VFP_DEFAULT ALLOWED_RANGES 1:2147483647
set_parameter_property VFP_DEFAULT HDL_PARAMETER true
add_parameter HDATA_DEFAULT POSITIVE 240
set_parameter_property HDATA_DEFAULT DEFAULT_VALUE 240
set_parameter_property HDATA_DEFAULT DISPLAY_NAME HDATA_DEFAULT
set_parameter_property HDATA_DEFAULT TYPE POSITIVE
set_parameter_property HDATA_DEFAULT UNITS None
set_parameter_property HDATA_DEFAULT ALLOWED_RANGES 1:2147483647
set_parameter_property HDATA_DEFAULT HDL_PARAMETER true
add_parameter VDATA_DEFAULT POSITIVE 320
set_parameter_property VDATA_DEFAULT DEFAULT_VALUE 320
set_parameter_property VDATA_DEFAULT DISPLAY_NAME VDATA_DEFAULT
set_parameter_property VDATA_DEFAULT TYPE POSITIVE
set_parameter_property VDATA_DEFAULT UNITS None
set_parameter_property VDATA_DEFAULT ALLOWED_RANGES 1:2147483647
set_parameter_property VDATA_DEFAULT HDL_PARAMETER true
add_parameter HSYNC_DEFAULT POSITIVE 2
set_parameter_property HSYNC_DEFAULT DEFAULT_VALUE 2
set_parameter_property HSYNC_DEFAULT DISPLAY_NAME HSYNC_DEFAULT
set_parameter_property HSYNC_DEFAULT TYPE POSITIVE
set_parameter_property HSYNC_DEFAULT UNITS None
set_parameter_property HSYNC_DEFAULT ALLOWED_RANGES 1:2147483647
set_parameter_property HSYNC_DEFAULT HDL_PARAMETER true
add_parameter VSYNC_DEFAULT POSITIVE 7
set_parameter_property VSYNC_DEFAULT DEFAULT_VALUE 7
set_parameter_property VSYNC_DEFAULT DISPLAY_NAME VSYNC_DEFAULT
set_parameter_property VSYNC_DEFAULT TYPE POSITIVE
set_parameter_property VSYNC_DEFAULT UNITS None
set_parameter_property VSYNC_DEFAULT ALLOWED_RANGES 1:2147483647
set_parameter_property VSYNC_DEFAULT HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1
#
# connection point csr
#
add_interface csr avalon end
set_interface_property csr addressUnits WORDS
set_interface_property csr associatedClock clock
set_interface_property csr associatedReset reset
set_interface_property csr bitsPerSymbol 8
set_interface_property csr burstOnBurstBoundariesOnly false
set_interface_property csr burstcountUnits WORDS
set_interface_property csr explicitAddressSpan 0
set_interface_property csr holdTime 0
set_interface_property csr linewrapBursts false
set_interface_property csr maximumPendingReadTransactions 0
set_interface_property csr maximumPendingWriteTransactions 0
set_interface_property csr readLatency 0
set_interface_property csr readWaitTime 1
set_interface_property csr setupTime 0
set_interface_property csr timingUnits Cycles
set_interface_property csr writeWaitTime 0
set_interface_property csr ENABLED true
set_interface_property csr EXPORT_OF ""
set_interface_property csr PORT_NAME_MAP ""
set_interface_property csr CMSIS_SVD_VARIABLES ""
set_interface_property csr SVD_ADDRESS_GROUP ""
add_interface_port csr address address Input 5
add_interface_port csr read read Input 1
add_interface_port csr write write Input 1
add_interface_port csr readdata readdata Output 32
add_interface_port csr writedata writedata Input 32
set_interface_assignment csr embeddedsw.configuration.isFlash 0
set_interface_assignment csr embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment csr embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment csr embeddedsw.configuration.isPrintableDevice 0
#
# connection point out
#
add_interface out conduit end
set_interface_property out associatedClock clock
set_interface_property out associatedReset ""
set_interface_property out ENABLED true
set_interface_property out EXPORT_OF ""
set_interface_property out PORT_NAME_MAP ""
set_interface_property out CMSIS_SVD_VARIABLES ""
set_interface_property out SVD_ADDRESS_GROUP ""
add_interface_port out hsync hsync Output 1
add_interface_port out g g Output 8
add_interface_port out b b Output 8
add_interface_port out de de Output 1
add_interface_port out vsync vsync Output 1
add_interface_port out r r Output 8
#
# connection point in
#
add_interface in avalon_streaming end
set_interface_property in associatedClock pixclk
set_interface_property in associatedReset reset
set_interface_property in dataBitsPerSymbol 24
set_interface_property in errorDescriptor ""
set_interface_property in firstSymbolInHighOrderBits true
set_interface_property in maxChannel 0
set_interface_property in readyLatency 0
set_interface_property in ENABLED true
set_interface_property in EXPORT_OF ""
set_interface_property in PORT_NAME_MAP ""
set_interface_property in CMSIS_SVD_VARIABLES ""
set_interface_property in SVD_ADDRESS_GROUP ""
add_interface_port in sink_ready ready Output 1
add_interface_port in sink_valid valid Input 1
add_interface_port in sink_data data Input 24
#
# connection point pixclk
#
add_interface pixclk clock end
set_interface_property pixclk clockRate 0
set_interface_property pixclk ENABLED true
set_interface_property pixclk EXPORT_OF ""
set_interface_property pixclk PORT_NAME_MAP ""
set_interface_property pixclk CMSIS_SVD_VARIABLES ""
set_interface_property pixclk SVD_ADDRESS_GROUP ""
add_interface_port pixclk pixclk clk Input 1
#
# connection point frame_sync
#
add_interface frame_sync conduit end
set_interface_property frame_sync associatedClock clock
set_interface_property frame_sync associatedReset ""
set_interface_property frame_sync ENABLED true
set_interface_property frame_sync EXPORT_OF ""
set_interface_property frame_sync PORT_NAME_MAP ""
set_interface_property frame_sync CMSIS_SVD_VARIABLES ""
set_interface_property frame_sync SVD_ADDRESS_GROUP ""
add_interface_port frame_sync frame_sync frame_sync Output 1