Disabled external gits
This commit is contained in:
@@ -0,0 +1,172 @@
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-- #############################################################################
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-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
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--
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-- BOARD : PrSoC extension board for DE0-Nano-SoC
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-- Author : Florian Depraz based on Sahand Kashani-Akhavan work
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-- Revision : 1.1
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-- Creation date : 06/02/2016
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--
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-- Syntax Rule : GROUP_NAME_N[bit]
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--
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-- GROUP : specify a particular interface (ex: SDR_)
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-- NAME : signal name (ex: CONFIG, D, ...)
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-- bit : signal index
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-- _N : to specify an active-low signal
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-- #############################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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entity DE0_Nano_SoC_PrSoC_extn_board_top_level is
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port(
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-------------------------------
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-- Comment ALL unused ports. --
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-------------------------------
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-- CLOCK
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FPGA_CLK1_50 : in std_logic;
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-- FPGA_CLK2_50 : in std_logic;
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-- FPGA_CLK3_50 : in std_logic;
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-- KEY on DE0 Nano SoC
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KEY_N : in std_logic_vector(1 downto 0);
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-- LEDs on DE0 Nano SoC
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-- LED : out std_logic_vector(7 downto 0);
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-- SWITCHES on DE0 Nano SoC
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-- SW : in std_logic_vector(3 downto 0);
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-- Servomotors pwm
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SERVO_0 : out std_logic;
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SERVO_1 : out std_logic;
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-- ADC Joysticks
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J0_SPI_CS_n : out std_logic;
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J0_SPI_MOSI : out std_logic;
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J0_SPI_MISO : in std_logic;
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J0_SPI_CLK : out std_logic;
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-- Lepton
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CAM_TH_SPI_CS_N : out std_logic;
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CAM_TH_MISO : in std_logic;
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CAM_TH_MOSI : out std_logic;
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CAM_TH_CLK : out std_logic;
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-- PCA9637
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-- PIO_SCL : inout std_logic;
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-- PIO_SDA : inout std_logic;
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-- PIO_INT_N : in std_logic;
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-- RESET_N : out std_logic;
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-- OV7670
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-- CAM_D : in std_logic_vector(9 downto 0);
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-- CAM_PIX_CLK : in std_logic;
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-- CAM_LV : in std_logic;
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-- CAM_FV : in std_logic;
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-- CAM_SYS_CLK : out std_logic;
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-- VGA and LCD shared signals
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-- VIDEO_CLK : out std_logic;
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-- VIDEO_VSYNC : out std_logic;
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-- VIDEO_HSYNC : out std_logic;
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-- VIDEO_B : out std_logic_vector(7 downto 0);
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-- VIDEO_G : out std_logic_vector(7 downto 0);
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-- VIDEO_R : out std_logic_vector(7 downto 0);
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-- LCD Specific signals
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-- LCD_DE : out std_logic;
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-- LCD_PIN_DAV_N : ? ?? std_logic;
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-- LCD_DISPLAY_EN : out std_logic;
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-- SPI_MISO : in std_logic;
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-- SPI_ENA_N : out std_logic;
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-- SPI_CLK : out std_logic;
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-- SPI_MOSI : out std_logic;
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-- SPI_DAT : inout std_logic;
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-- I2C TOUCH SCREEN
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-- TS_SCL : inout std_logic;
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-- TS_SDA : inout std_logic;
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-- BLUETOOTH (BLE)
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-- BLT_TXD : in std_logic;
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-- BLT_RXD : out std_logic;
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-- I2C For VGA, PAL and OV7670 cameras
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-- CAM_PAL_VGA_SDA : inout std_logic;
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-- CAM_PAL_VGA_SCL : inout std_logic;
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-- ONE WIRE
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-- BOARD_ID : inout std_logic;
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-- PAL Camera
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-- PAL_VD_VD : in std_logic_vector(7 downto 0);
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-- PAL_VD_VSO : in std_logic;
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-- PAL_VD_HSO : in std_logic;
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-- PAL_VD_CLKO : in std_logic;
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-- PAL_PWDN : out std_logic;
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-- WIFI
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-- FROM_ESP_TXD : in std_logic;
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-- TO_ESP_RXD : out std_logic;
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-- LED RGB
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-- LED_BGR : out std_logic;
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-- HPS
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HPS_CONV_USB_N : inout std_logic;
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HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
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HPS_DDR3_BA : out std_logic_vector(2 downto 0);
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HPS_DDR3_CAS_N : out std_logic;
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HPS_DDR3_CK_N : out std_logic;
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HPS_DDR3_CK_P : out std_logic;
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HPS_DDR3_CKE : out std_logic;
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HPS_DDR3_CS_N : out std_logic;
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HPS_DDR3_DM : out std_logic_vector(3 downto 0);
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HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
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HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
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HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
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HPS_DDR3_ODT : out std_logic;
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HPS_DDR3_RAS_N : out std_logic;
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HPS_DDR3_RESET_N : out std_logic;
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HPS_DDR3_RZQ : in std_logic;
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HPS_DDR3_WE_N : out std_logic;
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HPS_ENET_GTX_CLK : out std_logic;
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HPS_ENET_INT_N : inout std_logic;
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HPS_ENET_MDC : out std_logic;
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HPS_ENET_MDIO : inout std_logic;
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HPS_ENET_RX_CLK : in std_logic;
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HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
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HPS_ENET_RX_DV : in std_logic;
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HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
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HPS_ENET_TX_EN : out std_logic;
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HPS_GSENSOR_INT : inout std_logic;
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HPS_I2C0_SCLK : inout std_logic;
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HPS_I2C0_SDAT : inout std_logic;
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HPS_I2C1_SCLK : inout std_logic;
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HPS_I2C1_SDAT : inout std_logic;
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HPS_KEY_N : inout std_logic;
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HPS_LED : inout std_logic;
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HPS_LTC_GPIO : inout std_logic;
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HPS_SD_CLK : out std_logic;
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HPS_SD_CMD : inout std_logic;
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HPS_SD_DATA : inout std_logic_vector(3 downto 0);
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HPS_SPIM_CLK : out std_logic;
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HPS_SPIM_MISO : in std_logic;
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HPS_SPIM_MOSI : out std_logic;
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HPS_SPIM_SS : inout std_logic;
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HPS_UART_RX : in std_logic;
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HPS_UART_TX : out std_logic;
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HPS_USB_CLKOUT : in std_logic;
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HPS_USB_DATA : inout std_logic_vector(7 downto 0);
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HPS_USB_DIR : in std_logic;
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HPS_USB_NXT : in std_logic;
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HPS_USB_STP : out std_logic
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);
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end entity DE0_Nano_SoC_PrSoC_extn_board_top_level;
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architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is
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begin
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end;
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138
cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204.vhd
Normal file
138
cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204.vhd
Normal file
@@ -0,0 +1,138 @@
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-- #############################################################################
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-- mcp3204.vhd
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-- ===========
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-- MCP3204 Avalon-MM slave interface.
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--
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-- Register map
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-- +-------+-----------+--------+------------------------------------+
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-- | RegNo | Name | Access | Description |
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-- +-------+-----------+--------+------------------------------------+
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-- | 0 | CHANNEL_0 | RO | 12-bit digital value of channel 0. |
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-- +-------+-----------+--------+------------------------------------+
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-- | 1 | CHANNEL_1 | RO | 12-bit digital value of channel 1. |
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-- +-------+-----------+--------+------------------------------------+
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-- | 2 | CHANNEL_2 | RO | 12-bit digital value of channel 2. |
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-- +-------+-----------+--------+------------------------------------+
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-- | 3 | CHANNEL_3 | RO | 12-bit digital value of channel 3. |
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-- +-------+-----------+--------+------------------------------------+
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--
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-- Author : Philémon Favrod [philemon.favrod@epfl.ch]
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-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
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-- Revision : 2
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-- Last modified : 2018-03-06
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-- #############################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity mcp3204 is
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port(
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-- Avalon Clock interface
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clk : in std_logic;
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-- Avalon Reset interface
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reset : in std_logic;
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-- Avalon-MM Slave interface
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address : in std_logic_vector(1 downto 0);
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read : in std_logic;
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readdata : out std_logic_vector(31 downto 0);
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-- Avalon Conduit interface
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CS_N : out std_logic;
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MOSI : out std_logic;
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MISO : in std_logic;
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SCLK : out std_logic
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);
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end entity;
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architecture arch of mcp3204 is
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constant NUM_CHANNELS : positive := 4;
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constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS))));
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type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range);
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signal data_reg : data_array;
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signal spi_busy, spi_start, spi_datavalid : std_logic;
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signal spi_channel : std_logic_vector(1 downto 0);
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signal spi_data : std_logic_vector(11 downto 0);
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type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA);
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signal state : state_t;
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signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0);
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begin
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SPI : entity work.mcp3204_spi
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port map(
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clk => clk,
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reset => reset,
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busy => spi_busy,
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start => spi_start,
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channel => spi_channel,
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data_valid => spi_datavalid,
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data => spi_data,
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SCLK => SCLK,
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CS_N => CS_N,
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MOSI => MOSI,
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MISO => MISO
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);
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-- FSM that dictates which channel is being read. The state of the component
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-- should be thought as the pair (state, channel)
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p_fsm : process(reset, clk)
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begin
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if reset = '1' then
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state <= READY;
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channel <= (others => '0');
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elsif rising_edge(clk) then
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case state is
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when READY =>
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if spi_busy = '0' then
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state <= INIT_READ_CHANNEL;
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end if;
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when INIT_READ_CHANNEL =>
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state <= WAIT_FOR_DATA;
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when WAIT_FOR_DATA =>
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if spi_datavalid = '1' then
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state <= READY;
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channel <= channel + 1;
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end if;
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end case;
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end if;
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end process p_fsm;
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-- Updates the internal registers when a new data is available
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p_data : process(reset, clk)
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begin
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if reset = '1' then
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for i in 0 to NUM_CHANNELS - 1 loop
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data_reg(i) <= (others => '0');
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end loop;
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elsif rising_edge(clk) then
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if state = WAIT_FOR_DATA and spi_datavalid = '1' then
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data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data;
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end if;
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end if;
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end process p_data;
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spi_start <= '1' when state = INIT_READ_CHANNEL else '0';
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spi_channel <= std_logic_vector(channel);
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-- Interface with the Avalon Switch Fabric
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p_avalon_read : process(reset, clk)
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begin
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if reset = '1' then
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readdata <= (others => '0');
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elsif rising_edge(clk) then
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if read = '1' then
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readdata <= data_reg(to_integer(unsigned(address)));
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end if;
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end if;
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end process p_avalon_read;
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end architecture;
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137
cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl
Normal file
137
cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204_hw.tcl
Normal file
@@ -0,0 +1,137 @@
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# TCL File Generated by Component Editor 16.0
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# Sun Feb 05 18:14:06 CET 2017
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# DO NOT MODIFY
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#
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# mcp3204 "mcp3204" v1.0
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# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.18:14:06
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# 4-Channel 12-Bit A/D Converter with SPI Serial Interface
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#
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#
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# request TCL package from ACDS 16.0
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#
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package require -exact qsys 16.0
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#
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# module mcp3204
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#
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set_module_property DESCRIPTION "4-Channel 12-Bit A/D Converter with SPI Serial Interface"
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set_module_property NAME mcp3204
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP Joystick
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set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan"
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set_module_property DISPLAY_NAME mcp3204
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL mcp3204
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file mcp3204.vhd VHDL PATH mcp3204.vhd TOP_LEVEL_FILE
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add_fileset_file mcp3204_spi.vhd VHDL PATH mcp3204_spi.vhd
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#
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# parameters
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||||
#
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||||
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||||
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||||
#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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||||
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||||
#
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# connection point reset
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||||
#
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||||
add_interface reset reset end
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||||
set_interface_property reset associatedClock clock
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set_interface_property reset synchronousEdges DEASSERT
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||||
set_interface_property reset ENABLED true
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||||
set_interface_property reset EXPORT_OF ""
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||||
set_interface_property reset PORT_NAME_MAP ""
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||||
set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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||||
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add_interface_port reset reset reset Input 1
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||||
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||||
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#
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# connection point avalon_slave_0
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||||
#
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||||
add_interface avalon_slave_0 avalon end
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||||
set_interface_property avalon_slave_0 addressUnits WORDS
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||||
set_interface_property avalon_slave_0 associatedClock clock
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||||
set_interface_property avalon_slave_0 associatedReset reset
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||||
set_interface_property avalon_slave_0 bitsPerSymbol 8
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set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
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||||
set_interface_property avalon_slave_0 burstcountUnits WORDS
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||||
set_interface_property avalon_slave_0 explicitAddressSpan 0
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||||
set_interface_property avalon_slave_0 holdTime 0
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||||
set_interface_property avalon_slave_0 linewrapBursts false
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||||
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
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||||
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
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||||
set_interface_property avalon_slave_0 readLatency 0
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||||
set_interface_property avalon_slave_0 readWaitTime 1
|
||||
set_interface_property avalon_slave_0 setupTime 0
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||||
set_interface_property avalon_slave_0 timingUnits Cycles
|
||||
set_interface_property avalon_slave_0 writeWaitTime 0
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||||
set_interface_property avalon_slave_0 ENABLED true
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||||
set_interface_property avalon_slave_0 EXPORT_OF ""
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set_interface_property avalon_slave_0 PORT_NAME_MAP ""
|
||||
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port avalon_slave_0 address address Input 2
|
||||
add_interface_port avalon_slave_0 read read Input 1
|
||||
add_interface_port avalon_slave_0 readdata readdata Output 32
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
|
||||
|
||||
|
||||
#
|
||||
# connection point conduit_end
|
||||
#
|
||||
add_interface conduit_end conduit end
|
||||
set_interface_property conduit_end associatedClock clock
|
||||
set_interface_property conduit_end associatedReset ""
|
||||
set_interface_property conduit_end ENABLED true
|
||||
set_interface_property conduit_end EXPORT_OF ""
|
||||
set_interface_property conduit_end PORT_NAME_MAP ""
|
||||
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port conduit_end CS_N cs_n Output 1
|
||||
add_interface_port conduit_end MOSI mosi Output 1
|
||||
add_interface_port conduit_end MISO miso Input 1
|
||||
add_interface_port conduit_end SCLK sclk Output 1
|
||||
|
||||
87
cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd
Normal file
87
cs309-psoc/lab_3_0/hw/hdl/joysticks/hdl/mcp3204_spi.vhd
Normal file
@@ -0,0 +1,87 @@
|
||||
-- #############################################################################
|
||||
-- mcp3204_spi.vhd
|
||||
-- ===============
|
||||
-- MCP3204 SPI interface.
|
||||
--
|
||||
-- Author : Philémon Favrod [philemon.favrod@epfl.ch]
|
||||
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
|
||||
-- Author : <insert your name> (<insert your e-mail address>)
|
||||
-- Revision : 1
|
||||
-- Last modified : <insert date>
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity mcp3204_spi is
|
||||
port(
|
||||
-- 50 MHz
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
busy : out std_logic;
|
||||
start : in std_logic;
|
||||
channel : in std_logic_vector(1 downto 0);
|
||||
data_valid : out std_logic;
|
||||
data : out std_logic_vector(11 downto 0);
|
||||
|
||||
-- 1 MHz
|
||||
SCLK : out std_logic;
|
||||
CS_N : out std_logic;
|
||||
MOSI : out std_logic;
|
||||
MISO : in std_logic
|
||||
);
|
||||
end mcp3204_spi;
|
||||
|
||||
architecture rtl of mcp3204_spi is
|
||||
signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24
|
||||
signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz
|
||||
signal reg_rising_edge_sclk : std_logic := '0';
|
||||
signal reg_falling_edge_sclk : std_logic := '0';
|
||||
|
||||
signal reg_sclk : std_logic := '0';
|
||||
|
||||
begin
|
||||
clk_divider_generation : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
reg_clk_divider_counter <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
reg_clk_divider_counter <= reg_clk_divider_counter + 1;
|
||||
reg_spi_en <= '0';
|
||||
reg_rising_edge_sclk <= '0';
|
||||
reg_falling_edge_sclk <= '0';
|
||||
|
||||
if reg_clk_divider_counter = 24 then
|
||||
reg_clk_divider_counter <= (others => '0');
|
||||
reg_spi_en <= '1';
|
||||
|
||||
if reg_sclk = '0' then
|
||||
reg_rising_edge_sclk <= '1';
|
||||
elsif reg_sclk = '1' then
|
||||
reg_falling_edge_sclk <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
SCLK_generation : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
reg_sclk <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if reg_spi_en = '1' then
|
||||
reg_sclk <= not reg_sclk;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
STATE_LOGIC : process(clk, reset)
|
||||
begin
|
||||
-- TODO: complete this process
|
||||
if reset = '1' then
|
||||
elsif rising_edge(clk) then
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture rtl;
|
||||
103
cs309-psoc/lab_3_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd
Normal file
103
cs309-psoc/lab_3_0/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd
Normal file
@@ -0,0 +1,103 @@
|
||||
-- #############################################################################
|
||||
-- tb_mcp3204_spi.vhd
|
||||
-- ==================
|
||||
-- Testbench for MCP3204 SPI interface.
|
||||
--
|
||||
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
|
||||
-- Revision : 1
|
||||
-- Last modified : 2018-03-06
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tb_mcp3204_spi is
|
||||
end entity;
|
||||
|
||||
architecture rtl of tb_mcp3204_spi is
|
||||
constant CLK_PERIOD : time := 20 ns;
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '0';
|
||||
signal sim_finished : boolean := false;
|
||||
|
||||
-- mcp3204_spi ------------------------------------------------------------
|
||||
signal busy : std_logic := '0';
|
||||
signal start : std_logic := '0';
|
||||
signal channel : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal data_valid : std_logic := '0';
|
||||
signal data : std_logic_vector(11 downto 0) := (others => '0');
|
||||
signal SCLK : std_logic := '0';
|
||||
signal CS_N : std_logic := '1';
|
||||
signal MOSI : std_logic := '0';
|
||||
signal MISO : std_logic := '0';
|
||||
|
||||
begin
|
||||
duv : entity work.mcp3204_spi
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
busy => busy,
|
||||
start => start,
|
||||
channel => channel,
|
||||
data_valid => data_valid,
|
||||
data => data,
|
||||
SCLK => SCLK,
|
||||
CS_N => CS_N,
|
||||
MOSI => MOSI,
|
||||
MISO => MISO
|
||||
);
|
||||
|
||||
clk <= not clk after CLK_PERIOD / 2 when not sim_finished;
|
||||
|
||||
sim : process
|
||||
procedure async_reset is
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
wait for CLK_PERIOD / 4;
|
||||
reset <= '1';
|
||||
|
||||
wait for CLK_PERIOD / 2;
|
||||
reset <= '0';
|
||||
end procedure async_reset;
|
||||
|
||||
procedure spi_transfer(constant channel_number : natural range 0 to 3) is
|
||||
begin
|
||||
if busy = '1' then
|
||||
wait until busy = '0';
|
||||
|
||||
else
|
||||
wait until falling_edge(clk);
|
||||
start <= '1';
|
||||
channel <= std_logic_vector(to_unsigned(channel_number, channel'length));
|
||||
|
||||
wait until falling_edge(clk);
|
||||
start <= '0';
|
||||
channel <= (others => '0');
|
||||
|
||||
wait until rising_edge(data_valid);
|
||||
wait until falling_edge(busy);
|
||||
end if;
|
||||
end procedure spi_transfer;
|
||||
|
||||
begin
|
||||
async_reset;
|
||||
|
||||
MISO <= '1';
|
||||
spi_transfer(0);
|
||||
|
||||
MISO <= '0';
|
||||
spi_transfer(1);
|
||||
|
||||
MISO <= '1';
|
||||
spi_transfer(2);
|
||||
|
||||
MISO <= '0';
|
||||
spi_transfer(3);
|
||||
|
||||
sim_finished <= true;
|
||||
wait;
|
||||
end process sim;
|
||||
end architecture rtl;
|
||||
|
||||
|
||||
139
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd
Normal file
139
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd
Normal file
@@ -0,0 +1,139 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.utils.all;
|
||||
|
||||
entity avalon_st_spi_master is
|
||||
generic(
|
||||
INPUT_CLK_FREQ : integer := 50000000;
|
||||
SPI_SCLK_FREQ : integer := 10000000;
|
||||
CPOL : integer := 1;
|
||||
CPHA : integer := 1
|
||||
);
|
||||
port(
|
||||
-- Input clock
|
||||
clk : in std_logic;
|
||||
|
||||
-- Reset
|
||||
reset : in std_logic;
|
||||
spi_cs_n : in std_logic;
|
||||
-- Sink Avalon ST Interface
|
||||
mosi_sink_data : in std_logic_vector(7 downto 0);
|
||||
mosi_sink_valid : in std_logic;
|
||||
mosi_sink_ready : out std_logic;
|
||||
|
||||
-- Source Avalon ST Interface
|
||||
miso_src_data : out std_logic_vector(7 downto 0);
|
||||
miso_src_valid : out std_logic;
|
||||
|
||||
-- SPI Master signals
|
||||
SCLK : out std_logic;
|
||||
MISO : in std_logic;
|
||||
MOSI : out std_logic;
|
||||
CS_n : out std_logic
|
||||
);
|
||||
end avalon_st_spi_master;
|
||||
|
||||
architecture rtl of avalon_st_spi_master is
|
||||
constant SCLK_PRESCALER_MAX : integer := INPUT_CLK_FREQ / SPI_SCLK_FREQ / 2;
|
||||
signal sclk_prescaler : unsigned(bitlength(SCLK_PRESCALER_MAX) downto 0);
|
||||
signal sclk_toggle : std_logic;
|
||||
|
||||
signal new_sink_buffer, cur_sink_buffer : std_logic_vector(mosi_sink_data'range);
|
||||
signal new_sink_buffer_busy, cur_sink_buffer_busy : std_logic;
|
||||
|
||||
signal miso_src_buffer : std_logic_vector(7 downto 0);
|
||||
|
||||
signal spi_done, i_sclk : std_logic;
|
||||
signal spi_bit_index : unsigned(2 downto 0);
|
||||
begin
|
||||
CS_n <= spi_cs_n;
|
||||
|
||||
p_sclk_prescaler : process(clk, reset) is
|
||||
begin
|
||||
if reset = '1' then
|
||||
sclk_prescaler <= to_unsigned(1, sclk_prescaler'length);
|
||||
elsif rising_edge(clk) then
|
||||
if sclk_prescaler = SCLK_PRESCALER_MAX then
|
||||
sclk_prescaler <= to_unsigned(1, sclk_prescaler'length);
|
||||
else
|
||||
sclk_prescaler <= sclk_prescaler + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process p_sclk_prescaler;
|
||||
sclk_toggle <= '1' when sclk_prescaler = SCLK_PRESCALER_MAX else '0';
|
||||
|
||||
p_avalon_st_sink : process(clk, reset) is
|
||||
begin
|
||||
if reset = '1' then
|
||||
new_sink_buffer_busy <= '0';
|
||||
new_sink_buffer <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if mosi_sink_valid = '1' then
|
||||
if new_sink_buffer_busy = '0' and cur_sink_buffer_busy = '1' then
|
||||
new_sink_buffer <= mosi_sink_data;
|
||||
new_sink_buffer_busy <= '1';
|
||||
end if;
|
||||
elsif new_sink_buffer_busy = '1' and cur_sink_buffer_busy = '0' then
|
||||
new_sink_buffer_busy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process p_avalon_st_sink;
|
||||
mosi_sink_ready <= not new_sink_buffer_busy;
|
||||
|
||||
p_cur_buffer : process(clk, reset) is
|
||||
begin
|
||||
if reset = '1' then
|
||||
cur_sink_buffer <= (others => '0');
|
||||
cur_sink_buffer_busy <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if mosi_sink_valid = '1' and cur_sink_buffer_busy = '0' then
|
||||
cur_sink_buffer <= mosi_sink_data;
|
||||
cur_sink_buffer_busy <= '1';
|
||||
elsif cur_sink_buffer_busy = '0' and new_sink_buffer_busy = '1' then
|
||||
cur_sink_buffer <= new_sink_buffer;
|
||||
cur_sink_buffer_busy <= '1';
|
||||
elsif cur_sink_buffer_busy = '1' and spi_done = '1' then
|
||||
cur_sink_buffer_busy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process p_cur_buffer;
|
||||
|
||||
p_spi : process(clk, reset) is
|
||||
begin
|
||||
if reset = '1' then
|
||||
spi_done <= '0';
|
||||
i_sclk <= to_unsigned(CPOL, 1)(0);
|
||||
spi_bit_index <= "000";
|
||||
MOSI <= '0';
|
||||
miso_src_data <= (others => '0');
|
||||
miso_src_valid <= '0';
|
||||
miso_src_buffer <= (others => '0');
|
||||
|
||||
elsif rising_edge(clk) then
|
||||
spi_done <= '0';
|
||||
miso_src_valid <= '0';
|
||||
if cur_sink_buffer_busy = '1' and sclk_toggle = '1' then
|
||||
if i_sclk /= to_unsigned(CPHA, 1)(0) then
|
||||
if spi_bit_index = "111" then
|
||||
spi_done <= '1';
|
||||
spi_bit_index <= "000";
|
||||
miso_src_valid <= '1';
|
||||
miso_src_data <= miso_src_buffer(7 downto 1) & MISO;
|
||||
else
|
||||
MOSI <= cur_sink_buffer(7 - to_integer(spi_bit_index));
|
||||
miso_src_buffer(7 - to_integer(spi_bit_index)) <= MISO;
|
||||
spi_bit_index <= spi_bit_index + 1;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
i_sclk <= not i_sclk;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process p_spi;
|
||||
SCLK <= i_sclk;
|
||||
|
||||
end rtl;
|
||||
87
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/byte2pix.vhd
Normal file
87
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/byte2pix.vhd
Normal file
@@ -0,0 +1,87 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Title : Byte stream to pixel converter for the Lepton Camera
|
||||
-- Project : PrSoC
|
||||
-------------------------------------------------------------------------------
|
||||
-- File : byte2pix.vhd
|
||||
-- Author : Philemon Orphee Favrod <pofavrod@lappc5.epfl.ch>
|
||||
-- Company :
|
||||
-- Created : 2016-03-21
|
||||
-- Last update: 2017-03-19
|
||||
-- Platform :
|
||||
-- Standard : VHDL'87
|
||||
-------------------------------------------------------------------------------
|
||||
-- Description: Converts a byte stream to a 14-bit pixel stream.
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright (c) 2016
|
||||
-------------------------------------------------------------------------------
|
||||
-- Revisions :
|
||||
-- Date Version Author Description
|
||||
-- 2016-03-21 1.0 pofavrod Created
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity byte2pix is
|
||||
port(
|
||||
clk, reset : in std_logic;
|
||||
byte_data : in std_logic_vector(7 downto 0);
|
||||
byte_valid : in std_logic;
|
||||
byte_sof : in std_logic;
|
||||
byte_eof : in std_logic;
|
||||
pix_data : out std_logic_vector(13 downto 0);
|
||||
pix_valid : out std_logic;
|
||||
pix_sof : out std_logic;
|
||||
pix_eof : out std_logic);
|
||||
|
||||
end byte2pix;
|
||||
|
||||
architecture rtl of byte2pix is
|
||||
signal last_sof : std_logic;
|
||||
signal msb : std_logic_vector(5 downto 0);
|
||||
signal cnt : std_logic; -- used to skip msb sampling every other time
|
||||
begin
|
||||
process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
msb <= (others => '0');
|
||||
cnt <= '0';
|
||||
last_sof <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if byte_valid = '1' then
|
||||
if cnt = '0' then
|
||||
msb <= byte_data(5 downto 0);
|
||||
last_sof <= byte_sof;
|
||||
end if;
|
||||
cnt <= not cnt;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
pix_data <= (others => '0');
|
||||
pix_valid <= '0';
|
||||
pix_sof <= '0';
|
||||
pix_eof <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
pix_data <= (others => '0');
|
||||
pix_valid <= '0';
|
||||
pix_sof <= '0';
|
||||
pix_eof <= '0';
|
||||
|
||||
if byte_valid = '1' then
|
||||
if cnt = '1' then
|
||||
pix_data <= msb & byte_data;
|
||||
pix_valid <= '1';
|
||||
pix_sof <= last_sof;
|
||||
pix_eof <= byte_eof;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture rtl;
|
||||
192
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd
Normal file
192
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/dual_ported_ram.vhd
Normal file
@@ -0,0 +1,192 @@
|
||||
-- megafunction wizard: %RAM: 2-PORT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altsyncram
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: dual_ported_ram.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altsyncram
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
--the Altera MegaCore Function License Agreement, or other
|
||||
--applicable license agreement, including, without limitation,
|
||||
--that your use is for the sole purpose of programming logic
|
||||
--devices manufactured by Altera and sold by Altera or its
|
||||
--authorized distributors. Please refer to the applicable
|
||||
--agreement for further details.
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
library altera_mf;
|
||||
use altera_mf.altera_mf_components.all;
|
||||
|
||||
entity dual_ported_ram is
|
||||
port(
|
||||
clock : in std_logic := '1';
|
||||
data : in std_logic_vector(15 downto 0);
|
||||
rdaddress : in std_logic_vector(12 downto 0);
|
||||
wraddress : in std_logic_vector(12 downto 0);
|
||||
wren : in std_logic := '0';
|
||||
q : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end dual_ported_ram;
|
||||
|
||||
architecture SYN of dual_ported_ram is
|
||||
signal sub_wire0 : std_logic_vector(15 downto 0);
|
||||
|
||||
begin
|
||||
q <= sub_wire0(15 downto 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
generic map(
|
||||
address_aclr_b => "NONE",
|
||||
address_reg_b => "CLOCK0",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_input_b => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
intended_device_family => "Cyclone V",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 8192,
|
||||
numwords_b => 8192,
|
||||
operation_mode => "DUAL_PORT",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_b => "CLOCK0",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_mixed_ports => "DONT_CARE",
|
||||
widthad_a => 13,
|
||||
widthad_b => 13,
|
||||
width_a => 16,
|
||||
width_b => 16,
|
||||
width_byteena_a => 1
|
||||
)
|
||||
port map(
|
||||
address_a => wraddress,
|
||||
address_b => rdaddress,
|
||||
clock0 => clock,
|
||||
data_a => data,
|
||||
wren_a => wren,
|
||||
q_b => sub_wire0
|
||||
);
|
||||
|
||||
end SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
||||
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
|
||||
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
|
||||
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
|
||||
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
|
||||
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
|
||||
-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]"
|
||||
-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]"
|
||||
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
|
||||
-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
|
||||
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
288
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton.vhd
Normal file
288
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton.vhd
Normal file
@@ -0,0 +1,288 @@
|
||||
-- Lepton Avalon Memory-Mapped Slave Interface
|
||||
-- Author: Philémon Favrod (philemon.favrod@epfl.ch)
|
||||
-- Modified by: Sahand Kashani-Akhavan (sahand.kashani-akhavan@epfl.ch)
|
||||
-- Revision: 2
|
||||
|
||||
-- Register map
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | RegNo | Name | Access | Description |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 0 | COMMAND | WO | Command |
|
||||
-- | | | | - Writing 1 starts capturing a frame & resets the |
|
||||
-- | | | | ERROR bit (bit 1) in the STATUS register. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 1 | STATUS | RO | Status |
|
||||
-- | | | | - Bit 0: 0 --> no capture in progress. |
|
||||
-- | | | | 1 --> capture in progress. |
|
||||
-- | | | | - Bit 1: 0 --> previous capture successful. |
|
||||
-- | | | | 1 --> error during previous capture. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 2 | MIN | RO | Minimum pixel value in frame. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 3 | MAX | RO | Maximum pixel value in frame. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 4 | SUM_LSB | RO | Sum of all pixels in frame (low 16 bits). |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 5 | SUM_MSB | RO | Sum of all pixels in frame (high 16 bits). |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 6 | ROW_IDX | RO | Current line being captured (1 <= ROW_IDX <= 60). |
|
||||
-- | | | | Available for debugging purposes. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 7 | RESERVED | - | Reserved |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 8 - 4807 | RAW BUFFER | RO | View into RAW pixel buffer. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 4808 - 8191 | RESERVED | - | Reserved |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 8192 - 12991 | ADJUSTED BUFFER | RO | View into adjusted (scaled) pixel buffer. |
|
||||
-- | | | | Values are scaled between MIN and MAX. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 12992 - 16383 | RESERVED | - | Reserved |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity lepton is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
address : in std_logic_vector(13 downto 0);
|
||||
readdata : out std_logic_vector(15 downto 0);
|
||||
writedata : in std_logic_vector(15 downto 0);
|
||||
read : in std_logic;
|
||||
write : in std_logic;
|
||||
|
||||
SCLK : out std_logic;
|
||||
CSn : out std_logic;
|
||||
MOSI : out std_logic;
|
||||
MISO : in std_logic
|
||||
);
|
||||
|
||||
end lepton;
|
||||
|
||||
architecture rtl of lepton is
|
||||
signal spi_cs_n : std_logic;
|
||||
signal spi_mosi_data : std_logic_vector(7 downto 0);
|
||||
signal spi_mosi_valid : std_logic;
|
||||
signal spi_mosi_ready : std_logic;
|
||||
signal spi_miso_data : std_logic_vector(7 downto 0);
|
||||
signal spi_miso_valid : std_logic;
|
||||
signal lepton_manager_start : std_logic;
|
||||
signal lepton_manager_error : std_logic;
|
||||
signal byte_data : std_logic_vector(7 downto 0);
|
||||
signal byte_valid : std_logic;
|
||||
signal byte_sof : std_logic;
|
||||
signal byte_eof : std_logic;
|
||||
signal pix_data : std_logic_vector(13 downto 0);
|
||||
signal pix_valid : std_logic;
|
||||
signal pix_sof : std_logic;
|
||||
signal pix_eof : std_logic;
|
||||
signal stat_min : std_logic_vector(13 downto 0);
|
||||
signal stat_max : std_logic_vector(13 downto 0);
|
||||
signal stat_sum : std_logic_vector(26 downto 0);
|
||||
signal stat_valid : std_logic;
|
||||
signal ram_data : std_logic_vector(15 downto 0);
|
||||
signal ram_wren : std_logic;
|
||||
signal ram_wraddress : std_logic_vector(12 downto 0);
|
||||
signal ram_rdaddress : std_logic_vector(12 downto 0);
|
||||
signal ram_q : std_logic_vector(15 downto 0);
|
||||
signal row_idx : std_logic_vector(5 downto 0);
|
||||
signal raw_pixel : std_logic_vector(13 downto 0);
|
||||
signal raw_max : std_logic_vector(13 downto 0);
|
||||
signal raw_min : std_logic_vector(13 downto 0);
|
||||
signal raw_sum : std_logic_vector(26 downto 0);
|
||||
signal adjusted_pixel : std_logic_vector(13 downto 0);
|
||||
|
||||
constant COMMAND_REG_OFFSET : std_logic_vector(address'range) := "00000000000000";
|
||||
constant STATUS_REG_OFFSET : std_logic_vector(address'range) := "00000000000001";
|
||||
constant MIN_REG_OFFSET : std_logic_vector(address'range) := "00000000000010";
|
||||
constant MAX_REG_OFFSET : std_logic_vector(address'range) := "00000000000011";
|
||||
constant SUM_LSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000100";
|
||||
constant SUM_MSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000101";
|
||||
constant ROW_IDX_REG_OFFSET : std_logic_vector(address'range) := "00000000000110";
|
||||
constant BUFFER_REG_OFFSET : unsigned(address'range) := "00000000001000";
|
||||
constant ADJUSTED_BUFFER_REG_OFFSET : unsigned(address'range) := "10000000000000";
|
||||
|
||||
constant IMAGE_SIZE : integer := 80 * 60;
|
||||
constant BUFFER_REG_LIMIT : unsigned(address'range) := unsigned(BUFFER_REG_OFFSET) + IMAGE_SIZE;
|
||||
|
||||
constant ADJUSTED_BUFFER_LIMIT : unsigned(address'range) := unsigned(ADJUSTED_BUFFER_REG_OFFSET) + IMAGE_SIZE;
|
||||
|
||||
signal max_reg : std_logic_vector(stat_max'range);
|
||||
signal min_reg : std_logic_vector(stat_min'range);
|
||||
signal sum_reg : std_logic_vector(stat_sum'range);
|
||||
signal error_reg : std_logic;
|
||||
|
||||
begin
|
||||
spi_controller0 : entity work.avalon_st_spi_master
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
spi_cs_n => spi_cs_n,
|
||||
mosi_sink_data => spi_mosi_data,
|
||||
mosi_sink_valid => spi_mosi_valid,
|
||||
mosi_sink_ready => spi_mosi_ready,
|
||||
miso_src_data => spi_miso_data,
|
||||
miso_src_valid => spi_miso_valid,
|
||||
SCLK => SCLK,
|
||||
MISO => MISO,
|
||||
MOSI => MOSI,
|
||||
CS_n => CSn
|
||||
);
|
||||
|
||||
lepton_manager0 : entity work.lepton_manager
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
spi_miso_sink_data => spi_miso_data,
|
||||
spi_miso_sink_valid => spi_miso_valid,
|
||||
spi_mosi_src_data => spi_mosi_data,
|
||||
spi_mosi_src_valid => spi_mosi_valid,
|
||||
spi_mosi_src_ready => spi_mosi_ready,
|
||||
lepton_out_data => byte_data,
|
||||
lepton_out_valid => byte_valid,
|
||||
lepton_out_sof => byte_sof,
|
||||
lepton_out_eof => byte_eof,
|
||||
row_idx => row_idx,
|
||||
error => lepton_manager_error,
|
||||
start => lepton_manager_start,
|
||||
spi_cs_n => spi_cs_n
|
||||
);
|
||||
|
||||
byte2pix0 : entity work.byte2pix
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
byte_data => byte_data,
|
||||
byte_valid => byte_valid,
|
||||
byte_sof => byte_sof,
|
||||
byte_eof => byte_eof,
|
||||
pix_data => pix_data,
|
||||
pix_valid => pix_valid,
|
||||
pix_sof => pix_sof,
|
||||
pix_eof => pix_eof
|
||||
);
|
||||
|
||||
lepton_stats0 : entity work.lepton_stats
|
||||
port map(
|
||||
reset => reset,
|
||||
clk => clk,
|
||||
pix_data => pix_data,
|
||||
pix_valid => pix_valid,
|
||||
pix_sof => pix_sof,
|
||||
pix_eof => pix_eof,
|
||||
stat_min => stat_min,
|
||||
stat_max => stat_max,
|
||||
stat_sum => stat_sum,
|
||||
stat_valid => stat_valid
|
||||
);
|
||||
|
||||
ram_writer0 : entity work.ram_writer
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
pix_data => pix_data,
|
||||
pix_valid => pix_valid,
|
||||
pix_sof => pix_sof,
|
||||
pix_eof => pix_eof,
|
||||
ram_data => ram_data,
|
||||
ram_wren => ram_wren,
|
||||
ram_wraddress => ram_wraddress
|
||||
);
|
||||
|
||||
dual_ported_ram0 : entity work.dual_ported_ram
|
||||
port map(
|
||||
clock => clk,
|
||||
data => ram_data,
|
||||
rdaddress => ram_rdaddress,
|
||||
wraddress => ram_wraddress,
|
||||
wren => ram_wren,
|
||||
q => ram_q
|
||||
);
|
||||
|
||||
level_adjuster0 : entity work.level_adjuster
|
||||
port map(
|
||||
clk => clk,
|
||||
raw_pixel => ram_q(13 downto 0),
|
||||
raw_max => max_reg,
|
||||
raw_min => min_reg,
|
||||
raw_sum => sum_reg,
|
||||
adjusted_pixel => adjusted_pixel
|
||||
);
|
||||
|
||||
p_lepton_start : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
lepton_manager_start <= '0';
|
||||
error_reg <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if write = '1' and address = COMMAND_REG_OFFSET then
|
||||
lepton_manager_start <= writedata(0);
|
||||
error_reg <= '0';
|
||||
elsif pix_eof = '1' then
|
||||
lepton_manager_start <= '0';
|
||||
elsif lepton_manager_error = '1' then
|
||||
error_reg <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process p_lepton_start;
|
||||
|
||||
p_stat_reg : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
min_reg <= (others => '0');
|
||||
max_reg <= (others => '0');
|
||||
sum_reg <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if stat_valid = '1' then
|
||||
min_reg <= stat_min;
|
||||
max_reg <= stat_max;
|
||||
sum_reg <= stat_sum;
|
||||
end if;
|
||||
end if;
|
||||
end process p_stat_reg;
|
||||
|
||||
p_read : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
readdata <= (others => '0');
|
||||
ram_rdaddress <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
readdata <= (others => '0');
|
||||
if read = '1' then
|
||||
case address is
|
||||
when STATUS_REG_OFFSET =>
|
||||
readdata(1) <= error_reg;
|
||||
readdata(0) <= lepton_manager_start;
|
||||
|
||||
when MIN_REG_OFFSET =>
|
||||
readdata <= "00" & min_reg;
|
||||
|
||||
when MAX_REG_OFFSET =>
|
||||
readdata <= "00" & max_reg;
|
||||
|
||||
when SUM_MSB_REG_OFFSET =>
|
||||
readdata <= "00000" & sum_reg(26 downto 16);
|
||||
|
||||
when SUM_LSB_REG_OFFSET =>
|
||||
readdata <= sum_reg(15 downto 0);
|
||||
|
||||
when ROW_IDX_REG_OFFSET =>
|
||||
readdata(5 downto 0) <= row_idx;
|
||||
|
||||
when others =>
|
||||
if unsigned(address) >= BUFFER_REG_OFFSET and unsigned(address) < BUFFER_REG_LIMIT then
|
||||
ram_rdaddress <= std_logic_vector(resize(unsigned(address) - BUFFER_REG_OFFSET, ram_rdaddress'length));
|
||||
readdata <= ram_q;
|
||||
elsif unsigned(address) >= ADJUSTED_BUFFER_REG_OFFSET and unsigned(address) < ADJUSTED_BUFFER_LIMIT then
|
||||
ram_rdaddress <= std_logic_vector(resize(unsigned(address) - ADJUSTED_BUFFER_REG_OFFSET, ram_rdaddress'length));
|
||||
readdata <= "00" & adjusted_pixel;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process p_read;
|
||||
|
||||
end rtl;
|
||||
148
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_hw.tcl
Normal file
148
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_hw.tcl
Normal file
@@ -0,0 +1,148 @@
|
||||
# TCL File Generated by Component Editor 16.0
|
||||
# Sun Feb 05 19:05:24 CET 2017
|
||||
# DO NOT MODIFY
|
||||
|
||||
|
||||
#
|
||||
# lepton "lepton" v1.0
|
||||
# Philemon Favrod & Sahand Kashani-Akhavan 2017.02.05.19:05:24
|
||||
# IR Camera 80x60
|
||||
#
|
||||
|
||||
#
|
||||
# request TCL package from ACDS 16.0
|
||||
#
|
||||
package require -exact qsys 16.0
|
||||
|
||||
|
||||
#
|
||||
# module lepton
|
||||
#
|
||||
set_module_property DESCRIPTION "IR Camera 80x60"
|
||||
set_module_property NAME lepton
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property INTERNAL false
|
||||
set_module_property OPAQUE_ADDRESS_MAP true
|
||||
set_module_property GROUP Camera
|
||||
set_module_property AUTHOR "Philemon Favrod & Sahand Kashani-Akhavan"
|
||||
set_module_property DISPLAY_NAME lepton
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
set_module_property EDITABLE true
|
||||
set_module_property REPORT_TO_TALKBACK false
|
||||
set_module_property ALLOW_GREYBOX_GENERATION false
|
||||
set_module_property REPORT_HIERARCHY false
|
||||
|
||||
|
||||
#
|
||||
# file sets
|
||||
#
|
||||
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
|
||||
set_fileset_property QUARTUS_SYNTH TOP_LEVEL lepton
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
|
||||
add_fileset_file avalon_st_spi_master.vhd VHDL PATH avalon_st_spi_master.vhd
|
||||
add_fileset_file byte2pix.vhd VHDL PATH byte2pix.vhd
|
||||
add_fileset_file dual_ported_ram.vhd VHDL PATH dual_ported_ram.vhd
|
||||
add_fileset_file lepton.vhd VHDL PATH lepton.vhd TOP_LEVEL_FILE
|
||||
add_fileset_file lepton_manager.vhd VHDL PATH lepton_manager.vhd
|
||||
add_fileset_file lepton_stats.vhd VHDL PATH lepton_stats.vhd
|
||||
add_fileset_file ram_writer.vhd VHDL PATH ram_writer.vhd
|
||||
add_fileset_file utils.vhd VHDL PATH utils.vhd
|
||||
add_fileset_file level_adjuster.vhd VHDL PATH level_adjuster.vhd
|
||||
add_fileset_file lpm_divider.vhd VHDL PATH lpm_divider.vhd
|
||||
|
||||
|
||||
#
|
||||
# parameters
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# display items
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# connection point clock
|
||||
#
|
||||
add_interface clock clock end
|
||||
set_interface_property clock clockRate 0
|
||||
set_interface_property clock ENABLED true
|
||||
set_interface_property clock EXPORT_OF ""
|
||||
set_interface_property clock PORT_NAME_MAP ""
|
||||
set_interface_property clock CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property clock SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point reset
|
||||
#
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
set_interface_property reset ENABLED true
|
||||
set_interface_property reset EXPORT_OF ""
|
||||
set_interface_property reset PORT_NAME_MAP ""
|
||||
set_interface_property reset CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property reset SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port reset reset reset Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point avalon_slave_0
|
||||
#
|
||||
add_interface avalon_slave_0 avalon end
|
||||
set_interface_property avalon_slave_0 addressUnits WORDS
|
||||
set_interface_property avalon_slave_0 associatedClock clock
|
||||
set_interface_property avalon_slave_0 associatedReset reset
|
||||
set_interface_property avalon_slave_0 bitsPerSymbol 8
|
||||
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
|
||||
set_interface_property avalon_slave_0 burstcountUnits WORDS
|
||||
set_interface_property avalon_slave_0 explicitAddressSpan 0
|
||||
set_interface_property avalon_slave_0 holdTime 0
|
||||
set_interface_property avalon_slave_0 linewrapBursts false
|
||||
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
|
||||
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
|
||||
set_interface_property avalon_slave_0 readLatency 0
|
||||
set_interface_property avalon_slave_0 readWaitStates 9
|
||||
set_interface_property avalon_slave_0 readWaitTime 9
|
||||
set_interface_property avalon_slave_0 setupTime 0
|
||||
set_interface_property avalon_slave_0 timingUnits Cycles
|
||||
set_interface_property avalon_slave_0 writeWaitTime 0
|
||||
set_interface_property avalon_slave_0 ENABLED true
|
||||
set_interface_property avalon_slave_0 EXPORT_OF ""
|
||||
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
|
||||
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port avalon_slave_0 address address Input 14
|
||||
add_interface_port avalon_slave_0 readdata readdata Output 16
|
||||
add_interface_port avalon_slave_0 writedata writedata Input 16
|
||||
add_interface_port avalon_slave_0 read read Input 1
|
||||
add_interface_port avalon_slave_0 write write Input 1
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
|
||||
|
||||
|
||||
#
|
||||
# connection point spi
|
||||
#
|
||||
add_interface spi conduit end
|
||||
set_interface_property spi associatedClock clock
|
||||
set_interface_property spi associatedReset ""
|
||||
set_interface_property spi ENABLED true
|
||||
set_interface_property spi EXPORT_OF ""
|
||||
set_interface_property spi PORT_NAME_MAP ""
|
||||
set_interface_property spi CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property spi SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port spi CSn cs_n Output 1
|
||||
add_interface_port spi MISO miso Input 1
|
||||
add_interface_port spi MOSI mosi Output 1
|
||||
add_interface_port spi SCLK sclk Output 1
|
||||
|
||||
235
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_manager.vhd
Normal file
235
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_manager.vhd
Normal file
@@ -0,0 +1,235 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity lepton_manager is
|
||||
generic(
|
||||
INPUT_CLK_FREQ : integer := 50000000);
|
||||
port(
|
||||
clk : in std_logic := '0';
|
||||
reset : in std_logic := '0';
|
||||
|
||||
-- Avalon ST Sink to receive SPI data
|
||||
spi_miso_sink_data : in std_logic_vector(7 downto 0);
|
||||
spi_miso_sink_valid : in std_logic;
|
||||
|
||||
-- Avalon ST Source to send SPI data
|
||||
spi_mosi_src_data : out std_logic_vector(7 downto 0);
|
||||
spi_mosi_src_valid : out std_logic;
|
||||
spi_mosi_src_ready : in std_logic := '0';
|
||||
|
||||
-- Filtered output to retransmit cleaned data (without the discard packets, see Lepton Datasheet on page 31)
|
||||
-- lepton_out_data is valid on rising edge when lepton_src_valid = '1'
|
||||
lepton_out_data : out std_logic_vector(7 downto 0);
|
||||
lepton_out_valid : out std_logic;
|
||||
lepton_out_sof : out std_logic;
|
||||
lepton_out_eof : out std_logic;
|
||||
|
||||
-- Some status
|
||||
row_idx : out std_logic_vector(5 downto 0);
|
||||
error : out std_logic;
|
||||
|
||||
-- Avalon MM Slave interface for configuration
|
||||
start : in std_logic;
|
||||
|
||||
-- The SPI Chip Select (Active low !)
|
||||
spi_cs_n : out std_logic := '0');
|
||||
end entity lepton_manager;
|
||||
|
||||
architecture rtl of lepton_manager is
|
||||
type state_t is (Idle, CSn, ReadHeader, ReadPayload, DiscardPayload, WaitBeforeIdle);
|
||||
signal state, next_state : state_t;
|
||||
|
||||
signal header_3_last_nibbles : std_logic_vector(11 downto 0);
|
||||
|
||||
constant CLOCK_TICKS_PER_37_MS : integer := 37 * (INPUT_CLK_FREQ / 1e3); -- the timeout delay for a frame
|
||||
constant CLOCK_TICKS_PER_200_MS : integer := 200 * (INPUT_CLK_FREQ / 1e3);
|
||||
constant CLOCK_TICKS_PER_200_NS : integer := (200 * (INPUT_CLK_FREQ / 1e6)) / 1e3;
|
||||
constant BYTES_PER_HEADER : integer := 4;
|
||||
constant BYTES_PER_PAYLOAD : integer := 160;
|
||||
|
||||
constant NUMBER_OF_LINES_PER_FRAME : positive := 60;
|
||||
signal counter, counter_max : integer range 1 to CLOCK_TICKS_PER_200_MS;
|
||||
signal line_counter : integer range 1 to NUMBER_OF_LINES_PER_FRAME;
|
||||
signal timeout_counter : integer range 1 to CLOCK_TICKS_PER_37_MS;
|
||||
signal counter_enabled : boolean;
|
||||
signal waited_long_enough : boolean;
|
||||
signal header_end, payload_end : boolean;
|
||||
begin
|
||||
|
||||
-- purpose: register for state
|
||||
p_fsm : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
state <= Idle;
|
||||
elsif rising_edge(clk) then
|
||||
state <= next_state;
|
||||
end if;
|
||||
end process p_fsm;
|
||||
|
||||
-- purpose: compute the next state
|
||||
p_nsl : process(header_3_last_nibbles, header_end, payload_end, start, spi_miso_sink_valid, state, waited_long_enough, line_counter)
|
||||
begin
|
||||
next_state <= state;
|
||||
|
||||
case state is
|
||||
when Idle =>
|
||||
if waited_long_enough and start = '1' then
|
||||
next_state <= CSn;
|
||||
end if;
|
||||
|
||||
when CSn =>
|
||||
if waited_long_enough then
|
||||
next_state <= ReadHeader;
|
||||
end if;
|
||||
|
||||
when ReadHeader =>
|
||||
if header_end then
|
||||
if header_3_last_nibbles(11 downto 8) = X"F" then
|
||||
next_state <= DiscardPayload;
|
||||
else
|
||||
next_state <= ReadPayload;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when DiscardPayload | ReadPayload =>
|
||||
if payload_end then
|
||||
next_state <= ReadHeader;
|
||||
|
||||
if line_counter = NUMBER_OF_LINES_PER_FRAME then
|
||||
next_state <= WaitBeforeIdle;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when WaitBeforeIdle =>
|
||||
if spi_miso_sink_valid = '1' then
|
||||
next_state <= Idle;
|
||||
end if;
|
||||
|
||||
end case;
|
||||
end process p_nsl;
|
||||
|
||||
p_counter : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
counter <= 1;
|
||||
line_counter <= 1;
|
||||
elsif rising_edge(clk) then
|
||||
if counter = counter_max and counter_enabled then
|
||||
counter <= 1;
|
||||
|
||||
if state = ReadPayload then
|
||||
if line_counter = NUMBER_OF_LINES_PER_FRAME then
|
||||
line_counter <= 1;
|
||||
else
|
||||
line_counter <= line_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
elsif counter_enabled then
|
||||
counter <= counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process p_counter;
|
||||
|
||||
p_error : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
error <= '0';
|
||||
timeout_counter <= 1;
|
||||
elsif rising_edge(clk) then
|
||||
if state /= ReadHeader and state /= ReadPayload and state /= ReadHeader then
|
||||
timeout_counter <= 1;
|
||||
error <= '0';
|
||||
else
|
||||
if timeout_counter = CLOCK_TICKS_PER_37_MS then
|
||||
error <= '1';
|
||||
else
|
||||
timeout_counter <= timeout_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
if state = ReadPayload and header_3_last_nibbles /= std_logic_vector(to_unsigned(line_counter - 1, header_3_last_nibbles'length)) then
|
||||
error <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process p_error;
|
||||
|
||||
-- purpose: wire the datapath
|
||||
p_datapath : process(counter, counter_enabled, counter_max, line_counter, spi_miso_sink_data, spi_miso_sink_valid, spi_mosi_src_ready, state)
|
||||
variable counter_ended : boolean;
|
||||
|
||||
begin
|
||||
counter_max <= 1;
|
||||
counter_enabled <= true;
|
||||
waited_long_enough <= false;
|
||||
lepton_out_data <= (others => '0');
|
||||
lepton_out_valid <= '0';
|
||||
lepton_out_sof <= '0';
|
||||
lepton_out_eof <= '0';
|
||||
spi_mosi_src_valid <= '0';
|
||||
spi_mosi_src_data <= (others => '0');
|
||||
spi_cs_n <= '0';
|
||||
header_end <= false;
|
||||
payload_end <= false;
|
||||
|
||||
counter_ended := (counter = counter_max and counter_enabled);
|
||||
|
||||
case state is
|
||||
when Idle =>
|
||||
counter_max <= CLOCK_TICKS_PER_200_MS;
|
||||
waited_long_enough <= counter_ended;
|
||||
spi_cs_n <= '1';
|
||||
|
||||
when CSn =>
|
||||
counter_max <= CLOCK_TICKS_PER_200_NS;
|
||||
waited_long_enough <= counter_ended;
|
||||
|
||||
when ReadHeader =>
|
||||
counter_max <= BYTES_PER_HEADER;
|
||||
counter_enabled <= spi_miso_sink_valid = '1';
|
||||
header_end <= counter_ended;
|
||||
spi_mosi_src_valid <= spi_mosi_src_ready;
|
||||
|
||||
when ReadPayload =>
|
||||
counter_max <= BYTES_PER_PAYLOAD;
|
||||
counter_enabled <= spi_miso_sink_valid = '1';
|
||||
lepton_out_data <= spi_miso_sink_data;
|
||||
lepton_out_valid <= spi_miso_sink_valid;
|
||||
payload_end <= counter_ended;
|
||||
spi_mosi_src_valid <= spi_mosi_src_ready;
|
||||
if spi_miso_sink_valid = '1' then
|
||||
if counter = 1 and counter_enabled and line_counter = 1 then
|
||||
lepton_out_sof <= '1';
|
||||
elsif counter_ended and line_counter = NUMBER_OF_LINES_PER_FRAME then
|
||||
lepton_out_eof <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when DiscardPayload =>
|
||||
counter_max <= BYTES_PER_PAYLOAD;
|
||||
counter_enabled <= spi_miso_sink_valid = '1';
|
||||
payload_end <= counter_ended;
|
||||
spi_mosi_src_valid <= spi_mosi_src_ready;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end process p_datapath;
|
||||
|
||||
p_capture_header : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
header_3_last_nibbles <= X"000";
|
||||
elsif rising_edge(clk) then
|
||||
if state = ReadHeader and spi_miso_sink_valid = '1' then
|
||||
if counter = 1 then
|
||||
header_3_last_nibbles(11 downto 8) <= spi_miso_sink_data(3 downto 0);
|
||||
elsif counter = 2 then
|
||||
header_3_last_nibbles(7 downto 0) <= spi_miso_sink_data;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process p_capture_header;
|
||||
|
||||
row_idx <= std_logic_vector(to_unsigned(line_counter, row_idx'length));
|
||||
|
||||
end architecture rtl;
|
||||
22
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_stats.vhd
Normal file
22
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lepton_stats.vhd
Normal file
@@ -0,0 +1,22 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity lepton_stats is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
pix_data : in std_logic_vector(13 downto 0);
|
||||
pix_valid : in std_logic;
|
||||
pix_sof : in std_logic;
|
||||
pix_eof : in std_logic;
|
||||
stat_min : out std_logic_vector(13 downto 0);
|
||||
stat_max : out std_logic_vector(13 downto 0);
|
||||
stat_sum : out std_logic_vector(26 downto 0);
|
||||
stat_valid : out std_logic);
|
||||
end lepton_stats;
|
||||
|
||||
architecture rtl of lepton_stats is
|
||||
begin
|
||||
-- TODO : complete this architecture
|
||||
end rtl;
|
||||
27
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/level_adjuster.vhd
Normal file
27
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/level_adjuster.vhd
Normal file
@@ -0,0 +1,27 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity level_adjuster is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
raw_pixel : in std_logic_vector(13 downto 0);
|
||||
raw_max : in std_logic_vector(13 downto 0);
|
||||
raw_min : in std_logic_vector(13 downto 0);
|
||||
raw_sum : in std_logic_vector(26 downto 0);
|
||||
adjusted_pixel : out std_logic_vector(13 downto 0));
|
||||
end level_adjuster;
|
||||
|
||||
architecture rtl of level_adjuster is
|
||||
component lpm_divider
|
||||
port(
|
||||
clock : in std_logic;
|
||||
denom : in std_logic_vector(13 downto 0);
|
||||
numer : in std_logic_vector(27 downto 0);
|
||||
quotient : out std_logic_vector(27 downto 0);
|
||||
remain : out std_logic_vector(13 downto 0));
|
||||
end component;
|
||||
|
||||
begin
|
||||
-- TODO : complete this architecture
|
||||
end rtl;
|
||||
133
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lpm_divider.vhd
Normal file
133
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/lpm_divider.vhd
Normal file
@@ -0,0 +1,133 @@
|
||||
-- megafunction wizard: %LPM_DIVIDE%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: LPM_DIVIDE
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: lpm_divider.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- LPM_DIVIDE
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- lpm
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
--the Altera MegaCore Function License Agreement, or other
|
||||
--applicable license agreement, including, without limitation,
|
||||
--that your use is for the sole purpose of programming logic
|
||||
--devices manufactured by Altera and sold by Altera or its
|
||||
--authorized distributors. Please refer to the applicable
|
||||
--agreement for further details.
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
library lpm;
|
||||
use lpm.all;
|
||||
|
||||
entity lpm_divider is
|
||||
port(
|
||||
clock : in std_logic;
|
||||
denom : in std_logic_vector(13 downto 0);
|
||||
numer : in std_logic_vector(27 downto 0);
|
||||
quotient : out std_logic_vector(27 downto 0);
|
||||
remain : out std_logic_vector(13 downto 0)
|
||||
);
|
||||
end lpm_divider;
|
||||
|
||||
architecture SYN of lpm_divider is
|
||||
signal sub_wire0 : std_logic_vector(27 downto 0);
|
||||
signal sub_wire1 : std_logic_vector(13 downto 0);
|
||||
|
||||
component lpm_divide
|
||||
generic(
|
||||
lpm_drepresentation : string;
|
||||
lpm_hint : string;
|
||||
lpm_nrepresentation : string;
|
||||
lpm_pipeline : natural;
|
||||
lpm_type : string;
|
||||
lpm_widthd : natural;
|
||||
lpm_widthn : natural
|
||||
);
|
||||
port(
|
||||
clock : in std_logic;
|
||||
denom : in std_logic_vector(13 downto 0);
|
||||
numer : in std_logic_vector(27 downto 0);
|
||||
quotient : out std_logic_vector(27 downto 0);
|
||||
remain : out std_logic_vector(13 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
quotient <= sub_wire0(27 downto 0);
|
||||
remain <= sub_wire1(13 downto 0);
|
||||
|
||||
LPM_DIVIDE_component : LPM_DIVIDE
|
||||
generic map(
|
||||
lpm_drepresentation => "UNSIGNED",
|
||||
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
|
||||
lpm_nrepresentation => "UNSIGNED",
|
||||
lpm_pipeline => 5,
|
||||
lpm_type => "LPM_DIVIDE",
|
||||
lpm_widthd => 14,
|
||||
lpm_widthn => 28
|
||||
)
|
||||
port map(
|
||||
clock => clock,
|
||||
denom => denom,
|
||||
numer => numer,
|
||||
quotient => sub_wire0,
|
||||
remain => sub_wire1
|
||||
);
|
||||
|
||||
end SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
|
||||
-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
|
||||
-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
|
||||
-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
|
||||
-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
|
||||
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "14"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "28"
|
||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
-- Retrieval info: USED_PORT: denom 0 0 14 0 INPUT NODEFVAL "denom[13..0]"
|
||||
-- Retrieval info: USED_PORT: numer 0 0 28 0 INPUT NODEFVAL "numer[27..0]"
|
||||
-- Retrieval info: USED_PORT: quotient 0 0 28 0 OUTPUT NODEFVAL "quotient[27..0]"
|
||||
-- Retrieval info: USED_PORT: remain 0 0 14 0 OUTPUT NODEFVAL "remain[13..0]"
|
||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @denom 0 0 14 0 denom 0 0 14 0
|
||||
-- Retrieval info: CONNECT: @numer 0 0 28 0 numer 0 0 28 0
|
||||
-- Retrieval info: CONNECT: quotient 0 0 28 0 @quotient 0 0 28 0
|
||||
-- Retrieval info: CONNECT: remain 0 0 14 0 @remain 0 0 14 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: lpm
|
||||
38
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/ram_writer.vhd
Normal file
38
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/ram_writer.vhd
Normal file
@@ -0,0 +1,38 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity ram_writer is
|
||||
port(
|
||||
clk, reset : in std_logic;
|
||||
pix_data : in std_logic_vector(13 downto 0);
|
||||
pix_valid : in std_logic;
|
||||
pix_sof : in std_logic;
|
||||
pix_eof : in std_logic;
|
||||
ram_data : out std_logic_vector(15 downto 0);
|
||||
ram_wren : out std_logic;
|
||||
ram_wraddress : out std_logic_vector(12 downto 0));
|
||||
|
||||
end ram_writer;
|
||||
|
||||
architecture rtl of ram_writer is
|
||||
signal wraddress_counter : unsigned(ram_wraddress'range);
|
||||
begin
|
||||
p_address_gen : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
wraddress_counter <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if pix_eof = '1' then
|
||||
wraddress_counter <= (others => '0');
|
||||
elsif pix_valid = '1' then
|
||||
wraddress_counter <= wraddress_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process p_address_gen;
|
||||
|
||||
ram_data <= "00" & pix_data;
|
||||
ram_wren <= pix_valid;
|
||||
ram_wraddress <= std_logic_vector(wraddress_counter);
|
||||
|
||||
end rtl;
|
||||
27
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/utils.vhd
Normal file
27
cs309-psoc/lab_3_0/hw/hdl/lepton/hdl/utils.vhd
Normal file
@@ -0,0 +1,27 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
package utils is
|
||||
function bitlength(number : positive) return positive;
|
||||
|
||||
end package utils;
|
||||
|
||||
package body utils is
|
||||
|
||||
-- purpose: returns the minimum # of bits needed to represent the input number
|
||||
function bitlength(number : positive) return positive is
|
||||
variable acc : positive := 1;
|
||||
variable i : natural := 0;
|
||||
begin
|
||||
while True loop
|
||||
if acc > number then
|
||||
return i;
|
||||
end if;
|
||||
|
||||
acc := acc * 2;
|
||||
i := i + 1;
|
||||
end loop;
|
||||
end function bitlength;
|
||||
|
||||
end package body utils;
|
||||
77
cs309-psoc/lab_3_0/hw/hdl/lepton/tb/lepton_tb.vhd
Normal file
77
cs309-psoc/lab_3_0/hw/hdl/lepton/tb/lepton_tb.vhd
Normal file
@@ -0,0 +1,77 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity lepton_tb is
|
||||
end lepton_tb;
|
||||
|
||||
architecture tb of lepton_tb is
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '0';
|
||||
signal address : std_logic_vector(13 downto 0) := (others => '0');
|
||||
signal readdata : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal writedata : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal read : std_logic := '0';
|
||||
signal write : std_logic := '0';
|
||||
signal SCLK : std_logic := '0';
|
||||
signal CSn : std_logic := '0';
|
||||
signal MOSI : std_logic := '0';
|
||||
signal MISO : std_logic := '1';
|
||||
|
||||
constant CLK_PERIOD : time := 20 ns;
|
||||
|
||||
signal sim_ended : boolean := false;
|
||||
|
||||
begin
|
||||
dut : entity work.lepton
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
address => address,
|
||||
readdata => readdata,
|
||||
writedata => writedata,
|
||||
read => read,
|
||||
write => write,
|
||||
SCLK => SCLK,
|
||||
CSn => CSn,
|
||||
MOSI => MOSI,
|
||||
MISO => MISO
|
||||
);
|
||||
|
||||
clk <= not clk after CLK_PERIOD / 2 when not sim_ended else '0';
|
||||
|
||||
miso_gen : process
|
||||
variable seed1, seed2 : positive;
|
||||
variable rand : real;
|
||||
begin
|
||||
if sim_ended then
|
||||
wait;
|
||||
else
|
||||
uniform(seed1, seed2, rand);
|
||||
wait until rising_edge(SCLK);
|
||||
MISO <= to_unsigned(integer(rand), 1)(0);
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
stimuli : process
|
||||
begin
|
||||
reset <= '1';
|
||||
write <= '0';
|
||||
|
||||
wait for 2 * CLK_PERIOD;
|
||||
reset <= '0';
|
||||
|
||||
wait for CLK_PERIOD;
|
||||
write <= '1';
|
||||
writedata(0) <= '1';
|
||||
wait for CLK_PERIOD;
|
||||
write <= '0';
|
||||
|
||||
wait for 17 ms;
|
||||
sim_ended <= true;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
end tb;
|
||||
42
cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm.vhd
Normal file
42
cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm.vhd
Normal file
@@ -0,0 +1,42 @@
|
||||
-- #############################################################################
|
||||
-- pwm.vhd
|
||||
-- =======
|
||||
-- PWM memory-mapped Avalon slave interface.
|
||||
--
|
||||
-- Author : <insert your name> (<insert your e-mail address>)
|
||||
-- Author : <insert your name> (<insert your e-mail address>)
|
||||
-- Revision : <insert revision>
|
||||
-- Last modified : <insert date>
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.pwm_constants.all;
|
||||
|
||||
entity pwm is
|
||||
port(
|
||||
-- Avalon Clock interface
|
||||
clk : in std_logic;
|
||||
|
||||
-- Avalon Reset interface
|
||||
reset : in std_logic;
|
||||
|
||||
-- Avalon-MM Slave interface
|
||||
address : in std_logic_vector(1 downto 0);
|
||||
read : in std_logic;
|
||||
write : in std_logic;
|
||||
readdata : out std_logic_vector(31 downto 0);
|
||||
writedata : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- Avalon Conduit interface
|
||||
pwm_out : out std_logic
|
||||
);
|
||||
end pwm;
|
||||
|
||||
architecture rtl of pwm is
|
||||
|
||||
begin
|
||||
|
||||
end architecture rtl;
|
||||
61
cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm_constants.vhd
Normal file
61
cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm_constants.vhd
Normal file
@@ -0,0 +1,61 @@
|
||||
-- #############################################################################
|
||||
-- pwm_constants.vhd
|
||||
-- =================
|
||||
-- This package contains constants used in the PWM design files.
|
||||
--
|
||||
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
|
||||
-- Revision : 2
|
||||
-- Last modified : 2018-02-28
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
package pwm_constants is
|
||||
-- Register map
|
||||
-- +--------+------------+--------+------------------------------------------------------------------------------+
|
||||
-- | RegNo | Name | Access | Description |
|
||||
-- +--------+------------+--------+------------------------------------------------------------------------------+
|
||||
-- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. |
|
||||
-- | | | | |
|
||||
-- | | | | This value can be read/written while the unit is in the middle of an ongoing |
|
||||
-- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an |
|
||||
-- | | | | ongoing pulse, so we adopt the following semantics for this register: |
|
||||
-- | | | | |
|
||||
-- | | | | >> WRITING a value in this register indicates the NEW period to apply to the |
|
||||
-- | | | | next pulse. |
|
||||
-- | | | | |
|
||||
-- | | | | >> READING a value from this register indicates the CURRENT period of the |
|
||||
-- | | | | ongoing pulse. |
|
||||
-- +--------+------------+--------+------------------------------------------------------------------------------+
|
||||
-- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] |
|
||||
-- | | | | |
|
||||
-- | | | | This value can be read/written while the unit is in the middle of an ongoing |
|
||||
-- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an |
|
||||
-- | | | | ongoing pulse, so we adopt the following semantics for this register: |
|
||||
-- | | | | |
|
||||
-- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to |
|
||||
-- | | | | the next pulse. |
|
||||
-- | | | | |
|
||||
-- | | | | >> READING a value from this register indicates the CURRENT duty cycle of |
|
||||
-- | | | | the ongoing pulse. |
|
||||
-- +--------+------------+--------+------------------------------------------------------------------------------+
|
||||
-- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.|
|
||||
-- | | | | Writing 1 to this register starts the PWM. |
|
||||
-- | | | | |
|
||||
-- | | | | >> Reading this register always returns 0. |
|
||||
-- +--------+------------+--------+------------------------------------------------------------------------------+
|
||||
constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00";
|
||||
constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01";
|
||||
constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10";
|
||||
|
||||
-- Default values of registers after reset (BEFORE writing START to the CTRL
|
||||
-- register with a new configuration)
|
||||
constant DEFAULT_PERIOD : natural := 4;
|
||||
constant DEFAULT_DUTY_CYCLE : natural := 2;
|
||||
end package pwm_constants;
|
||||
|
||||
package body pwm_constants is
|
||||
|
||||
end package body pwm_constants;
|
||||
135
cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm_hw.tcl
Normal file
135
cs309-psoc/lab_3_0/hw/hdl/pantilt/hdl/pwm_hw.tcl
Normal file
@@ -0,0 +1,135 @@
|
||||
# TCL File Generated by Component Editor 16.0
|
||||
# Tue Feb 28 12:18:00 CET 2017
|
||||
# DO NOT MODIFY
|
||||
|
||||
|
||||
#
|
||||
# pwm "pwm" v1.0
|
||||
# 2017.02.28.12:18:00
|
||||
# Pan-tilt
|
||||
#
|
||||
|
||||
#
|
||||
# request TCL package from ACDS 16.0
|
||||
#
|
||||
package require -exact qsys 16.0
|
||||
|
||||
|
||||
#
|
||||
# module pwm
|
||||
#
|
||||
set_module_property DESCRIPTION Pan-tilt
|
||||
set_module_property NAME pwm
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property INTERNAL false
|
||||
set_module_property OPAQUE_ADDRESS_MAP true
|
||||
set_module_property GROUP Pan-tilt
|
||||
set_module_property AUTHOR ""
|
||||
set_module_property DISPLAY_NAME pwm
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
set_module_property EDITABLE true
|
||||
set_module_property REPORT_TO_TALKBACK false
|
||||
set_module_property ALLOW_GREYBOX_GENERATION false
|
||||
set_module_property REPORT_HIERARCHY false
|
||||
|
||||
|
||||
#
|
||||
# file sets
|
||||
#
|
||||
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
|
||||
set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
|
||||
add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE
|
||||
add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd
|
||||
|
||||
|
||||
#
|
||||
# parameters
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# display items
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# connection point clock
|
||||
#
|
||||
add_interface clock clock end
|
||||
set_interface_property clock clockRate 0
|
||||
set_interface_property clock ENABLED true
|
||||
set_interface_property clock EXPORT_OF ""
|
||||
set_interface_property clock PORT_NAME_MAP ""
|
||||
set_interface_property clock CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property clock SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point reset
|
||||
#
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
set_interface_property reset ENABLED true
|
||||
set_interface_property reset EXPORT_OF ""
|
||||
set_interface_property reset PORT_NAME_MAP ""
|
||||
set_interface_property reset CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property reset SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port reset reset reset Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point avalon_slave_0
|
||||
#
|
||||
add_interface avalon_slave_0 avalon end
|
||||
set_interface_property avalon_slave_0 addressUnits WORDS
|
||||
set_interface_property avalon_slave_0 associatedClock clock
|
||||
set_interface_property avalon_slave_0 associatedReset reset
|
||||
set_interface_property avalon_slave_0 bitsPerSymbol 8
|
||||
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
|
||||
set_interface_property avalon_slave_0 burstcountUnits WORDS
|
||||
set_interface_property avalon_slave_0 explicitAddressSpan 0
|
||||
set_interface_property avalon_slave_0 holdTime 0
|
||||
set_interface_property avalon_slave_0 linewrapBursts false
|
||||
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
|
||||
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
|
||||
set_interface_property avalon_slave_0 readLatency 0
|
||||
set_interface_property avalon_slave_0 readWaitTime 1
|
||||
set_interface_property avalon_slave_0 setupTime 0
|
||||
set_interface_property avalon_slave_0 timingUnits Cycles
|
||||
set_interface_property avalon_slave_0 writeWaitTime 0
|
||||
set_interface_property avalon_slave_0 ENABLED true
|
||||
set_interface_property avalon_slave_0 EXPORT_OF ""
|
||||
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
|
||||
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port avalon_slave_0 address address Input 2
|
||||
add_interface_port avalon_slave_0 read read Input 1
|
||||
add_interface_port avalon_slave_0 write write Input 1
|
||||
add_interface_port avalon_slave_0 readdata readdata Output 32
|
||||
add_interface_port avalon_slave_0 writedata writedata Input 32
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
|
||||
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
|
||||
|
||||
|
||||
#
|
||||
# connection point conduit_end
|
||||
#
|
||||
add_interface conduit_end conduit end
|
||||
set_interface_property conduit_end associatedClock clock
|
||||
set_interface_property conduit_end associatedReset ""
|
||||
set_interface_property conduit_end ENABLED true
|
||||
set_interface_property conduit_end EXPORT_OF ""
|
||||
set_interface_property conduit_end PORT_NAME_MAP ""
|
||||
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port conduit_end pwm_out pwm Output 1
|
||||
205
cs309-psoc/lab_3_0/hw/hdl/pantilt/tb/tb_pwm.vhd
Normal file
205
cs309-psoc/lab_3_0/hw/hdl/pantilt/tb/tb_pwm.vhd
Normal file
@@ -0,0 +1,205 @@
|
||||
-- #############################################################################
|
||||
-- tb_pwm.vhd
|
||||
-- ==========
|
||||
-- Testbench for PWM memory-mapped Avalon slave interface.
|
||||
--
|
||||
-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
|
||||
-- Revision : 2
|
||||
-- Last modified : 2018-02-28
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.pwm_constants.all;
|
||||
|
||||
entity tb_pwm is
|
||||
end entity;
|
||||
|
||||
architecture rtl of tb_pwm is
|
||||
|
||||
-- 50 MHz clock
|
||||
constant CLK_PERIOD : time := 20 ns;
|
||||
|
||||
-- Signal used to end simulator when we finished submitting our test cases
|
||||
signal sim_finished : boolean := false;
|
||||
|
||||
-- PWM PORTS
|
||||
signal clk : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal address : std_logic_vector(1 downto 0);
|
||||
signal read : std_logic;
|
||||
signal write : std_logic;
|
||||
signal readdata : std_logic_vector(31 downto 0);
|
||||
signal writedata : std_logic_vector(31 downto 0);
|
||||
signal pwm_out : std_logic;
|
||||
|
||||
-- Values of registers we are going to use to configure the PWM unit
|
||||
constant CONFIG_PERIOD : natural := 100;
|
||||
constant CONFIG_DUTY_CYCLE : natural := 20;
|
||||
constant CONFIG_CTRL_START : natural := 1;
|
||||
constant CONFIG_CTRL_STOP : natural := 0;
|
||||
|
||||
begin
|
||||
|
||||
-- Instantiate DUT
|
||||
dut : entity work.pwm
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
address => address,
|
||||
read => read,
|
||||
write => write,
|
||||
readdata => readdata,
|
||||
writedata => writedata,
|
||||
pwm_out => pwm_out
|
||||
);
|
||||
|
||||
-- Generate clk signal
|
||||
clk_generation : process
|
||||
begin
|
||||
if not sim_finished then
|
||||
clk <= '1';
|
||||
wait for CLK_PERIOD / 2;
|
||||
clk <= '0';
|
||||
wait for CLK_PERIOD / 2;
|
||||
else
|
||||
wait;
|
||||
end if;
|
||||
end process clk_generation;
|
||||
|
||||
-- Test PWM
|
||||
simulation : process
|
||||
|
||||
procedure async_reset is
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
wait for CLK_PERIOD / 4;
|
||||
|
||||
reset <= '1';
|
||||
wait for CLK_PERIOD / 2;
|
||||
|
||||
reset <= '0';
|
||||
wait for CLK_PERIOD / 4;
|
||||
end procedure async_reset;
|
||||
|
||||
procedure write_register(constant ofst : in std_logic_vector(1 downto 0);
|
||||
constant val : in natural) is
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
|
||||
address <= ofst;
|
||||
write <= '1';
|
||||
writedata <= std_logic_vector(to_unsigned(val, writedata'length));
|
||||
wait until rising_edge(clk);
|
||||
|
||||
address <= (others => '0');
|
||||
write <= '0';
|
||||
writedata <= (others => '0');
|
||||
wait until rising_edge(clk);
|
||||
end procedure write_register;
|
||||
|
||||
procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
|
||||
address <= ofst;
|
||||
read <= '1';
|
||||
-- The read has a 1 cycle wait-state, so we need to keep the read
|
||||
-- signal high for 2 clock cycles.
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
|
||||
address <= (others => '0');
|
||||
read <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure read_register;
|
||||
|
||||
procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0);
|
||||
constant expected_val : in natural) is
|
||||
begin
|
||||
read_register(ofst);
|
||||
|
||||
case ofst is
|
||||
when REG_PERIOD_OFST =>
|
||||
assert to_integer(unsigned(readdata)) = expected_val
|
||||
report "Unexpected PERIOD: " &
|
||||
"PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " &
|
||||
"PERIOD_expected = " & integer'image(expected_val)
|
||||
severity error;
|
||||
|
||||
when REG_DUTY_CYCLE_OFST =>
|
||||
assert to_integer(unsigned(readdata)) = expected_val
|
||||
report "Unexpected DUTY_CYCLE: " &
|
||||
"DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " &
|
||||
"DUTY_CYCLE_expected = " & integer'image(expected_val)
|
||||
severity error;
|
||||
|
||||
when REG_CTRL_OFST =>
|
||||
assert to_integer(unsigned(readdata)) = expected_val
|
||||
report "Unexpected CTRL: " &
|
||||
"CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " &
|
||||
"CTRL_expected = " & integer'image(expected_val)
|
||||
severity error;
|
||||
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end procedure read_register_check;
|
||||
|
||||
begin
|
||||
|
||||
-- Default values
|
||||
reset <= '0';
|
||||
address <= (others => '0');
|
||||
read <= '0';
|
||||
write <= '0';
|
||||
writedata <= (others => '0');
|
||||
wait until rising_edge(clk);
|
||||
|
||||
-- Reset the circuit
|
||||
async_reset;
|
||||
|
||||
-- Write desired configuration to PWM Avalon-MM slave.
|
||||
write_register(REG_PERIOD_OFST, CONFIG_PERIOD);
|
||||
write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
|
||||
|
||||
-- Read back configuration from PWM Avalon-MM slave. Note that we have
|
||||
-- not started the PWM unit yet, so the new configuration must not be
|
||||
-- read back at this point (as per the register map).
|
||||
read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD);
|
||||
read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE);
|
||||
read_register_check(REG_CTRL_OFST, 0);
|
||||
|
||||
-- Start PWM
|
||||
write_register(REG_CTRL_OFST, CONFIG_CTRL_START);
|
||||
|
||||
-- Wait until PWM pulses for the first time after we sent START.
|
||||
wait until rising_edge(pwm_out);
|
||||
|
||||
-- Read back configuration from PWM Avalon-MM slave. Now that we have
|
||||
-- started the PWM unit, we should be able to read back the
|
||||
-- configuration we wrote (as per the register map).
|
||||
read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD);
|
||||
read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
|
||||
read_register_check(REG_CTRL_OFST, 0);
|
||||
|
||||
-- Wait for 2 PWM periods to finish
|
||||
wait for 2 * CLK_PERIOD * CONFIG_PERIOD;
|
||||
|
||||
-- Stop PWM.
|
||||
write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP);
|
||||
|
||||
-- Wait for PWM period to finish
|
||||
wait for 1 * CLK_PERIOD * CONFIG_PERIOD;
|
||||
|
||||
-- Instruct "clk_generation" process to halt execution.
|
||||
sim_finished <= true;
|
||||
|
||||
-- Make this process wait indefinitely (it will never re-execute from
|
||||
-- its beginning again).
|
||||
wait;
|
||||
end process simulation;
|
||||
end architecture rtl;
|
||||
|
||||
Reference in New Issue
Block a user