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choelzl
2022-04-07 18:54:11 +02:00
parent 15e7120d6d
commit 0fb3e365d4
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138
cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204.vhd Normal file
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-- #############################################################################
-- mcp3204.vhd
-- ===========
-- MCP3204 Avalon-MM slave interface.
--
-- Register map
-- +-------+-----------+--------+------------------------------------+
-- | RegNo | Name | Access | Description |
-- +-------+-----------+--------+------------------------------------+
-- | 0 | CHANNEL_0 | RO | 12-bit digital value of channel 0. |
-- +-------+-----------+--------+------------------------------------+
-- | 1 | CHANNEL_1 | RO | 12-bit digital value of channel 1. |
-- +-------+-----------+--------+------------------------------------+
-- | 2 | CHANNEL_2 | RO | 12-bit digital value of channel 2. |
-- +-------+-----------+--------+------------------------------------+
-- | 3 | CHANNEL_3 | RO | 12-bit digital value of channel 3. |
-- +-------+-----------+--------+------------------------------------+
--
-- Author : Philémon Favrod [philemon.favrod@epfl.ch]
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
-- Revision : 2
-- Last modified : 2018-03-06
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity mcp3204 is
port(
-- Avalon Clock interface
clk : in std_logic;
-- Avalon Reset interface
reset : in std_logic;
-- Avalon-MM Slave interface
address : in std_logic_vector(1 downto 0);
read : in std_logic;
readdata : out std_logic_vector(31 downto 0);
-- Avalon Conduit interface
CS_N : out std_logic;
MOSI : out std_logic;
MISO : in std_logic;
SCLK : out std_logic
);
end entity;
architecture arch of mcp3204 is
constant NUM_CHANNELS : positive := 4;
constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS))));
type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range);
signal data_reg : data_array;
signal spi_busy, spi_start, spi_datavalid : std_logic;
signal spi_channel : std_logic_vector(1 downto 0);
signal spi_data : std_logic_vector(11 downto 0);
type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA);
signal state : state_t;
signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0);
begin
SPI : entity work.mcp3204_spi
port map(
clk => clk,
reset => reset,
busy => spi_busy,
start => spi_start,
channel => spi_channel,
data_valid => spi_datavalid,
data => spi_data,
SCLK => SCLK,
CS_N => CS_N,
MOSI => MOSI,
MISO => MISO
);
-- FSM that dictates which channel is being read. The state of the component
-- should be thought as the pair (state, channel)
p_fsm : process(reset, clk)
begin
if reset = '1' then
state <= READY;
channel <= (others => '0');
elsif rising_edge(clk) then
case state is
when READY =>
if spi_busy = '0' then
state <= INIT_READ_CHANNEL;
end if;
when INIT_READ_CHANNEL =>
state <= WAIT_FOR_DATA;
when WAIT_FOR_DATA =>
if spi_datavalid = '1' then
state <= READY;
channel <= channel + 1;
end if;
end case;
end if;
end process p_fsm;
-- Updates the internal registers when a new data is available
p_data : process(reset, clk)
begin
if reset = '1' then
for i in 0 to NUM_CHANNELS - 1 loop
data_reg(i) <= (others => '0');
end loop;
elsif rising_edge(clk) then
if state = WAIT_FOR_DATA and spi_datavalid = '1' then
data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data;
end if;
end if;
end process p_data;
spi_start <= '1' when state = INIT_READ_CHANNEL else '0';
spi_channel <= std_logic_vector(channel);
-- Interface with the Avalon Switch Fabric
p_avalon_read : process(reset, clk)
begin
if reset = '1' then
readdata <= (others => '0');
elsif rising_edge(clk) then
if read = '1' then
readdata <= data_reg(to_integer(unsigned(address)));
end if;
end if;
end process p_avalon_read;
end architecture;

87
cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd Normal file
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-- #############################################################################
-- mcp3204_spi.vhd
-- ===============
-- MCP3204 SPI interface.
--
-- Author : Philémon Favrod [philemon.favrod@epfl.ch]
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
-- Author : <insert your name> (<insert your e-mail address>)
-- Revision : 1
-- Last modified : <insert date>
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mcp3204_spi is
port(
-- 50 MHz
clk : in std_logic;
reset : in std_logic;
busy : out std_logic;
start : in std_logic;
channel : in std_logic_vector(1 downto 0);
data_valid : out std_logic;
data : out std_logic_vector(11 downto 0);
-- 1 MHz
SCLK : out std_logic;
CS_N : out std_logic;
MOSI : out std_logic;
MISO : in std_logic
);
end mcp3204_spi;
architecture rtl of mcp3204_spi is
signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24
signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz
signal reg_rising_edge_sclk : std_logic := '0';
signal reg_falling_edge_sclk : std_logic := '0';
signal reg_sclk : std_logic := '0';
begin
clk_divider_generation : process(clk, reset)
begin
if reset = '1' then
reg_clk_divider_counter <= (others => '0');
elsif rising_edge(clk) then
reg_clk_divider_counter <= reg_clk_divider_counter + 1;
reg_spi_en <= '0';
reg_rising_edge_sclk <= '0';
reg_falling_edge_sclk <= '0';
if reg_clk_divider_counter = 24 then
reg_clk_divider_counter <= (others => '0');
reg_spi_en <= '1';
if reg_sclk = '0' then
reg_rising_edge_sclk <= '1';
elsif reg_sclk = '1' then
reg_falling_edge_sclk <= '1';
end if;
end if;
end if;
end process;
SCLK_generation : process(clk, reset)
begin
if reset = '1' then
reg_sclk <= '0';
elsif rising_edge(clk) then
if reg_spi_en = '1' then
reg_sclk <= not reg_sclk;
end if;
end if;
end process;
STATE_LOGIC : process(clk, reset)
begin
-- TODO: complete this process
if reset = '1' then
elsif rising_edge(clk) then
end if;
end process;
end architecture rtl;

103
cs309-psoc/lab_2_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd Normal file
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-- #############################################################################
-- tb_mcp3204_spi.vhd
-- ==================
-- Testbench for MCP3204 SPI interface.
--
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
-- Revision : 1
-- Last modified : 2018-03-06
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_mcp3204_spi is
end entity;
architecture rtl of tb_mcp3204_spi is
constant CLK_PERIOD : time := 20 ns;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal sim_finished : boolean := false;
-- mcp3204_spi ------------------------------------------------------------
signal busy : std_logic := '0';
signal start : std_logic := '0';
signal channel : std_logic_vector(1 downto 0) := (others => '0');
signal data_valid : std_logic := '0';
signal data : std_logic_vector(11 downto 0) := (others => '0');
signal SCLK : std_logic := '0';
signal CS_N : std_logic := '1';
signal MOSI : std_logic := '0';
signal MISO : std_logic := '0';
begin
duv : entity work.mcp3204_spi
port map(
clk => clk,
reset => reset,
busy => busy,
start => start,
channel => channel,
data_valid => data_valid,
data => data,
SCLK => SCLK,
CS_N => CS_N,
MOSI => MOSI,
MISO => MISO
);
clk <= not clk after CLK_PERIOD / 2 when not sim_finished;
sim : process
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
end procedure async_reset;
procedure spi_transfer(constant channel_number : natural range 0 to 3) is
begin
if busy = '1' then
wait until busy = '0';
else
wait until falling_edge(clk);
start <= '1';
channel <= std_logic_vector(to_unsigned(channel_number, channel'length));
wait until falling_edge(clk);
start <= '0';
channel <= (others => '0');
wait until rising_edge(data_valid);
wait until falling_edge(busy);
end if;
end procedure spi_transfer;
begin
async_reset;
MISO <= '1';
spi_transfer(0);
MISO <= '0';
spi_transfer(1);
MISO <= '1';
spi_transfer(2);
MISO <= '0';
spi_transfer(3);
sim_finished <= true;
wait;
end process sim;
end architecture rtl;