Disabled external gits
This commit is contained in:
@@ -0,0 +1,203 @@
|
||||
-- #############################################################################
|
||||
-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
|
||||
--
|
||||
-- BOARD : PrSoC extension board for DE0-Nano-SoC
|
||||
-- Author : Florian Depraz based on Sahand Kashani-Akhavan work
|
||||
-- Revision : 1.1
|
||||
-- Creation date : 06/02/2016
|
||||
--
|
||||
-- Syntax Rule : GROUP_NAME_N[bit]
|
||||
--
|
||||
-- GROUP : specify a particular interface (ex: SDR_)
|
||||
-- NAME : signal name (ex: CONFIG, D, ...)
|
||||
-- bit : signal index
|
||||
-- _N : to specify an active-low signal
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity DE0_Nano_SoC_PrSoC_extn_board_top_level is
|
||||
port(
|
||||
-------------------------------
|
||||
-- Comment ALL unused ports. --
|
||||
-------------------------------
|
||||
|
||||
-- CLOCK
|
||||
FPGA_CLK1_50 : in std_logic;
|
||||
-- FPGA_CLK2_50 : in std_logic;
|
||||
-- FPGA_CLK3_50 : in std_logic;
|
||||
|
||||
-- KEY on DE0 Nano SoC
|
||||
KEY_N : in std_logic_vector(1 downto 0);
|
||||
|
||||
-- LEDs on DE0 Nano SoC
|
||||
-- LED : out std_logic_vector(7 downto 0);
|
||||
|
||||
-- SWITCHES on DE0 Nano SoC
|
||||
-- SW : in std_logic_vector(3 downto 0);
|
||||
|
||||
-- Servomotors pwm
|
||||
SERVO_0 : out std_logic;
|
||||
SERVO_1 : out std_logic;
|
||||
|
||||
-- ADC Joysticks
|
||||
J0_SPI_CS_n : out std_logic;
|
||||
J0_SPI_MOSI : out std_logic;
|
||||
J0_SPI_MISO : in std_logic;
|
||||
J0_SPI_CLK : out std_logic;
|
||||
|
||||
-- Lepton
|
||||
CAM_TH_SPI_CS_N : out std_logic;
|
||||
CAM_TH_MISO : in std_logic;
|
||||
CAM_TH_MOSI : out std_logic;
|
||||
CAM_TH_CLK : out std_logic
|
||||
|
||||
-- PCA9637
|
||||
-- PIO_SCL : inout std_logic;
|
||||
-- PIO_SDA : inout std_logic;
|
||||
-- PIO_INT_N : in std_logic;
|
||||
-- RESET_N : out std_logic;
|
||||
|
||||
-- OV7670
|
||||
-- CAM_D : in std_logic_vector(9 downto 0);
|
||||
-- CAM_PIX_CLK : in std_logic;
|
||||
-- CAM_LV : in std_logic;
|
||||
-- CAM_FV : in std_logic;
|
||||
-- CAM_SYS_CLK : out std_logic;
|
||||
|
||||
-- VGA and LCD shared signals
|
||||
-- VIDEO_CLK : out std_logic;
|
||||
-- VIDEO_VSYNC : out std_logic;
|
||||
-- VIDEO_HSYNC : out std_logic;
|
||||
-- VIDEO_B : out std_logic_vector(7 downto 0);
|
||||
-- VIDEO_G : out std_logic_vector(7 downto 0);
|
||||
-- VIDEO_R : out std_logic_vector(7 downto 0);
|
||||
|
||||
-- LCD Specific signals
|
||||
-- LCD_DE : out std_logic;
|
||||
-- LCD_PIN_DAV_N : ? ?? std_logic;
|
||||
-- LCD_DISPLAY_EN : out std_logic;
|
||||
-- SPI_MISO : in std_logic;
|
||||
-- SPI_ENA_N : out std_logic;
|
||||
-- SPI_CLK : out std_logic;
|
||||
-- SPI_MOSI : out std_logic;
|
||||
-- SPI_DAT : inout std_logic;
|
||||
|
||||
-- I2C TOUCH SCREEN
|
||||
-- TS_SCL : inout std_logic;
|
||||
-- TS_SDA : inout std_logic;
|
||||
|
||||
-- BLUETOOTH (BLE)
|
||||
-- BLT_TXD : in std_logic;
|
||||
-- BLT_RXD : out std_logic;
|
||||
|
||||
-- I2C For VGA, PAL and OV7670 cameras
|
||||
-- CAM_PAL_VGA_SDA : inout std_logic;
|
||||
-- CAM_PAL_VGA_SCL : inout std_logic;
|
||||
|
||||
-- ONE WIRE
|
||||
-- BOARD_ID : inout std_logic;
|
||||
|
||||
-- PAL Camera
|
||||
-- PAL_VD_VD : in std_logic_vector(7 downto 0);
|
||||
-- PAL_VD_VSO : in std_logic;
|
||||
-- PAL_VD_HSO : in std_logic;
|
||||
-- PAL_VD_CLKO : in std_logic;
|
||||
-- PAL_PWDN : out std_logic;
|
||||
|
||||
-- WIFI
|
||||
-- FROM_ESP_TXD : in std_logic;
|
||||
-- TO_ESP_RXD : out std_logic;
|
||||
|
||||
-- LED RGB
|
||||
-- LED_BGR : out std_logic;
|
||||
|
||||
-- HPS
|
||||
-- HPS_CONV_USB_N : inout std_logic;
|
||||
-- HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
|
||||
-- HPS_DDR3_BA : out std_logic_vector(2 downto 0);
|
||||
-- HPS_DDR3_CAS_N : out std_logic;
|
||||
-- HPS_DDR3_CK_N : out std_logic;
|
||||
-- HPS_DDR3_CK_P : out std_logic;
|
||||
-- HPS_DDR3_CKE : out std_logic;
|
||||
|
||||
-- HPS_DDR3_CS_N : out std_logic;
|
||||
-- HPS_DDR3_DM : out std_logic_vector(3 downto 0);
|
||||
-- HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
|
||||
-- HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
|
||||
-- HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
|
||||
-- HPS_DDR3_ODT : out std_logic;
|
||||
-- HPS_DDR3_RAS_N : out std_logic;
|
||||
-- HPS_DDR3_RESET_N : out std_logic;
|
||||
-- HPS_DDR3_RZQ : in std_logic;
|
||||
-- HPS_DDR3_WE_N : out std_logic;
|
||||
-- HPS_ENET_GTX_CLK : out std_logic;
|
||||
-- HPS_ENET_INT_N : inout std_logic;
|
||||
-- HPS_ENET_MDC : out std_logic;
|
||||
-- HPS_ENET_MDIO : inout std_logic;
|
||||
-- HPS_ENET_RX_CLK : in std_logic;
|
||||
-- HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
|
||||
-- HPS_ENET_RX_DV : in std_logic;
|
||||
-- HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
|
||||
-- HPS_ENET_TX_EN : out std_logic;
|
||||
-- HPS_GSENSOR_INT : inout std_logic;
|
||||
-- HPS_I2C0_SCLK : inout std_logic;
|
||||
-- HPS_I2C0_SDAT : inout std_logic;
|
||||
-- HPS_I2C1_SCLK : inout std_logic;
|
||||
-- HPS_I2C1_SDAT : inout std_logic;
|
||||
-- HPS_KEY_N : inout std_logic;
|
||||
-- HPS_LED : inout std_logic;
|
||||
-- HPS_LTC_GPIO : inout std_logic;
|
||||
-- HPS_SD_CLK : out std_logic;
|
||||
-- HPS_SD_CMD : inout std_logic;
|
||||
-- HPS_SD_DATA : inout std_logic_vector(3 downto 0);
|
||||
-- HPS_SPIM_CLK : out std_logic;
|
||||
-- HPS_SPIM_MISO : in std_logic;
|
||||
-- HPS_SPIM_MOSI : out std_logic;
|
||||
-- HPS_SPIM_SS : inout std_logic;
|
||||
-- HPS_UART_RX : in std_logic;
|
||||
-- HPS_UART_TX : out std_logic;
|
||||
-- HPS_USB_CLKOUT : in std_logic;
|
||||
-- HPS_USB_DATA : inout std_logic_vector(7 downto 0);
|
||||
-- HPS_USB_DIR : in std_logic;
|
||||
-- HPS_USB_NXT : in std_logic;
|
||||
-- HPS_USB_STP : out std_logic
|
||||
);
|
||||
end entity DE0_Nano_SoC_PrSoC_extn_board_top_level;
|
||||
|
||||
architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is
|
||||
component soc_system is
|
||||
port (
|
||||
clk_clk : in std_logic := 'X'; -- clk
|
||||
lepton_0_conduit_end_mosi : out std_logic; -- mosi
|
||||
lepton_0_conduit_end_miso : in std_logic := 'X'; -- miso
|
||||
lepton_0_conduit_end_sclk : out std_logic; -- sclk
|
||||
lepton_0_conduit_end_cs_n : out std_logic; -- cs_n
|
||||
mcp3204_0_conduit_end_cs_n : out std_logic; -- cs_n
|
||||
mcp3204_0_conduit_end_miso : in std_logic := 'X'; -- miso
|
||||
mcp3204_0_conduit_end_mosi : out std_logic; -- mosi
|
||||
mcp3204_0_conduit_end_sclk : out std_logic; -- sclk
|
||||
pwm_0_conduit_end_pwm_out : out std_logic; -- pwm_out
|
||||
pwm_1_conduit_end_pwm_out : out std_logic; -- pwm_out
|
||||
reset_reset_n : in std_logic := 'X' -- reset_n
|
||||
);
|
||||
end component soc_system;
|
||||
begin
|
||||
u0 : component soc_system
|
||||
port map (
|
||||
clk_clk => FPGA_CLK1_50, -- clk.clk
|
||||
lepton_0_conduit_end_mosi => CAM_TH_MOSI, -- lepton_0_conduit_end.mosi
|
||||
lepton_0_conduit_end_miso => CAM_TH_MISO, -- .miso
|
||||
lepton_0_conduit_end_sclk => CAM_TH_CLK, -- .sclk
|
||||
lepton_0_conduit_end_cs_n => CAM_TH_SPI_CS_N, -- .cs_n
|
||||
mcp3204_0_conduit_end_cs_n => J0_SPI_CS_n, -- mcp3204_0_conduit_end.cs_n
|
||||
mcp3204_0_conduit_end_miso => J0_SPI_MISO, -- .miso
|
||||
mcp3204_0_conduit_end_mosi => J0_SPI_MOSI, -- .mosi
|
||||
mcp3204_0_conduit_end_sclk => J0_SPI_CLK, -- .sclk
|
||||
pwm_0_conduit_end_pwm_out => SERVO_0, -- pwm_0_conduit_end.pwm_out
|
||||
pwm_1_conduit_end_pwm_out => SERVO_1, -- pwm_1_conduit_end.pwm_out
|
||||
reset_reset_n => KEY_N(0) -- reset.reset_n
|
||||
);
|
||||
|
||||
end;
|
||||
138
cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204.vhd
Normal file
138
cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204.vhd
Normal file
@@ -0,0 +1,138 @@
|
||||
-- #############################################################################
|
||||
-- mcp3204.vhd
|
||||
-- ===========
|
||||
-- MCP3204 Avalon-MM slave interface.
|
||||
--
|
||||
-- Register map
|
||||
-- +-------+-----------+--------+------------------------------------+
|
||||
-- | RegNo | Name | Access | Description |
|
||||
-- +-------+-----------+--------+------------------------------------+
|
||||
-- | 0 | CHANNEL_0 | RO | 12-bit digital value of channel 0. |
|
||||
-- +-------+-----------+--------+------------------------------------+
|
||||
-- | 1 | CHANNEL_1 | RO | 12-bit digital value of channel 1. |
|
||||
-- +-------+-----------+--------+------------------------------------+
|
||||
-- | 2 | CHANNEL_2 | RO | 12-bit digital value of channel 2. |
|
||||
-- +-------+-----------+--------+------------------------------------+
|
||||
-- | 3 | CHANNEL_3 | RO | 12-bit digital value of channel 3. |
|
||||
-- +-------+-----------+--------+------------------------------------+
|
||||
--
|
||||
-- Author : Philémon Favrod [philemon.favrod@epfl.ch]
|
||||
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
|
||||
-- Revision : 2
|
||||
-- Last modified : 2018-03-06
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity mcp3204 is
|
||||
port(
|
||||
-- Avalon Clock interface
|
||||
clk : in std_logic;
|
||||
|
||||
-- Avalon Reset interface
|
||||
reset : in std_logic;
|
||||
|
||||
-- Avalon-MM Slave interface
|
||||
address : in std_logic_vector(1 downto 0);
|
||||
read : in std_logic;
|
||||
readdata : out std_logic_vector(31 downto 0);
|
||||
|
||||
-- Avalon Conduit interface
|
||||
CS_N : out std_logic;
|
||||
MOSI : out std_logic;
|
||||
MISO : in std_logic;
|
||||
SCLK : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture arch of mcp3204 is
|
||||
constant NUM_CHANNELS : positive := 4;
|
||||
constant CHANNEL_WIDTH : positive := integer(ceil(log2(real(NUM_CHANNELS))));
|
||||
|
||||
type data_array is array (NUM_CHANNELS - 1 downto 0) of std_logic_vector(readdata'range);
|
||||
signal data_reg : data_array;
|
||||
|
||||
signal spi_busy, spi_start, spi_datavalid : std_logic;
|
||||
signal spi_channel : std_logic_vector(1 downto 0);
|
||||
signal spi_data : std_logic_vector(11 downto 0);
|
||||
|
||||
type state_t is (READY, INIT_READ_CHANNEL, WAIT_FOR_DATA);
|
||||
signal state : state_t;
|
||||
|
||||
signal channel : unsigned(CHANNEL_WIDTH - 1 downto 0);
|
||||
|
||||
begin
|
||||
SPI : entity work.mcp3204_spi
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
busy => spi_busy,
|
||||
start => spi_start,
|
||||
channel => spi_channel,
|
||||
data_valid => spi_datavalid,
|
||||
data => spi_data,
|
||||
SCLK => SCLK,
|
||||
CS_N => CS_N,
|
||||
MOSI => MOSI,
|
||||
MISO => MISO
|
||||
);
|
||||
|
||||
-- FSM that dictates which channel is being read. The state of the component
|
||||
-- should be thought as the pair (state, channel)
|
||||
p_fsm : process(reset, clk)
|
||||
begin
|
||||
if reset = '1' then
|
||||
state <= READY;
|
||||
channel <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
case state is
|
||||
when READY =>
|
||||
if spi_busy = '0' then
|
||||
state <= INIT_READ_CHANNEL;
|
||||
end if;
|
||||
|
||||
when INIT_READ_CHANNEL =>
|
||||
state <= WAIT_FOR_DATA;
|
||||
|
||||
when WAIT_FOR_DATA =>
|
||||
if spi_datavalid = '1' then
|
||||
state <= READY;
|
||||
channel <= channel + 1;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end process p_fsm;
|
||||
|
||||
-- Updates the internal registers when a new data is available
|
||||
p_data : process(reset, clk)
|
||||
begin
|
||||
if reset = '1' then
|
||||
for i in 0 to NUM_CHANNELS - 1 loop
|
||||
data_reg(i) <= (others => '0');
|
||||
end loop;
|
||||
elsif rising_edge(clk) then
|
||||
if state = WAIT_FOR_DATA and spi_datavalid = '1' then
|
||||
data_reg(to_integer(channel)) <= (31 downto 12 => '0') & spi_data;
|
||||
end if;
|
||||
end if;
|
||||
end process p_data;
|
||||
|
||||
spi_start <= '1' when state = INIT_READ_CHANNEL else '0';
|
||||
spi_channel <= std_logic_vector(channel);
|
||||
|
||||
-- Interface with the Avalon Switch Fabric
|
||||
p_avalon_read : process(reset, clk)
|
||||
begin
|
||||
if reset = '1' then
|
||||
readdata <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if read = '1' then
|
||||
readdata <= data_reg(to_integer(unsigned(address)));
|
||||
end if;
|
||||
end if;
|
||||
end process p_avalon_read;
|
||||
|
||||
end architecture;
|
||||
87
cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd
Normal file
87
cs309-psoc/lab_2_1/hw/hdl/joysticks/hdl/mcp3204_spi.vhd
Normal file
@@ -0,0 +1,87 @@
|
||||
-- #############################################################################
|
||||
-- mcp3204_spi.vhd
|
||||
-- ===============
|
||||
-- MCP3204 SPI interface.
|
||||
--
|
||||
-- Author : Philémon Favrod [philemon.favrod@epfl.ch]
|
||||
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
|
||||
-- Author : <insert your name> (<insert your e-mail address>)
|
||||
-- Revision : 1
|
||||
-- Last modified : <insert date>
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity mcp3204_spi is
|
||||
port(
|
||||
-- 50 MHz
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
busy : out std_logic;
|
||||
start : in std_logic;
|
||||
channel : in std_logic_vector(1 downto 0);
|
||||
data_valid : out std_logic;
|
||||
data : out std_logic_vector(11 downto 0);
|
||||
|
||||
-- 1 MHz
|
||||
SCLK : out std_logic;
|
||||
CS_N : out std_logic;
|
||||
MOSI : out std_logic;
|
||||
MISO : in std_logic
|
||||
);
|
||||
end mcp3204_spi;
|
||||
|
||||
architecture rtl of mcp3204_spi is
|
||||
signal reg_clk_divider_counter : unsigned(4 downto 0) := (others => '0'); -- need to be able to count until 24
|
||||
signal reg_spi_en : std_logic := '0'; -- pulses every 0.5 MHz
|
||||
signal reg_rising_edge_sclk : std_logic := '0';
|
||||
signal reg_falling_edge_sclk : std_logic := '0';
|
||||
|
||||
signal reg_sclk : std_logic := '0';
|
||||
|
||||
begin
|
||||
clk_divider_generation : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
reg_clk_divider_counter <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
reg_clk_divider_counter <= reg_clk_divider_counter + 1;
|
||||
reg_spi_en <= '0';
|
||||
reg_rising_edge_sclk <= '0';
|
||||
reg_falling_edge_sclk <= '0';
|
||||
|
||||
if reg_clk_divider_counter = 24 then
|
||||
reg_clk_divider_counter <= (others => '0');
|
||||
reg_spi_en <= '1';
|
||||
|
||||
if reg_sclk = '0' then
|
||||
reg_rising_edge_sclk <= '1';
|
||||
elsif reg_sclk = '1' then
|
||||
reg_falling_edge_sclk <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
SCLK_generation : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
reg_sclk <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if reg_spi_en = '1' then
|
||||
reg_sclk <= not reg_sclk;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
STATE_LOGIC : process(clk, reset)
|
||||
begin
|
||||
-- TODO: complete this process
|
||||
if reset = '1' then
|
||||
elsif rising_edge(clk) then
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture rtl;
|
||||
103
cs309-psoc/lab_2_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd
Normal file
103
cs309-psoc/lab_2_1/hw/hdl/joysticks/tb/tb_mcp3204_spi.vhd
Normal file
@@ -0,0 +1,103 @@
|
||||
-- #############################################################################
|
||||
-- tb_mcp3204_spi.vhd
|
||||
-- ==================
|
||||
-- Testbench for MCP3204 SPI interface.
|
||||
--
|
||||
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
|
||||
-- Revision : 1
|
||||
-- Last modified : 2018-03-06
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tb_mcp3204_spi is
|
||||
end entity;
|
||||
|
||||
architecture rtl of tb_mcp3204_spi is
|
||||
constant CLK_PERIOD : time := 20 ns;
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '0';
|
||||
signal sim_finished : boolean := false;
|
||||
|
||||
-- mcp3204_spi ------------------------------------------------------------
|
||||
signal busy : std_logic := '0';
|
||||
signal start : std_logic := '0';
|
||||
signal channel : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal data_valid : std_logic := '0';
|
||||
signal data : std_logic_vector(11 downto 0) := (others => '0');
|
||||
signal SCLK : std_logic := '0';
|
||||
signal CS_N : std_logic := '1';
|
||||
signal MOSI : std_logic := '0';
|
||||
signal MISO : std_logic := '0';
|
||||
|
||||
begin
|
||||
duv : entity work.mcp3204_spi
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
busy => busy,
|
||||
start => start,
|
||||
channel => channel,
|
||||
data_valid => data_valid,
|
||||
data => data,
|
||||
SCLK => SCLK,
|
||||
CS_N => CS_N,
|
||||
MOSI => MOSI,
|
||||
MISO => MISO
|
||||
);
|
||||
|
||||
clk <= not clk after CLK_PERIOD / 2 when not sim_finished;
|
||||
|
||||
sim : process
|
||||
procedure async_reset is
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
wait for CLK_PERIOD / 4;
|
||||
reset <= '1';
|
||||
|
||||
wait for CLK_PERIOD / 2;
|
||||
reset <= '0';
|
||||
end procedure async_reset;
|
||||
|
||||
procedure spi_transfer(constant channel_number : natural range 0 to 3) is
|
||||
begin
|
||||
if busy = '1' then
|
||||
wait until busy = '0';
|
||||
|
||||
else
|
||||
wait until falling_edge(clk);
|
||||
start <= '1';
|
||||
channel <= std_logic_vector(to_unsigned(channel_number, channel'length));
|
||||
|
||||
wait until falling_edge(clk);
|
||||
start <= '0';
|
||||
channel <= (others => '0');
|
||||
|
||||
wait until rising_edge(data_valid);
|
||||
wait until falling_edge(busy);
|
||||
end if;
|
||||
end procedure spi_transfer;
|
||||
|
||||
begin
|
||||
async_reset;
|
||||
|
||||
MISO <= '1';
|
||||
spi_transfer(0);
|
||||
|
||||
MISO <= '0';
|
||||
spi_transfer(1);
|
||||
|
||||
MISO <= '1';
|
||||
spi_transfer(2);
|
||||
|
||||
MISO <= '0';
|
||||
spi_transfer(3);
|
||||
|
||||
sim_finished <= true;
|
||||
wait;
|
||||
end process sim;
|
||||
end architecture rtl;
|
||||
|
||||
|
||||
139
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd
Normal file
139
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/avalon_st_spi_master.vhd
Normal file
@@ -0,0 +1,139 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.utils.all;
|
||||
|
||||
entity avalon_st_spi_master is
|
||||
generic(
|
||||
INPUT_CLK_FREQ : integer := 50000000;
|
||||
SPI_SCLK_FREQ : integer := 10000000;
|
||||
CPOL : integer := 1;
|
||||
CPHA : integer := 1
|
||||
);
|
||||
port(
|
||||
-- Input clock
|
||||
clk : in std_logic;
|
||||
|
||||
-- Reset
|
||||
reset : in std_logic;
|
||||
spi_cs_n : in std_logic;
|
||||
-- Sink Avalon ST Interface
|
||||
mosi_sink_data : in std_logic_vector(7 downto 0);
|
||||
mosi_sink_valid : in std_logic;
|
||||
mosi_sink_ready : out std_logic;
|
||||
|
||||
-- Source Avalon ST Interface
|
||||
miso_src_data : out std_logic_vector(7 downto 0);
|
||||
miso_src_valid : out std_logic;
|
||||
|
||||
-- SPI Master signals
|
||||
SCLK : out std_logic;
|
||||
MISO : in std_logic;
|
||||
MOSI : out std_logic;
|
||||
CS_n : out std_logic
|
||||
);
|
||||
end avalon_st_spi_master;
|
||||
|
||||
architecture rtl of avalon_st_spi_master is
|
||||
constant SCLK_PRESCALER_MAX : integer := INPUT_CLK_FREQ / SPI_SCLK_FREQ / 2;
|
||||
signal sclk_prescaler : unsigned(bitlength(SCLK_PRESCALER_MAX) downto 0);
|
||||
signal sclk_toggle : std_logic;
|
||||
|
||||
signal new_sink_buffer, cur_sink_buffer : std_logic_vector(mosi_sink_data'range);
|
||||
signal new_sink_buffer_busy, cur_sink_buffer_busy : std_logic;
|
||||
|
||||
signal miso_src_buffer : std_logic_vector(7 downto 0);
|
||||
|
||||
signal spi_done, i_sclk : std_logic;
|
||||
signal spi_bit_index : unsigned(2 downto 0);
|
||||
begin
|
||||
CS_n <= spi_cs_n;
|
||||
|
||||
p_sclk_prescaler : process(clk, reset) is
|
||||
begin
|
||||
if reset = '1' then
|
||||
sclk_prescaler <= to_unsigned(1, sclk_prescaler'length);
|
||||
elsif rising_edge(clk) then
|
||||
if sclk_prescaler = SCLK_PRESCALER_MAX then
|
||||
sclk_prescaler <= to_unsigned(1, sclk_prescaler'length);
|
||||
else
|
||||
sclk_prescaler <= sclk_prescaler + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process p_sclk_prescaler;
|
||||
sclk_toggle <= '1' when sclk_prescaler = SCLK_PRESCALER_MAX else '0';
|
||||
|
||||
p_avalon_st_sink : process(clk, reset) is
|
||||
begin
|
||||
if reset = '1' then
|
||||
new_sink_buffer_busy <= '0';
|
||||
new_sink_buffer <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if mosi_sink_valid = '1' then
|
||||
if new_sink_buffer_busy = '0' and cur_sink_buffer_busy = '1' then
|
||||
new_sink_buffer <= mosi_sink_data;
|
||||
new_sink_buffer_busy <= '1';
|
||||
end if;
|
||||
elsif new_sink_buffer_busy = '1' and cur_sink_buffer_busy = '0' then
|
||||
new_sink_buffer_busy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process p_avalon_st_sink;
|
||||
mosi_sink_ready <= not new_sink_buffer_busy;
|
||||
|
||||
p_cur_buffer : process(clk, reset) is
|
||||
begin
|
||||
if reset = '1' then
|
||||
cur_sink_buffer <= (others => '0');
|
||||
cur_sink_buffer_busy <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if mosi_sink_valid = '1' and cur_sink_buffer_busy = '0' then
|
||||
cur_sink_buffer <= mosi_sink_data;
|
||||
cur_sink_buffer_busy <= '1';
|
||||
elsif cur_sink_buffer_busy = '0' and new_sink_buffer_busy = '1' then
|
||||
cur_sink_buffer <= new_sink_buffer;
|
||||
cur_sink_buffer_busy <= '1';
|
||||
elsif cur_sink_buffer_busy = '1' and spi_done = '1' then
|
||||
cur_sink_buffer_busy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process p_cur_buffer;
|
||||
|
||||
p_spi : process(clk, reset) is
|
||||
begin
|
||||
if reset = '1' then
|
||||
spi_done <= '0';
|
||||
i_sclk <= to_unsigned(CPOL, 1)(0);
|
||||
spi_bit_index <= "000";
|
||||
MOSI <= '0';
|
||||
miso_src_data <= (others => '0');
|
||||
miso_src_valid <= '0';
|
||||
miso_src_buffer <= (others => '0');
|
||||
|
||||
elsif rising_edge(clk) then
|
||||
spi_done <= '0';
|
||||
miso_src_valid <= '0';
|
||||
if cur_sink_buffer_busy = '1' and sclk_toggle = '1' then
|
||||
if i_sclk /= to_unsigned(CPHA, 1)(0) then
|
||||
if spi_bit_index = "111" then
|
||||
spi_done <= '1';
|
||||
spi_bit_index <= "000";
|
||||
miso_src_valid <= '1';
|
||||
miso_src_data <= miso_src_buffer(7 downto 1) & MISO;
|
||||
else
|
||||
MOSI <= cur_sink_buffer(7 - to_integer(spi_bit_index));
|
||||
miso_src_buffer(7 - to_integer(spi_bit_index)) <= MISO;
|
||||
spi_bit_index <= spi_bit_index + 1;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
i_sclk <= not i_sclk;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process p_spi;
|
||||
SCLK <= i_sclk;
|
||||
|
||||
end rtl;
|
||||
87
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/byte2pix.vhd
Normal file
87
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/byte2pix.vhd
Normal file
@@ -0,0 +1,87 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Title : Byte stream to pixel converter for the Lepton Camera
|
||||
-- Project : PrSoC
|
||||
-------------------------------------------------------------------------------
|
||||
-- File : byte2pix.vhd
|
||||
-- Author : Philemon Orphee Favrod <pofavrod@lappc5.epfl.ch>
|
||||
-- Company :
|
||||
-- Created : 2016-03-21
|
||||
-- Last update: 2017-03-19
|
||||
-- Platform :
|
||||
-- Standard : VHDL'87
|
||||
-------------------------------------------------------------------------------
|
||||
-- Description: Converts a byte stream to a 14-bit pixel stream.
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright (c) 2016
|
||||
-------------------------------------------------------------------------------
|
||||
-- Revisions :
|
||||
-- Date Version Author Description
|
||||
-- 2016-03-21 1.0 pofavrod Created
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity byte2pix is
|
||||
port(
|
||||
clk, reset : in std_logic;
|
||||
byte_data : in std_logic_vector(7 downto 0);
|
||||
byte_valid : in std_logic;
|
||||
byte_sof : in std_logic;
|
||||
byte_eof : in std_logic;
|
||||
pix_data : out std_logic_vector(13 downto 0);
|
||||
pix_valid : out std_logic;
|
||||
pix_sof : out std_logic;
|
||||
pix_eof : out std_logic);
|
||||
|
||||
end byte2pix;
|
||||
|
||||
architecture rtl of byte2pix is
|
||||
signal last_sof : std_logic;
|
||||
signal msb : std_logic_vector(5 downto 0);
|
||||
signal cnt : std_logic; -- used to skip msb sampling every other time
|
||||
begin
|
||||
process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
msb <= (others => '0');
|
||||
cnt <= '0';
|
||||
last_sof <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if byte_valid = '1' then
|
||||
if cnt = '0' then
|
||||
msb <= byte_data(5 downto 0);
|
||||
last_sof <= byte_sof;
|
||||
end if;
|
||||
cnt <= not cnt;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
pix_data <= (others => '0');
|
||||
pix_valid <= '0';
|
||||
pix_sof <= '0';
|
||||
pix_eof <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
pix_data <= (others => '0');
|
||||
pix_valid <= '0';
|
||||
pix_sof <= '0';
|
||||
pix_eof <= '0';
|
||||
|
||||
if byte_valid = '1' then
|
||||
if cnt = '1' then
|
||||
pix_data <= msb & byte_data;
|
||||
pix_valid <= '1';
|
||||
pix_sof <= last_sof;
|
||||
pix_eof <= byte_eof;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture rtl;
|
||||
192
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd
Normal file
192
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/dual_ported_ram.vhd
Normal file
@@ -0,0 +1,192 @@
|
||||
-- megafunction wizard: %RAM: 2-PORT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altsyncram
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: dual_ported_ram.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altsyncram
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
--the Altera MegaCore Function License Agreement, or other
|
||||
--applicable license agreement, including, without limitation,
|
||||
--that your use is for the sole purpose of programming logic
|
||||
--devices manufactured by Altera and sold by Altera or its
|
||||
--authorized distributors. Please refer to the applicable
|
||||
--agreement for further details.
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
library altera_mf;
|
||||
use altera_mf.altera_mf_components.all;
|
||||
|
||||
entity dual_ported_ram is
|
||||
port(
|
||||
clock : in std_logic := '1';
|
||||
data : in std_logic_vector(15 downto 0);
|
||||
rdaddress : in std_logic_vector(12 downto 0);
|
||||
wraddress : in std_logic_vector(12 downto 0);
|
||||
wren : in std_logic := '0';
|
||||
q : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end dual_ported_ram;
|
||||
|
||||
architecture SYN of dual_ported_ram is
|
||||
signal sub_wire0 : std_logic_vector(15 downto 0);
|
||||
|
||||
begin
|
||||
q <= sub_wire0(15 downto 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
generic map(
|
||||
address_aclr_b => "NONE",
|
||||
address_reg_b => "CLOCK0",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_input_b => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
intended_device_family => "Cyclone V",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 8192,
|
||||
numwords_b => 8192,
|
||||
operation_mode => "DUAL_PORT",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_b => "CLOCK0",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_mixed_ports => "DONT_CARE",
|
||||
widthad_a => 13,
|
||||
widthad_b => 13,
|
||||
width_a => 16,
|
||||
width_b => 16,
|
||||
width_byteena_a => 1
|
||||
)
|
||||
port map(
|
||||
address_a => wraddress,
|
||||
address_b => rdaddress,
|
||||
clock0 => clock,
|
||||
data_a => data,
|
||||
wren_a => wren,
|
||||
q_b => sub_wire0
|
||||
);
|
||||
|
||||
end SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
||||
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
|
||||
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
|
||||
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
|
||||
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
|
||||
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
|
||||
-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]"
|
||||
-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]"
|
||||
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
|
||||
-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
|
||||
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_ported_ram_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
288
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton.vhd
Normal file
288
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton.vhd
Normal file
@@ -0,0 +1,288 @@
|
||||
-- Lepton Avalon Memory-Mapped Slave Interface
|
||||
-- Author: Philémon Favrod (philemon.favrod@epfl.ch)
|
||||
-- Modified by: Sahand Kashani-Akhavan (sahand.kashani-akhavan@epfl.ch)
|
||||
-- Revision: 2
|
||||
|
||||
-- Register map
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | RegNo | Name | Access | Description |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 0 | COMMAND | WO | Command |
|
||||
-- | | | | - Writing 1 starts capturing a frame & resets the |
|
||||
-- | | | | ERROR bit (bit 1) in the STATUS register. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 1 | STATUS | RO | Status |
|
||||
-- | | | | - Bit 0: 0 --> no capture in progress. |
|
||||
-- | | | | 1 --> capture in progress. |
|
||||
-- | | | | - Bit 1: 0 --> previous capture successful. |
|
||||
-- | | | | 1 --> error during previous capture. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 2 | MIN | RO | Minimum pixel value in frame. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 3 | MAX | RO | Maximum pixel value in frame. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 4 | SUM_LSB | RO | Sum of all pixels in frame (low 16 bits). |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 5 | SUM_MSB | RO | Sum of all pixels in frame (high 16 bits). |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 6 | ROW_IDX | RO | Current line being captured (1 <= ROW_IDX <= 60). |
|
||||
-- | | | | Available for debugging purposes. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 7 | RESERVED | - | Reserved |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 8 - 4807 | RAW BUFFER | RO | View into RAW pixel buffer. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 4808 - 8191 | RESERVED | - | Reserved |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 8192 - 12991 | ADJUSTED BUFFER | RO | View into adjusted (scaled) pixel buffer. |
|
||||
-- | | | | Values are scaled between MIN and MAX. |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
-- | 12992 - 16383 | RESERVED | - | Reserved |
|
||||
-- +---------------+-----------------+--------+---------------------------------------------------+
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity lepton is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
address : in std_logic_vector(13 downto 0);
|
||||
readdata : out std_logic_vector(15 downto 0);
|
||||
writedata : in std_logic_vector(15 downto 0);
|
||||
read : in std_logic;
|
||||
write : in std_logic;
|
||||
|
||||
SCLK : out std_logic;
|
||||
CSn : out std_logic;
|
||||
MOSI : out std_logic;
|
||||
MISO : in std_logic
|
||||
);
|
||||
|
||||
end lepton;
|
||||
|
||||
architecture rtl of lepton is
|
||||
signal spi_cs_n : std_logic;
|
||||
signal spi_mosi_data : std_logic_vector(7 downto 0);
|
||||
signal spi_mosi_valid : std_logic;
|
||||
signal spi_mosi_ready : std_logic;
|
||||
signal spi_miso_data : std_logic_vector(7 downto 0);
|
||||
signal spi_miso_valid : std_logic;
|
||||
signal lepton_manager_start : std_logic;
|
||||
signal lepton_manager_error : std_logic;
|
||||
signal byte_data : std_logic_vector(7 downto 0);
|
||||
signal byte_valid : std_logic;
|
||||
signal byte_sof : std_logic;
|
||||
signal byte_eof : std_logic;
|
||||
signal pix_data : std_logic_vector(13 downto 0);
|
||||
signal pix_valid : std_logic;
|
||||
signal pix_sof : std_logic;
|
||||
signal pix_eof : std_logic;
|
||||
signal stat_min : std_logic_vector(13 downto 0);
|
||||
signal stat_max : std_logic_vector(13 downto 0);
|
||||
signal stat_sum : std_logic_vector(26 downto 0);
|
||||
signal stat_valid : std_logic;
|
||||
signal ram_data : std_logic_vector(15 downto 0);
|
||||
signal ram_wren : std_logic;
|
||||
signal ram_wraddress : std_logic_vector(12 downto 0);
|
||||
signal ram_rdaddress : std_logic_vector(12 downto 0);
|
||||
signal ram_q : std_logic_vector(15 downto 0);
|
||||
signal row_idx : std_logic_vector(5 downto 0);
|
||||
signal raw_pixel : std_logic_vector(13 downto 0);
|
||||
signal raw_max : std_logic_vector(13 downto 0);
|
||||
signal raw_min : std_logic_vector(13 downto 0);
|
||||
signal raw_sum : std_logic_vector(26 downto 0);
|
||||
signal adjusted_pixel : std_logic_vector(13 downto 0);
|
||||
|
||||
constant COMMAND_REG_OFFSET : std_logic_vector(address'range) := "00000000000000";
|
||||
constant STATUS_REG_OFFSET : std_logic_vector(address'range) := "00000000000001";
|
||||
constant MIN_REG_OFFSET : std_logic_vector(address'range) := "00000000000010";
|
||||
constant MAX_REG_OFFSET : std_logic_vector(address'range) := "00000000000011";
|
||||
constant SUM_LSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000100";
|
||||
constant SUM_MSB_REG_OFFSET : std_logic_vector(address'range) := "00000000000101";
|
||||
constant ROW_IDX_REG_OFFSET : std_logic_vector(address'range) := "00000000000110";
|
||||
constant BUFFER_REG_OFFSET : unsigned(address'range) := "00000000001000";
|
||||
constant ADJUSTED_BUFFER_REG_OFFSET : unsigned(address'range) := "10000000000000";
|
||||
|
||||
constant IMAGE_SIZE : integer := 80 * 60;
|
||||
constant BUFFER_REG_LIMIT : unsigned(address'range) := unsigned(BUFFER_REG_OFFSET) + IMAGE_SIZE;
|
||||
|
||||
constant ADJUSTED_BUFFER_LIMIT : unsigned(address'range) := unsigned(ADJUSTED_BUFFER_REG_OFFSET) + IMAGE_SIZE;
|
||||
|
||||
signal max_reg : std_logic_vector(stat_max'range);
|
||||
signal min_reg : std_logic_vector(stat_min'range);
|
||||
signal sum_reg : std_logic_vector(stat_sum'range);
|
||||
signal error_reg : std_logic;
|
||||
|
||||
begin
|
||||
spi_controller0 : entity work.avalon_st_spi_master
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
spi_cs_n => spi_cs_n,
|
||||
mosi_sink_data => spi_mosi_data,
|
||||
mosi_sink_valid => spi_mosi_valid,
|
||||
mosi_sink_ready => spi_mosi_ready,
|
||||
miso_src_data => spi_miso_data,
|
||||
miso_src_valid => spi_miso_valid,
|
||||
SCLK => SCLK,
|
||||
MISO => MISO,
|
||||
MOSI => MOSI,
|
||||
CS_n => CSn
|
||||
);
|
||||
|
||||
lepton_manager0 : entity work.lepton_manager
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
spi_miso_sink_data => spi_miso_data,
|
||||
spi_miso_sink_valid => spi_miso_valid,
|
||||
spi_mosi_src_data => spi_mosi_data,
|
||||
spi_mosi_src_valid => spi_mosi_valid,
|
||||
spi_mosi_src_ready => spi_mosi_ready,
|
||||
lepton_out_data => byte_data,
|
||||
lepton_out_valid => byte_valid,
|
||||
lepton_out_sof => byte_sof,
|
||||
lepton_out_eof => byte_eof,
|
||||
row_idx => row_idx,
|
||||
error => lepton_manager_error,
|
||||
start => lepton_manager_start,
|
||||
spi_cs_n => spi_cs_n
|
||||
);
|
||||
|
||||
byte2pix0 : entity work.byte2pix
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
byte_data => byte_data,
|
||||
byte_valid => byte_valid,
|
||||
byte_sof => byte_sof,
|
||||
byte_eof => byte_eof,
|
||||
pix_data => pix_data,
|
||||
pix_valid => pix_valid,
|
||||
pix_sof => pix_sof,
|
||||
pix_eof => pix_eof
|
||||
);
|
||||
|
||||
lepton_stats0 : entity work.lepton_stats
|
||||
port map(
|
||||
reset => reset,
|
||||
clk => clk,
|
||||
pix_data => pix_data,
|
||||
pix_valid => pix_valid,
|
||||
pix_sof => pix_sof,
|
||||
pix_eof => pix_eof,
|
||||
stat_min => stat_min,
|
||||
stat_max => stat_max,
|
||||
stat_sum => stat_sum,
|
||||
stat_valid => stat_valid
|
||||
);
|
||||
|
||||
ram_writer0 : entity work.ram_writer
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
pix_data => pix_data,
|
||||
pix_valid => pix_valid,
|
||||
pix_sof => pix_sof,
|
||||
pix_eof => pix_eof,
|
||||
ram_data => ram_data,
|
||||
ram_wren => ram_wren,
|
||||
ram_wraddress => ram_wraddress
|
||||
);
|
||||
|
||||
dual_ported_ram0 : entity work.dual_ported_ram
|
||||
port map(
|
||||
clock => clk,
|
||||
data => ram_data,
|
||||
rdaddress => ram_rdaddress,
|
||||
wraddress => ram_wraddress,
|
||||
wren => ram_wren,
|
||||
q => ram_q
|
||||
);
|
||||
|
||||
level_adjuster0 : entity work.level_adjuster
|
||||
port map(
|
||||
clk => clk,
|
||||
raw_pixel => ram_q(13 downto 0),
|
||||
raw_max => max_reg,
|
||||
raw_min => min_reg,
|
||||
raw_sum => sum_reg,
|
||||
adjusted_pixel => adjusted_pixel
|
||||
);
|
||||
|
||||
p_lepton_start : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
lepton_manager_start <= '0';
|
||||
error_reg <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if write = '1' and address = COMMAND_REG_OFFSET then
|
||||
lepton_manager_start <= writedata(0);
|
||||
error_reg <= '0';
|
||||
elsif pix_eof = '1' then
|
||||
lepton_manager_start <= '0';
|
||||
elsif lepton_manager_error = '1' then
|
||||
error_reg <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process p_lepton_start;
|
||||
|
||||
p_stat_reg : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
min_reg <= (others => '0');
|
||||
max_reg <= (others => '0');
|
||||
sum_reg <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if stat_valid = '1' then
|
||||
min_reg <= stat_min;
|
||||
max_reg <= stat_max;
|
||||
sum_reg <= stat_sum;
|
||||
end if;
|
||||
end if;
|
||||
end process p_stat_reg;
|
||||
|
||||
p_read : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
readdata <= (others => '0');
|
||||
ram_rdaddress <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
readdata <= (others => '0');
|
||||
if read = '1' then
|
||||
case address is
|
||||
when STATUS_REG_OFFSET =>
|
||||
readdata(1) <= error_reg;
|
||||
readdata(0) <= lepton_manager_start;
|
||||
|
||||
when MIN_REG_OFFSET =>
|
||||
readdata <= "00" & min_reg;
|
||||
|
||||
when MAX_REG_OFFSET =>
|
||||
readdata <= "00" & max_reg;
|
||||
|
||||
when SUM_MSB_REG_OFFSET =>
|
||||
readdata <= "00000" & sum_reg(26 downto 16);
|
||||
|
||||
when SUM_LSB_REG_OFFSET =>
|
||||
readdata <= sum_reg(15 downto 0);
|
||||
|
||||
when ROW_IDX_REG_OFFSET =>
|
||||
readdata(5 downto 0) <= row_idx;
|
||||
|
||||
when others =>
|
||||
if unsigned(address) >= BUFFER_REG_OFFSET and unsigned(address) < BUFFER_REG_LIMIT then
|
||||
ram_rdaddress <= std_logic_vector(resize(unsigned(address) - BUFFER_REG_OFFSET, ram_rdaddress'length));
|
||||
readdata <= ram_q;
|
||||
elsif unsigned(address) >= ADJUSTED_BUFFER_REG_OFFSET and unsigned(address) < ADJUSTED_BUFFER_LIMIT then
|
||||
ram_rdaddress <= std_logic_vector(resize(unsigned(address) - ADJUSTED_BUFFER_REG_OFFSET, ram_rdaddress'length));
|
||||
readdata <= "00" & adjusted_pixel;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process p_read;
|
||||
|
||||
end rtl;
|
||||
235
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton_manager.vhd
Normal file
235
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton_manager.vhd
Normal file
@@ -0,0 +1,235 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity lepton_manager is
|
||||
generic(
|
||||
INPUT_CLK_FREQ : integer := 50000000);
|
||||
port(
|
||||
clk : in std_logic := '0';
|
||||
reset : in std_logic := '0';
|
||||
|
||||
-- Avalon ST Sink to receive SPI data
|
||||
spi_miso_sink_data : in std_logic_vector(7 downto 0);
|
||||
spi_miso_sink_valid : in std_logic;
|
||||
|
||||
-- Avalon ST Source to send SPI data
|
||||
spi_mosi_src_data : out std_logic_vector(7 downto 0);
|
||||
spi_mosi_src_valid : out std_logic;
|
||||
spi_mosi_src_ready : in std_logic := '0';
|
||||
|
||||
-- Filtered output to retransmit cleaned data (without the discard packets, see Lepton Datasheet on page 31)
|
||||
-- lepton_out_data is valid on rising edge when lepton_src_valid = '1'
|
||||
lepton_out_data : out std_logic_vector(7 downto 0);
|
||||
lepton_out_valid : out std_logic;
|
||||
lepton_out_sof : out std_logic;
|
||||
lepton_out_eof : out std_logic;
|
||||
|
||||
-- Some status
|
||||
row_idx : out std_logic_vector(5 downto 0);
|
||||
error : out std_logic;
|
||||
|
||||
-- Avalon MM Slave interface for configuration
|
||||
start : in std_logic;
|
||||
|
||||
-- The SPI Chip Select (Active low !)
|
||||
spi_cs_n : out std_logic := '0');
|
||||
end entity lepton_manager;
|
||||
|
||||
architecture rtl of lepton_manager is
|
||||
type state_t is (Idle, CSn, ReadHeader, ReadPayload, DiscardPayload, WaitBeforeIdle);
|
||||
signal state, next_state : state_t;
|
||||
|
||||
signal header_3_last_nibbles : std_logic_vector(11 downto 0);
|
||||
|
||||
constant CLOCK_TICKS_PER_37_MS : integer := 37 * (INPUT_CLK_FREQ / 1e3); -- the timeout delay for a frame
|
||||
constant CLOCK_TICKS_PER_200_MS : integer := 200 * (INPUT_CLK_FREQ / 1e3);
|
||||
constant CLOCK_TICKS_PER_200_NS : integer := (200 * (INPUT_CLK_FREQ / 1e6)) / 1e3;
|
||||
constant BYTES_PER_HEADER : integer := 4;
|
||||
constant BYTES_PER_PAYLOAD : integer := 160;
|
||||
|
||||
constant NUMBER_OF_LINES_PER_FRAME : positive := 60;
|
||||
signal counter, counter_max : integer range 1 to CLOCK_TICKS_PER_200_MS;
|
||||
signal line_counter : integer range 1 to NUMBER_OF_LINES_PER_FRAME;
|
||||
signal timeout_counter : integer range 1 to CLOCK_TICKS_PER_37_MS;
|
||||
signal counter_enabled : boolean;
|
||||
signal waited_long_enough : boolean;
|
||||
signal header_end, payload_end : boolean;
|
||||
begin
|
||||
|
||||
-- purpose: register for state
|
||||
p_fsm : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
state <= Idle;
|
||||
elsif rising_edge(clk) then
|
||||
state <= next_state;
|
||||
end if;
|
||||
end process p_fsm;
|
||||
|
||||
-- purpose: compute the next state
|
||||
p_nsl : process(header_3_last_nibbles, header_end, payload_end, start, spi_miso_sink_valid, state, waited_long_enough, line_counter)
|
||||
begin
|
||||
next_state <= state;
|
||||
|
||||
case state is
|
||||
when Idle =>
|
||||
if waited_long_enough and start = '1' then
|
||||
next_state <= CSn;
|
||||
end if;
|
||||
|
||||
when CSn =>
|
||||
if waited_long_enough then
|
||||
next_state <= ReadHeader;
|
||||
end if;
|
||||
|
||||
when ReadHeader =>
|
||||
if header_end then
|
||||
if header_3_last_nibbles(11 downto 8) = X"F" then
|
||||
next_state <= DiscardPayload;
|
||||
else
|
||||
next_state <= ReadPayload;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when DiscardPayload | ReadPayload =>
|
||||
if payload_end then
|
||||
next_state <= ReadHeader;
|
||||
|
||||
if line_counter = NUMBER_OF_LINES_PER_FRAME then
|
||||
next_state <= WaitBeforeIdle;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when WaitBeforeIdle =>
|
||||
if spi_miso_sink_valid = '1' then
|
||||
next_state <= Idle;
|
||||
end if;
|
||||
|
||||
end case;
|
||||
end process p_nsl;
|
||||
|
||||
p_counter : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
counter <= 1;
|
||||
line_counter <= 1;
|
||||
elsif rising_edge(clk) then
|
||||
if counter = counter_max and counter_enabled then
|
||||
counter <= 1;
|
||||
|
||||
if state = ReadPayload then
|
||||
if line_counter = NUMBER_OF_LINES_PER_FRAME then
|
||||
line_counter <= 1;
|
||||
else
|
||||
line_counter <= line_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
elsif counter_enabled then
|
||||
counter <= counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process p_counter;
|
||||
|
||||
p_error : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
error <= '0';
|
||||
timeout_counter <= 1;
|
||||
elsif rising_edge(clk) then
|
||||
if state /= ReadHeader and state /= ReadPayload and state /= ReadHeader then
|
||||
timeout_counter <= 1;
|
||||
error <= '0';
|
||||
else
|
||||
if timeout_counter = CLOCK_TICKS_PER_37_MS then
|
||||
error <= '1';
|
||||
else
|
||||
timeout_counter <= timeout_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
if state = ReadPayload and header_3_last_nibbles /= std_logic_vector(to_unsigned(line_counter - 1, header_3_last_nibbles'length)) then
|
||||
error <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process p_error;
|
||||
|
||||
-- purpose: wire the datapath
|
||||
p_datapath : process(counter, counter_enabled, counter_max, line_counter, spi_miso_sink_data, spi_miso_sink_valid, spi_mosi_src_ready, state)
|
||||
variable counter_ended : boolean;
|
||||
|
||||
begin
|
||||
counter_max <= 1;
|
||||
counter_enabled <= true;
|
||||
waited_long_enough <= false;
|
||||
lepton_out_data <= (others => '0');
|
||||
lepton_out_valid <= '0';
|
||||
lepton_out_sof <= '0';
|
||||
lepton_out_eof <= '0';
|
||||
spi_mosi_src_valid <= '0';
|
||||
spi_mosi_src_data <= (others => '0');
|
||||
spi_cs_n <= '0';
|
||||
header_end <= false;
|
||||
payload_end <= false;
|
||||
|
||||
counter_ended := (counter = counter_max and counter_enabled);
|
||||
|
||||
case state is
|
||||
when Idle =>
|
||||
counter_max <= CLOCK_TICKS_PER_200_MS;
|
||||
waited_long_enough <= counter_ended;
|
||||
spi_cs_n <= '1';
|
||||
|
||||
when CSn =>
|
||||
counter_max <= CLOCK_TICKS_PER_200_NS;
|
||||
waited_long_enough <= counter_ended;
|
||||
|
||||
when ReadHeader =>
|
||||
counter_max <= BYTES_PER_HEADER;
|
||||
counter_enabled <= spi_miso_sink_valid = '1';
|
||||
header_end <= counter_ended;
|
||||
spi_mosi_src_valid <= spi_mosi_src_ready;
|
||||
|
||||
when ReadPayload =>
|
||||
counter_max <= BYTES_PER_PAYLOAD;
|
||||
counter_enabled <= spi_miso_sink_valid = '1';
|
||||
lepton_out_data <= spi_miso_sink_data;
|
||||
lepton_out_valid <= spi_miso_sink_valid;
|
||||
payload_end <= counter_ended;
|
||||
spi_mosi_src_valid <= spi_mosi_src_ready;
|
||||
if spi_miso_sink_valid = '1' then
|
||||
if counter = 1 and counter_enabled and line_counter = 1 then
|
||||
lepton_out_sof <= '1';
|
||||
elsif counter_ended and line_counter = NUMBER_OF_LINES_PER_FRAME then
|
||||
lepton_out_eof <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when DiscardPayload =>
|
||||
counter_max <= BYTES_PER_PAYLOAD;
|
||||
counter_enabled <= spi_miso_sink_valid = '1';
|
||||
payload_end <= counter_ended;
|
||||
spi_mosi_src_valid <= spi_mosi_src_ready;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end process p_datapath;
|
||||
|
||||
p_capture_header : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
header_3_last_nibbles <= X"000";
|
||||
elsif rising_edge(clk) then
|
||||
if state = ReadHeader and spi_miso_sink_valid = '1' then
|
||||
if counter = 1 then
|
||||
header_3_last_nibbles(11 downto 8) <= spi_miso_sink_data(3 downto 0);
|
||||
elsif counter = 2 then
|
||||
header_3_last_nibbles(7 downto 0) <= spi_miso_sink_data;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process p_capture_header;
|
||||
|
||||
row_idx <= std_logic_vector(to_unsigned(line_counter, row_idx'length));
|
||||
|
||||
end architecture rtl;
|
||||
78
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton_stats.vhd
Normal file
78
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lepton_stats.vhd
Normal file
@@ -0,0 +1,78 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity lepton_stats is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
pix_data : in std_logic_vector(13 downto 0);
|
||||
pix_valid : in std_logic;
|
||||
pix_sof : in std_logic;
|
||||
pix_eof : in std_logic;
|
||||
stat_min : out std_logic_vector(13 downto 0);
|
||||
stat_max : out std_logic_vector(13 downto 0);
|
||||
stat_sum : out std_logic_vector(26 downto 0);
|
||||
stat_valid : out std_logic);
|
||||
end lepton_stats;
|
||||
|
||||
architecture rtl of lepton_stats is
|
||||
|
||||
-- The accumulated sum, min and max of the pixel values
|
||||
signal curr_min : unsigned(13 downto 0);
|
||||
signal curr_max : unsigned(13 downto 0);
|
||||
signal curr_sum : unsigned(26 downto 0);
|
||||
|
||||
-- The next value of the registers
|
||||
signal next_min : unsigned(13 downto 0);
|
||||
signal next_max : unsigned(13 downto 0);
|
||||
signal next_sum : unsigned(26 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- This is the synchronous transition logic
|
||||
transition_logic : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
curr_sum <= (others => '0');
|
||||
curr_min <= (others => '0');
|
||||
curr_max <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
curr_min <= next_min;
|
||||
curr_max <= next_max;
|
||||
curr_sum <= next_sum;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- This is the combinatorial transition logic
|
||||
next_min <=
|
||||
curr_min when pix_valid = '0' else
|
||||
unsigned(pix_data) when pix_sof = '1' else
|
||||
curr_min when unsigned(pix_data) >= curr_min else
|
||||
unsigned(pix_data);
|
||||
|
||||
next_max <=
|
||||
curr_max when pix_valid = '0' else
|
||||
unsigned(pix_data) when pix_sof = '1' else
|
||||
curr_max when unsigned(pix_data) <= curr_max else
|
||||
unsigned(pix_data);
|
||||
|
||||
next_sum <=
|
||||
curr_sum when pix_valid = '0' else
|
||||
unsigned((26 downto 14 => '0') & pix_data) when pix_sof = '1' else
|
||||
curr_sum + unsigned((26 downto 14 => '0') & pix_data);
|
||||
|
||||
-- This is the synchronous output logic
|
||||
output_logic : process(clk, reset)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
stat_valid <= pix_eof;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- This is the combinatorial output logic
|
||||
stat_min <= std_logic_vector(curr_min);
|
||||
stat_max <= std_logic_vector(curr_max);
|
||||
stat_sum <= std_logic_vector(curr_sum);
|
||||
|
||||
end rtl;
|
||||
50
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/level_adjuster.vhd
Normal file
50
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/level_adjuster.vhd
Normal file
@@ -0,0 +1,50 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity level_adjuster is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
raw_pixel : in std_logic_vector(13 downto 0);
|
||||
raw_max : in std_logic_vector(13 downto 0);
|
||||
raw_min : in std_logic_vector(13 downto 0);
|
||||
raw_sum : in std_logic_vector(26 downto 0);
|
||||
adjusted_pixel : out std_logic_vector(13 downto 0));
|
||||
end level_adjuster;
|
||||
|
||||
architecture rtl of level_adjuster is
|
||||
component lpm_divider
|
||||
port(
|
||||
clock : in std_logic;
|
||||
denom : in std_logic_vector(13 downto 0);
|
||||
numer : in std_logic_vector(27 downto 0);
|
||||
quotient : out std_logic_vector(27 downto 0);
|
||||
remain : out std_logic_vector(13 downto 0));
|
||||
end component;
|
||||
|
||||
-- Intermediate signals needed by the divider
|
||||
signal numer : std_logic_vector(27 downto 0);
|
||||
signal denom : std_logic_vector(13 downto 0);
|
||||
signal quot : std_logic_vector(27 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Computation of the intermediate signals
|
||||
numer <= std_logic_vector((13 downto 0 => '1') * (unsigned(raw_pixel) - unsigned(raw_min)));
|
||||
denom <= std_logic_vector(unsigned(raw_max) - unsigned(raw_min));
|
||||
|
||||
-- We compute the remaineder of (x - min) / (max - min)
|
||||
divider : lpm_divider port map(
|
||||
clock => clk,
|
||||
numer => numer,
|
||||
denom => denom,
|
||||
quotient => quot,
|
||||
remain => open
|
||||
);
|
||||
|
||||
-- And we only keep the LSB of the quotient (we know the MSB must be 0)
|
||||
adjusted_pixel <=
|
||||
(adjusted_pixel'range => '0') when denom = (denom'range => '0') else
|
||||
quot(13 downto 0);
|
||||
|
||||
end rtl;
|
||||
133
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lpm_divider.vhd
Normal file
133
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/lpm_divider.vhd
Normal file
@@ -0,0 +1,133 @@
|
||||
-- megafunction wizard: %LPM_DIVIDE%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: LPM_DIVIDE
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: lpm_divider.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- LPM_DIVIDE
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- lpm
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
--the Altera MegaCore Function License Agreement, or other
|
||||
--applicable license agreement, including, without limitation,
|
||||
--that your use is for the sole purpose of programming logic
|
||||
--devices manufactured by Altera and sold by Altera or its
|
||||
--authorized distributors. Please refer to the applicable
|
||||
--agreement for further details.
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
library lpm;
|
||||
use lpm.all;
|
||||
|
||||
entity lpm_divider is
|
||||
port(
|
||||
clock : in std_logic;
|
||||
denom : in std_logic_vector(13 downto 0);
|
||||
numer : in std_logic_vector(27 downto 0);
|
||||
quotient : out std_logic_vector(27 downto 0);
|
||||
remain : out std_logic_vector(13 downto 0)
|
||||
);
|
||||
end lpm_divider;
|
||||
|
||||
architecture SYN of lpm_divider is
|
||||
signal sub_wire0 : std_logic_vector(27 downto 0);
|
||||
signal sub_wire1 : std_logic_vector(13 downto 0);
|
||||
|
||||
component lpm_divide
|
||||
generic(
|
||||
lpm_drepresentation : string;
|
||||
lpm_hint : string;
|
||||
lpm_nrepresentation : string;
|
||||
lpm_pipeline : natural;
|
||||
lpm_type : string;
|
||||
lpm_widthd : natural;
|
||||
lpm_widthn : natural
|
||||
);
|
||||
port(
|
||||
clock : in std_logic;
|
||||
denom : in std_logic_vector(13 downto 0);
|
||||
numer : in std_logic_vector(27 downto 0);
|
||||
quotient : out std_logic_vector(27 downto 0);
|
||||
remain : out std_logic_vector(13 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
quotient <= sub_wire0(27 downto 0);
|
||||
remain <= sub_wire1(13 downto 0);
|
||||
|
||||
LPM_DIVIDE_component : LPM_DIVIDE
|
||||
generic map(
|
||||
lpm_drepresentation => "UNSIGNED",
|
||||
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
|
||||
lpm_nrepresentation => "UNSIGNED",
|
||||
lpm_pipeline => 5,
|
||||
lpm_type => "LPM_DIVIDE",
|
||||
lpm_widthd => 14,
|
||||
lpm_widthn => 28
|
||||
)
|
||||
port map(
|
||||
clock => clock,
|
||||
denom => denom,
|
||||
numer => numer,
|
||||
quotient => sub_wire0,
|
||||
remain => sub_wire1
|
||||
);
|
||||
|
||||
end SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
|
||||
-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
|
||||
-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
|
||||
-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
|
||||
-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
|
||||
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "14"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "28"
|
||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
-- Retrieval info: USED_PORT: denom 0 0 14 0 INPUT NODEFVAL "denom[13..0]"
|
||||
-- Retrieval info: USED_PORT: numer 0 0 28 0 INPUT NODEFVAL "numer[27..0]"
|
||||
-- Retrieval info: USED_PORT: quotient 0 0 28 0 OUTPUT NODEFVAL "quotient[27..0]"
|
||||
-- Retrieval info: USED_PORT: remain 0 0 14 0 OUTPUT NODEFVAL "remain[13..0]"
|
||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @denom 0 0 14 0 denom 0 0 14 0
|
||||
-- Retrieval info: CONNECT: @numer 0 0 28 0 numer 0 0 28 0
|
||||
-- Retrieval info: CONNECT: quotient 0 0 28 0 @quotient 0 0 28 0
|
||||
-- Retrieval info: CONNECT: remain 0 0 14 0 @remain 0 0 14 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divider_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: lpm
|
||||
38
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/ram_writer.vhd
Normal file
38
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/ram_writer.vhd
Normal file
@@ -0,0 +1,38 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity ram_writer is
|
||||
port(
|
||||
clk, reset : in std_logic;
|
||||
pix_data : in std_logic_vector(13 downto 0);
|
||||
pix_valid : in std_logic;
|
||||
pix_sof : in std_logic;
|
||||
pix_eof : in std_logic;
|
||||
ram_data : out std_logic_vector(15 downto 0);
|
||||
ram_wren : out std_logic;
|
||||
ram_wraddress : out std_logic_vector(12 downto 0));
|
||||
|
||||
end ram_writer;
|
||||
|
||||
architecture rtl of ram_writer is
|
||||
signal wraddress_counter : unsigned(ram_wraddress'range);
|
||||
begin
|
||||
p_address_gen : process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
wraddress_counter <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if pix_eof = '1' then
|
||||
wraddress_counter <= (others => '0');
|
||||
elsif pix_valid = '1' then
|
||||
wraddress_counter <= wraddress_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process p_address_gen;
|
||||
|
||||
ram_data <= "00" & pix_data;
|
||||
ram_wren <= pix_valid;
|
||||
ram_wraddress <= std_logic_vector(wraddress_counter);
|
||||
|
||||
end rtl;
|
||||
27
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/utils.vhd
Normal file
27
cs309-psoc/lab_2_1/hw/hdl/lepton/hdl/utils.vhd
Normal file
@@ -0,0 +1,27 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
package utils is
|
||||
function bitlength(number : positive) return positive;
|
||||
|
||||
end package utils;
|
||||
|
||||
package body utils is
|
||||
|
||||
-- purpose: returns the minimum # of bits needed to represent the input number
|
||||
function bitlength(number : positive) return positive is
|
||||
variable acc : positive := 1;
|
||||
variable i : natural := 0;
|
||||
begin
|
||||
while True loop
|
||||
if acc > number then
|
||||
return i;
|
||||
end if;
|
||||
|
||||
acc := acc * 2;
|
||||
i := i + 1;
|
||||
end loop;
|
||||
end function bitlength;
|
||||
|
||||
end package body utils;
|
||||
77
cs309-psoc/lab_2_1/hw/hdl/lepton/tb/lepton_tb.vhd
Normal file
77
cs309-psoc/lab_2_1/hw/hdl/lepton/tb/lepton_tb.vhd
Normal file
@@ -0,0 +1,77 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity lepton_tb is
|
||||
end lepton_tb;
|
||||
|
||||
architecture tb of lepton_tb is
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '0';
|
||||
signal address : std_logic_vector(13 downto 0) := (others => '0');
|
||||
signal readdata : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal writedata : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal read : std_logic := '0';
|
||||
signal write : std_logic := '0';
|
||||
signal SCLK : std_logic := '0';
|
||||
signal CSn : std_logic := '0';
|
||||
signal MOSI : std_logic := '0';
|
||||
signal MISO : std_logic := '1';
|
||||
|
||||
constant CLK_PERIOD : time := 20 ns;
|
||||
|
||||
signal sim_ended : boolean := false;
|
||||
|
||||
begin
|
||||
dut : entity work.lepton
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
address => address,
|
||||
readdata => readdata,
|
||||
writedata => writedata,
|
||||
read => read,
|
||||
write => write,
|
||||
SCLK => SCLK,
|
||||
CSn => CSn,
|
||||
MOSI => MOSI,
|
||||
MISO => MISO
|
||||
);
|
||||
|
||||
clk <= not clk after CLK_PERIOD / 2 when not sim_ended else '0';
|
||||
|
||||
miso_gen : process
|
||||
variable seed1, seed2 : positive;
|
||||
variable rand : real;
|
||||
begin
|
||||
if sim_ended then
|
||||
wait;
|
||||
else
|
||||
uniform(seed1, seed2, rand);
|
||||
wait until rising_edge(SCLK);
|
||||
MISO <= to_unsigned(integer(rand), 1)(0);
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
stimuli : process
|
||||
begin
|
||||
reset <= '1';
|
||||
write <= '0';
|
||||
|
||||
wait for 2 * CLK_PERIOD;
|
||||
reset <= '0';
|
||||
|
||||
wait for CLK_PERIOD;
|
||||
write <= '1';
|
||||
writedata(0) <= '1';
|
||||
wait for CLK_PERIOD;
|
||||
write <= '0';
|
||||
|
||||
wait for 17 ms;
|
||||
sim_ended <= true;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
end tb;
|
||||
42
cs309-psoc/lab_2_1/hw/hdl/pantilt/hdl/pwm.vhd
Normal file
42
cs309-psoc/lab_2_1/hw/hdl/pantilt/hdl/pwm.vhd
Normal file
@@ -0,0 +1,42 @@
|
||||
-- #############################################################################
|
||||
-- pwm.vhd
|
||||
-- =======
|
||||
-- PWM memory-mapped Avalon slave interface.
|
||||
--
|
||||
-- Author : <insert your name> (<insert your e-mail address>)
|
||||
-- Author : <insert your name> (<insert your e-mail address>)
|
||||
-- Revision : <insert revision>
|
||||
-- Last modified : <insert date>
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.pwm_constants.all;
|
||||
|
||||
entity pwm is
|
||||
port(
|
||||
-- Avalon Clock interface
|
||||
clk : in std_logic;
|
||||
|
||||
-- Avalon Reset interface
|
||||
reset : in std_logic;
|
||||
|
||||
-- Avalon-MM Slave interface
|
||||
address : in std_logic_vector(1 downto 0);
|
||||
read : in std_logic;
|
||||
write : in std_logic;
|
||||
readdata : out std_logic_vector(31 downto 0);
|
||||
writedata : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- Avalon Conduit interface
|
||||
pwm_out : out std_logic
|
||||
);
|
||||
end pwm;
|
||||
|
||||
architecture rtl of pwm is
|
||||
|
||||
begin
|
||||
|
||||
end architecture rtl;
|
||||
61
cs309-psoc/lab_2_1/hw/hdl/pantilt/hdl/pwm_constants.vhd
Normal file
61
cs309-psoc/lab_2_1/hw/hdl/pantilt/hdl/pwm_constants.vhd
Normal file
@@ -0,0 +1,61 @@
|
||||
-- #############################################################################
|
||||
-- pwm_constants.vhd
|
||||
-- =================
|
||||
-- This package contains constants used in the PWM design files.
|
||||
--
|
||||
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
|
||||
-- Revision : 2
|
||||
-- Last modified : 2018-02-28
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
package pwm_constants is
|
||||
-- Register map
|
||||
-- +--------+------------+--------+------------------------------------------------------------------------------+
|
||||
-- | RegNo | Name | Access | Description |
|
||||
-- +--------+------------+--------+------------------------------------------------------------------------------+
|
||||
-- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. |
|
||||
-- | | | | |
|
||||
-- | | | | This value can be read/written while the unit is in the middle of an ongoing |
|
||||
-- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an |
|
||||
-- | | | | ongoing pulse, so we adopt the following semantics for this register: |
|
||||
-- | | | | |
|
||||
-- | | | | >> WRITING a value in this register indicates the NEW period to apply to the |
|
||||
-- | | | | next pulse. |
|
||||
-- | | | | |
|
||||
-- | | | | >> READING a value from this register indicates the CURRENT period of the |
|
||||
-- | | | | ongoing pulse. |
|
||||
-- +--------+------------+--------+------------------------------------------------------------------------------+
|
||||
-- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] |
|
||||
-- | | | | |
|
||||
-- | | | | This value can be read/written while the unit is in the middle of an ongoing |
|
||||
-- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an |
|
||||
-- | | | | ongoing pulse, so we adopt the following semantics for this register: |
|
||||
-- | | | | |
|
||||
-- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to |
|
||||
-- | | | | the next pulse. |
|
||||
-- | | | | |
|
||||
-- | | | | >> READING a value from this register indicates the CURRENT duty cycle of |
|
||||
-- | | | | the ongoing pulse. |
|
||||
-- +--------+------------+--------+------------------------------------------------------------------------------+
|
||||
-- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.|
|
||||
-- | | | | Writing 1 to this register starts the PWM. |
|
||||
-- | | | | |
|
||||
-- | | | | >> Reading this register always returns 0. |
|
||||
-- +--------+------------+--------+------------------------------------------------------------------------------+
|
||||
constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00";
|
||||
constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01";
|
||||
constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10";
|
||||
|
||||
-- Default values of registers after reset (BEFORE writing START to the CTRL
|
||||
-- register with a new configuration)
|
||||
constant DEFAULT_PERIOD : natural := 4;
|
||||
constant DEFAULT_DUTY_CYCLE : natural := 2;
|
||||
end package pwm_constants;
|
||||
|
||||
package body pwm_constants is
|
||||
|
||||
end package body pwm_constants;
|
||||
205
cs309-psoc/lab_2_1/hw/hdl/pantilt/tb/tb_pwm.vhd
Normal file
205
cs309-psoc/lab_2_1/hw/hdl/pantilt/tb/tb_pwm.vhd
Normal file
@@ -0,0 +1,205 @@
|
||||
-- #############################################################################
|
||||
-- tb_pwm.vhd
|
||||
-- ==========
|
||||
-- Testbench for PWM memory-mapped Avalon slave interface.
|
||||
--
|
||||
-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
|
||||
-- Revision : 2
|
||||
-- Last modified : 2018-02-28
|
||||
-- #############################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.pwm_constants.all;
|
||||
|
||||
entity tb_pwm is
|
||||
end entity;
|
||||
|
||||
architecture rtl of tb_pwm is
|
||||
|
||||
-- 50 MHz clock
|
||||
constant CLK_PERIOD : time := 20 ns;
|
||||
|
||||
-- Signal used to end simulator when we finished submitting our test cases
|
||||
signal sim_finished : boolean := false;
|
||||
|
||||
-- PWM PORTS
|
||||
signal clk : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal address : std_logic_vector(1 downto 0);
|
||||
signal read : std_logic;
|
||||
signal write : std_logic;
|
||||
signal readdata : std_logic_vector(31 downto 0);
|
||||
signal writedata : std_logic_vector(31 downto 0);
|
||||
signal pwm_out : std_logic;
|
||||
|
||||
-- Values of registers we are going to use to configure the PWM unit
|
||||
constant CONFIG_PERIOD : natural := 100;
|
||||
constant CONFIG_DUTY_CYCLE : natural := 20;
|
||||
constant CONFIG_CTRL_START : natural := 1;
|
||||
constant CONFIG_CTRL_STOP : natural := 0;
|
||||
|
||||
begin
|
||||
|
||||
-- Instantiate DUT
|
||||
dut : entity work.pwm
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
address => address,
|
||||
read => read,
|
||||
write => write,
|
||||
readdata => readdata,
|
||||
writedata => writedata,
|
||||
pwm_out => pwm_out
|
||||
);
|
||||
|
||||
-- Generate clk signal
|
||||
clk_generation : process
|
||||
begin
|
||||
if not sim_finished then
|
||||
clk <= '1';
|
||||
wait for CLK_PERIOD / 2;
|
||||
clk <= '0';
|
||||
wait for CLK_PERIOD / 2;
|
||||
else
|
||||
wait;
|
||||
end if;
|
||||
end process clk_generation;
|
||||
|
||||
-- Test PWM
|
||||
simulation : process
|
||||
|
||||
procedure async_reset is
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
wait for CLK_PERIOD / 4;
|
||||
|
||||
reset <= '1';
|
||||
wait for CLK_PERIOD / 2;
|
||||
|
||||
reset <= '0';
|
||||
wait for CLK_PERIOD / 4;
|
||||
end procedure async_reset;
|
||||
|
||||
procedure write_register(constant ofst : in std_logic_vector(1 downto 0);
|
||||
constant val : in natural) is
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
|
||||
address <= ofst;
|
||||
write <= '1';
|
||||
writedata <= std_logic_vector(to_unsigned(val, writedata'length));
|
||||
wait until rising_edge(clk);
|
||||
|
||||
address <= (others => '0');
|
||||
write <= '0';
|
||||
writedata <= (others => '0');
|
||||
wait until rising_edge(clk);
|
||||
end procedure write_register;
|
||||
|
||||
procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
|
||||
address <= ofst;
|
||||
read <= '1';
|
||||
-- The read has a 1 cycle wait-state, so we need to keep the read
|
||||
-- signal high for 2 clock cycles.
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
|
||||
address <= (others => '0');
|
||||
read <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure read_register;
|
||||
|
||||
procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0);
|
||||
constant expected_val : in natural) is
|
||||
begin
|
||||
read_register(ofst);
|
||||
|
||||
case ofst is
|
||||
when REG_PERIOD_OFST =>
|
||||
assert to_integer(unsigned(readdata)) = expected_val
|
||||
report "Unexpected PERIOD: " &
|
||||
"PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " &
|
||||
"PERIOD_expected = " & integer'image(expected_val)
|
||||
severity error;
|
||||
|
||||
when REG_DUTY_CYCLE_OFST =>
|
||||
assert to_integer(unsigned(readdata)) = expected_val
|
||||
report "Unexpected DUTY_CYCLE: " &
|
||||
"DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " &
|
||||
"DUTY_CYCLE_expected = " & integer'image(expected_val)
|
||||
severity error;
|
||||
|
||||
when REG_CTRL_OFST =>
|
||||
assert to_integer(unsigned(readdata)) = expected_val
|
||||
report "Unexpected CTRL: " &
|
||||
"CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " &
|
||||
"CTRL_expected = " & integer'image(expected_val)
|
||||
severity error;
|
||||
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end procedure read_register_check;
|
||||
|
||||
begin
|
||||
|
||||
-- Default values
|
||||
reset <= '0';
|
||||
address <= (others => '0');
|
||||
read <= '0';
|
||||
write <= '0';
|
||||
writedata <= (others => '0');
|
||||
wait until rising_edge(clk);
|
||||
|
||||
-- Reset the circuit
|
||||
async_reset;
|
||||
|
||||
-- Write desired configuration to PWM Avalon-MM slave.
|
||||
write_register(REG_PERIOD_OFST, CONFIG_PERIOD);
|
||||
write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
|
||||
|
||||
-- Read back configuration from PWM Avalon-MM slave. Note that we have
|
||||
-- not started the PWM unit yet, so the new configuration must not be
|
||||
-- read back at this point (as per the register map).
|
||||
read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD);
|
||||
read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE);
|
||||
read_register_check(REG_CTRL_OFST, 0);
|
||||
|
||||
-- Start PWM
|
||||
write_register(REG_CTRL_OFST, CONFIG_CTRL_START);
|
||||
|
||||
-- Wait until PWM pulses for the first time after we sent START.
|
||||
wait until rising_edge(pwm_out);
|
||||
|
||||
-- Read back configuration from PWM Avalon-MM slave. Now that we have
|
||||
-- started the PWM unit, we should be able to read back the
|
||||
-- configuration we wrote (as per the register map).
|
||||
read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD);
|
||||
read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
|
||||
read_register_check(REG_CTRL_OFST, 0);
|
||||
|
||||
-- Wait for 2 PWM periods to finish
|
||||
wait for 2 * CLK_PERIOD * CONFIG_PERIOD;
|
||||
|
||||
-- Stop PWM.
|
||||
write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP);
|
||||
|
||||
-- Wait for PWM period to finish
|
||||
wait for 1 * CLK_PERIOD * CONFIG_PERIOD;
|
||||
|
||||
-- Instruct "clk_generation" process to halt execution.
|
||||
sim_finished <= true;
|
||||
|
||||
-- Make this process wait indefinitely (it will never re-execute from
|
||||
-- its beginning again).
|
||||
wait;
|
||||
end process simulation;
|
||||
end architecture rtl;
|
||||
|
||||
31
cs309-psoc/lab_2_1/hw/quartus/lab_2_1.qpf
Normal file
31
cs309-psoc/lab_2_1/hw/quartus/lab_2_1.qpf
Normal file
@@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
# the Altera MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Altera and sold by Altera or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
|
||||
# Date created = 11:03:02 February 05, 2016
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "15.1"
|
||||
DATE = "11:03:02 February 05, 2016"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "lab_2_1"
|
||||
811
cs309-psoc/lab_2_1/hw/quartus/lab_2_1.qsf
Normal file
811
cs309-psoc/lab_2_1/hw/quartus/lab_2_1.qsf
Normal file
@@ -0,0 +1,811 @@
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
|
||||
|
||||
set_global_assignment -name SMART_RECOMPILE OFF
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
|
||||
set_global_assignment -name SDC_FILE lab_2_1.sdc
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name DEVICE 5CSEMA4U23C6
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
|
||||
|
||||
#============================================================
|
||||
# ADC
|
||||
#============================================================
|
||||
set_location_assignment PIN_U9 -to ADC_CONVST
|
||||
set_location_assignment PIN_V10 -to ADC_SCK
|
||||
set_location_assignment PIN_AC4 -to ADC_SDI
|
||||
set_location_assignment PIN_AD4 -to ADC_SDO
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
|
||||
|
||||
#============================================================
|
||||
# ARDUINO Extention OV7670 CAMERA
|
||||
#============================================================
|
||||
set_location_assignment PIN_AE15 -to CAM_D[0]
|
||||
set_location_assignment PIN_AE15 -to CAM_D_0
|
||||
set_location_assignment PIN_AF17 -to CAM_D[1]
|
||||
set_location_assignment PIN_AF17 -to CAM_D_1
|
||||
set_location_assignment PIN_AH8 -to CAM_D[2]
|
||||
set_location_assignment PIN_AH8 -to CAM_D_2
|
||||
set_location_assignment PIN_AG8 -to CAM_D[3]
|
||||
set_location_assignment PIN_AG8 -to CAM_D_3
|
||||
set_location_assignment PIN_U13 -to CAM_D[4]
|
||||
set_location_assignment PIN_U13 -to CAM_D_4
|
||||
set_location_assignment PIN_U14 -to CAM_D[5]
|
||||
set_location_assignment PIN_U14 -to CAM_D_5
|
||||
set_location_assignment PIN_AG9 -to CAM_D[6]
|
||||
set_location_assignment PIN_AG9 -to CAM_D_6
|
||||
set_location_assignment PIN_AG10 -to CAM_D[7]
|
||||
set_location_assignment PIN_AG10 -to CAM_D_7
|
||||
set_location_assignment PIN_AF13 -to CAM_D[8]
|
||||
set_location_assignment PIN_AF13 -to CAM_D_8
|
||||
set_location_assignment PIN_AG13 -to CAM_D[9]
|
||||
set_location_assignment PIN_AG13 -to CAM_D_9
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9
|
||||
|
||||
#============================================================
|
||||
# Arduino Extension LEPTON CAMERA THERMAL CAM_TH
|
||||
#============================================================
|
||||
set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N
|
||||
set_location_assignment PIN_AG16 -to CAM_TH_MOSI
|
||||
set_location_assignment PIN_AH11 -to CAM_TH_MISO
|
||||
set_location_assignment PIN_AH12 -to CAM_TH_CLK
|
||||
set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA
|
||||
set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL
|
||||
|
||||
set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
set_location_assignment PIN_V11 -to FPGA_CLK1_50
|
||||
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
|
||||
set_location_assignment PIN_E11 -to FPGA_CLK3_50
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
|
||||
|
||||
#============================================================
|
||||
# HPS
|
||||
#============================================================
|
||||
set_location_assignment PIN_C6 -to HPS_CONV_USB_N
|
||||
set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0]
|
||||
set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0
|
||||
set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1]
|
||||
set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1
|
||||
set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2]
|
||||
set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2
|
||||
set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3]
|
||||
set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3
|
||||
set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4]
|
||||
set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4
|
||||
set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5]
|
||||
set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5
|
||||
set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6]
|
||||
set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6
|
||||
set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7]
|
||||
set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7
|
||||
set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8]
|
||||
set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8
|
||||
set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9]
|
||||
set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9
|
||||
set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10]
|
||||
set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10
|
||||
set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11]
|
||||
set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11
|
||||
set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12]
|
||||
set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12
|
||||
set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13]
|
||||
set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13
|
||||
set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14]
|
||||
set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14
|
||||
set_location_assignment PIN_A27 -to HPS_DDR3_BA[0]
|
||||
set_location_assignment PIN_A27 -to HPS_DDR3_BA_0
|
||||
set_location_assignment PIN_H25 -to HPS_DDR3_BA[1]
|
||||
set_location_assignment PIN_H25 -to HPS_DDR3_BA_1
|
||||
set_location_assignment PIN_G25 -to HPS_DDR3_BA[2]
|
||||
set_location_assignment PIN_G25 -to HPS_DDR3_BA_2
|
||||
set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N
|
||||
set_location_assignment PIN_L28 -to HPS_DDR3_CKE
|
||||
set_location_assignment PIN_N20 -to HPS_DDR3_CK_N
|
||||
set_location_assignment PIN_N21 -to HPS_DDR3_CK_P
|
||||
set_location_assignment PIN_L21 -to HPS_DDR3_CS_N
|
||||
set_location_assignment PIN_G28 -to HPS_DDR3_DM[0]
|
||||
set_location_assignment PIN_G28 -to HPS_DDR3_DM_0
|
||||
set_location_assignment PIN_P28 -to HPS_DDR3_DM[1]
|
||||
set_location_assignment PIN_P28 -to HPS_DDR3_DM_1
|
||||
set_location_assignment PIN_W28 -to HPS_DDR3_DM[2]
|
||||
set_location_assignment PIN_W28 -to HPS_DDR3_DM_2
|
||||
set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3]
|
||||
set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3
|
||||
set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0]
|
||||
set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0
|
||||
set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1]
|
||||
set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1
|
||||
set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2]
|
||||
set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2
|
||||
set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3]
|
||||
set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3
|
||||
set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4]
|
||||
set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4
|
||||
set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5]
|
||||
set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5
|
||||
set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6]
|
||||
set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6
|
||||
set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7]
|
||||
set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7
|
||||
set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8]
|
||||
set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8
|
||||
set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9]
|
||||
set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9
|
||||
set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10]
|
||||
set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10
|
||||
set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11]
|
||||
set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11
|
||||
set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12]
|
||||
set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12
|
||||
set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13]
|
||||
set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13
|
||||
set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14]
|
||||
set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14
|
||||
set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15]
|
||||
set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15
|
||||
set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16]
|
||||
set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16
|
||||
set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17]
|
||||
set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17
|
||||
set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18]
|
||||
set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18
|
||||
set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19]
|
||||
set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19
|
||||
set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20]
|
||||
set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20
|
||||
set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21]
|
||||
set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21
|
||||
set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22]
|
||||
set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22
|
||||
set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23]
|
||||
set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23
|
||||
set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24]
|
||||
set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24
|
||||
set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25]
|
||||
set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25
|
||||
set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26]
|
||||
set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26
|
||||
set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27]
|
||||
set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27
|
||||
set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28]
|
||||
set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28
|
||||
set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29]
|
||||
set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29
|
||||
set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30]
|
||||
set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30
|
||||
set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31]
|
||||
set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31
|
||||
set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0]
|
||||
set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0
|
||||
set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1]
|
||||
set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1
|
||||
set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2]
|
||||
set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2
|
||||
set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3]
|
||||
set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3
|
||||
set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0]
|
||||
set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0
|
||||
set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1]
|
||||
set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1
|
||||
set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2]
|
||||
set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2
|
||||
set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3]
|
||||
set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3
|
||||
set_location_assignment PIN_D28 -to HPS_DDR3_ODT
|
||||
set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N
|
||||
set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N
|
||||
set_location_assignment PIN_D25 -to HPS_DDR3_RZQ
|
||||
set_location_assignment PIN_E25 -to HPS_DDR3_WE_N
|
||||
set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK
|
||||
set_location_assignment PIN_B14 -to HPS_ENET_INT_N
|
||||
set_location_assignment PIN_A13 -to HPS_ENET_MDC
|
||||
set_location_assignment PIN_E16 -to HPS_ENET_MDIO
|
||||
set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK
|
||||
set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0]
|
||||
set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0
|
||||
set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1]
|
||||
set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1
|
||||
set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2]
|
||||
set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2
|
||||
set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3]
|
||||
set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3
|
||||
set_location_assignment PIN_J13 -to HPS_ENET_RX_DV
|
||||
set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0]
|
||||
set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0
|
||||
set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1]
|
||||
set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1
|
||||
set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2]
|
||||
set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2
|
||||
set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3]
|
||||
set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3
|
||||
set_location_assignment PIN_A12 -to HPS_ENET_TX_EN
|
||||
set_location_assignment PIN_A17 -to HPS_GSENSOR_INT
|
||||
set_location_assignment PIN_C18 -to HPS_I2C0_SCLK
|
||||
set_location_assignment PIN_A19 -to HPS_I2C0_SDAT
|
||||
set_location_assignment PIN_K18 -to HPS_I2C1_SCLK
|
||||
set_location_assignment PIN_A21 -to HPS_I2C1_SDAT
|
||||
set_location_assignment PIN_J18 -to HPS_KEY_N
|
||||
set_location_assignment PIN_A20 -to HPS_LED
|
||||
set_location_assignment PIN_H13 -to HPS_LTC_GPIO
|
||||
set_location_assignment PIN_B8 -to HPS_SD_CLK
|
||||
set_location_assignment PIN_D14 -to HPS_SD_CMD
|
||||
set_location_assignment PIN_C13 -to HPS_SD_DATA[0]
|
||||
set_location_assignment PIN_C13 -to HPS_SD_DATA_0
|
||||
set_location_assignment PIN_B6 -to HPS_SD_DATA[1]
|
||||
set_location_assignment PIN_B6 -to HPS_SD_DATA_1
|
||||
set_location_assignment PIN_B11 -to HPS_SD_DATA[2]
|
||||
set_location_assignment PIN_B11 -to HPS_SD_DATA_2
|
||||
set_location_assignment PIN_B9 -to HPS_SD_DATA[3]
|
||||
set_location_assignment PIN_B9 -to HPS_SD_DATA_3
|
||||
set_location_assignment PIN_C19 -to HPS_SPIM_CLK
|
||||
set_location_assignment PIN_B19 -to HPS_SPIM_MISO
|
||||
set_location_assignment PIN_B16 -to HPS_SPIM_MOSI
|
||||
set_location_assignment PIN_C16 -to HPS_SPIM_SS
|
||||
set_location_assignment PIN_A22 -to HPS_UART_RX
|
||||
set_location_assignment PIN_B21 -to HPS_UART_TX
|
||||
set_location_assignment PIN_G4 -to HPS_USB_CLKOUT
|
||||
set_location_assignment PIN_C10 -to HPS_USB_DATA[0]
|
||||
set_location_assignment PIN_C10 -to HPS_USB_DATA_0
|
||||
set_location_assignment PIN_F5 -to HPS_USB_DATA[1]
|
||||
set_location_assignment PIN_F5 -to HPS_USB_DATA_1
|
||||
set_location_assignment PIN_C9 -to HPS_USB_DATA[2]
|
||||
set_location_assignment PIN_C9 -to HPS_USB_DATA_2
|
||||
set_location_assignment PIN_C4 -to HPS_USB_DATA[3]
|
||||
set_location_assignment PIN_C4 -to HPS_USB_DATA_3
|
||||
set_location_assignment PIN_C8 -to HPS_USB_DATA[4]
|
||||
set_location_assignment PIN_C8 -to HPS_USB_DATA_4
|
||||
set_location_assignment PIN_D4 -to HPS_USB_DATA[5]
|
||||
set_location_assignment PIN_D4 -to HPS_USB_DATA_5
|
||||
set_location_assignment PIN_C7 -to HPS_USB_DATA[6]
|
||||
set_location_assignment PIN_C7 -to HPS_USB_DATA_6
|
||||
set_location_assignment PIN_F4 -to HPS_USB_DATA[7]
|
||||
set_location_assignment PIN_F4 -to HPS_USB_DATA_7
|
||||
set_location_assignment PIN_E5 -to HPS_USB_DIR
|
||||
set_location_assignment PIN_D5 -to HPS_USB_NXT
|
||||
set_location_assignment PIN_C5 -to HPS_USB_STP
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
|
||||
|
||||
#============================================================
|
||||
# KEY_N
|
||||
#============================================================
|
||||
set_location_assignment PIN_AH17 -to KEY_N[0]
|
||||
set_location_assignment PIN_AH17 -to KEY_N_0
|
||||
set_location_assignment PIN_AH16 -to KEY_N[1]
|
||||
set_location_assignment PIN_AH16 -to KEY_N_1
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
set_location_assignment PIN_W15 -to LED[0]
|
||||
set_location_assignment PIN_W15 -to LED_0
|
||||
set_location_assignment PIN_AA24 -to LED[1]
|
||||
set_location_assignment PIN_AA24 -to LED_1
|
||||
set_location_assignment PIN_V16 -to LED[2]
|
||||
set_location_assignment PIN_V16 -to LED_2
|
||||
set_location_assignment PIN_V15 -to LED[3]
|
||||
set_location_assignment PIN_V15 -to LED_3
|
||||
set_location_assignment PIN_AF26 -to LED[4]
|
||||
set_location_assignment PIN_AF26 -to LED_4
|
||||
set_location_assignment PIN_AE26 -to LED[5]
|
||||
set_location_assignment PIN_AE26 -to LED_5
|
||||
set_location_assignment PIN_Y16 -to LED[6]
|
||||
set_location_assignment PIN_Y16 -to LED_6
|
||||
set_location_assignment PIN_AA23 -to LED[7]
|
||||
set_location_assignment PIN_AA23 -to LED_7
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7
|
||||
|
||||
#============================================================
|
||||
# SW
|
||||
#============================================================
|
||||
set_location_assignment PIN_L10 -to SW[0]
|
||||
set_location_assignment PIN_L10 -to SW_0
|
||||
set_location_assignment PIN_L9 -to SW[1]
|
||||
set_location_assignment PIN_L9 -to SW_1
|
||||
set_location_assignment PIN_H6 -to SW[2]
|
||||
set_location_assignment PIN_H6 -to SW_2
|
||||
set_location_assignment PIN_H5 -to SW[3]
|
||||
set_location_assignment PIN_H5 -to SW_3
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3
|
||||
|
||||
#============================================================
|
||||
# GPIO_0, GPIO_0 connect to GPIO Default
|
||||
#============================================================
|
||||
set_location_assignment PIN_V12 -to PIO_INT_N
|
||||
set_location_assignment PIN_AE11 -to PIO_SCL
|
||||
set_location_assignment PIN_AE12 -to PIO_SDA
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA
|
||||
|
||||
set_location_assignment PIN_AF7 -to PIR_OUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT
|
||||
|
||||
set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA
|
||||
set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL
|
||||
set_location_assignment PIN_T11 -to CAM_SYS_CLK
|
||||
set_location_assignment PIN_AG6 -to CAM_LV
|
||||
set_location_assignment PIN_AH2 -to CAM_PIX_CLK
|
||||
set_location_assignment PIN_AE4 -to CAM_FV
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV
|
||||
|
||||
set_location_assignment PIN_Y8 -to PAL_VD_HSO
|
||||
set_location_assignment PIN_AB4 -to PAL_VD_VSO
|
||||
set_location_assignment PIN_AG5 -to PAL_VD_VD[0]
|
||||
set_location_assignment PIN_AG5 -to PAL_VD_VD_0
|
||||
set_location_assignment PIN_AH5 -to PAL_VD_VD[1]
|
||||
set_location_assignment PIN_AH5 -to PAL_VD_VD_1
|
||||
set_location_assignment PIN_AH6 -to PAL_VD_VD[2]
|
||||
set_location_assignment PIN_AH6 -to PAL_VD_VD_2
|
||||
set_location_assignment PIN_T8 -to PAL_VD_VD[3]
|
||||
set_location_assignment PIN_T8 -to PAL_VD_VD_3
|
||||
set_location_assignment PIN_T12 -to PAL_VD_VD[4]
|
||||
set_location_assignment PIN_T12 -to PAL_VD_VD_4
|
||||
set_location_assignment PIN_Y5 -to PAL_VD_VD[5]
|
||||
set_location_assignment PIN_Y5 -to PAL_VD_VD_5
|
||||
set_location_assignment PIN_Y4 -to PAL_VD_VD[6]
|
||||
set_location_assignment PIN_Y4 -to PAL_VD_VD_6
|
||||
set_location_assignment PIN_W8 -to PAL_VD_VD[7]
|
||||
set_location_assignment PIN_W8 -to PAL_VD_VD_7
|
||||
set_location_assignment PIN_AH4 -to PAL_VD_CLKO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO
|
||||
|
||||
set_location_assignment PIN_AH3 -to SERVO_0
|
||||
set_location_assignment PIN_AF4 -to SERVO_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1
|
||||
|
||||
set_location_assignment PIN_AD12 -to J0_SPI_CLK
|
||||
set_location_assignment PIN_AD11 -to J0_SPI_MISO
|
||||
set_location_assignment PIN_AF9 -to J0_SPI_CS_N
|
||||
set_location_assignment PIN_AD10 -to J0_SPI_MOSI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI
|
||||
|
||||
set_location_assignment PIN_AF5 -to FROM_ESP_TXD
|
||||
set_location_assignment PIN_T13 -to TO_ESP_RXD
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD
|
||||
|
||||
set_location_assignment PIN_AE7 -to SPI_MISO
|
||||
set_location_assignment PIN_AF6 -to SPI_ENA_N
|
||||
set_location_assignment PIN_AE8 -to SPI_CLK
|
||||
set_location_assignment PIN_AE9 -to SPI_MOSI
|
||||
set_location_assignment PIN_AF10 -to SPI_DAT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT
|
||||
|
||||
set_location_assignment PIN_AF11 -to LED_BGR
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR
|
||||
|
||||
#============================================================
|
||||
# GPIO_1, GPIO_1 connect to GPIO Default
|
||||
#============================================================
|
||||
set_location_assignment PIN_AA15 -to RESET_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N
|
||||
|
||||
set_location_assignment PIN_AG28 -to TS_SCL
|
||||
set_location_assignment PIN_AH27 -to TS_SDA
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA
|
||||
|
||||
set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N
|
||||
set_location_assignment PIN_AG26 -to LCD_DE
|
||||
set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN
|
||||
|
||||
set_location_assignment PIN_AH24 -to BLT_TXD
|
||||
set_location_assignment PIN_AE22 -to BLT_RXD
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD
|
||||
|
||||
set_location_assignment PIN_AG20 -to BOARD_ID
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID
|
||||
|
||||
set_location_assignment PIN_AF21 -to VIDEO_HSYNC
|
||||
set_location_assignment PIN_AG19 -to VIDEO_VSYNC
|
||||
set_location_assignment PIN_AF20 -to VIDEO_CLK
|
||||
set_location_assignment PIN_AG23 -to VIDEO_B[0]
|
||||
set_location_assignment PIN_AG23 -to VIDEO_B_0
|
||||
set_location_assignment PIN_AH23 -to VIDEO_B[1]
|
||||
set_location_assignment PIN_AH23 -to VIDEO_B_1
|
||||
set_location_assignment PIN_AF25 -to VIDEO_B[2]
|
||||
set_location_assignment PIN_AF25 -to VIDEO_B_2
|
||||
set_location_assignment PIN_AG24 -to VIDEO_B[3]
|
||||
set_location_assignment PIN_AG24 -to VIDEO_B_3
|
||||
set_location_assignment PIN_AA19 -to VIDEO_B[4]
|
||||
set_location_assignment PIN_AA19 -to VIDEO_B_4
|
||||
set_location_assignment PIN_AH26 -to VIDEO_B[5]
|
||||
set_location_assignment PIN_AH26 -to VIDEO_B_5
|
||||
set_location_assignment PIN_AG18 -to VIDEO_B[6]
|
||||
set_location_assignment PIN_AG18 -to VIDEO_B_6
|
||||
set_location_assignment PIN_AC23 -to VIDEO_B[7]
|
||||
set_location_assignment PIN_AC23 -to VIDEO_B_7
|
||||
set_location_assignment PIN_AH22 -to VIDEO_G[0]
|
||||
set_location_assignment PIN_AH22 -to VIDEO_G_0
|
||||
set_location_assignment PIN_AF22 -to VIDEO_G[1]
|
||||
set_location_assignment PIN_AF22 -to VIDEO_G_1
|
||||
set_location_assignment PIN_AD20 -to VIDEO_G[2]
|
||||
set_location_assignment PIN_AD20 -to VIDEO_G_2
|
||||
set_location_assignment PIN_AE24 -to VIDEO_G[3]
|
||||
set_location_assignment PIN_AE24 -to VIDEO_G_3
|
||||
set_location_assignment PIN_AE20 -to VIDEO_G[4]
|
||||
set_location_assignment PIN_AE20 -to VIDEO_G_4
|
||||
set_location_assignment PIN_AD19 -to VIDEO_G[5]
|
||||
set_location_assignment PIN_AD19 -to VIDEO_G_5
|
||||
set_location_assignment PIN_AF18 -to VIDEO_G[6]
|
||||
set_location_assignment PIN_AF18 -to VIDEO_G_6
|
||||
set_location_assignment PIN_AE19 -to VIDEO_G[7]
|
||||
set_location_assignment PIN_AE19 -to VIDEO_G_7
|
||||
set_location_assignment PIN_AC22 -to VIDEO_R[0]
|
||||
set_location_assignment PIN_AC22 -to VIDEO_R_0
|
||||
set_location_assignment PIN_AA18 -to VIDEO_R[1]
|
||||
set_location_assignment PIN_AA18 -to VIDEO_R_1
|
||||
set_location_assignment PIN_AE23 -to VIDEO_R[2]
|
||||
set_location_assignment PIN_AE23 -to VIDEO_R_2
|
||||
set_location_assignment PIN_AD23 -to VIDEO_R[3]
|
||||
set_location_assignment PIN_AD23 -to VIDEO_R_3
|
||||
set_location_assignment PIN_AH18 -to VIDEO_R[4]
|
||||
set_location_assignment PIN_AH18 -to VIDEO_R_4
|
||||
set_location_assignment PIN_AG21 -to VIDEO_R[5]
|
||||
set_location_assignment PIN_AG21 -to VIDEO_R_5
|
||||
set_location_assignment PIN_AH21 -to VIDEO_R[6]
|
||||
set_location_assignment PIN_AH21 -to VIDEO_R_6
|
||||
set_location_assignment PIN_AH19 -to VIDEO_R[7]
|
||||
set_location_assignment PIN_AH19 -to VIDEO_R_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7
|
||||
6
cs309-psoc/lab_2_1/hw/quartus/lab_2_1.sdc
Normal file
6
cs309-psoc/lab_2_1/hw/quartus/lab_2_1.sdc
Normal file
@@ -0,0 +1,6 @@
|
||||
create_clock -period 20 [get_ports FPGA_CLK1_50]
|
||||
create_clock -period 20 [get_ports FPGA_CLK2_50]
|
||||
create_clock -period 20 [get_ports FPGA_CLK3_50]
|
||||
|
||||
derive_pll_clocks
|
||||
derive_clock_uncertainty
|
||||
731
cs309-psoc/lab_2_1/hw/quartus/soc_system.qsys
Normal file
731
cs309-psoc/lab_2_1/hw/quartus/soc_system.qsys
Normal file
File diff suppressed because one or more lines are too long
BIN
cs309-psoc/lab_2_1/lab_2_1.pdf
Normal file
BIN
cs309-psoc/lab_2_1/lab_2_1.pdf
Normal file
Binary file not shown.
31
cs309-psoc/lab_2_1/sw/nios/application/app.c
Normal file
31
cs309-psoc/lab_2_1/sw/nios/application/app.c
Normal file
@@ -0,0 +1,31 @@
|
||||
#include <io.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "lepton/lepton.h"
|
||||
#include "system.h"
|
||||
|
||||
int main(void) {
|
||||
// Hardware control structures
|
||||
lepton_dev lepton = lepton_inst((void *) LEPTON_0_BASE);
|
||||
|
||||
// Initialize hardware
|
||||
lepton_init(&lepton);
|
||||
|
||||
// =========================================================================
|
||||
|
||||
|
||||
do {
|
||||
lepton_start_capture(&lepton);
|
||||
lepton_wait_until_eof(&lepton);
|
||||
} while(lepton_error_check(&lepton));
|
||||
|
||||
//
|
||||
// =========================================================================
|
||||
|
||||
// Save the adjusted (rescaled) buffer to a file.
|
||||
lepton_save_capture(&lepton, true, "/mnt/host/output.pgm");
|
||||
|
||||
return EXIT_SUCCESS;
|
||||
}
|
||||
79
cs309-psoc/lab_2_1/sw/nios/application/joysticks/joysticks.c
Normal file
79
cs309-psoc/lab_2_1/sw/nios/application/joysticks/joysticks.c
Normal file
@@ -0,0 +1,79 @@
|
||||
#include "joysticks.h"
|
||||
|
||||
#define JOYSTICK_RIGHT_VRY_MCP3204_CHANNEL (0)
|
||||
#define JOYSTICK_RIGHT_VRX_MCP3204_CHANNEL (1)
|
||||
#define JOYSTICK_LEFT_VRY_MCP3204_CHANNEL (2)
|
||||
#define JOYSTICK_LEFT_VRX_MCP3204_CHANNEL (3)
|
||||
|
||||
/**
|
||||
* joysticks_inst
|
||||
*
|
||||
* Instantiate a joysticks device structure.
|
||||
*
|
||||
* @param base Base address of the MCP3204 component connected to the joysticks.
|
||||
*/
|
||||
joysticks_dev joysticks_inst(void *mcp3204_base) {
|
||||
joysticks_dev dev;
|
||||
dev.mcp3204 = mcp3204_inst((void *) mcp3204_base);
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
/**
|
||||
* joysticks_init
|
||||
*
|
||||
* Initializes the joysticks device.
|
||||
*
|
||||
* @param dev joysticks device structure.
|
||||
*/
|
||||
void joysticks_init(joysticks_dev *dev) {
|
||||
mcp3204_init(&(dev->mcp3204));
|
||||
}
|
||||
|
||||
/**
|
||||
* joysticks_read_left_vertical
|
||||
*
|
||||
* Returns the vertical position of the left joystick. Return value ranges
|
||||
* between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
|
||||
*
|
||||
* @param dev joysticks device structure.
|
||||
*/
|
||||
uint32_t joysticks_read_left_vertical(joysticks_dev *dev) {
|
||||
return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,LV_CHANNEL);
|
||||
}
|
||||
|
||||
/**
|
||||
* joysticks_read_left_horizontal
|
||||
*
|
||||
* Returns the horizontal position of the left joystick. Return value ranges
|
||||
* between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
|
||||
*
|
||||
* @param dev joysticks device structure.
|
||||
*/
|
||||
uint32_t joysticks_read_left_horizontal(joysticks_dev *dev) {
|
||||
return mcp3204_read(&dev->mcp3204,LH_CHANNEL);
|
||||
}
|
||||
|
||||
/**
|
||||
* joysticks_read_right_vertical
|
||||
*
|
||||
* Returns the vertical position of the right joystick. Return value ranges
|
||||
* between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
|
||||
*
|
||||
* @param dev joysticks device structure.
|
||||
*/
|
||||
uint32_t joysticks_read_right_vertical(joysticks_dev *dev) {
|
||||
return JOYSTICKS_MAX_VALUE - mcp3204_read(&dev->mcp3204,RV_CHANNEL);
|
||||
}
|
||||
|
||||
/**
|
||||
* joysticks_read_right_horizontal
|
||||
*
|
||||
* Returns the horizontal position of the left joystick. Return value ranges
|
||||
* between JOYSTICKS_MIN_VALUE and JOYSTICKS_MAX_VALUE.
|
||||
*
|
||||
* @param dev joysticks device structure.
|
||||
*/
|
||||
uint32_t joysticks_read_right_horizontal(joysticks_dev *dev) {
|
||||
return mcp3204_read(&dev->mcp3204,RH_CHANNEL);
|
||||
}
|
||||
33
cs309-psoc/lab_2_1/sw/nios/application/joysticks/joysticks.h
Normal file
33
cs309-psoc/lab_2_1/sw/nios/application/joysticks/joysticks.h
Normal file
@@ -0,0 +1,33 @@
|
||||
#ifndef __JOYSTICKS_H__
|
||||
#define __JOYSTICKS_H__
|
||||
|
||||
#include "mcp3204/mcp3204.h"
|
||||
|
||||
/* joysticks device structure */
|
||||
typedef struct joysticks_dev {
|
||||
mcp3204_dev mcp3204; /* MCP3204 device handle */
|
||||
} joysticks_dev;
|
||||
|
||||
/*******************************************************************************
|
||||
* Public API
|
||||
******************************************************************************/
|
||||
|
||||
#define JOYSTICKS_MIN_VALUE (MCP3204_MIN_VALUE)
|
||||
#define JOYSTICKS_MAX_VALUE (MCP3204_MAX_VALUE)
|
||||
|
||||
#define LV_CHANNEL 0
|
||||
#define LH_CHANNEL 1
|
||||
#define RV_CHANNEL 2
|
||||
#define RH_CHANNEL 3
|
||||
#define CC_CHANNEL "this is a joke"
|
||||
|
||||
joysticks_dev joysticks_inst(void *mcp3204_base);
|
||||
|
||||
void joysticks_init(joysticks_dev *dev);
|
||||
|
||||
uint32_t joysticks_read_left_vertical(joysticks_dev *dev);
|
||||
uint32_t joysticks_read_left_horizontal(joysticks_dev *dev);
|
||||
uint32_t joysticks_read_right_vertical(joysticks_dev *dev);
|
||||
uint32_t joysticks_read_right_horizontal(joysticks_dev *dev);
|
||||
|
||||
#endif /* __JOYSTICKS_H__ */
|
||||
@@ -0,0 +1,50 @@
|
||||
#include <assert.h>
|
||||
#include <io.h>
|
||||
|
||||
#include "mcp3204.h"
|
||||
#include "mcp3204_regs.h"
|
||||
|
||||
#define MCP3204_NUM_CHANNELS (4)
|
||||
|
||||
/**
|
||||
* mcp3204_inst
|
||||
*
|
||||
* Instantiate a mcp3204 device structure.
|
||||
*
|
||||
* @param base Base address of the component.
|
||||
*/
|
||||
mcp3204_dev mcp3204_inst(void *base) {
|
||||
mcp3204_dev dev;
|
||||
dev.base = base;
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
/**
|
||||
* mcp3204_init
|
||||
*
|
||||
* Initializes the mcp3204 device.
|
||||
*
|
||||
* @param dev mcp3204 device structure.
|
||||
*/
|
||||
void mcp3204_init(mcp3204_dev *dev) {
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* mcp3204_read
|
||||
*
|
||||
* Reads the register corresponding to the supplied channel parameter.
|
||||
*
|
||||
* @param dev mcp3204 device structure.
|
||||
* @param channel channel to be read
|
||||
*/
|
||||
uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel) {
|
||||
switch(channel){
|
||||
case 0: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_0_OFST);
|
||||
case 1: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_1_OFST);
|
||||
case 2: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_2_OFST);
|
||||
case 3: return IORD_32DIRECT(dev->base, MCP3204_CHANNEL_3_OFST);
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,23 @@
|
||||
#ifndef __MCP3204_H__
|
||||
#define __MCP3204_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* mcp3204 device structure */
|
||||
typedef struct mcp3204_dev {
|
||||
void *base; /* Base address of component */
|
||||
} mcp3204_dev;
|
||||
|
||||
/*******************************************************************************
|
||||
* Public API
|
||||
******************************************************************************/
|
||||
|
||||
#define MCP3204_MIN_VALUE (0)
|
||||
#define MCP3204_MAX_VALUE (4095)
|
||||
|
||||
mcp3204_dev mcp3204_inst(void *base);
|
||||
|
||||
void mcp3204_init(mcp3204_dev *dev);
|
||||
uint32_t mcp3204_read(mcp3204_dev *dev, uint32_t channel);
|
||||
|
||||
#endif /* __MCP3204_H__ */
|
||||
@@ -0,0 +1,9 @@
|
||||
#ifndef __MCP3204_REGS_H__
|
||||
#define __MCP3204_REGS_H__
|
||||
|
||||
#define MCP3204_CHANNEL_0_OFST (0 * 4) /* RO */
|
||||
#define MCP3204_CHANNEL_1_OFST (1 * 4) /* RO */
|
||||
#define MCP3204_CHANNEL_2_OFST (2 * 4) /* RO */
|
||||
#define MCP3204_CHANNEL_3_OFST (3 * 4) /* RO */
|
||||
|
||||
#endif /* __MCP3204_REGS_H__ */
|
||||
118
cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton.c
Normal file
118
cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton.c
Normal file
@@ -0,0 +1,118 @@
|
||||
#include <assert.h>
|
||||
#include <inttypes.h>
|
||||
#include <io.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "lepton_regs.h"
|
||||
#include "lepton.h"
|
||||
|
||||
/**
|
||||
* lepton_inst
|
||||
*
|
||||
* Instantiate a lepton device structure.
|
||||
*
|
||||
* @param base Base address of the component.
|
||||
*/
|
||||
lepton_dev lepton_inst(void *base) {
|
||||
lepton_dev dev;
|
||||
dev.base = base;
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
/**
|
||||
* lepton_init
|
||||
*
|
||||
* Initializes the lepton device.
|
||||
*
|
||||
* @param dev lepton device structure.
|
||||
*/
|
||||
void lepton_init(lepton_dev *dev) {
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* lepton_start_capture
|
||||
*
|
||||
* Instructs the device to start the frame capture process.
|
||||
*
|
||||
* @param dev lepton device structure.
|
||||
*/
|
||||
void lepton_start_capture(lepton_dev *dev) {
|
||||
IOWR_16DIRECT(dev->base, LEPTON_REGS_COMMAND_OFST, 0x1);
|
||||
}
|
||||
|
||||
/**
|
||||
* lepton_error_check
|
||||
*
|
||||
* @abstract Check for errors at the device level.
|
||||
* @param dev lepton device structure.
|
||||
* @return true if there was an error, and false otherwise.
|
||||
*/
|
||||
bool lepton_error_check(lepton_dev *dev) {
|
||||
return (IORD_16DIRECT(dev->base, LEPTON_REGS_STATUS_OFST) & 0x2) != 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* lepton_wait_until_eof
|
||||
*
|
||||
* Waits until the frame being captured has been fully received and saved in the
|
||||
* internal memory.
|
||||
*
|
||||
* @param dev lepton device structure.
|
||||
*/
|
||||
void lepton_wait_until_eof(lepton_dev *dev) {
|
||||
while (IORD_16DIRECT(dev->base, LEPTON_REGS_STATUS_OFST) & 0x1);
|
||||
}
|
||||
|
||||
/**
|
||||
* lepton_save_capture
|
||||
*
|
||||
* Saves the captured frame on the host filesystem under the supplied filename.
|
||||
* The frame will be saved in PGM format.
|
||||
*
|
||||
* @param dev lepton device structure.
|
||||
* @param adjusted Setting this parameter to false will cause RAW sensor data to
|
||||
* be written to the file.
|
||||
* Setting this parameter to true will cause a preprocessed image
|
||||
* (with a stretched dynamic range) to be saved to the file.
|
||||
*
|
||||
* @param fname the output file name.
|
||||
*/
|
||||
void lepton_save_capture(lepton_dev *dev, bool adjusted, const char *fname) {
|
||||
FILE *fp = fopen(fname, "w");
|
||||
assert(fp);
|
||||
|
||||
const uint8_t num_rows = 60;
|
||||
const uint8_t num_cols = 80;
|
||||
|
||||
uint16_t offset = LEPTON_REGS_RAW_BUFFER_OFST;
|
||||
uint16_t max_value = IORD_16DIRECT(dev->base, LEPTON_REGS_MAX_OFST);
|
||||
if (adjusted) {
|
||||
offset = LEPTON_REGS_ADJUSTED_BUFFER_OFST;
|
||||
max_value = 0x3fff;
|
||||
}
|
||||
|
||||
/* Write PGM header */
|
||||
fprintf(fp, "P2\n%" PRIu8 " %" PRIu8 "\n%" PRIu16, num_cols, num_rows, max_value);
|
||||
|
||||
/* Write body */
|
||||
uint8_t row = 0;
|
||||
for (row = 0; row < num_rows; ++row) {
|
||||
fprintf(fp, "\n");
|
||||
|
||||
uint8_t col = 0;
|
||||
for (col = 0; col < num_cols; ++col) {
|
||||
if (col > 0) {
|
||||
fprintf(fp, " ");
|
||||
}
|
||||
|
||||
uint16_t current_ofst = offset + (row * num_cols + col) * sizeof(uint16_t);
|
||||
uint16_t pix_value = IORD_16DIRECT(dev->base, current_ofst);
|
||||
fprintf(fp, "%" PRIu16, pix_value);
|
||||
}
|
||||
}
|
||||
|
||||
assert(!fclose(fp));
|
||||
}
|
||||
23
cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton.h
Normal file
23
cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton.h
Normal file
@@ -0,0 +1,23 @@
|
||||
#ifndef __LEPTON_H__
|
||||
#define __LEPTON_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
/* lepton device structure */
|
||||
typedef struct {
|
||||
void *base; /* Base address of the component */
|
||||
} lepton_dev;
|
||||
|
||||
/*******************************************************************************
|
||||
* Public API
|
||||
******************************************************************************/
|
||||
|
||||
lepton_dev lepton_inst(void *base);
|
||||
|
||||
void lepton_init(lepton_dev *dev);
|
||||
void lepton_start_capture(lepton_dev *dev);
|
||||
void lepton_wait_until_eof(lepton_dev *dev);
|
||||
bool lepton_error_check(lepton_dev *dev);
|
||||
void lepton_save_capture(lepton_dev *dev, bool adjusted, const char *fname);
|
||||
|
||||
#endif /* __LEPTON_H__ */
|
||||
25
cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton_regs.h
Normal file
25
cs309-psoc/lab_2_1/sw/nios/application/lepton/lepton_regs.h
Normal file
@@ -0,0 +1,25 @@
|
||||
#ifndef __LEPTON_REGS_H__
|
||||
#define __LEPTON_REGS_H__
|
||||
|
||||
/* Register offsets */
|
||||
#define LEPTON_REGS_COMMAND_OFST ( 0 * 2) /* WO */
|
||||
#define LEPTON_REGS_STATUS_OFST ( 1 * 2) /* RO */
|
||||
#define LEPTON_REGS_MIN_OFST ( 2 * 2) /* RO */
|
||||
#define LEPTON_REGS_MAX_OFST ( 3 * 2) /* RO */
|
||||
#define LEPTON_REGS_SUM_LSB_OFST ( 4 * 2) /* RO */
|
||||
#define LEPTON_REGS_SUM_MSB_OFST ( 5 * 2) /* RO */
|
||||
#define LEPTON_REGS_ROW_IDX_OFST ( 6 * 2) /* RO */
|
||||
#define LEPTON_REGS_RAW_BUFFER_OFST ( 8 * 2) /* RO */
|
||||
#define LEPTON_REGS_ADJUSTED_BUFFER_OFST (8192 * 2) /* RO */
|
||||
|
||||
/* Command register */
|
||||
#define LEPTON_COMMAND_START (0x0001)
|
||||
|
||||
/* Status register */
|
||||
#define LEPTON_STATUS_CAPTURE_IN_PROGRESS_MASK (1 << 0)
|
||||
#define LEPTON_STATUS_ERROR_MASK (1 << 1)
|
||||
|
||||
#define LEPTON_REGS_BUFFER_NUM_PIXELS (80 * 60)
|
||||
#define LEPTON_REGS_BUFFER_BYTELENGTH (LEPTON_REGS_BUFFER_NUM_PIXELS * 2)
|
||||
|
||||
#endif /* __LEPTON_REGS_H__ */
|
||||
63
cs309-psoc/lab_2_1/sw/nios/application/output_bottle.pgm
Normal file
63
cs309-psoc/lab_2_1/sw/nios/application/output_bottle.pgm
Normal file
@@ -0,0 +1,63 @@
|
||||
P2
|
||||
80 60
|
||||
16383
|
||||
11667 11607 11546 11335 11063 11093 11032 10730 10458 10549 10398 10367 10186 10126 10035 9944 10156 10518 11728 13904 16383 15143 13934 13299 12997 12846 12453 12121 11728 11637 11576 11335 11183 11183 10881 10942 10851 10791 10518 10488 10337 10126 10095 10126 10005 9914 9853 10035 10035 9914 10035 9974 9944 9763 9702 9672 9521 9400 9370 9309 9279 9219 9279 9158 9037 8916 8735 8796 8735 8675 8584 8493 8584 8554 8584 8644 8463 8372 8342 8251
|
||||
12030 11758 11758 11607 11304 11183 11123 11032 10760 10730 10488 10549 10428 10246 10095 10156 10186 10670 11728 13692 16201 14992 13753 13178 12816 12604 12332 12030 11728 11486 11456 11304 11123 10972 10851 10670 10670 10700 10458 10398 10246 10126 10065 9944 9884 9884 9823 9944 9914 9914 9974 9914 9763 9763 9612 9551 9491 9279 9309 9340 9188 9128 9340 9128 8977 8947 8765 8765 8765 8675 8644 8433 8675 8614 8614 8523 8433 8493 8342 8040
|
||||
12302 12090 11879 11788 11667 11516 11365 11304 10972 10881 10760 10760 10398 10367 10156 10126 10277 10700 11576 13481 16171 15053 13783 13148 12785 12513 12211 11788 11697 11365 11274 11153 10972 10730 10639 10700 10579 10639 10277 10246 10126 10005 10005 9914 9823 9884 9793 9884 9914 9884 9974 9914 9733 9672 9612 9430 9430 9340 9219 9249 9098 9219 9249 9037 9037 8856 8735 8644 8735 8614 8614 8372 8523 8554 8433 8493 8403 8342 8221 8010
|
||||
12876 12574 12453 12151 11909 11909 11758 11637 11365 11335 11183 11032 10730 10730 10398 10428 10398 10821 11395 13209 16050 14901 13813 13239 12906 12574 12181 11818 11546 11365 11123 11002 10942 10700 10639 10609 10609 10458 10398 10277 10035 9853 9914 9914 9672 9763 9672 9823 9974 9884 9853 9823 9672 9702 9581 9521 9491 9370 9279 9219 9219 9188 9249 9037 9007 8886 8765 8826 8765 8614 8463 8372 8523 8463 8463 8433 8342 8282 8131 7859
|
||||
12937 13027 12755 12725 12574 12453 12272 12121 11607 11848 11486 11304 11123 10791 10639 10609 10609 10791 11395 12997 15929 14841 13723 13058 12785 12393 11969 11728 11365 11244 11093 10881 10851 10549 10428 10428 10337 10458 10216 10095 9884 9853 9672 9642 9672 9642 9581 9763 9763 9672 9733 9702 9612 9612 9612 9491 9521 9249 9219 9249 9098 9188 9128 9037 8977 8916 8826 8826 8765 8614 8584 8403 8403 8403 8433 8372 8282 8282 8070 7768
|
||||
13420 13450 13541 13511 13148 12816 12755 12513 12393 12423 12181 11939 11637 11425 11183 11123 11153 10821 11365 12816 15566 14841 13753 13088 12665 12332 12090 11667 11304 11093 10972 10942 10700 10337 10186 10277 10277 10246 10005 10005 9793 9581 9551 9551 9521 9461 9461 9581 9702 9551 9672 9672 9702 9581 9612 9400 9461 9249 9219 9188 9188 9188 9219 9158 9068 8947 8826 8826 8796 8705 8493 8342 8403 8554 8463 8463 8312 8282 8070 7738
|
||||
12725 13027 13209 13239 13088 13027 12695 12362 12302 12332 12332 12272 12151 11939 11546 11244 11123 10791 11123 12483 15536 14780 13511 12997 12634 12241 11879 11576 11063 10942 10730 10579 10337 10186 9974 10065 9944 10065 9763 9823 9581 9551 9400 9400 9309 9340 9249 9400 9642 9491 9581 9642 9551 9581 9430 9340 9400 9249 9219 9400 9249 9249 9219 9098 9098 8977 8856 8916 8856 8735 8493 8342 8433 8584 8523 8493 8342 8251 8040 7828
|
||||
12030 12302 12665 12785 12574 12423 12302 12241 11909 12000 12000 12090 11848 11818 11365 11093 10700 10246 11002 12211 15415 14660 13602 12906 12513 12272 11788 11486 11032 10760 10639 10428 10307 10005 9944 9884 9793 9853 9702 9702 9521 9400 9400 9279 9279 9249 9279 9430 9491 9521 9521 9612 9551 9491 9461 9521 9430 9279 9188 9219 9309 9188 9279 9188 9219 9007 8916 8977 8916 8796 8584 8493 8554 8584 8554 8554 8433 8372 8070 7889
|
||||
9853 10156 10549 10942 10821 11304 11304 11395 11304 11576 11486 11637 11516 11516 10972 10942 10367 9581 10730 11818 15264 14599 13450 12876 12483 12272 11728 11395 10972 10760 10670 10428 10246 10095 9914 9853 9884 9853 9672 9551 9491 9309 9400 9279 9309 9400 9188 9370 9491 9430 9581 9551 9581 9581 9491 9400 9521 9370 9279 9370 9370 9400 9461 9370 9098 9219 9037 9068 9068 8735 8796 8614 8614 8705 8675 8796 8554 8372 8251 7889
|
||||
6710 7042 7284 7677 7738 8100 8251 8523 8523 8916 9037 9279 9279 9188 9188 9219 8826 8131 10246 11425 14962 14478 13571 12906 12453 12181 11758 11395 10972 10730 10549 10398 10337 10035 9823 9763 9793 9793 9612 9672 9400 9340 9430 9340 9279 9309 9219 9400 9461 9430 9551 9733 9551 9521 9551 9461 9672 9400 9309 9491 9340 9430 9461 9309 9249 9098 9037 9098 9037 9007 8856 8644 8735 8765 8675 8735 8523 8403 8312 7949
|
||||
4443 4624 4685 4775 4806 5017 4866 5017 5017 5289 5471 5954 6015 6045 5864 6347 6136 6136 9642 11032 14780 14418 13602 12967 12453 12241 11697 11486 11002 10791 10549 10428 10277 10065 9884 9853 9733 9823 9612 9612 9370 9370 9370 9249 9279 9340 9188 9430 9491 9551 9612 9672 9581 9612 9581 9581 9551 9521 9430 9370 9400 9461 9370 9430 9158 9128 9007 9128 9098 8977 8826 8796 8796 8856 8644 8614 8463 8312 8342 8010
|
||||
4171 4231 4352 4382 4322 4292 4382 4322 4201 4413 4534 4987 4564 4261 4352 4382 4352 5289 9098 10821 14629 14418 13420 12665 12423 12302 11758 11335 10911 10670 10518 10307 10246 10126 9884 9823 9884 9884 9581 9581 9491 9370 9188 9279 9188 9249 9158 9340 9400 9581 9551 9491 9400 9581 9491 9461 9521 9340 9370 9309 9370 9400 9340 8947 8796 8523 8614 9037 9037 9037 9007 8826 8886 8856 8765 8765 8312 8312 8040 7949
|
||||
4141 4080 4261 4261 4141 4141 4171 4110 4141 4382 4503 4382 4050 4050 3989 4141 3989 5017 8735 10428 14206 14267 13420 12755 12211 11848 10851 10367 10065 10458 10307 10246 10095 9974 9763 9702 9763 9581 8886 8463 8342 8705 9007 9188 9340 9188 9249 9370 9400 9279 8856 7556 7284 7466 8433 9370 9461 9370 9370 9249 9370 9158 6891 4382 3687 3838 5078 8282 9037 8947 9037 8826 8977 8977 8886 8403 7435 6740 6196 5984
|
||||
4231 4020 4201 4141 4080 4141 4141 4080 4141 4201 4443 4231 3959 3959 3929 4141 3989 4775 8584 10367 14297 14327 13360 12695 12181 8523 5350 4745 4775 6740 10035 10186 10095 10005 9793 9702 9763 8070 4503 3899 3959 4261 7586 9188 9098 9068 9158 9400 9340 9098 5319 3445 3083 3445 4866 8977 9400 9430 9309 9249 9340 8916 4775 2659 2508 2508 3234 7919 8947 9037 9037 8886 8977 8856 8705 6075 3022 2418 2206 1874
|
||||
4352 4050 4020 4171 4141 4110 4110 4050 4020 4080 4292 4201 3959 3989 3959 3989 3899 4594 8463 10277 14025 14176 13420 12665 11788 6921 4171 3748 3415 5440 9581 10035 10035 9884 9702 9672 9612 7163 3627 3113 2962 3324 7012 8765 9128 9037 9007 9249 9249 8705 4534 2841 2720 2690 4201 8644 9249 9309 9219 9340 9128 8614 3989 2539 2327 2146 2962 7466 8947 8977 9068 8947 9037 8916 8765 5622 2297 1874 1753 1662
|
||||
4261 4080 4110 4110 4050 4110 3959 4050 3899 4110 4322 4141 3929 3959 3838 3959 3929 4594 8312 10186 13904 13995 13269 12423 11516 6166 3869 3415 3052 4896 9249 9974 9944 9763 9672 9521 9370 6921 3264 2780 2629 3143 6770 8735 8977 8916 8977 9068 9098 8523 4382 2629 2448 2599 4413 8584 9249 9249 9279 9188 9098 8523 4534 2327 2206 2115 3597 8070 8856 8916 9128 8977 8977 8916 8554 4896 2055 1692 1692 1662
|
||||
4382 4080 4050 4020 4020 4050 3959 3989 3989 3929 4080 4231 3899 4020 3869 3899 3899 4382 8010 10095 13602 13783 13088 12453 11546 6801 3657 3083 2901 5319 9461 9823 9914 9793 9491 9491 9400 7859 3355 2659 2478 3355 7647 8735 8856 8886 8916 9037 9037 8644 4775 2508 2327 2387 4957 8886 9188 9249 9279 9158 9098 8584 4382 2206 1994 1874 3445 8221 8947 8977 9098 8977 8947 8796 8675 4654 2115 1753 1753 1541
|
||||
4292 4231 4080 4080 3959 3929 4020 3929 3959 3989 4050 4261 3989 3929 3929 3869 3748 4352 7828 9702 13239 13723 12906 12241 11456 6287 3445 2811 2720 4957 9188 9823 9853 9551 9491 9461 9400 7617 3234 2508 2267 3113 7345 8493 8705 8675 8735 8916 8916 8523 4564 2387 2115 2297 4322 8675 9098 9158 9249 9098 9068 8372 3838 1964 1843 1874 3052 7919 8916 8977 9007 8947 8947 8826 8554 4413 1994 1722 1722 1571
|
||||
4231 4231 4141 4141 4110 3959 3959 3959 3869 3899 4020 4110 4110 4050 3869 3899 3869 4292 7496 9612 12967 13662 12906 12151 11123 5652 3264 2750 2690 4292 8977 9823 9793 9551 9309 9370 9340 6982 2962 2297 2115 2780 6831 8493 8584 8584 8644 8735 8886 8282 3929 2176 1934 2267 3717 8403 9128 9098 9219 9128 9068 8131 3204 1843 1662 1571 2387 7435 8977 8916 8886 8856 8856 8796 8493 4443 1874 1541 1541 1481
|
||||
4443 4322 4141 4201 4080 4020 3929 3899 3929 3929 3989 4050 3959 4141 3929 3869 3869 4110 7194 9279 12695 13571 12906 11909 10488 4624 3052 2629 2539 3687 8312 9702 9612 9400 9309 9279 9098 5864 2539 2085 1964 2448 6045 8282 8433 8493 8433 8614 8705 7738 3113 1994 1753 1964 3113 7919 8886 9007 9068 9068 9007 7466 2478 1541 1511 1329 1994 6589 8675 8916 8916 8705 8826 8796 8372 4201 1874 1571 1571 1299
|
||||
4382 4231 4201 4231 4110 4080 4110 3899 3869 3959 3869 3989 3869 3959 3989 3838 3838 4050 7103 9128 12423 13511 12634 11939 9521 4020 2811 2448 2327 3294 7677 9309 9461 9309 9098 9219 8947 4775 2357 2025 1753 2085 5078 8100 8372 8372 8221 8554 8523 6770 2448 1753 1662 1874 2629 6982 8826 8856 8947 9068 8856 6196 2025 1299 1390 1209 1632 5471 8705 8856 8765 8735 8705 8796 8372 4110 1662 1541 1511 1118
|
||||
4322 3989 4110 4201 4171 4020 4020 3899 3959 3869 3929 3869 3838 3929 3929 3989 3929 3989 7012 9098 12211 13360 12574 11697 8191 3687 2599 2327 2236 2871 6498 9249 9461 9128 9037 9098 8463 3899 1994 1783 1571 1813 3959 7798 8161 8161 8161 8342 8251 5652 2115 1571 1632 1722 2327 5924 8796 8856 8826 9007 8584 4745 1692 1269 1148 1057 1450 3899 8312 8584 8675 8675 8644 8554 8282 4080 1602 1390 1450 1148
|
||||
4201 3959 3899 4020 4201 3989 4201 3989 3808 3989 3838 3869 3717 3808 3808 3929 3748 3989 6710 8886 11939 13209 12453 11365 6408 3415 2418 2327 2025 2569 5017 8977 9188 8977 8856 8856 7496 2901 1813 1571 1360 1541 3083 7254 8161 8131 8010 8221 7979 4322 1874 1481 1481 1571 2025 4715 8463 8675 8644 8916 8070 3294 1360 1088 1027 846 1118 2750 7586 8403 8523 8433 8644 8493 8131 3929 1662 1329 1420 1027
|
||||
4201 3959 3899 3899 3959 4020 3959 4080 3838 3838 3869 3838 3657 3657 3687 3748 3717 3869 6256 8705 11546 13058 12332 10760 4896 2901 2297 2146 1964 2085 3929 8161 9098 8765 8826 8765 5984 2297 1662 1541 1329 1390 2206 6166 7919 7949 7919 8010 6589 2811 1692 1390 1390 1390 1813 3234 7828 8493 8523 8614 6952 2025 1118 816 846 725 816 1843 6347 8372 8372 8342 8403 8251 7889 3687 1511 1269 1269 1027
|
||||
4201 3989 3899 3989 3929 3899 3989 4050 3989 3899 3869 3838 3687 3597 3687 3627 3808 3959 6377 8584 11153 13148 12121 9400 3869 2569 2267 2055 1874 1934 2871 6952 8796 8826 8765 8372 4413 2115 1571 1450 1299 1269 1662 4594 7738 7889 7889 7707 3989 1874 1511 1481 1360 1450 1541 2267 6740 8493 8372 8251 5078 1269 997 785 846 755 664 1360 4473 8282 8251 8251 8251 8191 7798 3566 1390 1088 967 876
|
||||
4261 3959 3959 3959 3899 3959 3838 3869 3959 3989 3929 3808 3687 3687 3597 3597 3687 3869 6045 8433 10670 13118 11909 7405 3355 2418 2146 2055 1722 1904 2327 5440 8554 8675 8584 7617 2932 1843 1450 1420 1239 1209 1390 3294 7345 7798 7738 5833 2357 1632 1420 1360 1299 1390 1511 1753 5168 8191 8251 7738 3143 1057 846 755 755 725 725 906 2569 7435 8161 8070 8221 8100 7466 3052 1239 967 785 725
|
||||
4231 3899 3838 3929 3869 3778 3959 3869 3717 3989 3959 3778 3566 3597 3687 3566 3657 3778 5954 8191 10488 12937 11456 5259 2962 2508 2055 1964 1662 1753 2025 3778 8131 8523 8433 6045 2327 1662 1420 1329 1148 1148 1239 2327 6347 7677 7586 4654 1874 1541 1299 1299 1269 1239 1360 1511 3415 7828 7859 6619 1722 876 785 695 604 604 513 785 1541 5833 7979 8040 8070 7949 6498 2146 967 725 664 725
|
||||
4110 3808 3838 3929 3808 3869 3838 3869 3687 3808 3899 3989 3748 3566 3536 3476 3476 3536 5682 8161 10277 12876 10156 3869 2539 2236 1994 1874 1602 1662 1783 2720 7224 8433 8131 4352 1964 1602 1450 1360 1209 1148 1148 1813 5259 7526 7496 5712 1964 1299 1299 1329 1209 1239 1239 1329 2176 6861 7798 5108 1027 816 664 604 574 423 634 513 1027 4413 7738 7798 7738 6498 3022 1269 755 634 544 453
|
||||
4050 3869 3838 3808 3838 3869 3778 3869 3748 3778 3748 3778 3808 3748 3566 3506 3476 3627 5652 8070 10156 12725 8342 3324 2418 2025 1813 1753 1571 1692 1783 2327 6075 8372 7738 3264 1813 1602 1360 1269 1209 1088 1057 1481 4020 7435 7405 4594 1783 1329 1209 1209 1148 1299 1209 1209 1571 5712 7435 3385 906 664 664 544 544 483 423 483 816 2962 7466 7677 5864 2418 1239 725 604 544 362 120
|
||||
4020 3869 3838 3869 3838 3929 3869 3838 3717 3748 3717 3778 3717 3717 3627 3506 3476 3627 5471 7859 9944 12393 6438 2932 2176 2025 1874 1692 1662 1571 1571 1934 4957 8282 6740 2539 1783 1511 1329 1239 1299 997 997 1209 2932 7163 7405 3415 1602 1239 1239 1088 1088 1088 1118 1118 1269 4322 6861 1994 755 574 574 513 513 544 392 483 634 1753 7133 6680 1994 876 664 423 362 392 211 181
|
||||
4050 3869 3748 3808 3748 3808 3869 3778 3778 3687 3657 3778 3627 3717 3687 3566 3476 3597 5168 7828 9551 11969 4866 2569 2055 1994 1843 1692 1753 1481 1541 1753 3899 8312 5773 2085 1571 1360 1209 1209 1239 906 967 1118 2146 6921 7254 2539 1390 1178 1209 1178 1118 1088 1027 997 997 2932 6226 1057 634 513 604 544 574 574 362 362 453 1209 6649 5743 876 513 392 423 362 392 332 181
|
||||
4171 3899 3959 3778 3778 3778 3838 3869 3657 3748 3717 3748 3506 3536 3627 3687 3536 3566 5017 7828 9279 11425 3899 2418 1994 1934 1722 1722 1843 1571 1390 1541 3173 8403 4866 1783 1420 1390 1209 1209 1360 816 906 937 1722 6589 7103 1753 1178 997 1118 1118 1057 1239 967 816 876 1843 5017 755 574 574 574 423 574 634 453 302 362 695 5229 4957 483 272 241 362 392 241 120 151
|
||||
4050 4020 3899 3808 3748 3778 3778 3778 3687 3748 3627 3657 3506 3506 3445 3506 3536 3597 4987 7949 9279 9974 3506 2357 2025 1843 1662 1783 1874 1541 1481 1450 2448 7224 3506 1662 1329 1329 1178 1178 1420 997 937 816 1299 4926 5017 1511 1118 1057 1027 1057 1118 1269 937 846 664 1148 2629 634 513 513 483 453 664 755 423 272 211 423 3173 3506 362 302 211 302 302 483 513 453
|
||||
4080 3929 3929 3869 3838 3778 3748 3717 3717 3687 3687 3657 3566 3566 3355 3476 3506 3566 4836 7556 7768 5803 2811 2146 1843 1813 1692 1843 1964 1602 1481 1390 2025 5078 2478 1511 1329 1329 1088 1209 1481 937 846 785 1118 3657 3748 1178 997 937 997 1057 1269 1299 1027 755 664 634 1178 513 362 453 453 453 604 755 423 241 181 423 2327 2780 392 181 272 423 302 695 1209 1722
|
||||
3959 3929 3929 3748 3838 3778 3717 3717 3687 3717 3657 3717 3566 3445 3536 3506 3445 3476 4413 6770 6861 4775 2690 2176 1843 1813 1692 1843 1904 1541 1450 1299 1722 4110 2055 1481 1269 1299 1239 1269 1390 1057 937 755 1027 2599 2569 1118 1148 906 997 1057 1239 1360 997 725 695 634 483 483 453 423 423 453 664 846 513 241 241 272 1299 1329 211 211 332 423 392 574 1329 1904
|
||||
4050 3869 3959 3869 3748 3778 3808 3778 3657 3748 3657 3717 3506 3476 3355 3415 3415 3324 3778 4896 5017 4050 2448 1994 1813 1753 1692 1843 1934 1450 1511 1209 1481 2629 1541 1360 1239 1269 1178 1269 1329 1057 846 695 876 1571 1511 1148 1088 846 967 1088 1269 1329 906 725 634 574 362 423 392 453 453 483 725 725 453 272 181 332 816 1088 241 423 332 423 392 604 1239 1813
|
||||
3899 3869 4050 3838 3748 3748 3748 3657 3687 3778 3627 3657 3445 3445 3445 3324 3294 3294 3264 3566 3385 2962 2297 2055 1843 1783 1662 1662 1753 1511 1360 1239 1420 2478 1420 1209 1299 1329 1178 1269 1329 1148 785 725 755 1571 1390 997 1027 816 967 1057 1148 1360 846 755 664 574 483 513 332 362 513 392 574 725 423 302 120 302 937 725 181 483 392 362 302 664 1360 1813
|
||||
3869 3838 4141 3838 3748 3687 3748 3717 3657 3717 3687 3657 3415 3506 3385 3264 3234 3294 3204 3264 3264 2871 2267 1934 1843 1783 1662 1692 1753 1420 1299 1209 1390 2418 1360 1269 1269 1269 1088 1178 1269 1088 816 634 906 1602 1420 937 967 846 967 1057 1088 1239 997 725 664 574 513 453 392 392 453 392 483 513 302 302 120 272 967 785 60 272 483 423 362 785 1299 1783
|
||||
3959 3838 3959 3899 3808 3748 3687 3657 3657 3748 3657 3597 3506 3445 3324 3385 3355 3264 3234 3264 3234 2871 2357 2055 1904 1783 1722 1662 1662 1511 1360 1148 1360 1964 1299 1178 1239 1269 1148 1118 1118 967 816 695 785 1511 1360 937 967 967 876 997 997 1057 755 604 695 513 483 423 453 423 453 423 423 362 302 151 120 211 816 785 211 332 453 453 362 574 1209 1874
|
||||
4050 3899 3959 3929 3808 3748 3748 3748 3627 3717 3687 3748 3476 3536 3476 3415 3355 3355 3234 3264 3173 2901 2327 1964 1904 1904 1813 1662 1692 1541 1420 1299 1269 1783 1329 1178 1269 1239 1088 1088 1027 906 755 695 725 1632 1450 876 967 937 906 937 846 997 785 664 695 634 483 453 483 423 423 423 513 362 272 181 151 120 785 876 211 332 483 392 272 544 1269 1692
|
||||
4020 3869 4080 4020 3899 3778 3808 3748 3657 3808 3717 3717 3627 3536 3445 3385 3385 3355 3264 3324 3143 2841 2206 2055 1904 1843 1753 1571 1692 1571 1299 1209 1329 1783 1239 1148 1148 1148 1057 1088 1027 906 725 604 785 1481 1481 816 937 876 906 967 967 967 816 725 664 604 544 513 453 362 544 423 453 453 211 181 151 90 755 725 120 423 453 513 392 483 1178 1843
|
||||
4020 4020 4080 4050 3869 3869 3838 3778 3627 3748 3687 3717 3536 3476 3506 3385 3415 3324 3264 3294 3234 2841 2206 1964 1934 1904 1813 1632 1662 1420 1299 1209 1329 1904 1178 1118 1148 1178 1118 1088 1088 846 785 634 755 1541 1450 876 816 725 846 967 937 937 846 695 725 755 544 453 513 544 604 453 513 453 241 241 90 272 937 816 0 574 513 544 362 513 1148 1904
|
||||
4050 4050 4020 3989 3899 3899 3869 3778 3748 3627 3657 3657 3536 3566 3506 3355 3506 3324 3204 3264 3143 2750 2267 2055 1934 1904 1783 1662 1722 1511 1360 1239 1269 1904 1209 1209 1209 1209 1088 1148 1057 876 816 604 816 1571 1420 906 846 816 755 906 906 997 846 725 634 664 574 392 423 483 574 423 392 423 392 302 181 272 876 755 181 604 664 483 362 544 1299 1904
|
||||
4231 4171 4141 3959 3989 3899 3808 3778 3717 3687 3748 3687 3506 3687 3506 3476 3506 3355 3294 3294 3173 2780 2206 2025 1874 1843 1813 1722 1662 1511 1360 1178 1329 1753 1209 1209 1209 1269 1148 1088 1088 906 725 604 785 1602 1420 816 906 755 937 937 876 1027 937 725 725 604 513 513 483 574 544 574 574 513 302 272 181 272 967 876 151 634 846 392 332 634 1299 2146
|
||||
4261 4201 4171 4020 4020 3959 3869 3959 3748 3687 3748 3778 3657 3627 3597 3445 3536 3476 3324 3324 3204 2780 2327 2055 1964 1904 1722 1783 1753 1571 1390 1239 1299 1874 1269 1148 1178 1269 1209 1118 1118 967 816 755 725 1541 1329 846 906 846 846 906 997 1027 876 725 695 664 664 604 574 574 664 513 634 513 392 332 241 302 967 937 211 574 755 423 453 423 1178 2206
|
||||
4443 4322 4201 4080 4050 4110 3989 4020 3748 3808 3778 3869 3657 3687 3687 3687 3536 3566 3415 3385 3294 2871 2236 2176 1934 1964 1813 1843 1843 1662 1420 1209 1329 1874 1299 1148 1239 1239 1239 1148 1148 997 846 755 816 1571 1329 937 997 816 906 906 1027 1088 876 664 695 604 695 664 634 634 604 574 664 544 423 332 241 362 1057 906 0 241 332 272 211 211 272 423
|
||||
4534 4503 4292 4171 4201 4231 4050 4141 4020 3989 3929 4080 3869 3929 3869 3899 3748 3597 3445 3476 3385 2871 2387 2146 2115 2025 1934 1964 1813 1602 1420 1269 1420 1874 1269 1329 1269 1299 1178 1178 1178 1027 906 755 906 1571 1360 906 906 876 906 997 997 1178 876 755 755 755 664 785 695 604 664 604 544 574 423 423 241 423 1148 906 90 272 272 241 211 60 120 241
|
||||
4836 4775 4594 4715 4715 4775 4866 4896 4624 4866 4836 4957 5017 5168 4987 4866 4715 4382 3476 3476 3385 3083 2357 2206 2146 1994 1904 1994 2055 1571 1481 1329 1541 2055 1329 1360 1360 1329 1209 1239 1209 1057 876 755 967 1662 1299 816 846 937 937 997 1118 1118 937 846 755 634 695 544 634 695 755 664 664 574 392 453 241 362 1209 816 90 151 211 272 241 120 90 151
|
||||
5773 6287 5954 5803 5773 6045 6166 6287 6136 6226 6287 6377 6226 6317 6105 6105 5712 5078 3717 3506 3385 3083 2448 2387 2236 2085 1874 2055 1994 1692 1541 1269 1541 2115 1269 1329 1450 1420 1239 1329 1178 1088 937 725 1027 1722 1299 816 1027 937 997 1057 1027 1088 906 816 816 725 755 755 725 695 695 695 725 725 544 332 332 362 1209 1088 211 151 241 272 302 181 181 90
|
||||
5924 6680 6801 6377 6559 6619 6710 6710 6801 6710 6649 6619 6559 6831 6619 6589 5319 4382 3627 3657 3476 3113 2448 2327 2236 2176 2025 2055 2055 1722 1571 1420 1602 2115 1390 1511 1420 1450 1299 1299 1299 1088 876 846 1027 1753 1571 967 1057 937 937 997 1027 1118 906 816 876 846 906 816 816 695 785 664 695 664 453 423 362 332 1722 1632 181 272 332 332 392 302 211 634
|
||||
5954 6770 7073 6921 6831 6770 6438 6468 6468 6408 6559 6498 6529 6831 6891 6680 5622 3929 3717 3657 3566 3143 2448 2418 2297 2267 2025 2025 2055 1753 1541 1390 1692 2115 1390 1511 1602 1450 1239 1329 1329 1148 937 816 1148 1813 1360 967 1118 906 1027 1088 1057 1148 997 876 846 1027 1027 876 725 816 846 755 755 695 513 453 483 544 1994 1843 272 302 332 332 362 392 513 937
|
||||
6559 7073 7345 7375 6861 6740 6408 6226 5833 5894 6317 6468 6468 6982 6921 6831 5561 4171 3808 3838 3748 3204 2448 2357 2357 2327 2146 2146 2025 1753 1632 1450 1843 2236 1360 1481 1481 1541 1269 1329 1420 1148 1057 906 1118 1964 1602 1027 1239 1057 1088 1118 1057 1118 1088 967 906 1088 1148 1027 816 846 906 785 785 785 604 604 513 513 1874 1904 332 513 423 302 362 302 604 937
|
||||
6619 7133 7677 7677 7435 6982 6347 5803 5803 6226 6438 6680 6498 6921 7163 6801 5591 4443 4020 4020 3899 3294 2539 2297 2357 2206 2085 2176 2055 1813 1662 1541 1813 2387 1390 1571 1541 1541 1329 1511 1481 1269 1088 997 1148 2115 1450 1178 1360 1118 1118 1209 1148 1209 1118 906 937 1057 1027 876 906 906 997 816 816 846 604 604 513 483 1571 1360 362 483 392 362 362 453 634 846
|
||||
6529 6649 7073 7284 7254 6649 6256 5833 6015 6770 6619 6831 6559 7042 6831 6287 5168 4624 4231 4110 3929 3324 2659 2478 2448 2327 2146 2176 2055 1874 1692 1571 1934 2387 1481 1722 1662 1571 1481 1511 1450 1239 1239 1057 1178 2327 1662 1239 1420 1148 1118 1178 1239 1209 1178 1027 967 1148 967 816 906 1027 937 846 785 846 755 755 664 634 1390 1118 483 513 483 483 362 332 453 725
|
||||
6680 6770 7133 7012 7103 6801 6649 6770 6649 6801 6377 6408 6166 6438 5984 5743 5017 4503 4261 4231 4050 3476 2780 2690 2508 2327 2236 2176 2025 1934 1783 1571 1994 2387 1541 1783 1722 1602 1481 1571 1571 1360 1269 1057 1178 2508 1481 1420 1481 1269 1360 1239 1299 1360 1118 1148 1088 1118 1148 906 1057 1057 1118 967 997 967 725 755 725 695 1511 1027 513 453 513 513 483 392 332 332
|
||||
7163 7314 7405 7314 7224 7345 7194 7194 7103 7012 6408 6196 5833 5712 5591 5289 4866 4503 4201 4261 3989 3445 2690 2780 2629 2539 2297 2327 2146 2055 1843 1511 1964 2508 1662 1843 1843 1692 1571 1662 1722 1602 1360 1178 1209 2569 1632 1329 1692 1420 1299 1239 1360 1511 1239 1178 1027 997 1269 1057 1118 1057 1148 997 1057 1148 846 785 755 634 937 483 483 483 513 634 544 362 211 392
|
||||
8100 8010 8070 7889 7738 7707 7798 7859 7586 7526 7284 7042 6529 6136 5652 5319 4926 4564 4261 4080 3929 3536 2750 2599 2720 2569 2327 2327 2115 2055 1843 1813 2085 2629 1722 1753 1783 1813 1753 1843 1753 1571 1481 1299 1390 2599 1843 1450 1602 1511 1390 1481 1450 1481 1420 1209 1118 1027 1209 1088 1088 1239 1329 1118 1178 1178 1088 937 876 634 816 423 544 725 634 695 604 513 241 332
|
||||
8433 8523 8251 8191 7979 7859 7889 7828 7586 7738 7647 7677 7617 7798 7526 6891 5622 4594 4292 4201 4050 3687 3083 2690 2659 2629 2508 2387 2115 2085 2055 1964 2206 2871 1874 1904 1874 1904 1964 1934 1722 1692 1541 1390 1481 2659 2146 1571 1632 1602 1571 1450 1450 1450 1269 1329 1269 1329 1964 1178 1299 1420 1329 1299 1178 1088 1088 1148 816 876 1269 574 695 785 755 785 695 604 392 574
|
||||
8765 8886 8554 8433 8493 8554 8493 8463 8070 8040 8100 8342 8282 8282 8554 8342 6680 4836 4352 4322 4020 3808 3415 3083 2690 2780 2690 2569 2387 2297 2418 2327 2599 2901 2448 2146 2236 2146 2085 2055 1874 1753 1692 1783 1934 2629 2418 1874 1874 1722 1783 1783 1753 1632 1299 1329 1390 1813 2659 2055 1722 1843 1662 1541 1481 1420 1299 1390 1178 1420 1934 1239 846 876 1027 906 876 755 332 604
|
||||
9823 9188 9068 9340 9642 9642 9884 10488 11667 11304 11183 10791 9823 9340 8735 7798 6075 4866 4322 4231 3989 3717 3536 3445 3385 3536 3294 3143 2992 2901 2932 2780 2932 3324 2901 2932 2780 2962 2629 2750 2599 2569 2629 2418 2629 2932 2659 2418 2267 2176 2055 1934 2025 1904 1692 1662 1753 2176 2841 2236 2085 2176 2146 1813 1843 1662 1692 1753 1571 1692 2176 1662 1269 1299 1299 1057 1118 1027 664 725
|
||||
63
cs309-psoc/lab_2_1/sw/nios/application/output_megane.pgm
Normal file
63
cs309-psoc/lab_2_1/sw/nios/application/output_megane.pgm
Normal file
@@ -0,0 +1,63 @@
|
||||
P2
|
||||
80 60
|
||||
16383
|
||||
5433 5186 5392 5268 5104 5227 5104 5063 5186 4857 5063 5186 5145 4898 5268 5021 4898 4816 5021 4939 5104 5104 4816 5104 4733 4939 4898 4569 4692 4733 4774 4939 4898 4610 4816 4816 5268 5474 6051 7491 7903 8150 8520 8561 8767 8808 8932 9220 9220 9179 9302 9014 7409 5598 4569 4157 4280 4034 4034 4034 3992 4075 4075 3910 3498 3293 2881 2757 2469 2552 2263 2263 2222 1975 1975 1852 1811 1728 1564 1152
|
||||
5351 5227 5186 5227 4980 5186 5227 4980 5145 4898 4857 5021 5021 4939 5063 4939 4733 4816 4816 4898 4774 4733 4774 4774 4569 4527 4569 4116 4239 4404 4610 4733 4651 4898 5598 6833 7532 7821 8191 8314 8479 8726 8891 9261 9385 9426 9714 9961 10249 10208 10290 10414 10002 8850 7244 4898 4445 4198 4116 3992 3992 4075 3869 3828 3622 3128 2799 2757 2510 2552 2346 2140 2140 1934 1934 1893 1646 1605 1358 1193
|
||||
5351 5021 5145 5104 4857 5145 4980 4939 5021 4816 5021 4816 4857 4733 4857 4692 4569 4445 4404 4527 4527 4527 4569 4527 4116 4198 4280 3869 3951 4239 4527 4816 5762 7244 7903 8150 8273 8150 8356 8726 8767 9055 9302 9879 10867 11031 11155 11484 11484 11484 11155 11072 10784 10167 9467 8397 7080 4980 4280 4075 3869 3951 4034 3787 3416 3128 2799 2428 2346 2469 2222 2099 1975 1975 1728 1564 1605 1523 1193 699
|
||||
5104 4980 5145 4898 4774 4980 4939 4816 4692 4733 4733 4651 4774 4610 4610 4486 4445 4404 4239 4322 4322 4239 4322 4280 3910 3951 4075 3663 3951 4116 5186 6997 8191 8314 8191 8232 8356 8603 8808 8808 8808 10043 11608 12925 13707 14077 14324 14365 14407 14242 13336 12390 11525 11402 11114 10373 9879 8520 6297 4569 4157 3951 3622 3540 3251 3169 2675 2552 2305 2263 2099 1934 1770 1564 1605 1481 1440 1358 1029 576
|
||||
4980 4939 4939 4857 4651 4774 4816 4774 4692 4486 4445 4651 4610 4280 4486 4239 3951 4034 3910 4157 3951 4116 4157 4075 3951 3951 3910 3663 3910 4939 7244 8356 8561 8314 8232 8479 8644 8726 8850 9508 11566 13748 14736 15148 15600 15847 16094 16259 16383 16341 15642 15230 14695 13995 13089 12348 11484 10496 9549 7779 4857 3951 3745 3457 3293 3004 2634 2552 2305 2263 1811 1605 1605 1481 1234 946 823 1234 699 411
|
||||
4774 4733 4733 4651 4610 4733 4774 4527 4610 4280 4445 4404 4445 4075 4239 3951 3787 3745 3787 3828 3869 3869 3869 4116 3910 3828 3992 3787 5145 7121 8191 8438 8520 8438 8603 8644 8726 9549 10620 13295 14654 15477 15806 16177 16218 16094 16012 16136 16136 16053 15806 15971 15600 15559 15600 14654 13336 11813 11196 10331 7697 4445 3745 3416 3128 2881 2510 2469 2140 2017 1646 1523 1440 1193 987 658 782 617 411 411
|
||||
4692 4651 4610 4651 4486 4569 4404 4527 4527 4280 4280 4239 4198 4075 3992 3745 3704 3869 3828 3869 3622 3787 3745 4034 3787 3910 3951 5021 7327 8191 8397 8644 8850 8767 8561 9179 11278 13295 14695 15724 15847 16012 15971 16053 16094 15971 15847 15765 15889 15642 15559 15559 15436 15765 15889 15559 14983 14036 12884 11813 10002 6009 3869 3416 3004 2757 2469 1975 1523 1770 1523 1193 1358 1070 658 576 493 123 246 41
|
||||
4610 4527 4527 4569 4363 4404 4486 4322 4527 4280 4198 4239 4198 3951 4075 3828 3704 3910 3745 3869 3745 3745 3745 4034 3704 3951 4816 6915 8150 8397 8603 9014 9014 8808 9879 12678 15024 15806 16012 16094 15971 16053 15847 16053 15889 15847 15724 15642 15724 15436 15395 15395 15395 15477 15436 15477 15683 15271 14324 12925 11155 7656 3992 3251 3046 2593 2305 2181 1358 1440 1152 1193 1029 864 576 452 288 288 41 0
|
||||
4610 4527 4651 4486 4280 4322 4239 4363 4157 3951 3992 4198 4198 4075 4075 3910 3745 3704 3663 3663 3663 3704 3581 3828 3622 4116 6339 8068 8438 8685 9055 9179 9467 10867 12925 15312 15847 16136 16136 16177 15930 15930 15518 15642 15600 15724 15642 15642 15683 15395 15353 15436 15230 15518 15271 15312 15436 15353 15065 13995 12102 9879 5762 3622 2881 2387 2140 1934 1564 1440 1317 1111 1029 823 535 288 288 329 123 41
|
||||
4527 4280 4404 4363 4280 4404 4157 4198 4075 3992 3910 3910 4116 4075 4034 3704 3745 3663 3581 3622 3663 3745 3745 3869 3869 4898 7903 8438 8726 8767 9179 9796 12225 12102 14530 15642 15847 16012 16177 16259 15724 15724 15436 15312 15271 15271 15312 15477 15436 15312 15353 15353 15271 15395 15353 15189 15230 15189 14818 14571 13460 12019 9508 6668 3375 2593 2181 1934 1399 1358 1399 1234 987 987 740 576 329 205 164 82
|
||||
4363 4322 4486 4280 4363 4280 4239 4239 4157 4075 3951 3992 4157 3951 4116 3910 3704 3704 3704 3745 3704 3828 3745 4034 4116 6833 8685 8685 8808 9179 9796 12472 12925 14036 15395 15683 15765 15930 16012 15971 15600 15395 15065 15024 15106 15065 15106 15271 15312 15312 15065 15106 15024 15271 15189 15271 15436 15271 14859 14571 14489 13336 10908 9302 6627 3869 2757 2222 1564 1399 1440 1070 1193 946 864 699 740 535 329 164
|
||||
4527 4280 4445 4445 4075 4239 4198 4157 4239 4116 3910 4198 4075 3992 4034 3828 3745 3745 3828 3787 3704 3745 3787 4034 4857 8191 9055 8808 9261 9714 12019 14818 13419 14859 15477 15600 15847 15806 15806 15724 15518 15312 15024 14983 15106 15024 15106 15230 15353 15230 15024 14942 14942 15106 15271 15230 15559 15477 14901 14695 14612 14242 11978 10825 9138 7038 4857 3128 2346 1770 1440 1358 1399 1193 1152 1070 987 535 246 41
|
||||
4445 4322 4404 4280 4116 4280 4157 4157 4198 4116 4075 4075 4116 4075 3992 3951 3828 3828 3869 3787 3704 3787 3704 4157 6380 8808 9220 9344 10208 10990 14530 14818 14201 15271 15353 15518 15477 15806 15642 15724 15477 15312 15148 15024 14983 14983 14901 14983 15353 15230 15106 14983 14736 14859 14983 14777 15230 15436 15065 14777 14818 14571 12884 11649 10249 8479 6791 5515 3416 2305 1811 1605 1440 1234 1029 905 823 658 411 123
|
||||
4322 4075 4322 4363 4280 4198 4116 4116 4239 4075 4075 4198 4239 3992 4034 3828 3745 3910 3869 3787 3663 3704 3787 4486 7532 9302 9508 10126 11361 12184 15312 14942 14736 15271 15312 15436 15559 15600 15600 15683 15436 15312 15065 14942 14942 14901 14901 14736 14901 15024 14901 14859 14654 14736 14654 14407 14736 14736 14818 14736 14324 14530 13460 12102 10743 9220 7656 6586 5762 4116 2428 1687 1399 1193 1070 699 782 658 576 164
|
||||
4198 4075 4322 4239 4280 4280 4157 4075 4280 4157 4075 4116 4075 3910 4075 3787 3910 3869 3787 3745 3622 3745 3828 4733 8273 9508 10126 11402 12266 14036 15436 15395 15230 15230 15312 15353 15436 15559 15600 15724 15312 15395 14983 14942 14777 14612 14571 14448 14612 14571 14365 14119 13542 13213 12678 12019 11484 10908 10496 10002 9673 9467 9055 8520 7697 6668 7080 6668 6092 5474 4527 2799 1440 905 699 617 493 617 535 452
|
||||
4116 4116 4198 4034 4157 4075 4075 4034 4198 3910 4034 4075 4075 3951 3992 3910 3828 3787 3745 3787 3622 3745 3869 5886 8891 9838 10496 12513 12678 15148 15559 15518 15312 15106 15148 15395 15395 15559 15518 15642 15477 15353 14942 14818 14942 14571 14571 14612 14777 14077 13007 11772 10661 10373 9796 9179 8973 8767 8232 7985 7656 7450 7080 6956 6092 5968 6009 7491 6133 5639 4939 4280 2510 1070 740 576 535 740 658 493
|
||||
4075 4116 4198 4157 4034 4116 4034 3951 4116 3992 3992 4116 4075 3910 4034 3869 3745 3828 3704 3704 3622 3745 4651 8191 9961 10414 11319 13707 13707 15353 15353 15106 15148 15148 15148 15189 15353 15518 15518 15683 15518 15436 15106 14942 14859 14736 14612 14077 13007 11978 11361 10743 9879 9714 9014 8479 8314 7985 7697 7532 7080 6997 6627 6215 6051 5474 5680 7656 6874 5762 5227 4733 4239 2181 1523 1111 946 1399 1029 864
|
||||
4198 4157 4239 4157 3992 4034 4075 4157 4239 3951 3869 3951 4034 3828 4116 3951 3745 3704 3622 3622 3704 4075 5474 9302 10578 10825 12554 14489 14654 15230 15065 15024 14942 14695 14695 14612 14736 15230 15230 15395 15436 15518 14983 14777 14365 13707 12842 12472 12102 11443 10825 10126 9632 9385 8808 8356 7985 7821 7450 7203 6997 6750 6586 6421 5845 5515 6092 8026 7697 6421 6174 5804 5433 4651 2963 2017 1893 1728 1317 782
|
||||
4280 4034 4198 4157 3910 3951 4034 4157 4404 4034 4034 4157 4034 4034 4075 3663 3622 3540 3663 3663 3622 4034 6668 9796 10949 11443 13501 15148 14942 14407 13913 13666 13089 12760 12143 12390 12678 13172 13625 14201 14160 13913 13295 13089 12925 12637 12513 12184 11525 11031 10496 10043 9385 9302 8726 8232 7944 7821 7574 7409 7285 7574 7409 6915 6462 6503 6668 8068 8685 7574 6668 6051 5639 5104 4034 2222 1852 1687 1234 1029
|
||||
4322 4239 4322 4198 3951 3992 4034 4198 4157 4075 3992 3910 3951 3828 3992 3540 3498 3498 3498 3622 3498 4692 7944 9961 11072 11937 13295 13378 11649 10537 9920 9796 9755 9714 10126 10496 11196 11525 11937 12554 12966 13048 12719 12925 12925 12801 12348 11937 11278 10743 10290 10002 9426 9055 8726 8232 8191 7903 7862 7738 7574 7574 7574 7368 6874 6874 7203 7862 8932 8232 7080 6586 5804 5063 3828 2140 1687 1646 946 1029
|
||||
4322 4363 4239 4198 3992 3992 3910 4157 4116 3951 4075 3951 3828 3787 3869 3540 3334 3416 3334 3498 3869 5680 8273 10331 10537 10002 8932 8068 8150 8273 8561 8932 9138 9179 9426 9920 10455 10908 11402 12184 12678 13501 14407 14489 14324 13254 12678 12019 11525 10949 10537 10043 9673 9302 9014 8644 8397 8191 8150 7903 7903 7738 7532 7368 7162 6956 7450 7738 9220 8438 7203 6586 5598 4733 2963 1111 823 782 740 699
|
||||
4404 4239 4322 4239 4034 4034 4116 3951 4034 3910 3951 3869 3787 3787 3828 3745 3375 3498 3416 3704 5433 6586 7697 7903 7327 7409 7821 7532 7532 7903 8150 8644 8891 9097 9261 9838 10167 10620 11237 11772 12719 14365 14859 14777 14736 14036 13254 12719 11896 11278 10867 10537 10085 9796 9344 9055 8932 8561 8356 8356 8191 7821 7409 7244 6997 7532 9879 7903 9055 8397 6997 6297 5433 4816 3087 987 782 699 452 576
|
||||
4280 3992 4198 4034 4116 3951 4034 3992 4075 3704 3828 3828 3663 3704 3828 3498 3416 3540 3457 4857 5845 6215 6503 6956 6833 7244 7450 7409 7491 7738 8026 8520 8850 9014 9344 9591 10167 10661 10990 12019 12801 14407 14489 14448 14407 14407 13830 13172 12390 11772 11031 10743 10167 9838 9426 9055 8973 8685 8561 8314 8026 7697 6997 6833 6668 8314 12842 8685 8932 8644 7080 5927 5021 4569 4280 2593 2675 2716 1070 370
|
||||
4280 4034 4198 4198 4075 4116 3992 3951 3951 3745 3828 3828 3869 3745 3787 3540 3375 3540 3869 5845 5845 6174 6544 6915 6750 7121 7409 7409 7656 7985 8273 8644 8808 8932 9385 9879 10208 10743 11566 12390 13419 14283 14283 14242 14242 14283 14077 13707 12801 11855 11319 10825 10249 9755 9385 9014 8891 8644 8273 8232 7821 7532 6997 6791 6627 9220 13954 10825 8685 8808 7285 5968 4733 4116 4239 4198 3869 3663 2799 905
|
||||
4157 3869 4157 4075 4034 3992 3951 3828 3869 3787 3745 3869 3869 3704 3869 3581 3457 3540 4980 6339 6092 6339 6586 6915 6956 7368 7656 7574 7862 8026 8191 8561 8932 9179 9508 10002 10414 11031 11731 12925 13789 14365 14160 13954 13995 14201 14324 13913 13460 12431 11649 11072 10455 9920 9426 8932 8891 8603 8232 7944 7738 7121 6627 6668 6503 11608 14283 12225 9920 9220 8232 6956 5886 5063 4610 4322 3992 3498 3540 1481
|
||||
4239 4034 4116 4157 4034 3992 3951 4075 3951 3704 3910 3910 3910 3581 3745 3540 3540 3992 5557 6339 6256 6215 6503 7121 7203 7574 7615 7491 7697 7944 8068 8603 8932 9055 9385 9838 10455 11072 11813 12925 13995 14283 14160 13872 13872 14036 14242 14077 13872 12966 12019 11278 10496 10167 9591 9179 8767 8438 7944 7821 7574 7162 7162 8150 11649 13789 14283 13460 11278 10043 8726 7738 6544 6009 5557 4898 4651 3828 3663 1975
|
||||
4034 3992 4157 4157 3992 4034 3992 4116 3992 4075 3828 3910 3828 3787 3787 3540 3457 3869 5433 6339 6668 6339 6339 6997 7038 7450 7532 7368 7697 7862 7985 8397 8726 9014 9302 9755 10496 11196 12143 13172 14119 14571 14036 13830 13830 13707 13748 13954 14242 13460 12307 11608 10825 10331 9673 9014 8767 8767 8767 9220 10167 11525 12678 14077 14407 14036 14530 13830 12431 10825 9467 8232 7409 6874 6256 5227 5104 5145 4239 3581
|
||||
4198 3951 4157 4075 4075 4116 4034 4075 4157 4075 3910 3951 3869 3663 3663 3540 3498 3663 4774 6133 6627 6627 6297 6750 7080 7327 7532 7532 7615 7738 7944 8356 8561 8808 9220 9714 10455 11402 12307 13172 14283 14448 13954 13954 13789 13748 13583 13707 14119 14242 13913 13542 12760 12637 12637 12719 13172 13872 14160 14571 14736 15024 14777 15148 14612 14201 14407 14530 13254 11443 10085 8932 7532 5762 4569 4404 4198 4157 3787 3663
|
||||
4280 4198 4116 4034 3992 4034 3992 4034 4116 4116 3951 3910 3910 3663 3787 3622 3457 3581 3869 5680 6462 6874 6421 6791 6997 7409 7491 7532 7615 7615 7532 8150 8603 8808 9097 9632 10290 11278 12184 13872 14407 14160 14036 13954 13954 13995 13913 13378 13995 14119 15024 15271 15230 15230 15353 15312 15189 15395 15230 15353 15148 15106 15189 15148 14942 14489 14201 14654 13213 11772 10085 8726 6421 4651 4075 4116 3581 3046 2799 2881
|
||||
4322 3828 4198 4075 3951 3951 3951 3910 4075 3828 3787 3787 3704 3581 3704 3622 3498 3498 3828 6051 6627 7038 7203 6750 6956 7203 7285 7080 7162 7327 7327 8150 8479 8850 9220 9920 10373 11443 13583 14489 14160 14283 14201 14119 14077 14201 13954 13789 13460 13419 14530 15436 15477 15559 15559 15477 15600 15518 15477 15312 14983 15106 14983 14983 14777 14365 13995 14119 13419 11813 9673 7532 5104 4322 3622 3416 3004 3128 2675 2510
|
||||
4157 4116 4034 4075 3869 4075 3951 3787 3992 3787 3663 3581 3663 3540 3828 3745 4322 4651 5145 6544 6215 7615 8479 7944 6750 6586 6874 6750 7162 7368 7656 8068 8397 8932 9508 10702 12472 14283 14818 14407 13995 14242 14283 14160 13995 14119 13995 13501 13048 13048 13583 15312 15436 15477 15436 15189 15189 15189 15189 15106 14654 14489 14736 14242 14160 13542 13089 13089 12966 10908 9097 6380 4157 3457 3210 3046 2757 2799 2716 2346
|
||||
4157 3951 4034 3951 3745 3910 3745 3745 3622 3581 3498 3540 3540 3498 3787 5310 6627 6586 6586 6791 6586 8603 9796 10085 8356 7203 7285 7327 7574 8232 8891 10043 11484 12966 14365 14983 15148 15106 15148 14119 13830 13995 14119 14036 14119 13913 13213 11772 12266 12390 12760 14695 15065 14942 14571 14736 14695 14818 14859 14859 14407 14365 14036 13789 13625 13295 13131 12719 12637 11031 9055 6380 3992 3540 3293 3004 2716 2799 2799 2675
|
||||
4075 3910 3992 3869 3745 3910 3828 3745 3787 3540 3581 3622 3581 3581 4486 6503 6874 6874 6874 7285 8109 9138 10537 10949 12842 12842 12637 12842 13625 13666 14077 14695 15148 15559 15436 15395 15477 15353 14942 13625 13460 13336 13378 13913 13995 13995 13048 10373 11443 12143 12554 14365 14777 14654 14448 14283 14201 14530 14160 14119 14036 14160 14036 13748 13501 13254 12925 12925 12884 11443 9385 7080 4363 3910 3622 3169 3004 2922 2799 2469
|
||||
4157 3828 4075 3951 3787 3992 3787 3787 3745 3663 3540 3704 3663 3581 5063 6503 6380 6833 7203 7656 8150 9179 10620 11855 13625 14530 14942 14901 14818 14818 15024 15271 15436 15477 15477 15518 15477 15353 14283 13625 13213 12637 12966 13666 14119 14036 13542 12554 12390 12390 12801 14242 14695 14654 14489 14119 14201 14119 13872 13995 13913 14077 13872 13954 13748 13995 13542 13625 13336 12019 10126 8150 5557 4157 3787 3416 3169 3046 2799 2140
|
||||
4034 3828 3992 3910 3745 3745 3787 3704 3663 3663 3622 3745 3745 3745 5433 6339 5845 6956 7285 7697 8356 9426 10702 12225 13625 14407 15106 14818 14736 14818 15024 15271 15189 15065 15065 15106 15312 15353 14489 13830 13872 13583 14119 14119 14324 14201 13913 13501 13789 13295 13583 14612 14571 14736 14489 14160 14077 13995 13913 13913 14077 14119 14283 13872 14119 14036 13995 13913 13501 12554 10496 8685 6874 4692 4116 3910 3375 3128 2799 2181
|
||||
3992 3828 3910 3828 3787 3745 3745 3745 3581 3457 3622 3663 3745 4239 5804 6544 6503 6997 7285 7615 8273 9261 10373 12060 13625 14201 14654 14448 14530 14612 14818 14859 14901 14695 14654 14901 15148 15353 14736 14365 14654 14407 14407 14283 14365 14160 13748 13830 14036 14242 14448 14859 14859 14983 14736 14242 14119 13954 13954 14077 14077 14283 14242 14119 14201 14119 14077 13913 13625 12801 10578 8520 7450 6009 4363 3910 3334 3004 2757 2222
|
||||
4034 3745 3869 3787 3745 3704 3663 3540 3581 3581 3540 3581 3745 4980 6009 6421 6544 6791 7080 7327 8026 8726 10126 11566 13089 13872 14324 14242 14448 14612 14612 14612 14365 14242 14324 14695 15148 15395 15271 15148 14777 14859 14489 14160 14324 14242 14119 14160 14283 14407 14530 14695 14695 14859 14736 14407 14242 14036 13913 13913 13913 14160 14201 14242 14283 14119 13913 13789 13583 12760 10620 8644 7244 6380 5557 4527 4280 3745 3210 2263
|
||||
4034 3745 3745 3787 3581 3622 3498 3498 3540 3457 3416 3540 3828 5227 6051 6256 6421 6709 6915 7327 7738 8561 9632 11361 12760 13625 14201 14324 14365 14489 14365 14160 14201 13913 14160 14695 15148 15271 15436 15312 15271 15024 14571 14407 14324 14365 14489 14283 14407 14283 14407 14571 14612 14859 14777 14530 14489 14201 13913 13872 13707 13954 14077 14077 13954 13501 13172 13336 13048 12431 10537 8685 7244 6215 5762 5310 4857 4610 4157 2881
|
||||
3828 3457 3787 3704 3540 3622 3498 3498 3416 3375 3498 3663 3951 5392 5968 6092 6133 6462 6791 7203 7615 8479 9179 10990 12719 13748 14283 14365 14365 14407 14283 14242 14119 13954 14242 14777 15230 15230 15148 15189 14901 14859 14736 14448 14612 14612 14448 14201 14324 14160 14365 14530 14448 14695 14818 14654 14654 14448 14201 13872 13748 13789 13830 13830 13666 13583 13089 13172 13172 12554 10496 8644 7327 6503 5845 5598 5227 5063 4692 3704
|
||||
3787 3416 3787 3704 3622 3622 3581 3540 3498 3375 3457 3622 3828 5433 6174 6215 6256 6421 6956 7450 7697 8397 9097 10784 12760 13707 14489 14654 14654 14407 14160 14283 14201 14160 14489 14983 15106 15065 14859 14859 14736 14695 14654 14283 14324 14119 13872 13913 13995 13995 14160 14201 14283 14654 14736 14859 14736 14571 14324 14036 13748 13830 13913 13830 13830 13583 12966 13172 13007 12719 10661 8850 7574 6709 6256 5680 5598 5433 4733 3663
|
||||
3745 3498 3704 3787 3622 3622 3622 3498 3581 3498 3457 3540 3869 5598 6256 6380 6421 6503 6956 7327 7779 8273 9055 10620 12719 13913 14530 14571 14777 14489 14242 14242 14365 14448 14777 15024 15106 14901 14818 14736 14654 14489 14324 14283 14077 13872 13789 13707 13830 13748 13789 14036 14077 14407 14530 14571 14983 14942 14736 14119 13830 13872 13872 13913 13872 13625 13213 13089 13007 12760 10990 8973 7738 6997 6380 6133 5721 5268 4898 3787
|
||||
3992 3581 3828 3951 3745 3828 3663 3745 3828 3663 3622 3663 4034 5598 6256 6462 6586 6750 7038 7532 7779 8356 9055 10414 12266 14077 14571 15024 14859 14489 14160 14201 14407 14530 15065 15148 15148 14901 14571 14654 14489 14448 14201 13954 13872 13872 13666 13707 13913 13872 13830 13872 13830 14201 14365 14571 14859 15065 14818 14489 14077 14119 14036 14036 13666 13583 13131 13048 12966 13007 10949 9302 8068 7244 6668 6297 5968 5598 5063 3787
|
||||
3951 3787 4075 3992 3951 4034 3992 3910 3869 3787 3581 3663 4075 5557 6380 6421 6544 6874 7244 7615 7738 8232 8891 10290 11731 13830 14654 14983 14859 14407 14036 14324 14530 14777 15230 15189 15024 14777 14612 14612 14489 14365 14160 14036 14036 14036 13954 13913 14201 14160 13995 14077 14119 14160 14407 14530 14901 15106 14942 14654 14077 14242 14283 14160 13830 13995 13625 13295 13089 13007 11402 9426 8314 7409 6709 6339 6051 5680 5021 3992
|
||||
4239 4239 4404 4198 3951 4034 3992 3869 3910 3787 3663 3745 4075 5474 6421 6791 6833 6956 7285 7574 7738 8356 8891 10002 11443 13419 14654 14983 15024 14571 14036 14448 14901 14942 15395 15353 15106 14777 14489 14489 14324 14242 14489 14530 14695 14571 14489 14365 14571 14407 14324 14242 14242 14324 14571 14818 14983 15230 15024 14612 14365 14283 14365 14448 14324 13954 13748 13748 13501 13336 11484 9632 8356 7491 7038 6544 6009 5557 5186 4034
|
||||
4322 4116 4322 4075 3910 3992 3869 3951 4034 3787 3828 3787 4116 5227 6421 6586 6791 6956 7285 7697 7821 8191 8891 9961 10949 12884 14407 14818 14901 14654 14365 14530 14942 15230 15353 15148 14901 14736 14571 14324 14242 14530 14530 14612 14818 14695 14612 14530 14654 14654 14736 14530 14242 14283 14571 14859 15065 15189 15065 14983 14571 14489 14612 14448 13995 13872 14036 13789 13542 13295 11484 9714 8397 7615 6915 6380 6051 5721 5351 4280
|
||||
4527 4157 4198 4075 3869 4034 3787 3910 4157 3869 3704 3869 4116 5063 6339 6709 6833 7038 7327 7697 7862 8273 8891 9632 10578 12431 14201 14777 14859 14695 14489 14695 15024 15189 15353 15230 14983 14859 14530 14448 14489 14489 14736 14612 14777 14818 14859 14818 14859 14736 14612 14736 14448 14489 14530 14859 15230 15395 15148 15024 14695 14612 14695 14489 14365 13995 13872 13830 13583 13213 11649 9796 8479 7574 7244 6586 6215 6009 5515 4239
|
||||
4363 3951 4157 4034 3869 3992 3869 3869 4075 3869 3787 3869 4075 5063 6380 6709 6915 7038 7327 7697 7862 8191 8850 9549 10455 12102 13872 14612 14942 14777 14448 14942 15148 15271 15230 15395 15395 14859 14448 14530 14654 14695 14901 14777 15024 15189 15148 15189 15189 15024 14983 14777 14654 14695 14859 14818 15148 15230 15353 15189 14859 14695 14654 14571 14160 14036 14036 14077 13583 13295 11443 9755 8520 7574 7080 6750 6215 6009 5392 4075
|
||||
4363 4034 4116 4157 4034 3992 3787 3951 4157 3910 3951 4034 4239 4857 6215 6750 6833 7244 7697 7738 7944 8150 8726 9467 10126 11566 13378 14407 14818 14695 14571 14942 15106 15189 15436 15518 15189 14859 14530 14571 14777 14859 15065 15189 15436 15600 15436 15559 15518 15353 15230 15230 15024 14901 15106 14901 15024 15271 15189 15271 14859 14654 14612 14448 14201 13995 13995 14077 13666 13295 11484 9714 8603 7656 7162 6668 6174 5804 5351 4198
|
||||
4445 3992 4280 4157 3992 4198 3992 3992 4034 3951 3910 4075 4239 4527 5927 6503 6791 7285 7532 7862 7903 8314 8479 9344 9879 11237 12925 14242 14736 14736 14612 14983 15148 15395 15353 15724 15312 14983 14818 15065 15024 15189 15477 15600 15724 15765 15847 15724 15847 15600 15518 15600 15148 15230 15065 15024 15148 15271 15230 15395 14983 14612 14530 14365 14077 14160 14201 14201 13830 13460 11361 9714 8561 7738 7162 6750 5968 5721 5186 4322
|
||||
4404 3992 4322 4198 4198 4116 4075 4198 4198 4075 4075 4075 4239 4198 5598 6339 6627 7162 7491 7779 7944 8273 8314 9055 9838 10990 12554 13954 14530 14654 14695 14901 15148 15477 15518 15642 15271 15065 15230 15312 15312 15518 15683 15889 15889 15889 16012 15971 15930 15889 15724 15724 15271 15230 15230 15106 15024 15230 14983 15106 15065 14901 14571 14448 14448 14283 14324 14160 13789 13089 11114 9385 8520 7697 7080 6380 5845 5268 4816 4322
|
||||
4445 4239 4404 4239 4157 4157 4157 4280 4280 4075 4157 4280 4157 4116 5186 6133 6791 7203 7491 7697 8026 8232 8438 9014 9632 10620 12060 13666 14489 14489 14489 14942 15230 15395 15724 15806 15724 15477 15436 15600 15518 15642 15889 16012 16094 15889 15971 15930 16012 15806 15806 15600 15395 15395 15353 15148 15065 15106 14859 14983 15106 14983 14695 14530 14489 14407 14201 13995 13542 12966 11031 9220 8479 7656 6997 6297 5598 5104 4733 4569
|
||||
4569 4116 4404 4322 4157 4239 4280 4363 4322 4198 4239 4322 4198 4034 4651 5762 6750 7285 7532 7903 8191 8644 8561 8973 9549 10496 11608 13089 14283 14365 14530 14818 15271 15395 15642 16094 15600 15724 15683 15806 15765 15806 15724 15930 15889 15930 15806 15889 16012 15765 15806 15642 15518 15642 15518 15148 15106 14777 14571 15065 14983 15024 14571 14571 14324 14407 14036 13954 13336 12719 10578 9261 8314 7450 6668 5927 5351 5104 4651 4198
|
||||
4733 4157 4322 4363 4157 4445 4280 4445 4363 4280 4322 4363 4322 4075 4322 5433 6586 7244 7532 7903 8273 8685 8726 9055 9385 10331 11278 12842 13995 14283 14530 14818 15312 15436 15765 16136 15847 15765 15847 15889 15724 15765 15600 15806 15889 15847 15847 15889 15889 15889 15847 15518 15395 15683 15477 15106 15024 14736 14571 15065 15395 15148 14777 14612 14612 14324 13830 13872 13213 12801 10578 9014 8026 6874 6051 4034 4527 4816 4569 4157
|
||||
4816 4527 4527 4569 4404 4486 4486 4445 4527 4280 4280 4363 4404 4198 4280 4816 6215 7244 7615 8026 8314 8603 8850 9055 9179 10126 11031 12266 13954 14407 14530 14901 15230 15477 16053 16177 15930 15971 16012 16053 15765 15889 15765 15724 15765 15930 15847 15971 15971 15930 15930 15600 15353 15477 15436 15189 15148 14942 14695 14901 15271 15230 15065 14901 14736 14448 14036 13748 12966 11731 9879 8191 6874 5104 4445 2757 3745 4692 4527 4239
|
||||
4857 4610 4774 4733 4569 4486 4404 4527 4445 4322 4363 4404 4486 4198 4363 4280 5433 7038 7491 7944 8314 8726 8932 9055 9055 10002 10620 11690 13666 14201 14489 15065 15395 15436 15806 15930 15642 15889 15971 16094 15642 15683 15765 15683 15889 15930 16012 15889 16053 15971 15930 15765 15395 15395 15436 15312 15189 14818 14818 15024 15148 15312 15189 15148 14777 14571 14160 13707 12060 7285 5845 4857 3046 2058 2099 2305 4280 4486 4610 4239
|
||||
5145 4774 4857 4857 4733 4733 4527 4363 4610 4404 4404 4445 4569 4404 4527 4322 4692 6586 7532 7944 8150 8520 8808 9138 9014 9755 10414 11237 13131 14119 14530 14942 15518 15518 15683 15518 15395 15847 15806 15765 15724 15889 15683 15765 15971 16012 16094 15971 16136 16053 15971 15930 15230 15477 15395 15189 15230 15189 15065 14942 15189 15312 15353 15312 14942 14530 14119 13583 11525 4363 2716 2510 2099 1811 1975 3992 4075 3540 4980 4445
|
||||
5145 4939 4898 4898 4774 4857 4651 4569 4651 4445 4486 4445 4651 4569 4404 4198 4198 5474 7121 7656 8026 8397 8644 8932 9014 9632 10167 10784 12348 14119 14695 15065 15477 15559 15559 15477 15477 15847 15889 15930 15930 15765 15765 15889 16136 16177 16300 16053 16259 16094 15930 15765 14901 15230 15230 15271 15106 15395 15230 15106 15024 15189 15353 15395 14695 14365 13913 13542 10949 3951 2675 2263 1975 1893 3210 4280 3087 2634 4939 4569
|
||||
5433 5021 5145 5104 4939 4980 4733 4733 4774 4569 4527 4569 4692 4404 4610 4363 4198 4445 6133 7327 7697 8068 8232 8356 8438 9302 9838 10496 11402 13131 14448 15106 15312 15600 15559 15600 15683 15847 15847 16012 15806 15847 15765 15806 16094 16300 16300 16053 16136 15806 15930 15642 15230 14942 14983 15024 15106 15148 15395 15189 15230 15436 15353 15230 14736 14201 13789 13172 10743 4280 2552 2058 2058 2552 4610 3787 2140 2922 4980 4486
|
||||
5515 5145 5186 5021 4898 4980 4857 4774 4939 4651 4733 4569 4733 4610 4774 4569 4322 4239 4692 6133 6874 7121 7121 6874 6544 7409 9261 9673 10373 11855 13419 14777 15230 15271 15559 15600 15600 15724 15642 15889 15847 15724 15559 15889 16012 16136 16094 16218 16300 15930 15683 15436 14983 14901 14901 14818 14818 15189 15189 15271 15189 15395 15395 15230 14942 14160 13460 13172 9755 3457 2263 1934 2140 3828 4651 3622 3951 4363 4898 4651
|
||||
5804 4898 5063 4980 5104 5515 5145 5433 5639 5186 5474 5392 5433 5351 5351 5104 4733 4733 4733 5392 5392 5392 5145 5021 4857 5186 6709 6668 6997 8397 10126 14160 14777 15230 15436 15477 15395 15559 15765 15477 15395 15436 15395 15600 16094 15971 16053 16094 16053 15724 15724 15312 14612 14859 14612 14489 15148 15518 15230 15353 15312 15271 15477 15312 14983 14119 13625 13336 9385 3457 2263 1770 2263 4692 4939 4527 3540 4898 4569 4569
|
||||
63
cs309-psoc/lab_2_1/sw/nios/application/output_pc.pgm
Normal file
63
cs309-psoc/lab_2_1/sw/nios/application/output_pc.pgm
Normal file
@@ -0,0 +1,63 @@
|
||||
P2
|
||||
80 60
|
||||
16383
|
||||
4899 5358 6175 6086 6022 6098 6124 6239 6111 6098 6098 6162 6150 6188 6328 6405 6481 6532 6532 6520 6532 6430 6532 6520 6481 6417 6430 6405 6341 5244 4746 4657 4478 4401 4325 4197 4197 4121 4223 4185 4185 4172 4172 4197 4197 4159 4134 4031 3968 3942 4108 4159 4108 4019 3993 3827 3929 4210 4172 4108 3942 2692 1288 2143 2998 3534 3317 2972 3904 4555 4529 4389 4095 2360 880 905 1046 931 484 331
|
||||
5384 5142 5907 6162 6188 6137 6188 6264 6137 5907 5882 5920 6035 6137 6213 6264 6354 6366 6430 6392 6354 6035 6264 6456 6430 6354 6252 6226 6239 5065 4427 4274 4172 4172 4044 3980 3929 3891 3929 4006 4057 3993 3993 4057 4057 4044 4082 3968 3929 4019 4172 4236 4146 4082 4070 4095 4185 4172 4185 4108 3968 2730 1186 2130 3483 3751 3840 2960 3725 4338 4350 4172 3840 2309 842 701 740 829 433 318
|
||||
5371 5078 4759 4325 5014 5869 6047 6341 6456 6277 6252 6150 6252 6264 6213 6264 6290 6290 6277 6290 6264 5907 6060 6430 6354 6303 6303 6175 6188 5256 4593 4376 4185 4108 4006 3968 3917 3815 3853 4006 4134 4108 4082 4134 4108 4108 4121 4108 4108 4121 4197 4312 4236 4210 4248 4299 4376 4389 4287 4134 3929 2909 1237 2271 3687 3827 4006 3100 3623 4210 4134 3993 3623 2143 765 599 689 740 318 255
|
||||
4720 4950 3406 2653 3355 4376 5371 6201 6558 6443 6328 6175 6086 5971 5958 5984 5958 5843 5677 5435 5435 5818 6213 5703 5831 6226 6264 6201 6150 5486 4644 4542 4389 4261 4134 4108 4044 4095 4134 4210 4210 4159 4134 4185 4350 4427 4427 4937 5282 4988 4925 5244 5461 5575 5728 5779 5652 5065 5052 4453 4044 3457 1696 2424 3483 3496 3955 3470 3700 4095 3993 3815 3521 2181 676 510 586 701 306 216
|
||||
3968 3393 2551 2398 3304 4185 4236 4784 5767 5882 5575 5295 5142 5052 5001 4899 4708 4695 4733 4733 4759 4861 4797 4504 4567 5409 5996 5856 5869 5754 4899 4440 4210 4159 4185 4236 4414 4555 4682 4797 4899 4874 4810 4848 5473 6430 6226 5869 6290 6481 6328 6596 6711 6698 6532 6392 6009 5065 5193 4695 4095 3687 2041 2398 3266 3304 3661 3368 3572 4044 3878 3725 3368 2118 599 472 535 599 306 204
|
||||
4185 3751 2679 2334 3075 3891 3802 3891 3980 4299 4555 4593 4682 4682 4657 4720 4555 3904 4478 4720 4708 4682 4657 4529 4708 5512 5907 5805 5831 5894 5537 5065 4440 4848 5384 5690 5805 5856 5958 5984 5882 5486 4899 5320 6111 6966 6928 6520 6609 6839 6941 7132 7413 7476 7234 6571 6290 5779 5397 4797 4146 3738 1990 2105 3036 3177 3355 3151 3432 3993 3827 3649 3291 2181 650 433 497 561 255 216
|
||||
3585 3393 2411 2181 2807 3636 3572 3585 3649 3649 3955 4376 4644 4874 5052 5065 5027 4223 4478 4682 4669 4784 5537 5652 5779 5945 6060 5882 6047 6201 6047 5907 5244 5065 5333 6009 6035 6162 6252 6188 6009 5767 5346 5728 6264 6966 7068 6864 6660 6787 7234 7515 8025 8650 8114 6928 6685 5703 5142 4695 4146 3866 2232 2169 2985 3049 3126 2947 3355 3929 3751 3610 3253 2169 561 344 408 459 255 102
|
||||
3725 3342 2807 2130 2768 4108 3610 3521 3419 3445 3623 3891 4185 5090 5537 5473 5690 5767 4861 4644 4746 4733 5371 5984 6086 6137 6188 6060 6098 6047 6047 6124 5984 5805 5971 6188 6303 6507 6379 6341 6150 6022 5920 6022 6520 6902 7081 7055 6864 6698 7311 7770 8268 8803 8038 6839 6532 5499 4657 4312 4019 3891 2602 2385 2921 3036 2985 2819 3253 3827 3674 3508 3164 2258 433 331 357 421 229 76
|
||||
3636 3177 2947 2207 3062 4287 3470 3393 3368 3342 3496 3687 3980 4708 5550 5677 5831 5971 5550 4784 4835 4848 5269 5971 6201 6239 6098 5805 5779 5907 6124 6277 6366 6430 6468 6775 7094 6851 6456 6532 6392 6213 6124 6354 6609 6877 7157 7209 6915 6698 7157 7757 7872 7630 7528 7068 6430 5626 5154 5039 4389 4236 2704 2653 2896 2947 2870 2794 3215 3827 3623 3445 3177 2220 459 293 318 382 216 89
|
||||
3381 2972 3062 2590 3470 4019 3445 3342 3381 3317 3381 3585 3904 4937 5818 6086 6111 6150 6047 5078 5103 5193 5779 6188 6558 6354 6086 5741 5805 6047 6264 6443 6468 6443 6609 6953 7502 7081 6660 6583 6507 6252 6252 6443 6596 6826 7145 7272 6992 6685 7004 7553 7464 7234 7132 6787 6430 5920 5779 5218 4401 3355 2641 2717 2819 2909 2768 2781 3138 3789 3585 3393 3215 2334 510 318 318 357 267 76
|
||||
3164 2909 2960 2564 3534 3610 3419 3432 3393 3330 3355 3432 3815 4376 5741 6417 6622 6532 6545 6430 6698 6736 6877 6724 6800 6660 6303 6111 5907 6098 6354 6392 6660 6634 6647 6877 7157 6724 6443 5843 5831 6226 6290 6443 6545 6762 7055 7285 6979 6571 6953 7464 7272 6966 6507 5894 5473 5320 5180 4874 4121 3138 2653 2666 2845 2845 2743 2730 3049 3764 3598 3445 3177 2411 535 306 344 408 204 76
|
||||
2985 2807 2832 2513 3100 3470 3432 3585 3432 3342 3355 3432 3738 4146 5831 6634 6941 6775 6953 6928 7387 7323 7106 6813 6698 6749 6507 6150 5843 5984 6379 6481 6634 6698 6711 6736 6775 6520 5129 3623 3508 5027 6162 6430 6545 6800 7068 7234 6979 6520 6877 7502 7221 7170 6915 4874 4274 4172 4197 4299 4134 3980 2998 2717 2807 2832 2717 2692 3011 3687 3585 3419 3126 2462 599 637 727 765 216 89
|
||||
2819 2807 2730 2551 2947 3445 3547 3585 3496 3393 3317 3393 3534 4031 5869 7004 7260 7374 7374 7795 8446 8344 7438 4912 4810 6111 6749 6264 5805 5894 6354 6532 6571 6647 6775 6762 6749 6520 4376 3610 3483 4440 6035 6443 6520 6826 7004 7311 7017 6520 6979 7681 7974 7757 7119 4861 4325 4159 4248 4236 4121 4159 3023 2666 2756 2858 2756 2756 2960 3687 3521 3406 3151 2551 701 714 842 816 204 0
|
||||
2832 2756 2666 2602 2972 3521 3585 3559 3547 3445 3355 3330 3432 3993 6201 7247 7591 8012 8204 8701 8931 8829 6545 4350 4223 4835 6839 6328 5831 5818 6315 6456 6315 6583 6468 6379 6252 5933 4899 3623 3840 5180 6315 6545 6558 6711 6966 7323 7081 6456 6902 7642 8012 7936 7374 4835 4057 4006 4057 4210 4172 4159 3126 2653 2756 2845 2832 2794 2934 3610 3508 3432 3177 2653 689 752 1071 727 165 63
|
||||
2756 2692 2653 2666 3062 3725 3661 3674 3661 3585 3381 3279 3419 3968 6405 7693 8191 8625 8612 8893 8995 8957 7260 4567 4236 5193 6303 6328 5971 5920 6264 6379 6201 6137 6073 6047 5371 4823 5231 5346 5614 6188 6596 6622 6571 6685 6915 7272 7094 6430 6800 7604 8000 7642 6915 4708 3980 3942 4057 4108 4134 4121 3126 2653 2781 2896 2832 2858 2934 3649 3496 3406 3113 2641 663 306 637 421 318 89
|
||||
2781 2666 2615 2717 3138 3904 3866 3789 3878 4057 3636 3304 3393 3802 6405 8408 8854 9020 8395 8791 8995 8957 9110 8433 7757 6864 6405 5894 6111 6277 6379 6201 6022 6009 5805 5652 5154 4491 4733 5741 6354 6622 6558 6609 6583 6660 6839 7247 7043 6417 6622 7425 7821 7285 6583 4797 3955 3776 3853 3993 3942 3993 3202 2653 2845 2972 2934 2921 2985 3623 3521 3393 3189 2743 765 293 306 382 331 178
|
||||
2743 2704 2653 2756 3036 3904 3917 3802 4108 4338 4095 3368 3381 3751 6596 9467 10296 9939 9122 8931 8931 8918 9569 10807 10845 9914 6877 5142 5256 5792 6035 5971 5856 5831 5601 5512 5154 4427 4606 5843 6545 6583 6481 6494 6545 6571 6736 7234 6966 6201 6494 7247 7311 6839 6150 4657 3853 3687 3827 3891 3904 3917 3253 2615 2921 3075 3075 2960 2896 3521 3457 3381 3177 2756 893 293 344 382 344 114
|
||||
2768 2717 2653 2743 2998 3891 3917 3815 4325 4606 4401 3470 3406 3636 6877 11751 12937 10794 10130 9569 9059 9084 9709 11126 11266 10449 7464 5180 4771 4899 5358 5716 5869 5805 5473 5614 5295 4274 4606 5843 6494 6481 6468 6481 6558 6022 6303 7221 6979 5588 6098 7145 6979 6762 6341 4746 3904 3751 3789 3827 3802 3815 3304 2628 2972 3253 3215 2998 2832 3330 3406 3342 3177 2781 1059 382 370 421 408 114
|
||||
2781 2653 2653 2730 2909 3751 3853 3789 4350 4861 4669 3687 3457 3636 6596 10373 11343 10475 9977 9416 9186 9033 9773 11330 11547 11011 7910 5882 5537 5231 4810 4695 5448 5703 5588 5512 4708 4134 4529 5818 6507 6583 6392 6532 6532 6226 6443 7209 7043 5971 6264 7068 7119 6724 6354 4682 3764 3610 3661 3725 3674 3700 3253 2628 3049 3342 3291 3075 2653 3100 3381 3368 3138 2845 1110 344 370 421 421 140
|
||||
2819 2653 2653 2692 2768 3649 3776 3802 4287 4950 4848 3751 3508 3623 5907 8982 9901 10041 9122 8906 8829 8842 9633 11343 11687 10960 7247 5831 5626 5703 5422 5065 4874 4848 5142 4312 3942 4019 4453 5779 6494 6634 6239 6392 6596 6213 6379 7234 7043 5984 6277 7055 7030 6673 6252 4720 3751 3508 3610 3661 3649 3700 3189 2513 3113 3432 3342 3202 2539 2883 3368 3266 3113 2896 1161 357 344 421 395 140
|
||||
2807 2692 2615 2704 2743 3534 3751 3789 4223 4848 4784 3776 3508 3585 5575 8587 9429 9888 9237 9225 9288 9173 9658 11343 11891 10985 6698 5792 5652 5244 5167 5231 5129 4886 4823 4580 3917 3993 4440 5805 6494 6736 6354 6481 6545 6328 6303 7106 7004 6137 6175 7043 7081 6762 6162 4733 3751 3470 3559 3636 3649 3623 3138 2373 3049 3483 3457 3342 2411 2679 3330 3240 3113 2845 1352 293 344 446 446 153
|
||||
2807 2692 2641 2704 2717 3368 3649 3738 4070 4529 4631 3789 3432 3521 4937 8063 9148 9811 9965 10003 9531 9327 9646 11292 11840 10654 6430 5665 5512 4644 4657 4899 5142 5269 5218 5142 4529 4197 4363 5652 6468 6724 6277 6341 6545 6430 6532 7119 7157 6494 6328 7004 7081 6724 6226 4784 3815 3585 3547 3610 3559 3649 2845 1837 2628 3559 3496 3291 2143 2551 3317 3215 3062 2870 1416 318 357 421 446 178
|
||||
2832 2730 2717 2717 2628 3304 3559 3700 3878 4350 4453 3559 3406 3483 4363 7438 8701 9901 10309 9760 9212 9186 9595 11177 11840 10181 6264 5563 5384 4312 4134 4363 4886 5205 5231 5180 5039 5039 4657 5677 6443 6762 6545 6596 6520 6545 6609 7170 7234 6634 6354 7030 7068 6724 5920 5154 4108 3827 3674 3661 3598 3674 2615 1250 2028 3661 3572 3508 2194 2602 3317 3215 3049 2921 1556 382 395 459 421 191
|
||||
2883 2845 2756 2781 2590 3177 3470 3572 3751 3993 3980 3457 3342 3432 3853 6379 9059 10373 10041 9518 9454 9339 9633 11024 11508 9850 6175 5461 5282 4299 3802 3878 4172 4657 4797 4835 5244 5435 5205 5614 6341 6775 6647 6634 6609 6545 6583 7157 7336 6698 6328 7068 7221 6736 5665 5563 5626 5448 5269 5116 4465 4414 3126 1084 1760 2807 3113 2704 2245 2666 3304 3164 3049 2870 1709 357 408 484 446 178
|
||||
3036 2934 2870 2896 2602 3049 3355 3496 3521 3598 3559 3381 3304 3381 3776 4720 9378 11317 11929 10373 9339 9186 9429 10870 11611 9939 6188 5397 5269 4248 3751 3521 3508 3649 3623 3827 4618 5626 5639 5754 6315 6813 6698 6634 6673 6622 6583 7094 7438 6749 6328 7132 7400 6315 4504 4708 5971 5869 5805 5933 5244 4657 3381 816 1314 2679 2858 2921 2118 2475 3215 3126 3075 2819 1850 472 535 574 523 191
|
||||
3189 3036 2960 3049 2615 2947 3253 3342 3381 3317 3419 3355 3304 3393 3751 4172 7553 14430 12491 10768 9135 8969 9225 10654 11891 10118 6098 5409 5256 4006 3393 3279 3164 3138 3036 3177 4197 5461 5524 5716 6111 6685 6749 6736 6749 6724 6520 7106 7515 6813 6150 7132 7617 6098 4376 4504 6098 6150 6098 6098 5129 4695 3483 752 1122 2309 2398 2488 1964 2475 3177 3075 2985 2794 1875 446 1059 956 701 204
|
||||
3266 3304 3138 3036 2513 2756 3202 3304 3279 3253 3381 3368 3406 3457 4236 4886 5524 11151 11036 9684 8842 8689 9020 10054 10985 9492 6060 5346 5039 3291 2909 2704 2590 2615 2692 2794 4095 5218 5371 5677 5754 6558 6749 6864 6928 6762 6545 7068 7604 6953 6175 7183 7808 6456 4414 4248 5945 6443 6379 6315 5307 4746 3585 701 854 1824 2258 1964 1939 2437 3164 3049 2934 2743 2003 535 1186 1007 778 255
|
||||
3304 3508 3304 3087 2385 2602 3126 3164 3151 3189 3330 3381 3457 3521 4401 6494 4912 7438 9212 8268 8880 8867 8957 9556 9416 8548 5856 5320 5193 3764 3496 3649 3674 3878 3955 4031 4478 5665 5665 4606 3955 4644 6481 7004 6966 6826 6571 7132 7642 7094 6264 7387 8178 7323 4886 4376 4886 6468 6622 6507 5448 4886 4172 1250 1314 3393 3572 3496 2679 2730 3177 3023 2934 2781 2079 484 995 1148 637 306
|
||||
3393 3649 3508 3113 2462 2602 3189 3164 3138 3151 3266 3355 3470 3674 4044 6443 5677 6073 8114 7923 8140 8548 8612 7349 4669 4631 5397 5256 5307 5014 5078 5090 5180 5307 5244 5256 5397 5792 5677 3764 3942 3661 5563 7030 7119 6890 6583 7094 7706 7298 6315 7476 8701 8638 6685 5945 4810 5256 6583 6787 5716 5001 4657 2334 1645 3585 3764 3815 2858 2794 3113 2998 2934 2768 2156 446 459 765 497 357
|
||||
3559 3802 3764 3470 2539 2628 3445 3164 3087 3151 3291 3406 3559 3789 4095 5665 6481 5295 7438 8025 7719 8561 8536 5409 4134 4019 4950 5231 5397 5856 6124 6137 6162 6277 6264 6443 6673 6762 6571 4733 3547 3827 5690 6826 7247 6966 6609 7145 7757 7425 6417 7642 9097 9773 10245 10079 8114 4848 5256 6775 5869 5014 4567 1531 1097 2858 3151 3036 2475 2322 2947 2985 2909 2717 2258 459 357 433 459 318
|
||||
3610 4197 3853 3317 2692 2641 3725 3406 3151 3126 3291 3457 3547 3891 4287 5256 6035 5346 6226 7209 7974 8536 6839 5575 4019 4095 5142 5244 5448 6787 7068 7055 6992 6941 6966 7094 7298 7515 7566 6992 6098 6226 6507 7285 7374 7106 6711 7094 7872 7591 6596 7834 9365 10551 12542 13933 11087 4695 4631 5103 5652 5014 4529 1429 893 1990 2207 2334 1939 2169 2985 2998 2896 2781 2373 497 357 433 446 331
|
||||
3636 4070 3470 3381 2756 2692 3815 3674 3228 3215 3355 3534 3789 3993 4759 5767 5524 5333 5818 7272 7949 8255 7821 7757 6800 5894 5537 5244 5499 6711 7094 7017 7043 6979 6813 6941 7949 7898 7910 8165 7834 7451 7451 7528 7413 7221 6864 7183 7936 7770 6813 8000 9505 10870 13601 16383 12618 5614 5307 4580 4542 4874 4682 1658 982 2692 2998 3049 2539 2207 3011 3075 2947 2794 2488 510 331 370 395 318
|
||||
4082 4044 4006 4019 3432 3291 3878 4044 3866 3661 3598 3840 4108 4248 5358 6417 6188 5588 5652 6622 7923 8331 8293 7846 7783 7311 5933 5320 5512 6596 7094 7068 7106 6430 4886 6545 8012 8051 8153 8229 8446 8012 7834 7783 7681 7451 7106 7323 8038 8127 7094 8089 9518 10666 12402 13014 11547 9059 6877 5103 4312 4338 4542 1888 969 2271 3138 2717 2334 2079 2985 3087 2960 2794 2551 612 344 382 395 331
|
||||
6124 5601 5537 5894 5869 5690 5626 5614 5218 4925 5065 4848 4784 4835 5524 6252 6673 6507 6226 6354 7413 8025 7744 7553 7668 7362 5996 5397 5512 7145 7961 8063 8025 8319 8217 8357 8574 8612 8650 8153 8484 8395 8025 8012 7910 7604 7145 7298 8051 8165 7196 7898 9467 10437 10922 10692 9441 8319 7757 6787 4861 4159 3980 1913 995 3100 3419 3776 3164 2079 2909 3049 2998 2807 2590 650 331 357 395 280
|
||||
6787 6532 6520 6698 6787 6749 6711 6660 6379 5818 5550 5575 5588 5524 5779 6252 6583 6941 7349 7451 6941 6915 7196 6928 7387 7374 6073 5422 5512 7425 8446 8523 8510 8497 8497 8484 8433 8638 8765 8791 8829 8523 8089 8063 7961 6762 7247 7464 7974 7464 8076 7961 9237 10181 10130 9952 9199 8740 8319 7846 6481 4478 3917 2118 1084 2998 3342 3572 3317 2041 2921 3113 3049 2832 2666 765 280 318 331 293
|
||||
6826 6787 6775 6813 6826 6826 6851 6698 5958 5626 5575 5588 5601 5473 5575 5933 6545 6915 7476 7719 7540 7119 6673 6277 6213 6137 5869 5473 5524 7119 7859 8000 8153 8114 7987 8089 7949 8051 8625 8791 8816 8459 8140 8025 8114 7489 7987 8191 8650 8548 8995 9225 9646 9722 9505 9327 8867 8536 8408 7949 6851 5282 4274 3062 1645 3011 3202 3317 3381 2488 3062 3151 3062 2870 2756 867 280 318 280 331
|
||||
6685 6787 6775 6915 6915 6800 6277 5869 5665 5665 5754 5805 5831 5563 5575 6009 6583 7068 7591 7795 7528 7362 7336 6366 5843 5971 5996 5473 5512 6992 8025 8025 8089 8063 8038 8051 8012 8063 8153 8165 8140 7872 7693 7642 7757 7693 7757 7936 7681 7910 7783 7757 7464 7374 7247 7119 7081 7030 6979 6800 6430 6124 4912 3317 2003 2756 3036 3075 3304 2564 2960 3228 3087 2947 2819 1007 331 331 306 357
|
||||
6520 6596 6839 6941 6902 6813 6303 6264 6481 6685 6851 6992 6800 6749 6839 7055 7515 7642 7821 7923 7770 7706 7719 7528 7540 7489 6379 5601 5550 6762 7693 7732 7744 7744 7591 7489 7451 7413 7425 7451 7451 7323 7336 7285 7247 7157 7068 7438 7196 7081 7170 7043 6545 6915 7438 6966 6086 6839 7196 6609 6277 5971 5027 3980 2028 2424 2985 2921 3100 2590 3113 3304 3151 2934 2858 1148 318 331 331 331
|
||||
5907 6277 7553 7757 7604 7783 7706 7630 7859 7770 7936 8140 7936 7846 8025 8191 8446 8752 8803 8433 8255 8306 8357 8255 8778 7681 5984 5563 5614 6035 7323 7961 8000 7910 7630 7451 7260 7400 7528 7476 7311 7336 7234 7247 7106 6953 6430 7119 6583 5971 5537 5167 4555 5103 5358 4886 4350 4874 5435 6175 5588 5269 4950 4299 2385 2500 2972 2870 2972 2679 3228 3368 3189 2985 2921 1352 382 497 586 267
|
||||
5371 5397 6379 6839 7260 6724 6736 7094 7196 7489 8038 7349 6673 6494 6992 8867 9977 10756 10858 9965 9339 9186 8791 9543 10092 7579 5563 5193 5167 5537 6660 7681 7374 7285 7081 6826 6736 6622 6647 6328 6290 6532 6430 6456 6405 6188 4886 6137 5422 5001 4185 3942 3929 3968 4236 4223 3725 3827 4274 5614 5333 5256 4669 4542 2768 2653 2972 2845 2883 2730 3228 3445 3202 3023 2998 1505 446 1084 1135 318
|
||||
5193 5065 6468 6864 7221 6941 7081 7311 7017 8025 8344 7719 6634 7043 7540 8293 9977 10207 9875 8599 7821 8000 7272 7528 7119 6328 5537 5269 5282 5588 6060 6328 6111 5971 5831 5741 5626 5346 5269 5371 5677 5958 5920 5945 5958 5869 5677 5690 5563 5409 4248 3751 3610 3572 3751 3853 3381 3317 3661 5193 5320 5244 5001 4823 2985 2858 2921 2794 2794 2832 3228 3496 3240 3062 3049 1696 459 1186 1007 395
|
||||
5193 5397 7221 7553 7579 7693 7642 7719 7642 7693 7757 7579 7400 7247 7209 7298 7145 7260 7004 6902 6941 7145 7170 6992 6188 5945 5958 5741 5754 6073 6098 5971 5869 5882 5856 5831 5537 5090 5014 5129 5486 5843 5818 5882 5805 5805 5716 5588 5563 5461 4401 3598 3419 3393 3368 3355 3113 2921 3240 4784 5244 5269 5116 4899 3151 2985 2883 2781 2756 2870 3240 3534 3317 3113 3126 1926 382 1097 1122 548
|
||||
5078 5409 7260 7579 7617 7591 7630 7681 7617 7591 7476 6915 6864 6520 6749 6736 6813 6558 6507 6813 6341 6762 7081 6992 6035 5728 6009 5856 5882 6111 6188 6035 5933 5958 5856 5882 5779 5282 4899 5039 5473 5869 5907 5856 5856 5767 5741 5626 5537 5499 4861 3572 3266 3189 3164 2960 2909 2692 2947 4299 5205 5244 5116 4963 3138 2985 2934 2819 2756 2858 3189 3521 3368 3138 3177 2092 395 446 408 472
|
||||
4899 5346 7234 7553 7553 7604 7553 7630 7553 7540 7464 7030 6890 6826 6800 6864 6736 6762 6634 6583 6826 6583 6698 6979 5894 5524 5882 5779 5882 6098 6226 6022 5920 5677 5639 5792 5754 5435 4950 5052 5639 5971 5945 5958 5920 5894 5907 5882 5818 5805 5473 3853 3177 3036 3062 2807 2692 2602 2743 3968 5167 5180 5052 4912 3317 2998 2921 2870 2819 2870 3189 3534 3393 3177 3177 2271 433 408 357 433
|
||||
4759 5256 7209 7502 7528 7502 7528 7566 7540 7451 7476 7323 6992 6890 6928 7017 6902 6902 6851 6813 6953 6839 6966 6877 6341 5512 5703 5767 5792 6009 6098 5805 5818 5665 5550 5690 5843 5486 5078 5563 6673 6366 6226 6341 6456 6430 6673 7757 7936 8102 8127 5614 3164 2909 2819 2807 2488 2577 2590 3687 5512 5116 4338 4350 3253 3023 2972 2909 2807 2896 3100 3521 3368 3151 3100 2424 484 395 395 421
|
||||
4644 5129 7004 7298 7349 7196 6953 7004 7170 7081 7017 6941 6685 6736 6775 6787 6685 6660 6660 6520 6366 6290 6073 6047 5894 5550 5397 5626 5652 5524 5563 5422 5614 5563 5512 5614 5869 5333 5435 5843 6647 7885 8191 8153 8625 8421 7859 13282 13741 13907 13945 10462 3508 2858 2768 2717 2373 2768 2551 3470 5767 5039 3980 3866 3177 3049 2985 2934 2883 2960 3023 3496 3342 3164 3215 2615 535 433 357 370
|
||||
4453 4453 5269 5779 5486 4427 3827 4095 5358 5078 4950 4976 4925 5039 5371 5524 5550 5677 5843 5703 5180 5320 5078 5052 5090 4988 5039 5065 5052 4899 4823 4950 5307 5282 5256 5193 5320 4835 4720 4325 5920 8331 9122 9173 9237 9212 9263 10271 10449 10717 10679 9620 4401 2998 2768 2628 2309 2947 2602 3802 6201 4988 3929 3827 3304 3049 3011 2960 2960 3023 3036 3432 3381 3240 3202 2756 650 446 382 382
|
||||
4197 4095 4287 5052 4976 4657 4682 4810 4784 4580 4363 4440 4644 4669 4759 5027 5358 5397 5473 4248 4070 3866 3917 3968 3993 3980 4057 4057 4070 4121 4031 4312 5103 5078 5039 5065 5065 4299 4210 3942 5371 7655 8433 9148 9505 9480 9378 9314 9288 9378 9390 9161 5639 3215 2781 2717 2347 2781 2692 3623 6047 5027 3878 3815 3291 2998 3075 3011 3011 3023 3087 3381 3368 3240 3177 2896 803 421 357 446
|
||||
4070 3904 3789 4682 4733 4312 4095 3917 3776 3508 3623 4121 4529 4555 4542 4593 5052 5256 5269 4057 3942 3789 3598 3712 3687 3712 3866 3968 4108 4172 4312 4542 5078 5180 5116 5116 5039 4555 4771 4389 4925 6341 6711 8842 9429 9327 8561 8421 8421 8599 8612 8319 7642 3700 2577 2539 2424 2794 2692 3330 5409 5014 3866 3764 3317 2972 3164 3177 3138 3100 2972 3381 3330 3240 3189 2972 867 472 370 446
|
||||
3968 3585 3445 3508 3419 3317 3189 3330 3266 3189 3355 4044 4325 4376 4376 4185 4401 4925 5218 4963 4861 4682 4695 4580 4580 4669 4784 4937 5129 5282 5346 5358 5282 5384 5282 5218 4810 4491 4886 5065 5358 5690 5065 8612 9378 9250 8548 8370 8280 8612 8561 8536 8357 5945 2717 2411 2500 2743 2832 3100 4350 4759 3751 3674 3330 2896 3138 3202 3279 3177 2832 3138 3291 3240 3228 2998 1122 523 459 408
|
||||
3840 3483 3304 3202 3126 3126 3062 3138 3164 3151 3304 4095 4580 4427 4376 4210 4453 4835 5142 5205 5205 4950 4925 4771 4759 4733 4835 4925 5065 5371 5422 5358 5167 5282 5052 5065 4631 4440 4363 4134 4312 5563 6507 8638 9135 9110 9084 8957 8893 9097 9148 9186 9033 8051 3381 2373 2385 2551 2590 2934 3266 3815 3330 3508 3266 2832 3151 3266 3317 3304 2666 2909 3304 3228 3215 3164 1288 548 497 459
|
||||
3725 3368 3228 3138 2998 3062 3049 3126 3113 3177 3342 4185 4657 4771 4567 4185 4159 4733 4950 4950 4886 4810 4784 4618 4644 4567 4504 4363 4338 4299 4185 4185 4236 5180 5014 4937 4044 3929 3776 3419 3738 5129 5639 6979 7209 7030 6928 6749 6622 6902 7196 7183 6928 6596 4070 2398 2169 2717 2641 2947 3011 3126 3266 3521 3317 2602 3100 3355 3419 3508 2666 2819 3291 3202 3266 3240 1480 599 510 548
|
||||
3636 3266 3177 3126 3036 3036 3023 3036 3062 3023 3279 4210 4759 4976 4759 4529 4771 4810 5014 4618 4669 4682 4580 4427 4491 4414 4389 4172 4070 4019 3968 3917 4197 5154 5065 4950 3980 3866 3776 3483 3649 4657 4861 4988 4784 5014 4988 4121 3853 4555 5703 5869 5690 5639 4669 2756 2398 2653 3049 2960 3317 3215 3457 3623 3253 2283 3023 3470 3521 3751 2947 2781 3445 3291 3368 3342 1709 752 778 842
|
||||
3483 3023 2972 3126 2985 2921 2870 2909 2921 2947 3202 4248 5039 5639 5779 5154 4912 4988 5078 5052 5001 4963 4848 4453 4146 4223 4363 4542 4657 4631 4606 4682 4733 5129 5065 5078 4338 4095 4223 4197 4338 4542 4542 4708 4682 4669 4720 4223 3623 3980 4937 5103 4784 5282 4976 3049 2653 2500 2921 3177 3470 3929 3215 3559 2832 1722 2628 3636 3610 3840 2781 2921 3598 3355 3432 3457 1913 893 1467 1441
|
||||
3419 3100 3151 3189 3062 2832 2768 2832 2909 3023 3177 4236 5078 5933 6277 5358 5001 5078 5231 5639 6379 6366 5256 4006 3393 3368 3483 3572 3802 3917 4006 4376 4823 4937 4720 4963 4861 4210 4159 4095 4350 4389 4401 4465 4542 4542 4516 4121 3547 3610 4236 4197 4006 5001 5039 3815 2845 2704 3036 3011 3075 3980 3253 3457 2730 1301 2054 3649 3534 3866 2794 3023 3751 3559 3547 3649 2271 931 1620 1569
|
||||
3075 2692 2615 3189 3049 2832 2781 2934 2947 2972 3189 4146 4988 5244 5409 5295 5154 5065 5244 5371 6188 6239 5205 4095 3853 3712 3457 3330 3164 3023 3049 3381 4248 4057 3993 4299 4797 4210 4019 4172 4185 4185 4095 4197 4197 4223 4274 4044 3419 3381 3521 3738 3304 4159 4159 3878 3202 3215 3011 3049 3023 3432 3342 3342 2794 1301 1645 2462 3100 3151 2870 3177 3878 3776 3789 3802 2615 944 1633 1582
|
||||
2972 2181 2858 3508 3215 2883 2832 2947 3023 3023 3062 3521 4440 4708 4644 4542 4516 4478 4478 4542 4440 4363 4210 4006 3891 3840 3725 3700 3636 3470 3406 3764 4236 4019 3980 4223 4695 3904 3100 3100 3304 3330 3228 3419 3457 3508 3534 3534 3381 3317 3381 2909 2590 3075 3304 3712 3904 3610 3330 3113 3215 3317 3585 3534 2896 1288 1492 2781 2972 3355 2972 3138 4108 4057 4095 4082 3036 918 791 880
|
||||
3725 3177 2972 3661 3687 3406 3355 3330 3381 3304 3011 3011 3342 3483 3508 3508 3547 3547 3496 3521 3534 3496 3521 3419 3547 3483 3496 3840 4453 4312 4172 3853 4453 4070 3917 4082 4682 4376 4057 4389 4210 3725 2985 2998 3049 3075 3138 3202 3904 4350 4542 4274 3815 3968 4657 4644 4504 4159 3700 3496 3406 3559 3470 3572 3049 1429 1633 2590 2679 2921 2679 3138 4223 4274 4274 4363 3445 1046 778 791
|
||||
3470 2870 2475 3113 3980 4134 4440 4108 4274 4427 3993 3432 3687 3764 3815 3802 3866 3929 3968 3993 4031 3993 4044 4031 4108 4185 4210 4593 5129 5154 4542 3228 3228 2985 2870 2768 2896 4070 4746 4606 4759 4874 4440 4478 4440 4401 4504 4453 4312 4172 4287 4746 4695 4580 4504 4618 4746 4542 4299 3917 3521 3700 3559 3598 3304 1658 1709 2972 3100 3023 2743 3151 4491 4593 4618 4618 3827 1110 752 740
|
||||
2909 2488 2641 3100 3304 3802 4223 3993 3789 4555 4963 4925 4988 5014 5103 5129 5116 5103 5193 5180 5180 5180 5193 5205 5295 5473 5614 5027 4759 4708 3980 3087 2960 2972 2896 2934 2807 3470 4261 4261 4504 5422 5256 5256 5256 5167 5065 4861 4312 3993 4185 4338 3955 3725 3725 4146 4963 4899 4516 4312 3866 3687 3610 3572 3508 2334 2156 3508 3534 3725 3381 3496 4555 4720 4759 4733 4082 1148 816 740
|
||||
109
cs309-psoc/lab_2_1/sw/nios/application/pantilt/pantilt.c
Normal file
109
cs309-psoc/lab_2_1/sw/nios/application/pantilt/pantilt.c
Normal file
@@ -0,0 +1,109 @@
|
||||
#include "pantilt.h"
|
||||
|
||||
/**
|
||||
* pantilt_inst
|
||||
*
|
||||
* Instantiate a pantilt device structure.
|
||||
*
|
||||
* @param pwm_v_base Base address of the vertical PWM component.
|
||||
* @param pwm_h_base Base address of the horizontal PWM component.
|
||||
*/
|
||||
pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) {
|
||||
pantilt_dev dev;
|
||||
dev.pwm_v = pwm_inst(pwm_v_base);
|
||||
dev.pwm_h = pwm_inst(pwm_h_base);
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
/**
|
||||
* pantilt_init
|
||||
*
|
||||
* Initializes the pantilt device.
|
||||
*
|
||||
* @param dev pantilt device structure.
|
||||
*/
|
||||
void pantilt_init(pantilt_dev *dev) {
|
||||
pwm_init(&(dev->pwm_v));
|
||||
pwm_init(&(dev->pwm_h));
|
||||
}
|
||||
|
||||
/**
|
||||
* pantilt_configure_vertical
|
||||
*
|
||||
* Configure the vertical PWM component.
|
||||
*
|
||||
* @param dev pantilt device structure.
|
||||
* @param duty_cycle pwm duty cycle in us.
|
||||
*/
|
||||
void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) {
|
||||
// Need to compensate for inverted servo rotation.
|
||||
duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US;
|
||||
|
||||
pwm_configure(&(dev->pwm_v),
|
||||
duty_cycle,
|
||||
PANTILT_PWM_PERIOD_US,
|
||||
PANTILT_PWM_CLOCK_FREQ_HZ);
|
||||
}
|
||||
|
||||
/**
|
||||
* pantilt_configure_horizontal
|
||||
*
|
||||
* Configure the horizontal PWM component.
|
||||
*
|
||||
* @param dev pantilt device structure.
|
||||
* @param duty_cycle pwm duty cycle in us.
|
||||
*/
|
||||
void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) {
|
||||
// Need to compensate for inverted servo rotation.
|
||||
duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US;
|
||||
|
||||
pwm_configure(&(dev->pwm_h),
|
||||
duty_cycle,
|
||||
PANTILT_PWM_PERIOD_US,
|
||||
PANTILT_PWM_CLOCK_FREQ_HZ);
|
||||
}
|
||||
|
||||
/**
|
||||
* pantilt_start_vertical
|
||||
*
|
||||
* Starts the vertical pwm controller.
|
||||
*
|
||||
* @param dev pantilt device structure.
|
||||
*/
|
||||
void pantilt_start_vertical(pantilt_dev *dev) {
|
||||
pwm_start(&(dev->pwm_v));
|
||||
}
|
||||
|
||||
/**
|
||||
* pantilt_start_horizontal
|
||||
*
|
||||
* Starts the horizontal pwm controller.
|
||||
*
|
||||
* @param dev pantilt device structure.
|
||||
*/
|
||||
void pantilt_start_horizontal(pantilt_dev *dev) {
|
||||
pwm_start(&(dev->pwm_h));
|
||||
}
|
||||
|
||||
/**
|
||||
* pantilt_stop_vertical
|
||||
*
|
||||
* Stops the vertical pwm controller.
|
||||
*
|
||||
* @param dev pantilt device structure.
|
||||
*/
|
||||
void pantilt_stop_vertical(pantilt_dev *dev) {
|
||||
pwm_stop(&(dev->pwm_v));
|
||||
}
|
||||
|
||||
/**
|
||||
* pantilt_stop_horizontal
|
||||
*
|
||||
* Stops the horizontal pwm controller.
|
||||
*
|
||||
* @param dev pantilt device structure.
|
||||
*/
|
||||
void pantilt_stop_horizontal(pantilt_dev *dev) {
|
||||
pwm_stop(&(dev->pwm_h));
|
||||
}
|
||||
39
cs309-psoc/lab_2_1/sw/nios/application/pantilt/pantilt.h
Normal file
39
cs309-psoc/lab_2_1/sw/nios/application/pantilt/pantilt.h
Normal file
@@ -0,0 +1,39 @@
|
||||
#ifndef __PANTILT_H__
|
||||
#define __PANTILT_H__
|
||||
|
||||
#include "pwm/pwm.h"
|
||||
|
||||
/* joysticks device structure */
|
||||
typedef struct pantilt_dev {
|
||||
pwm_dev pwm_v; /* Vertical PWM device handle */
|
||||
pwm_dev pwm_h; /* Horizontal PWM device handle */
|
||||
} pantilt_dev;
|
||||
|
||||
/*******************************************************************************
|
||||
* Public API
|
||||
******************************************************************************/
|
||||
|
||||
#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz
|
||||
|
||||
#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms
|
||||
|
||||
/* Vertical servo */
|
||||
#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms
|
||||
#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms
|
||||
|
||||
/* Horizontal servo */
|
||||
#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms
|
||||
#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms
|
||||
|
||||
pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base);
|
||||
|
||||
void pantilt_init(pantilt_dev *dev);
|
||||
|
||||
void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle);
|
||||
void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle);
|
||||
void pantilt_start_vertical(pantilt_dev *dev);
|
||||
void pantilt_start_horizontal(pantilt_dev *dev);
|
||||
void pantilt_stop_vertical(pantilt_dev *dev);
|
||||
void pantilt_stop_horizontal(pantilt_dev *dev);
|
||||
|
||||
#endif /* __PANTILT_H__ */
|
||||
71
cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm.c
Normal file
71
cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm.c
Normal file
@@ -0,0 +1,71 @@
|
||||
#include <io.h>
|
||||
|
||||
#include "pwm.h"
|
||||
#include "pwm_regs.h"
|
||||
|
||||
#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000))
|
||||
|
||||
|
||||
/**
|
||||
* pwm_inst
|
||||
*
|
||||
* Instantiate a pwm device structure.
|
||||
*
|
||||
* @param base Base address of the component.
|
||||
*/
|
||||
pwm_dev pwm_inst(void *base) {
|
||||
pwm_dev dev;
|
||||
|
||||
dev.base = base;
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
/**
|
||||
* pwm_init
|
||||
*
|
||||
* Initializes the pwm device. This function stops the controller.
|
||||
*
|
||||
* @param dev pwm device structure.
|
||||
*/
|
||||
void pwm_init(pwm_dev *dev) {
|
||||
pwm_stop(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* pwm_configure
|
||||
*
|
||||
* Configure pwm component.
|
||||
*
|
||||
* @param dev pwm device structure.
|
||||
* @param duty_cycle pwm duty cycle in us.
|
||||
* @param period pwm period in us.
|
||||
* @param module_frequency frequency at which the component is clocked.
|
||||
*/
|
||||
void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) {
|
||||
|
||||
IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency));
|
||||
IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency));
|
||||
}
|
||||
|
||||
/**
|
||||
* pwm_start
|
||||
*
|
||||
* Starts the pwm controller.
|
||||
*
|
||||
* @param dev pwm device structure.
|
||||
*/
|
||||
void pwm_start(pwm_dev *dev) {
|
||||
IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* pwm_stop
|
||||
*
|
||||
* Stops the pwm controller.
|
||||
*
|
||||
* @param dev pwm device structure.
|
||||
*/
|
||||
void pwm_stop(pwm_dev *dev) {
|
||||
IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK);
|
||||
}
|
||||
21
cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm.h
Normal file
21
cs309-psoc/lab_2_1/sw/nios/application/pantilt/pwm/pwm.h
Normal file
@@ -0,0 +1,21 @@
|
||||
#ifndef __PWM_H__
|
||||
#define __PWM_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* pwm device structure */
|
||||
typedef struct pwm_dev {
|
||||
void *base; /* Base address of component */
|
||||
} pwm_dev;
|
||||
|
||||
/*******************************************************************************
|
||||
* Public API
|
||||
******************************************************************************/
|
||||
pwm_dev pwm_inst(void *base);
|
||||
|
||||
void pwm_init(pwm_dev *dev);
|
||||
void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency);
|
||||
void pwm_start(pwm_dev *dev);
|
||||
void pwm_stop(pwm_dev *dev);
|
||||
|
||||
#endif /* __PWM_H__ */
|
||||
@@ -0,0 +1,11 @@
|
||||
#ifndef __PWM_REGS_H__
|
||||
#define __PWM_REGS_H__
|
||||
|
||||
#define PWM_PERIOD_OFST (0 * 4) /* RW */
|
||||
#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */
|
||||
#define PWM_CTRL_OFST (2 * 4) /* WO */
|
||||
|
||||
#define PWM_CTRL_STOP_MASK (0)
|
||||
#define PWM_CTRL_START_MASK (1)
|
||||
|
||||
#endif /* __PWM_REGS_H__ */
|
||||
Reference in New Issue
Block a user