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Disabled external gits

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choelzl
2022-04-07 18:54:11 +02:00
parent 15e7120d6d
commit 0fb3e365d4
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187
cs309-psoc/lab_1_1/hw/hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd Normal file
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-- #############################################################################
-- DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
--
-- BOARD : PrSoC extension board for DE0-Nano-SoC
-- Author : Florian Depraz based on Sahand Kashani-Akhavan work
-- Revision : 1.1
-- Creation date : 06/02/2016
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_PrSoC_extn_board_top_level is
port(
-------------------------------
-- Comment ALL unused ports. --
-------------------------------
-- CLOCK
FPGA_CLK1_50 : in std_logic;
-- FPGA_CLK2_50 : in std_logic;
-- FPGA_CLK3_50 : in std_logic;
-- KEY on DE0 Nano SoC
KEY_N : in std_logic_vector(1 downto 0);
-- LEDs on DE0 Nano SoC
-- LED : out std_logic_vector(7 downto 0);
-- SWITCHES on DE0 Nano SoC
-- SW : in std_logic_vector(3 downto 0);
-- Servomotors pwm
SERVO_0 : out std_logic;
SERVO_1 : out std_logic
-- ADC Joysticks
-- J0_SPI_CS_n : out std_logic;
-- J0_SPI_MOSI : out std_logic;
-- J0_SPI_MISO : in std_logic;
-- J0_SPI_CLK : out std_logic;
-- Lepton
-- CAM_TH_SPI_CS_N : out std_logic;
-- CAM_TH_MISO : in std_logic;
-- CAM_TH_MOSI : out std_logic;
-- CAM_TH_CLK : out std_logic;
-- PCA9637
-- PIO_SCL : inout std_logic;
-- PIO_SDA : inout std_logic;
-- PIO_INT_N : in std_logic;
-- RESET_N : out std_logic;
-- OV7670
-- CAM_D : in std_logic_vector(9 downto 0);
-- CAM_PIX_CLK : in std_logic;
-- CAM_LV : in std_logic;
-- CAM_FV : in std_logic;
-- CAM_SYS_CLK : out std_logic;
-- VGA and LCD shared signals
-- VIDEO_CLK : out std_logic;
-- VIDEO_VSYNC : out std_logic;
-- VIDEO_HSYNC : out std_logic;
-- VIDEO_B : out std_logic_vector(7 downto 0);
-- VIDEO_G : out std_logic_vector(7 downto 0);
-- VIDEO_R : out std_logic_vector(7 downto 0);
-- LCD Specific signals
-- LCD_DE : out std_logic;
-- LCD_PIN_DAV_N : ? ?? std_logic;
-- LCD_DISPLAY_EN : out std_logic;
-- SPI_MISO : in std_logic;
-- SPI_ENA_N : out std_logic;
-- SPI_CLK : out std_logic;
-- SPI_MOSI : out std_logic;
-- SPI_DAT : inout std_logic;
-- I2C TOUCH SCREEN
-- TS_SCL : inout std_logic;
-- TS_SDA : inout std_logic;
-- BLUETOOTH (BLE)
-- BLT_TXD : in std_logic;
-- BLT_RXD : out std_logic;
-- I2C For VGA, PAL and OV7670 cameras
-- CAM_PAL_VGA_SDA : inout std_logic;
-- CAM_PAL_VGA_SCL : inout std_logic;
-- ONE WIRE
-- BOARD_ID : inout std_logic;
-- PAL Camera
-- PAL_VD_VD : in std_logic_vector(7 downto 0);
-- PAL_VD_VSO : in std_logic;
-- PAL_VD_HSO : in std_logic;
-- PAL_VD_CLKO : in std_logic;
-- PAL_PWDN : out std_logic;
-- WIFI
-- FROM_ESP_TXD : in std_logic;
-- TO_ESP_RXD : out std_logic;
-- LED RGB
-- LED_BGR : out std_logic;
-- HPS
-- HPS_CONV_USB_N : inout std_logic;
-- HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
-- HPS_DDR3_BA : out std_logic_vector(2 downto 0);
-- HPS_DDR3_CAS_N : out std_logic;
-- HPS_DDR3_CK_N : out std_logic;
-- HPS_DDR3_CK_P : out std_logic;
-- HPS_DDR3_CKE : out std_logic;
-- HPS_DDR3_CS_N : out std_logic;
-- HPS_DDR3_DM : out std_logic_vector(3 downto 0);
-- HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
-- HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
-- HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
-- HPS_DDR3_ODT : out std_logic;
-- HPS_DDR3_RAS_N : out std_logic;
-- HPS_DDR3_RESET_N : out std_logic;
-- HPS_DDR3_RZQ : in std_logic;
-- HPS_DDR3_WE_N : out std_logic;
-- HPS_ENET_GTX_CLK : out std_logic;
-- HPS_ENET_INT_N : inout std_logic;
-- HPS_ENET_MDC : out std_logic;
-- HPS_ENET_MDIO : inout std_logic;
-- HPS_ENET_RX_CLK : in std_logic;
-- HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
-- HPS_ENET_RX_DV : in std_logic;
-- HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
-- HPS_ENET_TX_EN : out std_logic;
-- HPS_GSENSOR_INT : inout std_logic;
-- HPS_I2C0_SCLK : inout std_logic;
-- HPS_I2C0_SDAT : inout std_logic;
-- HPS_I2C1_SCLK : inout std_logic;
-- HPS_I2C1_SDAT : inout std_logic;
-- HPS_KEY_N : inout std_logic;
-- HPS_LED : inout std_logic;
-- HPS_LTC_GPIO : inout std_logic;
-- HPS_SD_CLK : out std_logic;
-- HPS_SD_CMD : inout std_logic;
-- HPS_SD_DATA : inout std_logic_vector(3 downto 0);
-- HPS_SPIM_CLK : out std_logic;
-- HPS_SPIM_MISO : in std_logic;
-- HPS_SPIM_MOSI : out std_logic;
-- HPS_SPIM_SS : inout std_logic;
-- HPS_UART_RX : in std_logic;
-- HPS_UART_TX : out std_logic;
-- HPS_USB_CLKOUT : in std_logic;
-- HPS_USB_DATA : inout std_logic_vector(7 downto 0);
-- HPS_USB_DIR : in std_logic;
-- HPS_USB_NXT : in std_logic;
-- HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_PrSoC_extn_board_top_level;
architecture rtl of DE0_Nano_SoC_PrSoC_extn_board_top_level is
component soc_system is
port (
clk_clk : in std_logic := 'X';
reset_reset_n : in std_logic := 'X';
pwm_0_conduit_end_pwm : out std_logic;
pwm_1_conduit_end_pwm : out std_logic
);
end component soc_system;
begin
soc_system_inst : component soc_system
port map (
clk_clk => FPGA_CLK1_50,
reset_reset_n => KEY_N(0),
pwm_0_conduit_end_pwm => SERVO_0,
pwm_1_conduit_end_pwm => SERVO_1
);
end;

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cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm.vhd Normal file
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-- #############################################################################
-- pwm.vhd
-- =======
-- PWM memory-mapped Avalon slave interface.
--
-- Author : Cedric Hoelzl (cedric.hoelzl@epfl.ch)
-- Author : Antoine Brunner (antoine.brunner@epfl.ch)
-- Revision : 0.0.1a_rc1
-- Last modified : a few billion clock cycles in the past
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pwm_constants.all;
entity pwm is
port(
-- Avalon Clock interface
clk : in std_logic;
-- Avalon Reset interface
reset : in std_logic;
-- Avalon-MM Slave interface
address : in std_logic_vector(1 downto 0);
read : in std_logic;
write : in std_logic;
readdata : out std_logic_vector(31 downto 0);
writedata : in std_logic_vector(31 downto 0);
-- Avalon Conduit interface
pwm_out : out std_logic
);
end pwm;
architecture rtl of pwm is
-- The period of the current and next PWM cycle
signal reg_next_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length);
signal reg_current_period : unsigned(writedata'range) := to_unsigned(DEFAULT_PERIOD, writedata'length);
-- The duty cycle of the current and next PWM cycle
signal reg_next_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length);
signal reg_current_dutycycle : unsigned(writedata'range) := to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length);
-- The status of the current and next PWM cycle
signal reg_prev_ctrl : std_logic := '0';
signal reg_current_ctrl : std_logic := '0';
-- The internal counter of the PWN
signal reg_counter : unsigned(writedata'range) := to_unsigned(0, writedata'length);
begin
--Avalon-MM slave write
process(clk, reset)
begin
if reset = '1' then
reg_next_period <= to_unsigned(DEFAULT_PERIOD, writedata'length);
reg_next_dutycycle <= to_unsigned(DEFAULT_DUTY_CYCLE, writedata'length);
reg_current_ctrl <= '0';
elsif rising_edge(clk) then
if write = '1' then
case address is
when REG_PERIOD_OFST =>
if unsigned(writedata) >= to_unsigned(2, writedata'length) then
reg_next_period <= unsigned(writedata);
end if;
when REG_DUTY_CYCLE_OFST =>
if (unsigned(writedata) >= to_unsigned(1, writedata'length)) and
(unsigned(writedata) <= reg_next_period) then
reg_next_dutycycle <= unsigned(writedata);
end if;
when REG_CTRL_OFST =>
reg_current_ctrl <= writedata(0);
when others => null;
end case;
end if;
end if;
end process;
--Avalon-MM slave read
process(clk, reset)
begin
if rising_edge(clk) then
if read = '1' then
case address is
when REG_PERIOD_OFST =>
readdata <= std_logic_vector(reg_current_period);
when REG_DUTY_CYCLE_OFST =>
readdata <= std_logic_vector(reg_current_dutycycle);
when others =>
readdata <= (others => '0');
end case;
end if;
end if;
end process;
-- Internal synchronous logic
process(clk, reset)
begin
if reset = '1' then
reg_counter <= to_unsigned(0, writedata'length);
reg_prev_ctrl <= '0';
elsif rising_edge(clk) then
if ((reg_prev_ctrl = '0') and (reg_current_ctrl = '1')) or
(reg_counter = reg_current_period - 1) then
reg_current_period <= reg_next_period;
reg_current_dutycycle <= reg_next_dutycycle;
reg_counter <= to_unsigned(0, writedata'length);
elsif (reg_current_ctrl = '1') then
reg_counter <= reg_counter + 1;
end if;
reg_prev_ctrl <= reg_current_ctrl;
end if;
end process;
-- Avalon Conduit interface
process(clk, reset)
begin
if rising_edge(clk) then
if (reg_counter < reg_current_dutycycle) and (reg_current_ctrl = '1') then
pwm_out <= '1';
else
pwm_out <= '0';
end if;
end if;
end process;
end architecture rtl;

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cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm_constants.vhd Normal file
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-- #############################################################################
-- pwm_constants.vhd
-- =================
-- This package contains constants used in the PWM design files.
--
-- Author : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
-- Revision : 2
-- Last modified : 2018-02-28
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pwm_constants is
-- Register map
-- +--------+------------+--------+------------------------------------------------------------------------------+
-- | RegNo | Name | Access | Description |
-- +--------+------------+--------+------------------------------------------------------------------------------+
-- | 0 | PERIOD | R/W | Period in clock cycles [2 <= period <= (2**32) - 1]. |
-- | | | | |
-- | | | | This value can be read/written while the unit is in the middle of an ongoing |
-- | | | | PWM pulse. To allow safe behaviour, one cannot modify the period of an |
-- | | | | ongoing pulse, so we adopt the following semantics for this register: |
-- | | | | |
-- | | | | >> WRITING a value in this register indicates the NEW period to apply to the |
-- | | | | next pulse. |
-- | | | | |
-- | | | | >> READING a value from this register indicates the CURRENT period of the |
-- | | | | ongoing pulse. |
-- +--------+------------+--------+------------------------------------------------------------------------------+
-- | 1 | DUTY_CYCLE | R/W | Duty cycle of the PWM [1 <= duty cycle <= period] |
-- | | | | |
-- | | | | This value can be read/written while the unit is in the middle of an ongoing |
-- | | | | PWM pulse. To allow safe behaviour, one cannot modify the duty cycle of an |
-- | | | | ongoing pulse, so we adopt the following semantics for this register: |
-- | | | | |
-- | | | | >> WRITING a value in this register indicates the NEW duty cycle to apply to |
-- | | | | the next pulse. |
-- | | | | |
-- | | | | >> READING a value from this register indicates the CURRENT duty cycle of |
-- | | | | the ongoing pulse. |
-- +--------+------------+--------+------------------------------------------------------------------------------+
-- | 2 | CTRL | WO | >> Writing 0 to this register stops the PWM once the ongoing pulse has ended.|
-- | | | | Writing 1 to this register starts the PWM. |
-- | | | | |
-- | | | | >> Reading this register always returns 0. |
-- +--------+------------+--------+------------------------------------------------------------------------------+
constant REG_PERIOD_OFST : std_logic_vector(1 downto 0) := "00";
constant REG_DUTY_CYCLE_OFST : std_logic_vector(1 downto 0) := "01";
constant REG_CTRL_OFST : std_logic_vector(1 downto 0) := "10";
-- Default values of registers after reset (BEFORE writing START to the CTRL
-- register with a new configuration)
constant DEFAULT_PERIOD : natural := 4;
constant DEFAULT_DUTY_CYCLE : natural := 2;
end package pwm_constants;
package body pwm_constants is
end package body pwm_constants;

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cs309-psoc/lab_1_1/hw/hdl/pantilt/hdl/pwm_hw.tcl Normal file
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# TCL File Generated by Component Editor 16.0
# Tue Feb 28 12:18:00 CET 2017
# DO NOT MODIFY
#
# pwm "pwm" v1.0
# 2017.02.28.12:18:00
# Pan-tilt
#
#
# request TCL package from ACDS 16.0
#
package require -exact qsys 16.0
#
# module pwm
#
set_module_property DESCRIPTION Pan-tilt
set_module_property NAME pwm
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP Pan-tilt
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME pwm
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL pwm
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file pwm.vhd VHDL PATH pwm.vhd TOP_LEVEL_FILE
add_fileset_file pwm_constants.vhd VHDL PATH pwm_constants.vhd
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1
#
# connection point avalon_slave_0
#
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
set_interface_property avalon_slave_0 EXPORT_OF ""
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
add_interface_port avalon_slave_0 address address Input 2
add_interface_port avalon_slave_0 read read Input 1
add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 readdata readdata Output 32
add_interface_port avalon_slave_0 writedata writedata Input 32
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock clock
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end pwm_out pwm Output 1

205
cs309-psoc/lab_1_1/hw/hdl/pantilt/tb/tb_pwm.vhd Normal file
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-- #############################################################################
-- tb_pwm.vhd
-- ==========
-- Testbench for PWM memory-mapped Avalon slave interface.
--
-- Modified by : Sahand Kashani-Akhavan [sahand.kashani-akhavan@epfl.ch]
-- Revision : 2
-- Last modified : 2018-02-28
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pwm_constants.all;
entity tb_pwm is
end entity;
architecture rtl of tb_pwm is
-- 50 MHz clock
constant CLK_PERIOD : time := 20 ns;
-- Signal used to end simulator when we finished submitting our test cases
signal sim_finished : boolean := false;
-- PWM PORTS
signal clk : std_logic;
signal reset : std_logic;
signal address : std_logic_vector(1 downto 0);
signal read : std_logic;
signal write : std_logic;
signal readdata : std_logic_vector(31 downto 0);
signal writedata : std_logic_vector(31 downto 0);
signal pwm_out : std_logic;
-- Values of registers we are going to use to configure the PWM unit
constant CONFIG_PERIOD : natural := 100;
constant CONFIG_DUTY_CYCLE : natural := 20;
constant CONFIG_CTRL_START : natural := 1;
constant CONFIG_CTRL_STOP : natural := 0;
begin
-- Instantiate DUT
dut : entity work.pwm
port map(
clk => clk,
reset => reset,
address => address,
read => read,
write => write,
readdata => readdata,
writedata => writedata,
pwm_out => pwm_out
);
-- Generate clk signal
clk_generation : process
begin
if not sim_finished then
clk <= '1';
wait for CLK_PERIOD / 2;
clk <= '0';
wait for CLK_PERIOD / 2;
else
wait;
end if;
end process clk_generation;
-- Test PWM
simulation : process
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
wait for CLK_PERIOD / 4;
end procedure async_reset;
procedure write_register(constant ofst : in std_logic_vector(1 downto 0);
constant val : in natural) is
begin
wait until rising_edge(clk);
address <= ofst;
write <= '1';
writedata <= std_logic_vector(to_unsigned(val, writedata'length));
wait until rising_edge(clk);
address <= (others => '0');
write <= '0';
writedata <= (others => '0');
wait until rising_edge(clk);
end procedure write_register;
procedure read_register(constant ofst : in std_logic_vector(1 downto 0)) is
begin
wait until rising_edge(clk);
address <= ofst;
read <= '1';
-- The read has a 1 cycle wait-state, so we need to keep the read
-- signal high for 2 clock cycles.
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= (others => '0');
read <= '0';
wait until rising_edge(clk);
end procedure read_register;
procedure read_register_check(constant ofst : in std_logic_vector(1 downto 0);
constant expected_val : in natural) is
begin
read_register(ofst);
case ofst is
when REG_PERIOD_OFST =>
assert to_integer(unsigned(readdata)) = expected_val
report "Unexpected PERIOD: " &
"PERIOD = " & integer'image(to_integer(unsigned(readdata))) & "; " &
"PERIOD_expected = " & integer'image(expected_val)
severity error;
when REG_DUTY_CYCLE_OFST =>
assert to_integer(unsigned(readdata)) = expected_val
report "Unexpected DUTY_CYCLE: " &
"DUTY_CYCLE = " & integer'image(to_integer(unsigned(readdata))) & "; " &
"DUTY_CYCLE_expected = " & integer'image(expected_val)
severity error;
when REG_CTRL_OFST =>
assert to_integer(unsigned(readdata)) = expected_val
report "Unexpected CTRL: " &
"CTRL = " & integer'image(to_integer(unsigned(readdata))) & "; " &
"CTRL_expected = " & integer'image(expected_val)
severity error;
when others =>
null;
end case;
end procedure read_register_check;
begin
-- Default values
reset <= '0';
address <= (others => '0');
read <= '0';
write <= '0';
writedata <= (others => '0');
wait until rising_edge(clk);
-- Reset the circuit
async_reset;
-- Write desired configuration to PWM Avalon-MM slave.
write_register(REG_PERIOD_OFST, CONFIG_PERIOD);
write_register(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
-- Read back configuration from PWM Avalon-MM slave. Note that we have
-- not started the PWM unit yet, so the new configuration must not be
-- read back at this point (as per the register map).
read_register_check(REG_PERIOD_OFST, DEFAULT_PERIOD);
read_register_check(REG_DUTY_CYCLE_OFST, DEFAULT_DUTY_CYCLE);
read_register_check(REG_CTRL_OFST, 0);
-- Start PWM
write_register(REG_CTRL_OFST, CONFIG_CTRL_START);
-- Wait until PWM pulses for the first time after we sent START.
wait until rising_edge(pwm_out);
-- Read back configuration from PWM Avalon-MM slave. Now that we have
-- started the PWM unit, we should be able to read back the
-- configuration we wrote (as per the register map).
read_register_check(REG_PERIOD_OFST, CONFIG_PERIOD);
read_register_check(REG_DUTY_CYCLE_OFST, CONFIG_DUTY_CYCLE);
read_register_check(REG_CTRL_OFST, 0);
-- Wait for 2 PWM periods to finish
wait for 2 * CLK_PERIOD * CONFIG_PERIOD;
-- Stop PWM.
write_register(REG_CTRL_OFST, CONFIG_CTRL_STOP);
-- Wait for PWM period to finish
wait for 1 * CLK_PERIOD * CONFIG_PERIOD;
-- Instruct "clk_generation" process to halt execution.
sim_finished <= true;
-- Make this process wait indefinitely (it will never re-execute from
-- its beginning again).
wait;
end process simulation;
end architecture rtl;

26
cs309-psoc/lab_1_1/hw/quartus/ip/components.ipx Normal file
View File

@@ -0,0 +1,26 @@
<?xml version="1.0" encoding="UTF-8"?>
<library>
<!-- date: 2017.02.28.12:24:56 -->
<!-- generated by: ip-make-ipx -->
<!-- -->
<!-- 1 in ../../hdl/ -->
<!-- -->
<component
name="pwm"
file="../../hdl/pantilt/hdl/pwm_hw.tcl"
displayName="pwm"
version="1.0"
description="Pan-tilt"
tags="AUTHORSHIP= /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
categories="Pan-tilt"
factory="TclModuleFactory">
<tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
<tag2 key="COMPONENT_EDITABLE" value="true" />
<tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
<tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
<tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
<tag2 key="REPORT_HIERARCHY" value="false" />
<tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
<tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
</component>
</library>

31
cs309-psoc/lab_1_1/hw/quartus/lab_1_1.qpf Normal file
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@@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
# Date created = 11:03:02 February 05, 2016
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "15.1"
DATE = "11:03:02 February 05, 2016"
# Revisions
PROJECT_REVISION = "lab_1_1"

812
cs309-psoc/lab_1_1/hw/quartus/lab_1_1.qsf Normal file
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@@ -0,0 +1,812 @@
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_PrSoC_extn_board_top_level
set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_PrSoC_extn_board_top_level.vhd
set_global_assignment -name QSYS_FILE soc_system.qsys
set_global_assignment -name SDC_FILE lab_1_1.sdc
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA4U23C6
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
#============================================================
# ADC
#============================================================
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
#============================================================
# ARDUINO Extention OV7670 CAMERA
#============================================================
set_location_assignment PIN_AE15 -to CAM_D[0]
set_location_assignment PIN_AE15 -to CAM_D_0
set_location_assignment PIN_AF17 -to CAM_D[1]
set_location_assignment PIN_AF17 -to CAM_D_1
set_location_assignment PIN_AH8 -to CAM_D[2]
set_location_assignment PIN_AH8 -to CAM_D_2
set_location_assignment PIN_AG8 -to CAM_D[3]
set_location_assignment PIN_AG8 -to CAM_D_3
set_location_assignment PIN_U13 -to CAM_D[4]
set_location_assignment PIN_U13 -to CAM_D_4
set_location_assignment PIN_U14 -to CAM_D[5]
set_location_assignment PIN_U14 -to CAM_D_5
set_location_assignment PIN_AG9 -to CAM_D[6]
set_location_assignment PIN_AG9 -to CAM_D_6
set_location_assignment PIN_AG10 -to CAM_D[7]
set_location_assignment PIN_AG10 -to CAM_D_7
set_location_assignment PIN_AF13 -to CAM_D[8]
set_location_assignment PIN_AF13 -to CAM_D_8
set_location_assignment PIN_AG13 -to CAM_D[9]
set_location_assignment PIN_AG13 -to CAM_D_9
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_8
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_D_9
#============================================================
# Arduino Extension LEPTON CAMERA THERMAL CAM_TH
#============================================================
set_location_assignment PIN_AF15 -to CAM_TH_SPI_CS_N
set_location_assignment PIN_AG16 -to CAM_TH_MOSI
set_location_assignment PIN_AH11 -to CAM_TH_MISO
set_location_assignment PIN_AH12 -to CAM_TH_CLK
set_location_assignment PIN_AH9 -to CAM_TH_I2C_SDA
set_location_assignment PIN_AG11 -to CAM_TH_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_SPI_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_TH_I2C_SCL
set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
#============================================================
# CLOCK
#============================================================
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
#============================================================
# HPS
#============================================================
set_location_assignment PIN_C6 -to HPS_CONV_USB_N
set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0]
set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0
set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1]
set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1
set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2]
set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2
set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3]
set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3
set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4]
set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4
set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5]
set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5
set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6]
set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6
set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7]
set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7
set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8]
set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8
set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9]
set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9
set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10]
set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10
set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11]
set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11
set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12]
set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12
set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13]
set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13
set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14]
set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14
set_location_assignment PIN_A27 -to HPS_DDR3_BA[0]
set_location_assignment PIN_A27 -to HPS_DDR3_BA_0
set_location_assignment PIN_H25 -to HPS_DDR3_BA[1]
set_location_assignment PIN_H25 -to HPS_DDR3_BA_1
set_location_assignment PIN_G25 -to HPS_DDR3_BA[2]
set_location_assignment PIN_G25 -to HPS_DDR3_BA_2
set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N
set_location_assignment PIN_L28 -to HPS_DDR3_CKE
set_location_assignment PIN_N20 -to HPS_DDR3_CK_N
set_location_assignment PIN_N21 -to HPS_DDR3_CK_P
set_location_assignment PIN_L21 -to HPS_DDR3_CS_N
set_location_assignment PIN_G28 -to HPS_DDR3_DM[0]
set_location_assignment PIN_G28 -to HPS_DDR3_DM_0
set_location_assignment PIN_P28 -to HPS_DDR3_DM[1]
set_location_assignment PIN_P28 -to HPS_DDR3_DM_1
set_location_assignment PIN_W28 -to HPS_DDR3_DM[2]
set_location_assignment PIN_W28 -to HPS_DDR3_DM_2
set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3]
set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3
set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0]
set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0
set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1]
set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1
set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2]
set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2
set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3]
set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3
set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4]
set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4
set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5]
set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5
set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6]
set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6
set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7]
set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7
set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8]
set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8
set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9]
set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9
set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10]
set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10
set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11]
set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11
set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12]
set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12
set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13]
set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13
set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14]
set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14
set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15]
set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15
set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16]
set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16
set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17]
set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17
set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18]
set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18
set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19]
set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19
set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20]
set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20
set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21]
set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21
set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22]
set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22
set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23]
set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23
set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24]
set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24
set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25]
set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25
set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26]
set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26
set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27]
set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27
set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28]
set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28
set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29]
set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29
set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30]
set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30
set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31]
set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31
set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0]
set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0
set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1]
set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1
set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2]
set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2
set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3]
set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3
set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0]
set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0
set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1]
set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1
set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2]
set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2
set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3]
set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3
set_location_assignment PIN_D28 -to HPS_DDR3_ODT
set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N
set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N
set_location_assignment PIN_D25 -to HPS_DDR3_RZQ
set_location_assignment PIN_E25 -to HPS_DDR3_WE_N
set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK
set_location_assignment PIN_B14 -to HPS_ENET_INT_N
set_location_assignment PIN_A13 -to HPS_ENET_MDC
set_location_assignment PIN_E16 -to HPS_ENET_MDIO
set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK
set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0]
set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0
set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1]
set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1
set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2]
set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2
set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3]
set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3
set_location_assignment PIN_J13 -to HPS_ENET_RX_DV
set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0]
set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0
set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1]
set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1
set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2]
set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2
set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3]
set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3
set_location_assignment PIN_A12 -to HPS_ENET_TX_EN
set_location_assignment PIN_A17 -to HPS_GSENSOR_INT
set_location_assignment PIN_C18 -to HPS_I2C0_SCLK
set_location_assignment PIN_A19 -to HPS_I2C0_SDAT
set_location_assignment PIN_K18 -to HPS_I2C1_SCLK
set_location_assignment PIN_A21 -to HPS_I2C1_SDAT
set_location_assignment PIN_J18 -to HPS_KEY_N
set_location_assignment PIN_A20 -to HPS_LED
set_location_assignment PIN_H13 -to HPS_LTC_GPIO
set_location_assignment PIN_B8 -to HPS_SD_CLK
set_location_assignment PIN_D14 -to HPS_SD_CMD
set_location_assignment PIN_C13 -to HPS_SD_DATA[0]
set_location_assignment PIN_C13 -to HPS_SD_DATA_0
set_location_assignment PIN_B6 -to HPS_SD_DATA[1]
set_location_assignment PIN_B6 -to HPS_SD_DATA_1
set_location_assignment PIN_B11 -to HPS_SD_DATA[2]
set_location_assignment PIN_B11 -to HPS_SD_DATA_2
set_location_assignment PIN_B9 -to HPS_SD_DATA[3]
set_location_assignment PIN_B9 -to HPS_SD_DATA_3
set_location_assignment PIN_C19 -to HPS_SPIM_CLK
set_location_assignment PIN_B19 -to HPS_SPIM_MISO
set_location_assignment PIN_B16 -to HPS_SPIM_MOSI
set_location_assignment PIN_C16 -to HPS_SPIM_SS
set_location_assignment PIN_A22 -to HPS_UART_RX
set_location_assignment PIN_B21 -to HPS_UART_TX
set_location_assignment PIN_G4 -to HPS_USB_CLKOUT
set_location_assignment PIN_C10 -to HPS_USB_DATA[0]
set_location_assignment PIN_C10 -to HPS_USB_DATA_0
set_location_assignment PIN_F5 -to HPS_USB_DATA[1]
set_location_assignment PIN_F5 -to HPS_USB_DATA_1
set_location_assignment PIN_C9 -to HPS_USB_DATA[2]
set_location_assignment PIN_C9 -to HPS_USB_DATA_2
set_location_assignment PIN_C4 -to HPS_USB_DATA[3]
set_location_assignment PIN_C4 -to HPS_USB_DATA_3
set_location_assignment PIN_C8 -to HPS_USB_DATA[4]
set_location_assignment PIN_C8 -to HPS_USB_DATA_4
set_location_assignment PIN_D4 -to HPS_USB_DATA[5]
set_location_assignment PIN_D4 -to HPS_USB_DATA_5
set_location_assignment PIN_C7 -to HPS_USB_DATA[6]
set_location_assignment PIN_C7 -to HPS_USB_DATA_6
set_location_assignment PIN_F4 -to HPS_USB_DATA[7]
set_location_assignment PIN_F4 -to HPS_USB_DATA_7
set_location_assignment PIN_E5 -to HPS_USB_DIR
set_location_assignment PIN_D5 -to HPS_USB_NXT
set_location_assignment PIN_C5 -to HPS_USB_STP
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
#============================================================
# KEY_N
#============================================================
set_location_assignment PIN_AH17 -to KEY_N[0]
set_location_assignment PIN_AH17 -to KEY_N_0
set_location_assignment PIN_AH16 -to KEY_N[1]
set_location_assignment PIN_AH16 -to KEY_N_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1
#============================================================
# LED
#============================================================
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_W15 -to LED_0
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_AA24 -to LED_1
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V16 -to LED_2
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_V15 -to LED_3
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AF26 -to LED_4
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_AE26 -to LED_5
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_Y16 -to LED_6
set_location_assignment PIN_AA23 -to LED[7]
set_location_assignment PIN_AA23 -to LED_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7
#============================================================
# SW
#============================================================
set_location_assignment PIN_L10 -to SW[0]
set_location_assignment PIN_L10 -to SW_0
set_location_assignment PIN_L9 -to SW[1]
set_location_assignment PIN_L9 -to SW_1
set_location_assignment PIN_H6 -to SW[2]
set_location_assignment PIN_H6 -to SW_2
set_location_assignment PIN_H5 -to SW[3]
set_location_assignment PIN_H5 -to SW_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3
#============================================================
# GPIO_0, GPIO_0 connect to GPIO Default
#============================================================
set_location_assignment PIN_V12 -to PIO_INT_N
set_location_assignment PIN_AE11 -to PIO_SCL
set_location_assignment PIN_AE12 -to PIO_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_INT_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO_SDA
set_location_assignment PIN_AF7 -to PIR_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIR_OUT
set_location_assignment PIN_W12 -to CAM_PAL_VGA_SDA
set_location_assignment PIN_AF8 -to CAM_PAL_VGA_SCL
set_location_assignment PIN_T11 -to CAM_SYS_CLK
set_location_assignment PIN_AG6 -to CAM_LV
set_location_assignment PIN_AH2 -to CAM_PIX_CLK
set_location_assignment PIN_AE4 -to CAM_FV
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PAL_VGA_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_SYS_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_LV
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_PIX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAM_FV
set_location_assignment PIN_Y8 -to PAL_VD_HSO
set_location_assignment PIN_AB4 -to PAL_VD_VSO
set_location_assignment PIN_AG5 -to PAL_VD_VD[0]
set_location_assignment PIN_AG5 -to PAL_VD_VD_0
set_location_assignment PIN_AH5 -to PAL_VD_VD[1]
set_location_assignment PIN_AH5 -to PAL_VD_VD_1
set_location_assignment PIN_AH6 -to PAL_VD_VD[2]
set_location_assignment PIN_AH6 -to PAL_VD_VD_2
set_location_assignment PIN_T8 -to PAL_VD_VD[3]
set_location_assignment PIN_T8 -to PAL_VD_VD_3
set_location_assignment PIN_T12 -to PAL_VD_VD[4]
set_location_assignment PIN_T12 -to PAL_VD_VD_4
set_location_assignment PIN_Y5 -to PAL_VD_VD[5]
set_location_assignment PIN_Y5 -to PAL_VD_VD_5
set_location_assignment PIN_Y4 -to PAL_VD_VD[6]
set_location_assignment PIN_Y4 -to PAL_VD_VD_6
set_location_assignment PIN_W8 -to PAL_VD_VD[7]
set_location_assignment PIN_W8 -to PAL_VD_VD_7
set_location_assignment PIN_AH4 -to PAL_VD_CLKO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_HSO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VSO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_VD_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PAL_VD_CLKO
set_location_assignment PIN_AH3 -to SERVO_0
set_location_assignment PIN_AF4 -to SERVO_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SERVO_1
set_location_assignment PIN_AD12 -to J0_SPI_CLK
set_location_assignment PIN_AD11 -to J0_SPI_MISO
set_location_assignment PIN_AF9 -to J0_SPI_CS_N
set_location_assignment PIN_AD10 -to J0_SPI_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to J0_SPI_MOSI
set_location_assignment PIN_AF5 -to FROM_ESP_TXD
set_location_assignment PIN_T13 -to TO_ESP_RXD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FROM_ESP_TXD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TO_ESP_RXD
set_location_assignment PIN_AE7 -to SPI_MISO
set_location_assignment PIN_AF6 -to SPI_ENA_N
set_location_assignment PIN_AE8 -to SPI_CLK
set_location_assignment PIN_AE9 -to SPI_MOSI
set_location_assignment PIN_AF10 -to SPI_DAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_ENA_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DAT
set_location_assignment PIN_AF11 -to LED_BGR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_BGR
#============================================================
# GPIO_1, GPIO_1 connect to GPIO Default
#============================================================
set_location_assignment PIN_AA15 -to RESET_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N
set_location_assignment PIN_AG28 -to TS_SCL
set_location_assignment PIN_AH27 -to TS_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TS_SDA
set_location_assignment PIN_Y15 -to LCD_PIN_DAV_N
set_location_assignment PIN_AG26 -to LCD_DE
set_location_assignment PIN_AF23 -to LCD_DISPLAY_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_PIN_DAV_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DISPLAY_EN
set_location_assignment PIN_AH24 -to BLT_TXD
set_location_assignment PIN_AE22 -to BLT_RXD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_TXD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BLT_RXD
set_location_assignment PIN_AG20 -to BOARD_ID
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_ID
set_location_assignment PIN_AF21 -to VIDEO_HSYNC
set_location_assignment PIN_AG19 -to VIDEO_VSYNC
set_location_assignment PIN_AF20 -to VIDEO_CLK
set_location_assignment PIN_AG23 -to VIDEO_B[0]
set_location_assignment PIN_AG23 -to VIDEO_B_0
set_location_assignment PIN_AH23 -to VIDEO_B[1]
set_location_assignment PIN_AH23 -to VIDEO_B_1
set_location_assignment PIN_AF25 -to VIDEO_B[2]
set_location_assignment PIN_AF25 -to VIDEO_B_2
set_location_assignment PIN_AG24 -to VIDEO_B[3]
set_location_assignment PIN_AG24 -to VIDEO_B_3
set_location_assignment PIN_AA19 -to VIDEO_B[4]
set_location_assignment PIN_AA19 -to VIDEO_B_4
set_location_assignment PIN_AH26 -to VIDEO_B[5]
set_location_assignment PIN_AH26 -to VIDEO_B_5
set_location_assignment PIN_AG18 -to VIDEO_B[6]
set_location_assignment PIN_AG18 -to VIDEO_B_6
set_location_assignment PIN_AC23 -to VIDEO_B[7]
set_location_assignment PIN_AC23 -to VIDEO_B_7
set_location_assignment PIN_AH22 -to VIDEO_G[0]
set_location_assignment PIN_AH22 -to VIDEO_G_0
set_location_assignment PIN_AF22 -to VIDEO_G[1]
set_location_assignment PIN_AF22 -to VIDEO_G_1
set_location_assignment PIN_AD20 -to VIDEO_G[2]
set_location_assignment PIN_AD20 -to VIDEO_G_2
set_location_assignment PIN_AE24 -to VIDEO_G[3]
set_location_assignment PIN_AE24 -to VIDEO_G_3
set_location_assignment PIN_AE20 -to VIDEO_G[4]
set_location_assignment PIN_AE20 -to VIDEO_G_4
set_location_assignment PIN_AD19 -to VIDEO_G[5]
set_location_assignment PIN_AD19 -to VIDEO_G_5
set_location_assignment PIN_AF18 -to VIDEO_G[6]
set_location_assignment PIN_AF18 -to VIDEO_G_6
set_location_assignment PIN_AE19 -to VIDEO_G[7]
set_location_assignment PIN_AE19 -to VIDEO_G_7
set_location_assignment PIN_AC22 -to VIDEO_R[0]
set_location_assignment PIN_AC22 -to VIDEO_R_0
set_location_assignment PIN_AA18 -to VIDEO_R[1]
set_location_assignment PIN_AA18 -to VIDEO_R_1
set_location_assignment PIN_AE23 -to VIDEO_R[2]
set_location_assignment PIN_AE23 -to VIDEO_R_2
set_location_assignment PIN_AD23 -to VIDEO_R[3]
set_location_assignment PIN_AD23 -to VIDEO_R_3
set_location_assignment PIN_AH18 -to VIDEO_R[4]
set_location_assignment PIN_AH18 -to VIDEO_R_4
set_location_assignment PIN_AG21 -to VIDEO_R[5]
set_location_assignment PIN_AG21 -to VIDEO_R_5
set_location_assignment PIN_AH21 -to VIDEO_R[6]
set_location_assignment PIN_AH21 -to VIDEO_R_6
set_location_assignment PIN_AH19 -to VIDEO_R[7]
set_location_assignment PIN_AH19 -to VIDEO_R_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_HSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_VSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_B_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_G_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_R_7

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cs309-psoc/lab_1_1/hw/quartus/lab_1_1.sdc Normal file
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create_clock -period 20 [get_ports FPGA_CLK1_50]
create_clock -period 20 [get_ports FPGA_CLK2_50]
create_clock -period 20 [get_ports FPGA_CLK3_50]
derive_pll_clocks
derive_clock_uncertainty

601
cs309-psoc/lab_1_1/hw/quartus/soc_system.qsys Normal file
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cs309-psoc/lab_1_1/lab_1_1.pdf Normal file
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cs309-psoc/lab_1_1/sw/nios/application/app.c Normal file
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#include <stdlib.h>
#include <io.h>
#include <stdio.h>
#include <inttypes.h>
#include <stdbool.h>
#include <unistd.h>
#include "pantilt/pantilt.h"
#include "system.h"
#define SLEEP_DURATION_US (25000) // 25 ms
#define PANTILT_STEP_US (25) // 25 us
#define PANTILT_PWM_V_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_V_MIN_DUTY_CYCLE_US + PANTILT_PWM_V_MAX_DUTY_CYCLE_US) / 2)
#define PANTILT_PWM_H_CENTER_DUTY_CYCLE_US ((PANTILT_PWM_H_MIN_DUTY_CYCLE_US + PANTILT_PWM_H_MAX_DUTY_CYCLE_US) / 2)
int main(void) {
// Hardware control structures
pantilt_dev pantilt = pantilt_inst((void *) PWM_0_BASE, (void *) PWM_1_BASE);
// Initialize hardware
pantilt_init(&pantilt);
// Center servos.
pantilt_configure_vertical(&pantilt, PANTILT_PWM_V_MIN_DUTY_CYCLE_US);
pantilt_configure_horizontal(&pantilt, PANTILT_PWM_H_MIN_DUTY_CYCLE_US);
pantilt_start_vertical(&pantilt);
pantilt_start_horizontal(&pantilt);
// Rotate servos in "square" motion
while (true) {
uint32_t v_duty_us = 0;
uint32_t h_duty_us = 0;
// bottom to top
v_duty_us = PANTILT_PWM_V_MIN_DUTY_CYCLE_US;
do {
pantilt_configure_vertical(&pantilt, v_duty_us);
v_duty_us += PANTILT_STEP_US;
usleep(SLEEP_DURATION_US);
} while (v_duty_us <= PANTILT_PWM_V_MAX_DUTY_CYCLE_US);
// left to right
h_duty_us = PANTILT_PWM_H_MIN_DUTY_CYCLE_US;
do {
pantilt_configure_horizontal(&pantilt, h_duty_us);
h_duty_us += PANTILT_STEP_US;
usleep(SLEEP_DURATION_US);
} while (h_duty_us <= PANTILT_PWM_H_MAX_DUTY_CYCLE_US);
// top to bottom
v_duty_us = PANTILT_PWM_V_MAX_DUTY_CYCLE_US;
do {
pantilt_configure_vertical(&pantilt, v_duty_us);
v_duty_us -= PANTILT_STEP_US;
usleep(SLEEP_DURATION_US);
} while (PANTILT_PWM_V_MIN_DUTY_CYCLE_US <= v_duty_us);
// left to right
h_duty_us = PANTILT_PWM_H_MAX_DUTY_CYCLE_US;
do {
pantilt_configure_horizontal(&pantilt, h_duty_us);
h_duty_us -= PANTILT_STEP_US;
usleep(SLEEP_DURATION_US);
} while (PANTILT_PWM_H_MIN_DUTY_CYCLE_US <= h_duty_us);
}
return EXIT_SUCCESS;
}

109
cs309-psoc/lab_1_1/sw/nios/application/pantilt/pantilt.c Normal file
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#include "pantilt.h"
/**
* pantilt_inst
*
* Instantiate a pantilt device structure.
*
* @param pwm_v_base Base address of the vertical PWM component.
* @param pwm_h_base Base address of the horizontal PWM component.
*/
pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base) {
pantilt_dev dev;
dev.pwm_v = pwm_inst(pwm_v_base);
dev.pwm_h = pwm_inst(pwm_h_base);
return dev;
}
/**
* pantilt_init
*
* Initializes the pantilt device.
*
* @param dev pantilt device structure.
*/
void pantilt_init(pantilt_dev *dev) {
pwm_init(&(dev->pwm_v));
pwm_init(&(dev->pwm_h));
}
/**
* pantilt_configure_vertical
*
* Configure the vertical PWM component.
*
* @param dev pantilt device structure.
* @param duty_cycle pwm duty cycle in us.
*/
void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle) {
// Need to compensate for inverted servo rotation.
duty_cycle = PANTILT_PWM_V_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_V_MIN_DUTY_CYCLE_US;
pwm_configure(&(dev->pwm_v),
duty_cycle,
PANTILT_PWM_PERIOD_US,
PANTILT_PWM_CLOCK_FREQ_HZ);
}
/**
* pantilt_configure_horizontal
*
* Configure the horizontal PWM component.
*
* @param dev pantilt device structure.
* @param duty_cycle pwm duty cycle in us.
*/
void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle) {
// Need to compensate for inverted servo rotation.
duty_cycle = PANTILT_PWM_H_MAX_DUTY_CYCLE_US - duty_cycle + PANTILT_PWM_H_MIN_DUTY_CYCLE_US;
pwm_configure(&(dev->pwm_h),
duty_cycle,
PANTILT_PWM_PERIOD_US,
PANTILT_PWM_CLOCK_FREQ_HZ);
}
/**
* pantilt_start_vertical
*
* Starts the vertical pwm controller.
*
* @param dev pantilt device structure.
*/
void pantilt_start_vertical(pantilt_dev *dev) {
pwm_start(&(dev->pwm_v));
}
/**
* pantilt_start_horizontal
*
* Starts the horizontal pwm controller.
*
* @param dev pantilt device structure.
*/
void pantilt_start_horizontal(pantilt_dev *dev) {
pwm_start(&(dev->pwm_h));
}
/**
* pantilt_stop_vertical
*
* Stops the vertical pwm controller.
*
* @param dev pantilt device structure.
*/
void pantilt_stop_vertical(pantilt_dev *dev) {
pwm_stop(&(dev->pwm_v));
}
/**
* pantilt_stop_horizontal
*
* Stops the horizontal pwm controller.
*
* @param dev pantilt device structure.
*/
void pantilt_stop_horizontal(pantilt_dev *dev) {
pwm_stop(&(dev->pwm_h));
}

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cs309-psoc/lab_1_1/sw/nios/application/pantilt/pantilt.h Normal file
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#ifndef __PANTILT_H__
#define __PANTILT_H__
#include "pwm/pwm.h"
/* joysticks device structure */
typedef struct pantilt_dev {
pwm_dev pwm_v; /* Vertical PWM device handle */
pwm_dev pwm_h; /* Horizontal PWM device handle */
} pantilt_dev;
/*******************************************************************************
* Public API
******************************************************************************/
#define PANTILT_PWM_CLOCK_FREQ_HZ (50000000) // 50.00 MHz
#define PANTILT_PWM_PERIOD_US (25000) // 25.00 ms
/* Vertical servo */
#define PANTILT_PWM_V_MIN_DUTY_CYCLE_US (950) // 0.95 ms
#define PANTILT_PWM_V_MAX_DUTY_CYCLE_US (2150) // 2.15 ms
/* Horizontal servo */
#define PANTILT_PWM_H_MIN_DUTY_CYCLE_US (1000) // 1.00 ms
#define PANTILT_PWM_H_MAX_DUTY_CYCLE_US (2000) // 2.00 ms
pantilt_dev pantilt_inst(void *pwm_v_base, void *pwm_h_base);
void pantilt_init(pantilt_dev *dev);
void pantilt_configure_vertical(pantilt_dev *dev, uint32_t duty_cycle);
void pantilt_configure_horizontal(pantilt_dev *dev, uint32_t duty_cycle);
void pantilt_start_vertical(pantilt_dev *dev);
void pantilt_start_horizontal(pantilt_dev *dev);
void pantilt_stop_vertical(pantilt_dev *dev);
void pantilt_stop_horizontal(pantilt_dev *dev);
#endif /* __PANTILT_H__ */

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cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm.c Normal file
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#include <io.h>
#include "pwm.h"
#include "pwm_regs.h"
#define MICROSEC_TO_CLK(time, freq) ((time)*((freq)/1000000))
/**
* pwm_inst
*
* Instantiate a pwm device structure.
*
* @param base Base address of the component.
*/
pwm_dev pwm_inst(void *base) {
pwm_dev dev;
dev.base = base;
return dev;
}
/**
* pwm_init
*
* Initializes the pwm device. This function stops the controller.
*
* @param dev pwm device structure.
*/
void pwm_init(pwm_dev *dev) {
pwm_stop(dev);
}
/**
* pwm_configure
*
* Configure pwm component.
*
* @param dev pwm device structure.
* @param duty_cycle pwm duty cycle in us.
* @param period pwm period in us.
* @param module_frequency frequency at which the component is clocked.
*/
void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency) {
IOWR_32DIRECT(dev->base, PWM_PERIOD_OFST, MICROSEC_TO_CLK(period, module_frequency));
IOWR_32DIRECT(dev->base, PWM_DUTY_CYCLE_OFST, MICROSEC_TO_CLK(duty_cycle, module_frequency));
}
/**
* pwm_start
*
* Starts the pwm controller.
*
* @param dev pwm device structure.
*/
void pwm_start(pwm_dev *dev) {
IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_START_MASK);
}
/**
* pwm_stop
*
* Stops the pwm controller.
*
* @param dev pwm device structure.
*/
void pwm_stop(pwm_dev *dev) {
IOWR_32DIRECT(dev->base, PWM_CTRL_OFST, PWM_CTRL_STOP_MASK);
}

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cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm.h Normal file
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#ifndef __PWM_H__
#define __PWM_H__
#include <stdint.h>
/* pwm device structure */
typedef struct pwm_dev {
void *base; /* Base address of component */
} pwm_dev;
/*******************************************************************************
* Public API
******************************************************************************/
pwm_dev pwm_inst(void *base);
void pwm_init(pwm_dev *dev);
void pwm_configure(pwm_dev *dev, uint32_t duty_cycle, uint32_t period, uint32_t module_frequency);
void pwm_start(pwm_dev *dev);
void pwm_stop(pwm_dev *dev);
#endif /* __PWM_H__ */

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cs309-psoc/lab_1_1/sw/nios/application/pantilt/pwm/pwm_regs.h Normal file
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#ifndef __PWM_REGS_H__
#define __PWM_REGS_H__
#define PWM_PERIOD_OFST (0 * 4) /* RW */
#define PWM_DUTY_CYCLE_OFST (1 * 4) /* RW */
#define PWM_CTRL_OFST (2 * 4) /* WO */
#define PWM_CTRL_STOP_MASK (0)
#define PWM_CTRL_START_MASK (1)
#endif /* __PWM_REGS_H__ */