89 lines
1.7 KiB
VHDL
89 lines
1.7 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity WS28XX is
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port(
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clk:in std_logic;
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nReset:in std_logic;
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--Internalinterface(i.e.Avalonslave).
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address:in std_logic;
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write:in std_logic;
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writedata:in std_logic_vector(31 downto 0);
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--Externalinterface(i.e.conduit).
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lout:out std_logic
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);
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end WS28XX;
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architecture comp of WS28XX is
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signal led_i : std_logic_vector(7 downto 0);
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signal led_v : std_logic_vector(23 downto 0);
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signal led_wr : std_logic;
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signal led_n : std_logic_vector(7 downto 0);
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signal led_n_wr : std_logic;
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signal ready : std_logic;
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begin
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--WSDriver.
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l0 : entity work.WSDriver
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generic map (
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F_CLK => 50000000,
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N_LED_MAX => 255
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)
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port map (
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clk => clk,
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rst_n => nReset,
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-- LED address and LED value
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led_wr_in => led_wr,
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led_in => led_v,
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addr_in => led_i,
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-- Write-enable & value of N bits to keep active
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n_wr_in => led_n_wr,
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n_in => led_n,
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-- Output 1-bit line for WS2812 strip
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ws_out => lout,
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-- Low while shifting LED values
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ready_out => ready
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);
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led_i <= writedata(31 downto 24);
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led_v <= writedata(23 downto 0);
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led_n <= writedata(7 downto 0);
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--Avalon slave - write to registers.
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process(write,address,nReset)
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begin
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if nReset = '0' then
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led_wr <= '0';
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led_n_wr <= '0';
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else
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led_wr <= '0';
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led_n_wr <= '0';
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if write = '1' then
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case address is
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when '0' =>
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led_wr <= '1';
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when '1' =>
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led_n_wr <= '1';
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when others =>
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null;
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end case;
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end if;
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end if;
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end process;
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end comp;
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