40 lines
974 B
VHDL
Executable File
40 lines
974 B
VHDL
Executable File
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity register_file is
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port(
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clk : in std_logic;
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aa : in std_logic_vector(4 downto 0);
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ab : in std_logic_vector(4 downto 0);
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aw : in std_logic_vector(4 downto 0);
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wren : in std_logic;
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wrdata : in std_logic_vector(31 downto 0);
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a : out std_logic_vector(31 downto 0);
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b : out std_logic_vector(31 downto 0)
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);
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end register_file;
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architecture synth of register_file is
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type reg_type is array(0 to 31) of std_logic_vector(31 downto 0);
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signal reg : reg_type := (others => (others => '0'));
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begin
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a <= reg(to_integer(unsigned(aa)));
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b <= reg(to_integer(unsigned(ab)));
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write: process(clk) is
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begin
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if(rising_edge(clk)) then
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if(wren = '1') then
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reg(to_integer(unsigned(aw))) <= wrdata;
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reg(0) <= (31 downto 0 => '0');
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end if;
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end if;
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end process write;
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end synth;
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