139 lines
3.4 KiB
VHDL
Executable File
139 lines
3.4 KiB
VHDL
Executable File
-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- PROGRAM "Quartus II 32-bit"
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-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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-- CREATED "Tue Oct 29 17:44:16 2013"
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY work;
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ENTITY ALU IS
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PORT
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(
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a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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op : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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s : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END ALU;
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ARCHITECTURE bdf_type OF ALU IS
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COMPONENT add_sub
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PORT(sub_mode : IN STD_LOGIC;
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a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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carry : OUT STD_LOGIC;
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zero : OUT STD_LOGIC;
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r : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT comparator
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PORT(carry : IN STD_LOGIC;
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zero : IN STD_LOGIC;
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a_31 : IN STD_LOGIC;
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b_31 : IN STD_LOGIC;
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diff_31 : IN STD_LOGIC;
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op : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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r : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT logic_unit
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PORT(a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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op : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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r : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT multiplexer
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PORT(i0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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i1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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i2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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i3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT shift_unit
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PORT(a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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op : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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r : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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SIGNAL addsub : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL carry : STD_LOGIC;
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SIGNAL comp_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL logic_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL shift_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL zero : STD_LOGIC;
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BEGIN
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b2v_add_sub_0 : add_sub
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PORT MAP(sub_mode => op(3),
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a => a,
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b => b,
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carry => carry,
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zero => zero,
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r => addsub);
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b2v_comparator_0 : comparator
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PORT MAP(carry => carry,
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zero => zero,
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a_31 => a(31),
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b_31 => b(31),
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diff_31 => addsub(31),
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op => op(2 DOWNTO 0),
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r => comp_r(0));
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b2v_logic_unit_0 : logic_unit
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PORT MAP(a => a,
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b => b,
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op => op(1 DOWNTO 0),
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r => logic_r);
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b2v_multiplexer_0 : multiplexer
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PORT MAP(i0 => addsub,
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i1 => comp_r,
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i2 => logic_r,
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i3 => shift_r,
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sel => op(5 DOWNTO 4),
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o => s);
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b2v_shift_unit_0 : shift_unit
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PORT MAP(a => a,
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b => b(4 DOWNTO 0),
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op => op(2 DOWNTO 0),
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r => shift_r);
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comp_r(31 DOWNTO 1) <= "0000000000000000000000000000000";
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END bdf_type; |