epfl-archive/cs208-ca/quartus/logic_unit.bsf
2022-04-07 18:43:21 +02:00

58 lines
1.9 KiB
Plaintext
Executable File

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 64 64 320 160)
(text "logic_unit" (rect 5 0 51 12)(font "Arial" ))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a[31..0]" (rect 0 0 37 12)(font "Arial" ))
(text "a[31..0]" (rect 21 27 58 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "b[31..0]" (rect 0 0 37 12)(font "Arial" ))
(text "b[31..0]" (rect 21 43 58 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "op[1..0]" (rect 0 0 37 12)(font "Arial" ))
(text "op[1..0]" (rect 21 59 58 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 256 48)
(output)
(text "r[31..0]" (rect 128 0 163 12)(font "Arial" ))
(text "r[31..0]" (rect 198 43 233 55)(font "Arial" ))
(line (pt 256 48)(pt 240 48)(line_width 3))
)
(drawing
(rectangle (rect 16 16 240 80)(line_width 1))
)
)