213 lines
6.9 KiB
VHDL
213 lines
6.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity WSDriver is
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generic (
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F_CLK : natural; -- Board frequency in Hz
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N_LED_MAX : natural -- Maximum number of LEDs to instantiate
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- LED address and LED value
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led_wr_in : in std_logic;
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led_in : in std_logic_vector(23 downto 0);
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addr_in : in std_logic_vector(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0);
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-- Write-enable and value of N LEDs to keep active/addressable
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n_wr_in : in std_logic;
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n_in : in std_logic_vector(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0);
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-- Output 1-bit line for WS2812 strip
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ws_out : out std_logic;
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-- Output Ready
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ready_out : out std_logic
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);
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end WSDriver;
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architecture Behavioral of WSDriver is
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constant F_WS : real := 1.0/((0.3)*10**(-6.0));
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constant T_RES_US : real := 50.0*10**(-6.0);
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constant RES_TICKS : integer := integer(ceil(T_RES_US*F_WS));
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constant BITS_PER_LED : integer := 24;
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subtype LED is std_logic_vector(BITS_PER_LED - 1 downto 0);
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type LED_array is array (natural range 0 to N_LED_MAX - 1) of LED;
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type State is (ready, tx, reset);
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signal ws_clk : std_logic;
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signal led_idx_reg, led_idx_next : natural range 0 to N_LED_MAX - 1;
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signal bit_idx_reg, bit_idx_next : natural range 0 to N_LED_MAX - 1;
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signal state_reg, state_next : State;
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constant WS_CLKS_PER_BIT : integer := 4;
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signal ws_cntr_reg, ws_cntr_next : integer range WS_CLKS_PER_BIT - 1 downto 0;
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signal ws_en : std_logic;
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signal leds_reg, leds_next : LED_array;
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-- Register for maintaining the set of driven LEDs
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signal n_leds_reg, n_leds_next : unsigned(integer(ceil(log2(real(N_LED_MAX)))) - 1 downto 0) := (others => '0');
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-- Currently accessed LED
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signal current_led : LED;
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-- Trailing reset counter
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signal reset_cntr_reg, reset_cntr_next : integer range RES_TICKS - 1 downto 0;
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-- Detecting wr_in assertions
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signal wr_in_detec_reg, wr_in_detec_next : std_logic := '0';
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begin
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-- Next-state LED and Bit index process
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process (all) begin
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bit_idx_next <= bit_idx_reg;
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led_idx_next <= led_idx_reg;
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reset_cntr_next <= reset_cntr_reg;
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state_next <= state_reg;
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wr_in_detec_next <= wr_in_detec_reg;
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-- Latch wr_in value, to ensure re-transition to tx state if wr_in occured
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-- during a non-ready state.
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if led_wr_in = '1' then
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wr_in_detec_next <= '1';
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end if;
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case state_reg is
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-- STATE READY
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when ready =>
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bit_idx_next <= BITS_PER_LED - 1;
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led_idx_next <= 0;
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if n_leds_reg /= 0 and wr_in_detec_reg = '1' then
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wr_in_detec_next <= '0';
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state_next <= tx;
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end if;
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-- STATE TX
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when tx =>
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if ws_cntr_reg = (WS_CLKS_PER_BIT - 1) and ws_clk ='1' then
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if bit_idx_reg = 0 then
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-- Transition to next LED
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bit_idx_next <= BITS_PER_LED - 1;
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led_idx_next <= led_idx_reg + 1;
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else
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-- Bit was fully shifted, transition to next bit
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bit_idx_next <= bit_idx_reg - 1;
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end if;
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-- All LEDs fully shifted out (+last bit of last led)? transition to ready
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if bit_idx_reg = 0 and led_idx_reg + 1 = n_leds_reg then
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state_next <= reset;
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end if;
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end if;
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-- STATE TRAILING RESET
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when reset =>
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if ws_clk ='1' then
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if reset_cntr_reg = RES_TICKS - 1 then
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reset_cntr_next <= 0;
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state_next <= ready;
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else
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reset_cntr_next <= reset_cntr_reg + 1;
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end if;
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end if;
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end case;
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end process;
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-- Currently accessed LED multiplexer
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current_led <= leds_reg(led_idx_reg) when state_reg = tx else (others => '0');
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-- Next state WS counter
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process (state_reg, ws_cntr_reg, ws_clk) begin
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ws_cntr_next <= ws_cntr_reg;
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if state_reg = ready or state_reg = reset then
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ws_cntr_next <= 0;
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elsif ws_clk = '1' then
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if ws_cntr_reg /= (WS_CLKS_PER_BIT - 1) then
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ws_cntr_next <= ws_cntr_reg + 1;
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else
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ws_cntr_next <= 0;
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end if;
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end if;
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end process;
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-- Next-state LED values
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process(led_wr_in, led_in, leds_reg, addr_in, n_wr_in, n_in) begin
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leds_next <= leds_reg;
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n_leds_next <= n_leds_reg;
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if led_wr_in = '1' then
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leds_next(to_integer(unsigned(addr_in))) <= led_in;
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end if;
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-- Set N LEDs precedes LED write operation
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if n_wr_in = '1' then
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n_leds_next <= unsigned(n_in);
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end if;
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end process;
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-- WS output clock
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clkgen_ent : entity work.ClkGen
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generic map (
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F_CLK => F_CLK,
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F_OUT => integer(F_WS)
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)
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port map (
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clk => clk,
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rst_n => rst_n,
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clk_o => ws_clk,
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en => ws_en
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);
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-- Only enable ws clock gen when required
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ws_en <= '1' when state_reg /= ready else '0';
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-- Clocking logic
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process(clk) begin
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if rising_edge(clk) then
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if rst_n = '0' then
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ws_cntr_reg <= 0;
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leds_reg <= (others => (others => '0'));
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n_leds_reg <= (others => '0');
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wr_in_detec_reg <= '0';
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bit_idx_reg <= BITS_PER_LED - 1;
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state_reg <= ready;
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led_idx_reg <= 0;
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reset_cntr_reg <= 0;
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else
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ws_cntr_reg <= ws_cntr_next;
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leds_reg <= leds_next;
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n_leds_reg <= n_leds_next;
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wr_in_detec_reg <= wr_in_detec_next;
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bit_idx_reg <= bit_idx_next;
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state_reg <= state_next;
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led_idx_reg <= led_idx_next;
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reset_cntr_reg <= reset_cntr_next;
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end if;
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end if;
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end process;
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-- WS2811 output bit sequence
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process(state_reg, ws_cntr_reg) begin
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ws_out <= '0';
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if state_reg = tx then
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case ws_cntr_reg is
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when 0 => ws_out <= '1';
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when 1 => ws_out <= current_led(bit_idx_reg);
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when 2 => ws_out <= '0';
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when 3 => ws_out <= '0';
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end case;
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end if;
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end process;
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ready_out <= '1' when state_reg = ready else '0';
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end Behavioral; |