33 lines
1009 B
VHDL
Executable File
33 lines
1009 B
VHDL
Executable File
library ieee;
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use ieee.std_logic_1164.all;
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entity seven_seg is
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port(address : in std_logic_vector(15 downto 0);
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wrdata : in std_logic_vector(7 downto 0);
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clk : in std_logic;
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reset_n : in std_logic;
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seg_out : out std_logic_vector(31 downto 0));
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end entity seven_seg;
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architecture rtl of seven_seg is
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type addr_t is array(3 downto 0) of std_logic_vector(15 downto 0);
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type reg_t is array(3 downto 0) of std_logic_vector(7 downto 0);
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constant addr_map : addr_t := (x"1198", x"119C", x"11A0", x"11A4");
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signal reg : reg_t;
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begin
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digits:for i in 3 downto 0 generate
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beh:process(clk, reset_n) is
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begin
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if(reset_n = '0') then
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reg(i) <= (others => '0');
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elsif(rising_edge(clk)) then
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if(address = addr_map(i)) then
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reg(i) <= wrdata;
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end if;
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end if;
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end process beh;
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seg_out(8 * (i + 1) - 1 downto 8 * i) <= reg(i);
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end generate;
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end architecture rtl;
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