293 lines
6.8 KiB
VHDL
Executable File
293 lines
6.8 KiB
VHDL
Executable File
-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- PROGRAM "Quartus II 32-bit"
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-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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-- CREATED "Wed Oct 30 17:22:54 2013"
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY work;
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ENTITY CPU IS
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PORT
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(
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reset_n : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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rddata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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write : OUT STD_LOGIC;
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read : OUT STD_LOGIC;
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address : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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wrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END CPU;
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ARCHITECTURE bdf_type OF CPU IS
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COMPONENT alu
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PORT(a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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op : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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s : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT controller
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PORT(clk : IN STD_LOGIC;
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reset_n : IN STD_LOGIC;
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op : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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opx : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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branch_op : OUT STD_LOGIC;
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imm_signed : OUT STD_LOGIC;
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ir_en : OUT STD_LOGIC;
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pc_add_imm : OUT STD_LOGIC;
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pc_en : OUT STD_LOGIC;
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pc_sel_a : OUT STD_LOGIC;
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pc_sel_imm : OUT STD_LOGIC;
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rf_wren : OUT STD_LOGIC;
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sel_addr : OUT STD_LOGIC;
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sel_b : OUT STD_LOGIC;
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sel_mem : OUT STD_LOGIC;
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sel_pc : OUT STD_LOGIC;
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sel_ra : OUT STD_LOGIC;
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sel_rC : OUT STD_LOGIC;
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write : OUT STD_LOGIC;
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read : OUT STD_LOGIC;
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op_alu : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT extend
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PORT(signed : IN STD_LOGIC;
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imm16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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imm32 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT ir
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PORT(clk : IN STD_LOGIC;
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enable : IN STD_LOGIC;
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D : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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Q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT mux2x16
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PORT(sel : IN STD_LOGIC;
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i0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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i1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT mux2x5
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PORT(sel : IN STD_LOGIC;
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i0 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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i1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT mux2x32
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PORT(sel : IN STD_LOGIC;
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i0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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i1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT pc
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PORT(clk : IN STD_LOGIC;
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reset_n : IN STD_LOGIC;
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en : IN STD_LOGIC;
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sel_a : IN STD_LOGIC;
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sel_imm : IN STD_LOGIC;
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add_imm : IN STD_LOGIC;
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a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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imm : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT register_file
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PORT(clk : IN STD_LOGIC;
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wren : IN STD_LOGIC;
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aa : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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ab : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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aw : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL alu_res : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL aw : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL branch_op : STD_LOGIC;
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SIGNAL branch_taken : STD_LOGIC;
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SIGNAL imm : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL imm_signed : STD_LOGIC;
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SIGNAL instr : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL ir_en : STD_LOGIC;
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SIGNAL op_alu : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL op_b : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL pc_add_imm : STD_LOGIC;
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SIGNAL pc_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL pc_en : STD_LOGIC;
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SIGNAL pc_sel_a : STD_LOGIC;
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SIGNAL pc_sel_imm : STD_LOGIC;
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SIGNAL pc_wren : STD_LOGIC;
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SIGNAL ra : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL rf_wren : STD_LOGIC;
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SIGNAL sel_addr : STD_LOGIC;
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SIGNAL sel_b : STD_LOGIC;
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SIGNAL sel_mem : STD_LOGIC;
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SIGNAL sel_pc : STD_LOGIC;
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SIGNAL sel_ra : STD_LOGIC;
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SIGNAL sel_rC : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN
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b2v_alu_0 : alu
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PORT MAP(a => a,
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b => op_b,
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op => op_alu,
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s => alu_res);
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branch_taken <= branch_op AND alu_res(0);
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b2v_controller_0 : controller
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PORT MAP(clk => clk,
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reset_n => reset_n,
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op => instr(5 DOWNTO 0),
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opx => instr(16 DOWNTO 11),
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branch_op => branch_op,
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imm_signed => imm_signed,
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ir_en => ir_en,
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pc_add_imm => pc_add_imm,
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pc_en => pc_wren,
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pc_sel_a => pc_sel_a,
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pc_sel_imm => pc_sel_imm,
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rf_wren => rf_wren,
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sel_addr => sel_addr,
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sel_b => sel_b,
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sel_mem => sel_mem,
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sel_pc => sel_pc,
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sel_ra => sel_ra,
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sel_rC => sel_rC,
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write => write,
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read => read,
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op_alu => op_alu);
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b2v_extend_0 : extend
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PORT MAP(signed => imm_signed,
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imm16 => instr(21 DOWNTO 6),
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imm32 => imm);
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b2v_IR_0 : ir
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PORT MAP(clk => clk,
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enable => ir_en,
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D => rddata,
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Q => instr);
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b2v_mux_addr : mux2x16
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PORT MAP(sel => sel_addr,
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i0 => pc_addr(15 DOWNTO 0),
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i1 => alu_res(15 DOWNTO 0),
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o => address);
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b2v_mux_aw : mux2x5
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PORT MAP(sel => sel_rC,
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i0 => SYNTHESIZED_WIRE_0,
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i1 => instr(21 DOWNTO 17),
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o => aw);
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b2v_mux_b : mux2x32
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PORT MAP(sel => sel_b,
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i0 => imm,
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i1 => b,
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o => op_b);
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b2v_mux_data : mux2x32
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PORT MAP(sel => SYNTHESIZED_WIRE_1,
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i0 => alu_res,
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i1 => SYNTHESIZED_WIRE_2,
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o => SYNTHESIZED_WIRE_3);
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b2v_mux_mem : mux2x32
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PORT MAP(sel => sel_mem,
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i0 => pc_addr,
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i1 => rddata,
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o => SYNTHESIZED_WIRE_2);
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b2v_mux_ra : mux2x5
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PORT MAP(sel => sel_ra,
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i0 => instr(26 DOWNTO 22),
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i1 => ra,
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o => SYNTHESIZED_WIRE_0);
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pc_en <= pc_wren OR branch_taken;
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b2v_PC_0 : pc
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PORT MAP(clk => clk,
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reset_n => reset_n,
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en => pc_en,
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sel_a => pc_sel_a,
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sel_imm => pc_sel_imm,
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add_imm => pc_add_imm,
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a => a(15 DOWNTO 0),
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imm => instr(21 DOWNTO 6),
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addr => pc_addr);
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SYNTHESIZED_WIRE_1 <= sel_pc OR sel_mem;
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b2v_register_file_0 : register_file
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PORT MAP(clk => clk,
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wren => rf_wren,
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aa => instr(31 DOWNTO 27),
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ab => instr(26 DOWNTO 22),
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aw => aw,
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wrdata => SYNTHESIZED_WIRE_3,
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a => a,
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b => b);
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wrdata <= b;
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ra <= "11111";
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END bdf_type; |