90 lines
1.9 KiB
VHDL
90 lines
1.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity PixTrans_tb is
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end PixTrans_tb;
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architecture test of PixTrans_tb is
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constant CLK_PERIOD : time := 20 ns;
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constant N_LED_MAX : integer := 255;
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constant MAX_H : natural := 4;
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constant MAX_W : natural := 4;
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constant ACTUAL_H : natural := 2;
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constant ACTUAL_W : natural := 2;
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signal clk : std_logic := '0';
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signal rst_n : std_logic;
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signal fifo_empty, lcd_req : std_logic;
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signal fifo_q : std_logic_vector(31 downto 0);
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signal w, h : natural;
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begin
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w <= ACTUAL_W;
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h <= ACTUAL_H;
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-- Instantiate DUT
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dut : entity work.PixTrans
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generic map (
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MAX_H => MAX_H,
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MAX_W => MAX_W
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)
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port map(
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clk => clk,
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rst_n => rst_n,
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lcd_req => lcd_req,
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fifo_q => fifo_q,
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fifo_empty => fifo_empty,
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w => w,
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h => h
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);
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-- Clocking process
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clk_generation : process
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begin
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clk <= not clk;
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wait for CLK_PERIOD / 2;
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end process;
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-- Testbench
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tb : process
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procedure getPixel is
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begin
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wait until rising_edge(clk);
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lcd_req <= '1';
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wait for CLK_PERIOD;
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wait until rising_edge(clk);
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lcd_req <= '0';
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wait for CLK_PERIOD*3;
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end procedure getPixel;
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begin
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-- Just let the FIFO interface always provide data
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fifo_q <= X"FFFF" & X"F0F0";
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fifo_empty <= '0';
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lcd_req <= '0';
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-- Reset
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rst_n <= '0';
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wait for CLK_PERIOD * 2.5;
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rst_n <= '1';
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wait for CLK_PERIOD * 2;
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-- Get some pixels
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for i in 1 to MAX_H*MAX_W loop
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report "hello";
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getPixel;
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end loop;
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-- Test finished
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wait;
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end process;
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end; |