142 lines
4.5 KiB
VHDL
142 lines
4.5 KiB
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.math_real.all;
|
|
use std.env.finish;
|
|
|
|
|
|
entity LCDController_tb is
|
|
end LCDController_tb;
|
|
|
|
architecture test of LCDController_tb is
|
|
constant CLK_PERIOD : time := 20 ns;
|
|
|
|
signal clk : std_logic := '0';
|
|
signal rst_n : std_logic;
|
|
signal waitreq, readdatavalid, fifo_almost_empty : std_logic;
|
|
|
|
-- Avalon slave interface
|
|
signal avalon_slave_address : std_logic_vector (3 downto 0);
|
|
signal avalon_slave_write : std_logic;
|
|
signal avalon_slave_writedata : std_logic_vector(31 downto 0);
|
|
signal avalon_slave_read : std_logic;
|
|
signal avalon_slave_readdata : std_logic_vector(31 downto 0);
|
|
|
|
-- Avalon master interface
|
|
signal avalon_master_waitreq : std_logic;
|
|
signal avalon_master_readdata : std_logic_vector(31 downto 0);
|
|
signal avalon_master_readdatavalid : std_logic;
|
|
|
|
signal avalon_master_read : std_logic;
|
|
signal irq : std_logic;
|
|
|
|
begin
|
|
|
|
-- Instantiate DUT
|
|
dut : entity work.LCDController
|
|
port map(
|
|
clk => clk,
|
|
rst_n => rst_n,
|
|
av_irq => irq,
|
|
|
|
avalon_slave_address => avalon_slave_address,
|
|
avalon_slave_write => avalon_slave_write,
|
|
avalon_slave_writedata => avalon_slave_writedata,
|
|
avalon_slave_read => avalon_slave_read,
|
|
avalon_slave_readdata => avalon_slave_readdata,
|
|
avalon_master_waitreq => avalon_master_waitreq,
|
|
avalon_master_readdata => avalon_master_readdata,
|
|
avalon_master_readdatavalid => avalon_master_readdatavalid,
|
|
avalon_master_read => avalon_master_read
|
|
);
|
|
|
|
-- Clocking process
|
|
clk_generation : process
|
|
begin
|
|
clk <= not clk;
|
|
wait for CLK_PERIOD / 2;
|
|
end process;
|
|
|
|
-- Testbench
|
|
tb : process
|
|
begin
|
|
avalon_slave_address <= "0011";
|
|
avalon_slave_write <= '0';
|
|
avalon_slave_writedata <= (others => 'Z');
|
|
|
|
-- Dummy signals from bus
|
|
avalon_master_readdata <= X"12341234";
|
|
avalon_master_readdatavalid <= '0';
|
|
avalon_master_waitreq <= '1';
|
|
|
|
-- Reset
|
|
rst_n <= '0';
|
|
wait for CLK_PERIOD * 2.5;
|
|
rst_n <= '1';
|
|
wait for CLK_PERIOD * 2;
|
|
|
|
-- Initiate CMD cycle
|
|
avalon_slave_address <= "0000";
|
|
wait until rising_edge(clk);
|
|
avalon_slave_writedata <= (27 downto 0 => '0') & "1000";
|
|
avalon_slave_write <= '1';
|
|
wait until rising_edge(clk);
|
|
avalon_slave_write <= '0';
|
|
wait for CLK_PERIOD * 20;
|
|
|
|
avalon_slave_address <= "0001";
|
|
wait until rising_edge(clk);
|
|
avalon_slave_writedata <= (27 downto 0 => '0') & "1111";
|
|
avalon_slave_write <= '1';
|
|
wait until rising_edge(clk);
|
|
avalon_slave_write <= '0';
|
|
wait for CLK_PERIOD * 20;
|
|
|
|
-- Loop refreshing
|
|
loop
|
|
wait for CLK_PERIOD * 50;
|
|
|
|
-- Initiate a refresh cycle
|
|
avalon_slave_address <= "0011";
|
|
wait until rising_edge(clk);
|
|
avalon_slave_write <= '1';
|
|
wait until rising_edge(clk);
|
|
avalon_slave_write <= '0';
|
|
|
|
-- Wait until bus grant
|
|
wait for CLK_PERIOD * 3;
|
|
avalon_master_waitreq <= '0';
|
|
wait for CLK_PERIOD;
|
|
|
|
-- Emulate that new read data is valid each cycle of the burst
|
|
avalon_master_readdatavalid <= '1';
|
|
for i in 0 to 15 loop
|
|
avalon_master_readdata <= std_logic_vector(to_unsigned(i*2 + ((i*2+1)*2**16), avalon_master_readdata'length));
|
|
wait for CLK_PERIOD;
|
|
end loop;
|
|
-- burst finished
|
|
avalon_master_readdatavalid <= '0';
|
|
|
|
loop
|
|
-- Wait until the previous 16 words have been shifted to LCD and new pixels
|
|
-- are requested
|
|
wait until avalon_master_read = '1' or irq = '1';
|
|
exit when irq = '1';
|
|
|
|
-- Wait some time for bus grant...
|
|
wait for CLK_PERIOD * 3;
|
|
|
|
-- Start providing some data
|
|
avalon_master_readdatavalid <= '1';
|
|
for i in 0 to 15 loop
|
|
avalon_master_readdata <= std_logic_vector(to_unsigned(i*2 + ((i*2+1)*2**16), avalon_master_readdata'length));
|
|
wait for CLK_PERIOD;
|
|
end loop;
|
|
avalon_master_readdatavalid <= '0';
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
end process;
|
|
|
|
end; |