108 lines
2.8 KiB
VHDL
108 lines
2.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity LCDAvalonMaster_tb is
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end LCDAvalonMaster_tb;
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architecture test of LCDAvalonMaster_tb is
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constant CLK_PERIOD : time := 20 ns;
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constant N_LED_MAX : integer := 255;
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-- 20 = 1 full burst + 1 non full burst
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constant NWORDS : natural := 20;
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constant NWORDS_MAX :natural := (320*240)/2;
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signal clk : std_logic := '0';
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signal rst_n : std_logic;
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signal waitreq, readdatavalid, refresh, fifo_almost_empty : std_logic;
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signal readdata : std_logic_vector(31 downto 0);
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signal baseaddress : std_logic_vector(31 downto 0);
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signal nwords_sig : std_logic_vector(integer(floor(log2(real(NWORDS_MAX)))) downto 0);
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begin
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nwords_sig <= std_logic_vector(to_unsigned(NWORDS, nwords_sig'length));
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-- Instantiate DUT
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dut : entity work.LCDAvalonMaster
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generic map (
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NWORDS_MAX => NWORDS_MAX
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)
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port map(
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clk => clk,
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rst_n => rst_n,
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waitreq => waitreq,
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readdatavalid => readdatavalid,
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refresh => refresh,
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fifo_almost_empty => fifo_almost_empty,
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readdata => readdata,
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baseaddress => baseaddress,
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nwords => nwords_sig
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);
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-- Clocking process
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clk_generation : process
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begin
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clk <= not clk;
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wait for CLK_PERIOD / 2;
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end process;
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-- Testbench
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tb : process
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begin
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while true loop
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-- Dummy signals from bus
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readdata <= X"12341234";
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readdatavalid <= '0';
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waitreq <= '1';
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baseaddress <= X"10000000";
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fifo_almost_empty <= '0';
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-- Reset
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rst_n <= '0';
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wait for CLK_PERIOD * 2.5;
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rst_n <= '1';
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wait for CLK_PERIOD * 2;
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-- Initiate a refresh cycle
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wait until rising_edge(clk);
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refresh <= '1';
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wait for CLK_PERIOD;
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refresh <= '0';
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-- Wait until bus grant
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wait for CLK_PERIOD * 3;
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waitreq <= '0';
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wait for CLK_PERIOD;
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-- Emulate that new read data is valid each cycle of the burst
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readdatavalid <= '1';
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for i in 1 to 16 loop
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wait for CLK_PERIOD;
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end loop;
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readdatavalid <= '0';
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wait for CLK_PERIOD * 5;
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-- Assert fifo_almost empty; should repromt another transfer
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fifo_almost_empty <= '1';
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wait for CLK_period;
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fifo_almost_empty <= '0';
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wait for CLK_PERIOD * 2;
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readdatavalid <= '1';
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for i in 1 to 16 loop
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wait for CLK_PERIOD;
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end loop;
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-- Test finished
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wait for CLK_PERIOD * 5;
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end loop;
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end process;
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end; |