194 lines
5.2 KiB
VHDL
Executable File
194 lines
5.2 KiB
VHDL
Executable File
-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, the Altera Quartus Prime License Agreement,
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-- the Altera MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Altera and sold by Altera or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-- PROGRAM "Quartus Prime"
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-- VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition"
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-- CREATED "Tue Oct 03 14:49:59 2017"
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY work;
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ENTITY GECKO IS
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PORT
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(
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clk : IN STD_LOGIC;
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reset_n : IN STD_LOGIC;
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in_buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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row1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
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row2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
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row3 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
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row4 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
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row5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
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row6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
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row7 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
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row8 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
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);
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END GECKO;
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ARCHITECTURE bdf_type OF GECKO IS
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COMPONENT buttons
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PORT(clk : IN STD_LOGIC;
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reset_n : IN STD_LOGIC;
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cs : IN STD_LOGIC;
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read : IN STD_LOGIC;
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write : IN STD_LOGIC;
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address : IN STD_LOGIC;
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buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT decoder
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PORT(address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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cs_RAM : OUT STD_LOGIC;
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cs_ROM : OUT STD_LOGIC;
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cs_Buttons : OUT STD_LOGIC;
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cs_LEDs : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT cpu
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PORT(clk : IN STD_LOGIC;
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reset_n : IN STD_LOGIC;
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rddata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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write : OUT STD_LOGIC;
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read : OUT STD_LOGIC;
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address : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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wrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT leds
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PORT(clk : IN STD_LOGIC;
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reset_n : IN STD_LOGIC;
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cs : IN STD_LOGIC;
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write : IN STD_LOGIC;
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read : IN STD_LOGIC;
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address : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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LEDs : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
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rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT ram
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PORT(clk : IN STD_LOGIC;
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cs : IN STD_LOGIC;
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write : IN STD_LOGIC;
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read : IN STD_LOGIC;
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address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT rom
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PORT(clk : IN STD_LOGIC;
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cs : IN STD_LOGIC;
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read : IN STD_LOGIC;
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address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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SIGNAL address : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL cs_Buttons : STD_LOGIC;
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SIGNAL cs_LEDs : STD_LOGIC;
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SIGNAL cs_RAM : STD_LOGIC;
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SIGNAL cs_ROM : STD_LOGIC;
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SIGNAL out_LEDs : STD_LOGIC_VECTOR(95 DOWNTO 0);
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SIGNAL rddata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL wrdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
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BEGIN
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b2v_buttons_0 : buttons
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PORT MAP(clk => clk,
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reset_n => reset_n,
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cs => cs_Buttons,
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read => SYNTHESIZED_WIRE_7,
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write => SYNTHESIZED_WIRE_8,
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address => address(2),
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buttons => in_buttons,
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wrdata => wrdata,
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rddata => rddata);
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b2v_decoder_0 : decoder
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PORT MAP(address => address,
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cs_RAM => cs_RAM,
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cs_ROM => cs_ROM,
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cs_Buttons => cs_Buttons,
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cs_LEDs => cs_LEDs);
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b2v_inst : cpu
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PORT MAP(clk => clk,
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reset_n => reset_n,
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rddata => rddata,
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write => SYNTHESIZED_WIRE_8,
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read => SYNTHESIZED_WIRE_7,
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address => address,
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wrdata => wrdata);
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b2v_LEDs_0 : leds
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PORT MAP(clk => clk,
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reset_n => reset_n,
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cs => cs_LEDs,
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write => SYNTHESIZED_WIRE_8,
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read => SYNTHESIZED_WIRE_7,
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address => address(3 DOWNTO 2),
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wrdata => wrdata,
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LEDs => out_LEDs,
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rddata => rddata);
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b2v_RAM_0 : ram
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PORT MAP(clk => clk,
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cs => cs_RAM,
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write => SYNTHESIZED_WIRE_8,
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read => SYNTHESIZED_WIRE_7,
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address => address(11 DOWNTO 2),
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wrdata => wrdata,
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rddata => rddata);
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b2v_ROM_0 : rom
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PORT MAP(clk => clk,
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cs => cs_ROM,
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read => SYNTHESIZED_WIRE_7,
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address => address(11 DOWNTO 2),
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rddata => rddata);
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row1(11 DOWNTO 0) <= out_LEDs(11 DOWNTO 0);
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row2(11 DOWNTO 0) <= out_LEDs(23 DOWNTO 12);
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row3(11 DOWNTO 0) <= out_LEDs(35 DOWNTO 24);
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row4(11 DOWNTO 0) <= out_LEDs(47 DOWNTO 36);
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row5(11 DOWNTO 0) <= out_LEDs(59 DOWNTO 48);
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row6(11 DOWNTO 0) <= out_LEDs(71 DOWNTO 60);
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row7(11 DOWNTO 0) <= out_LEDs(83 DOWNTO 72);
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row8(11 DOWNTO 0) <= out_LEDs(95 DOWNTO 84);
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END bdf_type; |