39 lines
1.3 KiB
VHDL
Executable File
39 lines
1.3 KiB
VHDL
Executable File
-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- PROGRAM "Quartus II 32-bit"
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-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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-- CREATED "Wed Oct 30 17:22:54 2013"
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY work;
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PORT
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(
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reset_n : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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rddata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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write : OUT STD_LOGIC;
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read : OUT STD_LOGIC;
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address : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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wrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END CPU;
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ARCHITECTURE bdf_type OF CPU IS
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BEGIN
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END bdf_type; |