54 lines
1.3 KiB
VHDL
Executable File
54 lines
1.3 KiB
VHDL
Executable File
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity PC is
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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en : in std_logic;
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sel_a : in std_logic;
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sel_imm : in std_logic;
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add_imm : in std_logic;
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imm : in std_logic_vector(15 downto 0);
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a : in std_logic_vector(15 downto 0);
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addr : out std_logic_vector(31 downto 0)
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);
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end PC;
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architecture synth of PC is
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signal s_addr : std_logic_vector(31 downto 0);
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signal n_addr : std_logic_vector(31 downto 0);
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begin
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inc_address : process(clk, reset_n, s_addr) is
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begin
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if (reset_n = '0') then
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n_addr <= (others => '0');
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elsif (rising_edge(clk)) then
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if (en = '1') then
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if (add_imm = '1') then
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n_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(s_addr)) + to_integer(signed(imm)),32));
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else
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n_addr <= std_logic_vector(unsigned(s_addr) + 4);
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end if;
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if(sel_imm = '1') then
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n_addr <= (15 downto 0 => '0') & imm(13 downto 0) & "00";
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elsif(sel_a = '1') then
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n_addr <= ((15 downto 0 => '0') & a);
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end if;
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end if;
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n_addr(1 downto 0) <= "00";
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end if;
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end process;
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s_addr <= n_addr;
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addr <= (15 downto 0 => '0') & s_addr(15 downto 0);
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end synth;
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