83 lines
56 KiB
Plaintext
Executable File
83 lines
56 KiB
Plaintext
Executable File
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1540375575649 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1540375575649 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 24 12:06:15 2018 " "Processing started: Wed Oct 24 12:06:15 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1540375575649 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375575649 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GECKO -c GECKO " "Command: quartus_map --read_settings_files=on --write_settings_files=off GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375575649 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1540375576961 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1540375576961 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gecko.bdf 1 1 " "Found 1 design units, including 1 entities, in source file gecko.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 GECKO " "Found entity 1: GECKO" { } { { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375587867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375587867 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.bdf 1 1 " "Found 1 design units, including 1 entities, in source file alu.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Found entity 1: ALU" { } { { "ALU.bdf" "" { Schematic "E:/cs208/quartus/ALU.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375587867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375587867 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.bdf 1 1 " "Found 1 design units, including 1 entities, in source file cpu.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CPU " "Found entity 1: CPU" { } { { "CPU.bdf" "" { Schematic "E:/cs208/quartus/CPU.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375587867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375587867 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/add_sub.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/add_sub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add_sub-synth " "Found design unit 1: add_sub-synth" { } { { "../vhdl/add_sub.vhd" "" { Text "E:/cs208/vhdl/add_sub.vhd" 16 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588429 ""} { "Info" "ISGN_ENTITY_NAME" "1 add_sub " "Found entity 1: add_sub" { } { { "../vhdl/add_sub.vhd" "" { Text "E:/cs208/vhdl/add_sub.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588429 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588429 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/buttons.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/buttons.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 buttons-synth " "Found design unit 1: buttons-synth" { } { { "../vhdl/buttons.vhd" "" { Text "E:/cs208/vhdl/buttons.vhd" 22 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588461 ""} { "Info" "ISGN_ENTITY_NAME" "1 buttons " "Found entity 1: buttons" { } { { "../vhdl/buttons.vhd" "" { Text "E:/cs208/vhdl/buttons.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588461 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/comparator.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/comparator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 comparator-synth " "Found design unit 1: comparator-synth" { } { { "../vhdl/comparator.vhd" "" { Text "E:/cs208/vhdl/comparator.vhd" 16 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588461 ""} { "Info" "ISGN_ENTITY_NAME" "1 comparator " "Found entity 1: comparator" { } { { "../vhdl/comparator.vhd" "" { Text "E:/cs208/vhdl/comparator.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588461 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/controller.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 controller-synth " "Found design unit 1: controller-synth" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 39 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588476 ""} { "Info" "ISGN_ENTITY_NAME" "1 controller " "Found entity 1: controller" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588476 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/decoder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-synth " "Found design unit 1: decoder-synth" { } { { "../vhdl/decoder.vhd" "" { Text "E:/cs208/vhdl/decoder.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588476 ""} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Found entity 1: decoder" { } { { "../vhdl/decoder.vhd" "" { Text "E:/cs208/vhdl/decoder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588476 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/extend.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/extend.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 extend-synth " "Found design unit 1: extend-synth" { } { { "../vhdl/extend.vhd" "" { Text "E:/cs208/vhdl/extend.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588492 ""} { "Info" "ISGN_ENTITY_NAME" "1 extend " "Found entity 1: extend" { } { { "../vhdl/extend.vhd" "" { Text "E:/cs208/vhdl/extend.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588492 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588492 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/ir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/ir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 IR-synth " "Found design unit 1: IR-synth" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588617 ""} { "Info" "ISGN_ENTITY_NAME" "1 IR " "Found entity 1: IR" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588617 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588617 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/leds.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/leds.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LEDs-synth " "Found design unit 1: LEDs-synth" { } { { "../vhdl/LEDs.vhd" "" { Text "E:/cs208/vhdl/LEDs.vhd" 22 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588617 ""} { "Info" "ISGN_ENTITY_NAME" "1 LEDs " "Found entity 1: LEDs" { } { { "../vhdl/LEDs.vhd" "" { Text "E:/cs208/vhdl/LEDs.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588617 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588617 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/logic_unit.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/logic_unit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 logic_unit-synth " "Found design unit 1: logic_unit-synth" { } { { "../vhdl/logic_unit.vhd" "" { Text "E:/cs208/vhdl/logic_unit.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588632 ""} { "Info" "ISGN_ENTITY_NAME" "1 logic_unit " "Found entity 1: logic_unit" { } { { "../vhdl/logic_unit.vhd" "" { Text "E:/cs208/vhdl/logic_unit.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588632 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/multiplexer.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/multiplexer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 multiplexer-synth " "Found design unit 1: multiplexer-synth" { } { { "../vhdl/multiplexer.vhd" "" { Text "E:/cs208/vhdl/multiplexer.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588632 ""} { "Info" "ISGN_ENTITY_NAME" "1 multiplexer " "Found entity 1: multiplexer" { } { { "../vhdl/multiplexer.vhd" "" { Text "E:/cs208/vhdl/multiplexer.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588632 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/mux2x5.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux2x5-synth " "Found design unit 1: mux2x5-synth" { } { { "../vhdl/mux2x5.vhd" "" { Text "E:/cs208/vhdl/mux2x5.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588648 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux2x5 " "Found entity 1: mux2x5" { } { { "../vhdl/mux2x5.vhd" "" { Text "E:/cs208/vhdl/mux2x5.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588648 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588648 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/mux2x16.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux2x16-synth " "Found design unit 1: mux2x16-synth" { } { { "../vhdl/mux2x16.vhd" "" { Text "E:/cs208/vhdl/mux2x16.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588773 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux2x16 " "Found entity 1: mux2x16" { } { { "../vhdl/mux2x16.vhd" "" { Text "E:/cs208/vhdl/mux2x16.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588773 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588773 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/mux2x32.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x32.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux2x32-synth " "Found design unit 1: mux2x32-synth" { } { { "../vhdl/mux2x32.vhd" "" { Text "E:/cs208/vhdl/mux2x32.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588773 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux2x32 " "Found entity 1: mux2x32" { } { { "../vhdl/mux2x32.vhd" "" { Text "E:/cs208/vhdl/mux2x32.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588773 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588773 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/pc.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/pc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PC-synth " "Found design unit 1: PC-synth" { } { { "../vhdl/PC.vhd" "" { Text "E:/cs208/vhdl/PC.vhd" 19 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588789 ""} { "Info" "ISGN_ENTITY_NAME" "1 PC " "Found entity 1: PC" { } { { "../vhdl/PC.vhd" "" { Text "E:/cs208/vhdl/PC.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588789 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588789 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/ram.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RAM-synth " "Found design unit 1: RAM-synth" { } { { "../vhdl/RAM.vhd" "" { Text "E:/cs208/vhdl/RAM.vhd" 16 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588789 ""} { "Info" "ISGN_ENTITY_NAME" "1 RAM " "Found entity 1: RAM" { } { { "../vhdl/RAM.vhd" "" { Text "E:/cs208/vhdl/RAM.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588789 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588789 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/register_file.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/register_file.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 register_file-synth " "Found design unit 1: register_file-synth" { } { { "../vhdl/register_file.vhd" "" { Text "E:/cs208/vhdl/register_file.vhd" 18 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588804 ""} { "Info" "ISGN_ENTITY_NAME" "1 register_file " "Found entity 1: register_file" { } { { "../vhdl/register_file.vhd" "" { Text "E:/cs208/vhdl/register_file.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588804 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/rom.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ROM-synth " "Found design unit 1: ROM-synth" { } { { "../vhdl/ROM.vhd" "" { Text "E:/cs208/vhdl/ROM.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588820 ""} { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" { } { { "../vhdl/ROM.vhd" "" { Text "E:/cs208/vhdl/ROM.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588820 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588820 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/rom_block.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/rom_block.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom_block-SYN " "Found design unit 1: rom_block-SYN" { } { { "../vhdl/ROM_Block.vhd" "" { Text "E:/cs208/vhdl/ROM_Block.vhd" 52 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588867 ""} { "Info" "ISGN_ENTITY_NAME" "1 ROM_Block " "Found entity 1: ROM_Block" { } { { "../vhdl/ROM_Block.vhd" "" { Text "E:/cs208/vhdl/ROM_Block.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588867 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/shift_unit.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/shift_unit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shift_unit-synth " "Found design unit 1: shift_unit-synth" { } { { "../vhdl/shift_unit.vhd" "" { Text "E:/cs208/vhdl/shift_unit.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588867 ""} { "Info" "ISGN_ENTITY_NAME" "1 shift_unit " "Found entity 1: shift_unit" { } { { "../vhdl/shift_unit.vhd" "" { Text "E:/cs208/vhdl/shift_unit.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375588867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375588867 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "GECKO " "Elaborating entity \"GECKO\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1540375589476 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LEDs LEDs:LEDs_0 " "Elaborating entity \"LEDs\" for hierarchy \"LEDs:LEDs_0\"" { } { { "GECKO.bdf" "LEDs_0" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 160 1040 1176 336 "LEDs_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589492 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:decoder_0 " "Elaborating entity \"decoder\" for hierarchy \"decoder:decoder_0\"" { } { { "GECKO.bdf" "decoder_0" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 96 408 544 232 "decoder_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589695 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CPU CPU:inst " "Elaborating entity \"CPU\" for hierarchy \"CPU:inst\"" { } { { "GECKO.bdf" "inst" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589695 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "controller CPU:inst\|controller:controller_0 " "Elaborating entity \"controller\" for hierarchy \"CPU:inst\|controller:controller_0\"" { } { { "CPU.bdf" "controller_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { -208 240 400 112 "controller_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589710 ""}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.RI_OP controller.vhd(58) " "Inferred latch for \"s_next.RI_OP\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589882 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.UI_OP controller.vhd(58) " "Inferred latch for \"s_next.UI_OP\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.JMPI controller.vhd(58) " "Inferred latch for \"s_next.JMPI\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.JMP controller.vhd(58) " "Inferred latch for \"s_next.JMP\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.CALLR controller.vhd(58) " "Inferred latch for \"s_next.CALLR\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.CALL controller.vhd(58) " "Inferred latch for \"s_next.CALL\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.BRANCH controller.vhd(58) " "Inferred latch for \"s_next.BRANCH\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.LOAD2 controller.vhd(58) " "Inferred latch for \"s_next.LOAD2\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.I_OP controller.vhd(58) " "Inferred latch for \"s_next.I_OP\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.LOAD1 controller.vhd(58) " "Inferred latch for \"s_next.LOAD1\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.BREAK controller.vhd(58) " "Inferred latch for \"s_next.BREAK\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.STORE controller.vhd(58) " "Inferred latch for \"s_next.STORE\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.R_OP controller.vhd(58) " "Inferred latch for \"s_next.R_OP\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.DECODE controller.vhd(58) " "Inferred latch for \"s_next.DECODE\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.FETCH2 controller.vhd(58) " "Inferred latch for \"s_next.FETCH2\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.FETCH1 controller.vhd(58) " "Inferred latch for \"s_next.FETCH1\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 "|GECKO|CPU:inst|controller:controller_0"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "IR CPU:inst\|IR:IR_0 " "Elaborating entity \"IR\" for hierarchy \"CPU:inst\|IR:IR_0\"" { } { { "CPU.bdf" "IR_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { 88 24 136 184 "IR_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux2x16 CPU:inst\|mux2x16:mux_addr " "Elaborating entity \"mux2x16\" for hierarchy \"CPU:inst\|mux2x16:mux_addr\"" { } { { "CPU.bdf" "mux_addr" { Schematic "E:/cs208/quartus/CPU.bdf" { { -40 1088 1144 56 "mux_addr" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589898 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PC CPU:inst\|PC:PC_0 " "Elaborating entity \"PC\" for hierarchy \"CPU:inst\|PC:PC_0\"" { } { { "CPU.bdf" "PC_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { -184 808 968 -8 "PC_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589914 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALU CPU:inst\|ALU:alu_0 " "Elaborating entity \"ALU\" for hierarchy \"CPU:inst\|ALU:alu_0\"" { } { { "CPU.bdf" "alu_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { 120 904 992 232 "alu_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589914 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multiplexer CPU:inst\|ALU:alu_0\|multiplexer:multiplexer_0 " "Elaborating entity \"multiplexer\" for hierarchy \"CPU:inst\|ALU:alu_0\|multiplexer:multiplexer_0\"" { } { { "ALU.bdf" "multiplexer_0" { Schematic "E:/cs208/quartus/ALU.bdf" { { -168 544 648 -32 "multiplexer_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589914 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub CPU:inst\|ALU:alu_0\|add_sub:add_sub_0 " "Elaborating entity \"add_sub\" for hierarchy \"CPU:inst\|ALU:alu_0\|add_sub:add_sub_0\"" { } { { "ALU.bdf" "add_sub_0" { Schematic "E:/cs208/quartus/ALU.bdf" { { -168 160 416 -72 "add_sub_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589929 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "comparator CPU:inst\|ALU:alu_0\|comparator:comparator_0 " "Elaborating entity \"comparator\" for hierarchy \"CPU:inst\|ALU:alu_0\|comparator:comparator_0\"" { } { { "ALU.bdf" "comparator_0" { Schematic "E:/cs208/quartus/ALU.bdf" { { -40 160 416 64 "comparator_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375589929 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "logic_unit CPU:inst\|ALU:alu_0\|logic_unit:logic_unit_0 " "Elaborating entity \"logic_unit\" for hierarchy \"CPU:inst\|ALU:alu_0\|logic_unit:logic_unit_0\"" { } { { "ALU.bdf" "logic_unit_0" { Schematic "E:/cs208/quartus/ALU.bdf" { { 80 160 416 176 "logic_unit_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590007 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_unit CPU:inst\|ALU:alu_0\|shift_unit:shift_unit_0 " "Elaborating entity \"shift_unit\" for hierarchy \"CPU:inst\|ALU:alu_0\|shift_unit:shift_unit_0\"" { } { { "ALU.bdf" "shift_unit_0" { Schematic "E:/cs208/quartus/ALU.bdf" { { 192 160 416 288 "shift_unit_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590023 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file CPU:inst\|register_file:register_file_0 " "Elaborating entity \"register_file\" for hierarchy \"CPU:inst\|register_file:register_file_0\"" { } { { "CPU.bdf" "register_file_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { 120 600 752 264 "register_file_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590039 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux2x5 CPU:inst\|mux2x5:mux_aw " "Elaborating entity \"mux2x5\" for hierarchy \"CPU:inst\|mux2x5:mux_aw\"" { } { { "CPU.bdf" "mux_aw" { Schematic "E:/cs208/quartus/CPU.bdf" { { 152 440 496 248 "mux_aw" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590179 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux2x32 CPU:inst\|mux2x32:mux_data " "Elaborating entity \"mux2x32\" for hierarchy \"CPU:inst\|mux2x32:mux_data\"" { } { { "CPU.bdf" "mux_data" { Schematic "E:/cs208/quartus/CPU.bdf" { { 144 1136 1192 240 "mux_data" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590179 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "extend CPU:inst\|extend:extend_0 " "Elaborating entity \"extend\" for hierarchy \"CPU:inst\|extend:extend_0\"" { } { { "CPU.bdf" "extend_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { 24 568 752 104 "extend_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590195 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:ROM_0 " "Elaborating entity \"ROM\" for hierarchy \"ROM:ROM_0\"" { } { { "GECKO.bdf" "ROM_0" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 176 616 736 296 "ROM_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590195 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM_Block ROM:ROM_0\|ROM_Block:romblock " "Elaborating entity \"ROM_Block\" for hierarchy \"ROM:ROM_0\|ROM_Block:romblock\"" { } { { "../vhdl/ROM.vhd" "romblock" { Text "E:/cs208/vhdl/ROM.vhd" 33 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590335 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component\"" { } { { "../vhdl/ROM_Block.vhd" "altsyncram_component" { Text "E:/cs208/vhdl/ROM_Block.vhd" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590554 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component\"" { } { { "../vhdl/ROM_Block.vhd" "" { Text "E:/cs208/vhdl/ROM_Block.vhd" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590554 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component " "Instantiated megafunction \"ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ../quartus/ROM.hex " "Parameter \"init_file\" = \"../quartus/ROM.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375590585 ""} } { { "../vhdl/ROM_Block.vhd" "" { Text "E:/cs208/vhdl/ROM_Block.vhd" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1540375590585 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rna1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_rna1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rna1 " "Found entity 1: altsyncram_rna1" { } { { "db/altsyncram_rna1.tdf" "" { Text "E:/cs208/quartus/db/altsyncram_rna1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375590695 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375590695 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_rna1 ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component\|altsyncram_rna1:auto_generated " "Elaborating entity \"altsyncram_rna1\" for hierarchy \"ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component\|altsyncram_rna1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590695 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM RAM:RAM_0 " "Elaborating entity \"RAM\" for hierarchy \"RAM:RAM_0\"" { } { { "GECKO.bdf" "RAM_0" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 176 816 960 296 "RAM_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590820 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "buttons buttons:buttons_0 " "Elaborating entity \"buttons\" for hierarchy \"buttons:buttons_0\"" { } { { "GECKO.bdf" "buttons_0" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 160 1248 1384 336 "buttons_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375590820 ""}
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{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[31\]\" " "Converted tri-state node \"rddata\[31\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[30\]\" " "Converted tri-state node \"rddata\[30\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[29\]\" " "Converted tri-state node \"rddata\[29\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[28\]\" " "Converted tri-state node \"rddata\[28\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[27\]\" " "Converted tri-state node \"rddata\[27\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[26\]\" " "Converted tri-state node \"rddata\[26\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[25\]\" " "Converted tri-state node \"rddata\[25\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[24\]\" " "Converted tri-state node \"rddata\[24\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[23\]\" " "Converted tri-state node \"rddata\[23\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[22\]\" " "Converted tri-state node \"rddata\[22\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[21\]\" " "Converted tri-state node \"rddata\[21\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[20\]\" " "Converted tri-state node \"rddata\[20\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[19\]\" " "Converted tri-state node \"rddata\[19\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[18\]\" " "Converted tri-state node \"rddata\[18\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[17\]\" " "Converted tri-state node \"rddata\[17\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[16\]\" " "Converted tri-state node \"rddata\[16\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[15\]\" " "Converted tri-state node \"rddata\[15\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[14\]\" " "Converted tri-state node \"rddata\[14\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[13\]\" " "Converted tri-state node \"rddata\[13\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[12\]\" " "Converted tri-state node \"rddata\[12\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[11\]\" " "Converted tri-state node \"rddata\[11\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[10\]\" " "Converted tri-state node \"rddata\[10\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[9\]\" " "Converted tri-state node \"rddata\[9\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[8\]\" " "Converted tri-state node \"rddata\[8\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[7\]\" " "Converted tri-state node \"rddata\[7\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[6\]\" " "Converted tri-state node \"rddata\[6\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[5\]\" " "Converted tri-state node \"rddata\[5\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[4\]\" " "Converted tri-state node \"rddata\[4\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[3\]\" " "Converted tri-state node \"rddata\[3\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[2\]\" " "Converted tri-state node \"rddata\[2\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[1\]\" " "Converted tri-state node \"rddata\[1\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[0\]\" " "Converted tri-state node \"rddata\[0\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540375592132 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Analysis & Synthesis" 0 -1 1540375592132 ""}
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{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "RAM:RAM_0\|reg_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"RAM:RAM_0\|reg_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE SINGLE_PORT " "Parameter OPERATION_MODE set to SINGLE_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540375595335 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 32 " "Parameter WIDTH_A set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540375595335 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 10 " "Parameter WIDTHAD_A set to 10" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540375595335 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 1024 " "Parameter NUMWORDS_A set to 1024" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540375595335 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Parameter OUTDATA_REG_A set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540375595335 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540375595335 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Parameter OUTDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540375595335 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540375595335 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540375595335 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/GECKO.ram0_RAM_15119.hdl.mif " "Parameter INIT_FILE set to db/GECKO.ram0_RAM_15119.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540375595335 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1540375595335 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1540375595335 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "RAM:RAM_0\|altsyncram:reg_rtl_0 " "Elaborated megafunction instantiation \"RAM:RAM_0\|altsyncram:reg_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375595398 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "RAM:RAM_0\|altsyncram:reg_rtl_0 " "Instantiated megafunction \"RAM:RAM_0\|altsyncram:reg_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE SINGLE_PORT " "Parameter \"OPERATION_MODE\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375595398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 32 " "Parameter \"WIDTH_A\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375595398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 10 " "Parameter \"WIDTHAD_A\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375595398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 1024 " "Parameter \"NUMWORDS_A\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375595398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375595398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375595398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375595398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375595398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375595398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/GECKO.ram0_RAM_15119.hdl.mif " "Parameter \"INIT_FILE\" = \"db/GECKO.ram0_RAM_15119.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540375595398 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1540375595398 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u781.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_u781.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u781 " "Found entity 1: altsyncram_u781" { } { { "db/altsyncram_u781.tdf" "" { Text "E:/cs208/quartus/db/altsyncram_u781.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540375595507 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375595507 ""}
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{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "../vhdl/LEDs.vhd" "" { Text "E:/cs208/vhdl/LEDs.vhd" 90 -1 0 } } { "../vhdl/buttons.vhd" "" { Text "E:/cs208/vhdl/buttons.vhd" 37 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1540375596366 ""}
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{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1540375596366 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1540375598659 ""}
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{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "17 " "17 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1540375602690 ""}
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1540375603346 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540375603346 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "3816 " "Implemented 3816 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1540375603721 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1540375603721 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3650 " "Implemented 3650 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1540375603721 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1540375603721 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1540375603721 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 34 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 34 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4843 " "Peak virtual memory: 4843 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1540375603831 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 24 12:06:43 2018 " "Processing ended: Wed Oct 24 12:06:43 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1540375603831 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1540375603831 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1540375603831 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1540375603831 ""}
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