892 lines
90 KiB
Plaintext
Executable File
892 lines
90 KiB
Plaintext
Executable File
Analysis & Synthesis report for GECKO
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Wed Oct 24 12:06:43 2018
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Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Source Files Read
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6. Analysis & Synthesis Resource Usage Summary
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7. Analysis & Synthesis Resource Utilization by Entity
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8. Analysis & Synthesis RAM Summary
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9. State Machine - |GECKO|CPU:inst|controller:controller_0|s_cur
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10. User-Specified and Inferred Latches
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11. Registers Removed During Synthesis
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12. Removed Registers Triggering Further Register Optimizations
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13. General Register Statistics
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14. Inverted Register Statistics
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15. Registers Packed Into Inferred Megafunctions
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16. Multiplexer Restructuring Statistics (Restructuring Performed)
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17. Source assignments for ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated
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18. Source assignments for RAM:RAM_0|altsyncram:reg_rtl_0|altsyncram_u781:auto_generated
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19. Parameter Settings for User Entity Instance: ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component
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20. Parameter Settings for Inferred Entity Instance: RAM:RAM_0|altsyncram:reg_rtl_0
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21. altsyncram Parameter Settings by Entity Instance
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22. Post-Synthesis Netlist Statistics for Top Partition
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23. Elapsed Time Per Partition
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24. Analysis & Synthesis Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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+----------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+------------------------------------+---------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Wed Oct 24 12:06:43 2018 ;
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; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Lite Edition ;
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; Revision Name ; GECKO ;
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; Top-level Entity Name ; GECKO ;
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; Family ; Cyclone IV E ;
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; Total logic elements ; 3,537 ;
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; Total combinational functions ; 2,508 ;
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; Dedicated logic registers ; 1,180 ;
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; Total registers ; 1180 ;
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; Total pins ; 102 ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 65,536 ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; Total PLLs ; 0 ;
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+------------------------------------+---------------------------------------------+
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+------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+------------------------------------------------------------------+--------------------+--------------------+
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; Option ; Setting ; Default Value ;
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+------------------------------------------------------------------+--------------------+--------------------+
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; Device ; EP4CE30F23C8 ; ;
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; Top-level entity name ; GECKO ; GECKO ;
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; Family name ; Cyclone IV E ; Cyclone V ;
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; Use smart compilation ; On ; Off ;
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; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Restructure Multiplexers ; Auto ; Auto ;
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
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; Preserve fewer node names ; On ; On ;
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; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
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; State Machine Processing ; Auto ; Auto ;
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; Safe State Machine ; Off ; Off ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; Ignore Verilog initial constructs ; Off ; Off ;
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
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; Infer RAMs from Raw Logic ; On ; On ;
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; Parallel Synthesis ; On ; On ;
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; DSP Block Balancing ; Auto ; Auto ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Redundant Logic Cells ; Off ; Off ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore LCELL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; On ; On ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique ; Balanced ; Balanced ;
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; Carry Chain Length ; 70 ; 70 ;
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; Auto Carry Chains ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
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; Auto ROM Replacement ; On ; On ;
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; Auto RAM Replacement ; On ; On ;
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; Auto DSP Block Replacement ; On ; On ;
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; Auto Shift Register Replacement ; Auto ; Auto ;
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; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
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; Auto Clock Enable Replacement ; On ; On ;
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; Strict RAM Replacement ; Off ; Off ;
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; Allow Synchronous Control Signals ; On ; On ;
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; Force Use of Synchronous Clear Signals ; Off ; Off ;
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; Auto RAM Block Balancing ; On ; On ;
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; Auto RAM to Logic Cell Conversion ; Off ; Off ;
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; Auto Resource Sharing ; Off ; Off ;
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; Allow Any RAM Size For Recognition ; Off ; Off ;
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; Allow Any ROM Size For Recognition ; Off ; Off ;
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; Allow Any Shift Register Size For Recognition ; Off ; Off ;
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; Use LogicLock Constraints during Resource Balancing ; On ; On ;
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; Ignore translate_off and synthesis_off directives ; Off ; Off ;
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; Timing-Driven Synthesis ; On ; On ;
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; Report Parameter Settings ; On ; On ;
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; Report Source Assignments ; On ; On ;
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; Report Connectivity Checks ; On ; On ;
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; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
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; Synchronization Register Chain Length ; 2 ; 2 ;
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; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
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; HDL message level ; Level2 ; Level2 ;
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; Suppress Register Optimization Related Messages ; Off ; Off ;
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; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
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; Clock MUX Protection ; On ; On ;
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; Auto Gated Clock Conversion ; Off ; Off ;
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; Block Design Naming ; Auto ; Auto ;
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; SDC constraint protection ; Off ; Off ;
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; Synthesis Effort ; Auto ; Auto ;
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; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
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; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
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; Analysis & Synthesis Message Level ; Medium ; Medium ;
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; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
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; Resource Aware Inference For Block RAM ; On ; On ;
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+------------------------------------------------------------------+--------------------+--------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 8 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 4 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 0.1% ;
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; Processor 3 ; 0.0% ;
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; Processor 4 ; 0.0% ;
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+----------------------------+-------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Source Files Read ;
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+----------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------+---------+
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; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
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+----------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------+---------+
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; GECKO.bdf ; yes ; User Block Diagram/Schematic File ; E:/cs208/quartus/GECKO.bdf ; ;
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; ALU.bdf ; yes ; User Block Diagram/Schematic File ; E:/cs208/quartus/ALU.bdf ; ;
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; CPU.bdf ; yes ; User Block Diagram/Schematic File ; E:/cs208/quartus/CPU.bdf ; ;
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; ../vhdl/add_sub.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/add_sub.vhd ; ;
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; ../vhdl/buttons.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/buttons.vhd ; ;
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; ../vhdl/comparator.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/comparator.vhd ; ;
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; ../vhdl/controller.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/controller.vhd ; ;
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; ../vhdl/decoder.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/decoder.vhd ; ;
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; ../vhdl/extend.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/extend.vhd ; ;
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; ../vhdl/IR.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/IR.vhd ; ;
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; ../vhdl/LEDs.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/LEDs.vhd ; ;
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; ../vhdl/logic_unit.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/logic_unit.vhd ; ;
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; ../vhdl/multiplexer.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/multiplexer.vhd ; ;
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; ../vhdl/mux2x5.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/mux2x5.vhd ; ;
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; ../vhdl/mux2x16.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/mux2x16.vhd ; ;
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; ../vhdl/mux2x32.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/mux2x32.vhd ; ;
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; ../vhdl/PC.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/PC.vhd ; ;
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; ../vhdl/RAM.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/RAM.vhd ; ;
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; ../vhdl/register_file.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/register_file.vhd ; ;
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; ../vhdl/ROM.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/ROM.vhd ; ;
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; ../vhdl/ROM_Block.vhd ; yes ; User Wizard-Generated File ; E:/cs208/vhdl/ROM_Block.vhd ; ;
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; ../vhdl/shift_unit.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/shift_unit.vhd ; ;
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; ROM.hex ; yes ; User Hexadecimal (Intel-Format) File ; E:/cs208/quartus/ROM.hex ; ;
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; altsyncram.tdf ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altsyncram.tdf ; ;
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; stratix_ram_block.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
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; lpm_mux.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/lpm_mux.inc ; ;
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; lpm_decode.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/lpm_decode.inc ; ;
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; aglobal180.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/aglobal180.inc ; ;
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; a_rdenreg.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
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; altrom.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altrom.inc ; ;
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; altram.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altram.inc ; ;
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; altdpram.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altdpram.inc ; ;
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; db/altsyncram_rna1.tdf ; yes ; Auto-Generated Megafunction ; E:/cs208/quartus/db/altsyncram_rna1.tdf ; ;
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; db/altsyncram_u781.tdf ; yes ; Auto-Generated Megafunction ; E:/cs208/quartus/db/altsyncram_u781.tdf ; ;
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; db/gecko.ram0_ram_15119.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; E:/cs208/quartus/db/gecko.ram0_ram_15119.hdl.mif ; ;
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+----------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------+---------+
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+---------------------------------------------------------+
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; Analysis & Synthesis Resource Usage Summary ;
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+---------------------------------------------+-----------+
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; Resource ; Usage ;
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+---------------------------------------------+-----------+
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; Estimated Total logic elements ; 3,537 ;
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; ; ;
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; Total combinational functions ; 2508 ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 1959 ;
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; -- 3 input functions ; 377 ;
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; -- <=2 input functions ; 172 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 2448 ;
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; -- arithmetic mode ; 60 ;
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; ; ;
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; Total registers ; 1180 ;
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; -- Dedicated logic registers ; 1180 ;
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; -- I/O registers ; 0 ;
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; ; ;
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; I/O pins ; 102 ;
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; Total memory bits ; 65536 ;
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; ; ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; ; ;
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; Maximum fan-out node ; clk~input ;
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; Maximum fan-out ; 1244 ;
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; Total fan-out ; 13957 ;
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; Average fan-out ; 3.53 ;
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+---------------------------------------------+-----------+
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Resource Utilization by Entity ;
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+----------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------+-----------------+--------------+
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; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+----------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------+-----------------+--------------+
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; |GECKO ; 2508 (113) ; 1180 (0) ; 65536 ; 0 ; 0 ; 0 ; 102 ; 0 ; |GECKO ; GECKO ; work ;
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; |CPU:inst| ; 2248 (3) ; 1054 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst ; CPU ; work ;
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; |ALU:alu_0| ; 495 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0 ; ALU ; work ;
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; |add_sub:add_sub_0| ; 77 (77) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0|add_sub:add_sub_0 ; add_sub ; work ;
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; |comparator:comparator_0| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0|comparator:comparator_0 ; comparator ; work ;
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; |logic_unit:logic_unit_0| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0|logic_unit:logic_unit_0 ; logic_unit ; work ;
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; |multiplexer:multiplexer_0| ; 81 (81) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0|multiplexer:multiplexer_0 ; multiplexer ; work ;
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; |shift_unit:shift_unit_0| ; 322 (322) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0 ; shift_unit ; work ;
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; |IR:IR_0| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|IR:IR_0 ; IR ; work ;
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; |PC:PC_0| ; 42 (42) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|PC:PC_0 ; PC ; work ;
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; |controller:controller_0| ; 183 (183) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|controller:controller_0 ; controller ; work ;
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; |mux2x16:mux_addr| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|mux2x16:mux_addr ; mux2x16 ; work ;
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; |mux2x32:mux_b| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|mux2x32:mux_b ; mux2x32 ; work ;
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; |mux2x32:mux_data| ; 140 (140) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|mux2x32:mux_data ; mux2x32 ; work ;
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; |mux2x5:mux_aw| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|mux2x5:mux_aw ; mux2x5 ; work ;
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; |register_file:register_file_0| ; 1334 (1334) ; 992 (992) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|register_file:register_file_0 ; register_file ; work ;
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; |LEDs:LEDs_0| ; 122 (122) ; 115 (115) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|LEDs:LEDs_0 ; LEDs ; work ;
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; |RAM:RAM_0| ; 2 (2) ; 1 (1) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|RAM:RAM_0 ; RAM ; work ;
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; |altsyncram:reg_rtl_0| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|RAM:RAM_0|altsyncram:reg_rtl_0 ; altsyncram ; work ;
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; |altsyncram_u781:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|RAM:RAM_0|altsyncram:reg_rtl_0|altsyncram_u781:auto_generated ; altsyncram_u781 ; work ;
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; |ROM:ROM_0| ; 4 (4) ; 1 (1) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|ROM:ROM_0 ; ROM ; work ;
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; |ROM_Block:romblock| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|ROM:ROM_0|ROM_Block:romblock ; ROM_Block ; work ;
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; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component ; altsyncram ; work ;
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; |altsyncram_rna1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated ; altsyncram_rna1 ; work ;
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; |buttons:buttons_0| ; 8 (8) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|buttons:buttons_0 ; buttons ; work ;
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; |decoder:decoder_0| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|decoder:decoder_0 ; decoder ; work ;
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+----------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------+-----------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis RAM Summary ;
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+--------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+-------+---------------------------------+
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; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
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+--------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+-------+---------------------------------+
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; RAM:RAM_0|altsyncram:reg_rtl_0|altsyncram_u781:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 1024 ; 32 ; -- ; -- ; 32768 ; db/GECKO.ram0_RAM_15119.hdl.mif ;
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; ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 1024 ; 32 ; -- ; -- ; 32768 ; ../quartus/ROM.hex ;
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+--------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+-------+---------------------------------+
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Encoding Type: One-Hot
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; State Machine - |GECKO|CPU:inst|controller:controller_0|s_cur ;
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+--------------+-------------+-------------+------------+-----------+-------------+------------+--------------+-------------+------------+-------------+-------------+-------------+------------+--------------+--------------+--------------+
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; Name ; s_cur.RI_OP ; s_cur.UI_OP ; s_cur.JMPI ; s_cur.JMP ; s_cur.CALLR ; s_cur.CALL ; s_cur.BRANCH ; s_cur.LOAD2 ; s_cur.I_OP ; s_cur.LOAD1 ; s_cur.BREAK ; s_cur.STORE ; s_cur.R_OP ; s_cur.DECODE ; s_cur.FETCH2 ; s_cur.FETCH1 ;
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+--------------+-------------+-------------+------------+-----------+-------------+------------+--------------+-------------+------------+-------------+-------------+-------------+------------+--------------+--------------+--------------+
|
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; s_cur.FETCH1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
; s_cur.FETCH2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
|
|
; s_cur.DECODE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
|
|
; s_cur.R_OP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
|
|
; s_cur.STORE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.BREAK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.LOAD1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.I_OP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.LOAD2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.BRANCH ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.CALL ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.CALLR ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.JMP ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.JMPI ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.UI_OP ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
; s_cur.RI_OP ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
|
+--------------+-------------+-------------+------------+-----------+-------------+------------+--------------+-------------+------------+-------------+-------------+-------------+------------+--------------+--------------+--------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------+
|
|
; User-Specified and Inferred Latches ;
|
|
+-----------------------------------------------------+---------------------+------------------------+
|
|
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
|
|
+-----------------------------------------------------+---------------------+------------------------+
|
|
; CPU:inst|controller:controller_0|s_next.R_OP_1618 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.BRANCH_1408 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.STORE_1583 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.LOAD1_1513 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.I_OP_1478 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.LOAD2_1443 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.CALL_1373 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.CALLR_1338 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.RI_OP_1198 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.UI_OP_1233 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.FETCH2_1688 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.JMP_1303 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.JMPI_1268 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.FETCH1_1723 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.DECODE_1653 ; GND ; yes ;
|
|
; CPU:inst|controller:controller_0|s_next.BREAK_1548 ; GND ; yes ;
|
|
; Number of user-specified and inferred latches = 16 ; ; ;
|
|
+-----------------------------------------------------+---------------------+------------------------+
|
|
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------+
|
|
; Registers Removed During Synthesis ;
|
|
+---------------------------------------------------+----------------------------------------+
|
|
; Register name ; Reason for Removal ;
|
|
+---------------------------------------------------+----------------------------------------+
|
|
; CPU:inst|register_file:register_file_0|reg[0][0] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][1] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][2] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][3] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][4] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][5] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][6] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][7] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][8] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][9] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][10] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][11] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][12] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][13] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][14] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][15] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][16] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][17] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][18] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][19] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][20] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][21] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][22] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][23] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][24] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][25] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][26] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][27] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][28] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][29] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][30] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|register_file:register_file_0|reg[0][31] ; Stuck at GND due to stuck port data_in ;
|
|
; CPU:inst|PC:PC_0|n_addr[0,1] ; Stuck at GND due to stuck port data_in ;
|
|
; buttons:buttons_0|read_reg ; Lost fanout ;
|
|
; CPU:inst|PC:PC_0|n_addr[16..31] ; Lost fanout ;
|
|
; Total Number of Removed Registers = 51 ; ;
|
|
+---------------------------------------------------+----------------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------+
|
|
; Removed Registers Triggering Further Register Optimizations ;
|
|
+---------------------------------------------------+---------------------------+----------------------------------------+
|
|
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
|
|
+---------------------------------------------------+---------------------------+----------------------------------------+
|
|
; CPU:inst|register_file:register_file_0|reg[0][31] ; Stuck at GND ; buttons:buttons_0|read_reg ;
|
|
; ; due to stuck port data_in ; ;
|
|
+---------------------------------------------------+---------------------------+----------------------------------------+
|
|
|
|
|
|
+------------------------------------------------------+
|
|
; General Register Statistics ;
|
|
+----------------------------------------------+-------+
|
|
; Statistic ; Value ;
|
|
+----------------------------------------------+-------+
|
|
; Total registers ; 1180 ;
|
|
; Number of registers using Synchronous Clear ; 8 ;
|
|
; Number of registers using Synchronous Load ; 14 ;
|
|
; Number of registers using Asynchronous Clear ; 154 ;
|
|
; Number of registers using Asynchronous Load ; 0 ;
|
|
; Number of registers using Clock Enable ; 1142 ;
|
|
; Number of registers using Preset ; 0 ;
|
|
+----------------------------------------------+-------+
|
|
|
|
|
|
+--------------------------------------------------+
|
|
; Inverted Register Statistics ;
|
|
+----------------------------------------+---------+
|
|
; Inverted Register ; Fan out ;
|
|
+----------------------------------------+---------+
|
|
; LEDs:LEDs_0|duty_cycle[3] ; 2 ;
|
|
; LEDs:LEDs_0|duty_cycle[2] ; 2 ;
|
|
; LEDs:LEDs_0|duty_cycle[1] ; 2 ;
|
|
; LEDs:LEDs_0|duty_cycle[0] ; 2 ;
|
|
; buttons:buttons_0|buttons_reg[0] ; 1 ;
|
|
; buttons:buttons_0|buttons_reg[1] ; 1 ;
|
|
; buttons:buttons_0|buttons_reg[3] ; 1 ;
|
|
; buttons:buttons_0|buttons_reg[2] ; 1 ;
|
|
; Total number of inverted registers = 8 ; ;
|
|
+----------------------------------------+---------+
|
|
|
|
|
|
+----------------------------------------------------------+
|
|
; Registers Packed Into Inferred Megafunctions ;
|
|
+-----------------------------+---------------------+------+
|
|
; Register Name ; Megafunction ; Type ;
|
|
+-----------------------------+---------------------+------+
|
|
; RAM:RAM_0|reg_address[0..9] ; RAM:RAM_0|reg_rtl_0 ; RAM ;
|
|
+-----------------------------+---------------------+------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------+
|
|
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------+
|
|
; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GECKO|CPU:inst|PC:PC_0|n_addr[22] ;
|
|
; 3:1 ; 14 bits ; 28 LEs ; 28 LEs ; 0 LEs ; Yes ; |GECKO|CPU:inst|PC:PC_0|n_addr[15] ;
|
|
; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0|v ;
|
|
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0|v ;
|
|
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0|v ;
|
|
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0|v ;
|
|
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|mux2x32:mux_data|o[1] ;
|
|
; 3:1 ; 14 bits ; 28 LEs ; 28 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|mux2x32:mux_data|o[9] ;
|
|
; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|mux2x5:mux_aw|o[0] ;
|
|
; 32:1 ; 32 bits ; 672 LEs ; 640 LEs ; 32 LEs ; No ; |GECKO|CPU:inst|register_file:register_file_0|Mux1 ;
|
|
; 32:1 ; 32 bits ; 672 LEs ; 640 LEs ; 32 LEs ; No ; |GECKO|CPU:inst|register_file:register_file_0|Mux48 ;
|
|
; 7:1 ; 24 bits ; 96 LEs ; 72 LEs ; 24 LEs ; No ; |GECKO|rddata[17] ;
|
|
; 7:1 ; 4 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |GECKO|rddata[6] ;
|
|
; 8:1 ; 4 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GECKO|rddata[1] ;
|
|
; 14:1 ; 15 bits ; 135 LEs ; 90 LEs ; 45 LEs ; No ; |GECKO|CPU:inst|ALU:alu_0|multiplexer:multiplexer_0|o[4] ;
|
|
; 16:1 ; 14 bits ; 140 LEs ; 126 LEs ; 14 LEs ; No ; |GECKO|CPU:inst|mux2x32:mux_data|o[29] ;
|
|
; 16:1 ; 2 bits ; 20 LEs ; 6 LEs ; 14 LEs ; No ; |GECKO|CPU:inst|controller:controller_0|s_next.JMPI ;
|
|
; 22:1 ; 2 bits ; 28 LEs ; 28 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|controller:controller_0|op_alu[1] ;
|
|
; 23:1 ; 2 bits ; 30 LEs ; 24 LEs ; 6 LEs ; No ; |GECKO|CPU:inst|controller:controller_0|op_alu[4] ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------+
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated ;
|
|
+---------------------------------+--------------------+------+------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+---------------------------------+--------------------+------+------------------------------------------------------+
|
|
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
|
|
+---------------------------------+--------------------+------+------------------------------------------------------+
|
|
|
|
|
|
+--------------------------------------------------------------------------------------+
|
|
; Source assignments for RAM:RAM_0|altsyncram:reg_rtl_0|altsyncram_u781:auto_generated ;
|
|
+---------------------------------+--------------------+------+------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+---------------------------------+--------------------+------+------------------------+
|
|
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
|
|
+---------------------------------+--------------------+------+------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component ;
|
|
+------------------------------------+----------------------+-----------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------+----------------------+-----------------------------------------------+
|
|
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; WIDTH_BYTEENA ; 1 ; Untyped ;
|
|
; OPERATION_MODE ; ROM ; Untyped ;
|
|
; WIDTH_A ; 32 ; Signed Integer ;
|
|
; WIDTHAD_A ; 10 ; Signed Integer ;
|
|
; NUMWORDS_A ; 1024 ; Signed Integer ;
|
|
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
|
|
; ADDRESS_ACLR_A ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_A ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
|
|
; INDATA_ACLR_A ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_A ; NONE ; Untyped ;
|
|
; WIDTH_B ; 1 ; Untyped ;
|
|
; WIDTHAD_B ; 1 ; Untyped ;
|
|
; NUMWORDS_B ; 1 ; Untyped ;
|
|
; INDATA_REG_B ; CLOCK1 ; Untyped ;
|
|
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
|
|
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
|
|
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
|
|
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
|
|
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
|
|
; INDATA_ACLR_B ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; ADDRESS_ACLR_B ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_B ; NONE ; Untyped ;
|
|
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_B ; NONE ; Untyped ;
|
|
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
|
|
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
|
|
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
|
|
; BYTE_SIZE ; 8 ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; INIT_FILE ; ../quartus/ROM.hex ; Untyped ;
|
|
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
|
|
; MAXIMUM_DEPTH ; 0 ; Untyped ;
|
|
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
|
|
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
|
|
; ENABLE_ECC ; FALSE ; Untyped ;
|
|
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
|
|
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CBXI_PARAMETER ; altsyncram_rna1 ; Untyped ;
|
|
+------------------------------------+----------------------+-----------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------+
|
|
; Parameter Settings for Inferred Entity Instance: RAM:RAM_0|altsyncram:reg_rtl_0 ;
|
|
+------------------------------------+---------------------------------+----------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------+---------------------------------+----------------+
|
|
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; WIDTH_BYTEENA ; 1 ; Untyped ;
|
|
; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
|
|
; WIDTH_A ; 32 ; Untyped ;
|
|
; WIDTHAD_A ; 10 ; Untyped ;
|
|
; NUMWORDS_A ; 1024 ; Untyped ;
|
|
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
|
|
; ADDRESS_ACLR_A ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_A ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
|
|
; INDATA_ACLR_A ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_A ; NONE ; Untyped ;
|
|
; WIDTH_B ; 1 ; Untyped ;
|
|
; WIDTHAD_B ; 1 ; Untyped ;
|
|
; NUMWORDS_B ; 1 ; Untyped ;
|
|
; INDATA_REG_B ; CLOCK1 ; Untyped ;
|
|
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
|
|
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
|
|
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
|
|
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
|
|
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
|
|
; INDATA_ACLR_B ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; ADDRESS_ACLR_B ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_B ; NONE ; Untyped ;
|
|
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_B ; NONE ; Untyped ;
|
|
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
|
|
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
|
|
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
|
|
; BYTE_SIZE ; 8 ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; INIT_FILE ; db/GECKO.ram0_RAM_15119.hdl.mif ; Untyped ;
|
|
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
|
|
; MAXIMUM_DEPTH ; 0 ; Untyped ;
|
|
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
|
|
; ENABLE_ECC ; FALSE ; Untyped ;
|
|
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
|
|
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CBXI_PARAMETER ; altsyncram_u781 ; Untyped ;
|
|
+------------------------------------+---------------------------------+----------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------+
|
|
; altsyncram Parameter Settings by Entity Instance ;
|
|
+-------------------------------------------+--------------------------------------------------------------+
|
|
; Name ; Value ;
|
|
+-------------------------------------------+--------------------------------------------------------------+
|
|
; Number of entity instances ; 2 ;
|
|
; Entity Instance ; ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component ;
|
|
; -- OPERATION_MODE ; ROM ;
|
|
; -- WIDTH_A ; 32 ;
|
|
; -- NUMWORDS_A ; 1024 ;
|
|
; -- OUTDATA_REG_A ; UNREGISTERED ;
|
|
; -- WIDTH_B ; 1 ;
|
|
; -- NUMWORDS_B ; 1 ;
|
|
; -- ADDRESS_REG_B ; CLOCK1 ;
|
|
; -- OUTDATA_REG_B ; UNREGISTERED ;
|
|
; -- RAM_BLOCK_TYPE ; AUTO ;
|
|
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
|
|
; Entity Instance ; RAM:RAM_0|altsyncram:reg_rtl_0 ;
|
|
; -- OPERATION_MODE ; SINGLE_PORT ;
|
|
; -- WIDTH_A ; 32 ;
|
|
; -- NUMWORDS_A ; 1024 ;
|
|
; -- OUTDATA_REG_A ; UNREGISTERED ;
|
|
; -- WIDTH_B ; 1 ;
|
|
; -- NUMWORDS_B ; 1 ;
|
|
; -- ADDRESS_REG_B ; CLOCK1 ;
|
|
; -- OUTDATA_REG_B ; UNREGISTERED ;
|
|
; -- RAM_BLOCK_TYPE ; AUTO ;
|
|
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
|
|
+-------------------------------------------+--------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------+
|
|
; Post-Synthesis Netlist Statistics for Top Partition ;
|
|
+-----------------------+-----------------------------+
|
|
; Type ; Count ;
|
|
+-----------------------+-----------------------------+
|
|
; boundary_port ; 102 ;
|
|
; cycloneiii_ff ; 1180 ;
|
|
; CLR ; 28 ;
|
|
; CLR SCLR ; 8 ;
|
|
; ENA ; 1024 ;
|
|
; ENA CLR ; 104 ;
|
|
; ENA CLR SLD ; 14 ;
|
|
; plain ; 2 ;
|
|
; cycloneiii_lcell_comb ; 2508 ;
|
|
; arith ; 60 ;
|
|
; 2 data inputs ; 8 ;
|
|
; 3 data inputs ; 52 ;
|
|
; normal ; 2448 ;
|
|
; 0 data inputs ; 1 ;
|
|
; 1 data inputs ; 10 ;
|
|
; 2 data inputs ; 153 ;
|
|
; 3 data inputs ; 325 ;
|
|
; 4 data inputs ; 1959 ;
|
|
; cycloneiii_ram_block ; 64 ;
|
|
; ; ;
|
|
; Max LUT depth ; 22.50 ;
|
|
; Average LUT depth ; 16.46 ;
|
|
+-----------------------+-----------------------------+
|
|
|
|
|
|
+-------------------------------+
|
|
; Elapsed Time Per Partition ;
|
|
+----------------+--------------+
|
|
; Partition Name ; Elapsed Time ;
|
|
+----------------+--------------+
|
|
; Top ; 00:00:10 ;
|
|
+----------------+--------------+
|
|
|
|
|
|
+-------------------------------+
|
|
; Analysis & Synthesis Messages ;
|
|
+-------------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Analysis & Synthesis
|
|
Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
|
|
Info: Processing started: Wed Oct 24 12:06:15 2018
|
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GECKO -c GECKO
|
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
|
Info (12021): Found 1 design units, including 1 entities, in source file gecko.bdf
|
|
Info (12023): Found entity 1: GECKO
|
|
Info (12021): Found 1 design units, including 1 entities, in source file alu.bdf
|
|
Info (12023): Found entity 1: ALU
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu.bdf
|
|
Info (12023): Found entity 1: CPU
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/add_sub.vhd
|
|
Info (12022): Found design unit 1: add_sub-synth File: E:/cs208/vhdl/add_sub.vhd Line: 16
|
|
Info (12023): Found entity 1: add_sub File: E:/cs208/vhdl/add_sub.vhd Line: 5
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/buttons.vhd
|
|
Info (12022): Found design unit 1: buttons-synth File: E:/cs208/vhdl/buttons.vhd Line: 22
|
|
Info (12023): Found entity 1: buttons File: E:/cs208/vhdl/buttons.vhd Line: 5
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/comparator.vhd
|
|
Info (12022): Found design unit 1: comparator-synth File: E:/cs208/vhdl/comparator.vhd Line: 16
|
|
Info (12023): Found entity 1: comparator File: E:/cs208/vhdl/comparator.vhd Line: 4
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/controller.vhd
|
|
Info (12022): Found design unit 1: controller-synth File: E:/cs208/vhdl/controller.vhd Line: 39
|
|
Info (12023): Found entity 1: controller File: E:/cs208/vhdl/controller.vhd Line: 4
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/decoder.vhd
|
|
Info (12022): Found design unit 1: decoder-synth File: E:/cs208/vhdl/decoder.vhd Line: 14
|
|
Info (12023): Found entity 1: decoder File: E:/cs208/vhdl/decoder.vhd Line: 4
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/extend.vhd
|
|
Info (12022): Found design unit 1: extend-synth File: E:/cs208/vhdl/extend.vhd Line: 12
|
|
Info (12023): Found entity 1: extend File: E:/cs208/vhdl/extend.vhd Line: 4
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/ir.vhd
|
|
Info (12022): Found design unit 1: IR-synth File: E:/cs208/vhdl/IR.vhd Line: 13
|
|
Info (12023): Found entity 1: IR File: E:/cs208/vhdl/IR.vhd Line: 4
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/leds.vhd
|
|
Info (12022): Found design unit 1: LEDs-synth File: E:/cs208/vhdl/LEDs.vhd Line: 22
|
|
Info (12023): Found entity 1: LEDs File: E:/cs208/vhdl/LEDs.vhd Line: 5
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/logic_unit.vhd
|
|
Info (12022): Found design unit 1: logic_unit-synth File: E:/cs208/vhdl/logic_unit.vhd Line: 13
|
|
Info (12023): Found entity 1: logic_unit File: E:/cs208/vhdl/logic_unit.vhd Line: 4
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/multiplexer.vhd
|
|
Info (12022): Found design unit 1: multiplexer-synth File: E:/cs208/vhdl/multiplexer.vhd Line: 15
|
|
Info (12023): Found entity 1: multiplexer File: E:/cs208/vhdl/multiplexer.vhd Line: 4
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x5.vhd
|
|
Info (12022): Found design unit 1: mux2x5-synth File: E:/cs208/vhdl/mux2x5.vhd Line: 13
|
|
Info (12023): Found entity 1: mux2x5 File: E:/cs208/vhdl/mux2x5.vhd Line: 4
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x16.vhd
|
|
Info (12022): Found design unit 1: mux2x16-synth File: E:/cs208/vhdl/mux2x16.vhd Line: 13
|
|
Info (12023): Found entity 1: mux2x16 File: E:/cs208/vhdl/mux2x16.vhd Line: 4
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x32.vhd
|
|
Info (12022): Found design unit 1: mux2x32-synth File: E:/cs208/vhdl/mux2x32.vhd Line: 13
|
|
Info (12023): Found entity 1: mux2x32 File: E:/cs208/vhdl/mux2x32.vhd Line: 4
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/pc.vhd
|
|
Info (12022): Found design unit 1: PC-synth File: E:/cs208/vhdl/PC.vhd Line: 19
|
|
Info (12023): Found entity 1: PC File: E:/cs208/vhdl/PC.vhd Line: 5
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/ram.vhd
|
|
Info (12022): Found design unit 1: RAM-synth File: E:/cs208/vhdl/RAM.vhd Line: 16
|
|
Info (12023): Found entity 1: RAM File: E:/cs208/vhdl/RAM.vhd Line: 5
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/register_file.vhd
|
|
Info (12022): Found design unit 1: register_file-synth File: E:/cs208/vhdl/register_file.vhd Line: 18
|
|
Info (12023): Found entity 1: register_file File: E:/cs208/vhdl/register_file.vhd Line: 5
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/rom.vhd
|
|
Info (12022): Found design unit 1: ROM-synth File: E:/cs208/vhdl/ROM.vhd Line: 15
|
|
Info (12023): Found entity 1: ROM File: E:/cs208/vhdl/ROM.vhd Line: 5
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/rom_block.vhd
|
|
Info (12022): Found design unit 1: rom_block-SYN File: E:/cs208/vhdl/ROM_Block.vhd Line: 52
|
|
Info (12023): Found entity 1: ROM_Block File: E:/cs208/vhdl/ROM_Block.vhd Line: 42
|
|
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/shift_unit.vhd
|
|
Info (12022): Found design unit 1: shift_unit-synth File: E:/cs208/vhdl/shift_unit.vhd Line: 14
|
|
Info (12023): Found entity 1: shift_unit File: E:/cs208/vhdl/shift_unit.vhd Line: 5
|
|
Info (12127): Elaborating entity "GECKO" for the top level hierarchy
|
|
Info (12128): Elaborating entity "LEDs" for hierarchy "LEDs:LEDs_0"
|
|
Info (12128): Elaborating entity "decoder" for hierarchy "decoder:decoder_0"
|
|
Info (12128): Elaborating entity "CPU" for hierarchy "CPU:inst"
|
|
Info (12128): Elaborating entity "controller" for hierarchy "CPU:inst|controller:controller_0"
|
|
Info (10041): Inferred latch for "s_next.RI_OP" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.UI_OP" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.JMPI" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.JMP" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.CALLR" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.CALL" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.BRANCH" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.LOAD2" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.I_OP" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.LOAD1" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.BREAK" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.STORE" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.R_OP" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.DECODE" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.FETCH2" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (10041): Inferred latch for "s_next.FETCH1" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
|
|
Info (12128): Elaborating entity "IR" for hierarchy "CPU:inst|IR:IR_0"
|
|
Info (12128): Elaborating entity "mux2x16" for hierarchy "CPU:inst|mux2x16:mux_addr"
|
|
Info (12128): Elaborating entity "PC" for hierarchy "CPU:inst|PC:PC_0"
|
|
Info (12128): Elaborating entity "ALU" for hierarchy "CPU:inst|ALU:alu_0"
|
|
Info (12128): Elaborating entity "multiplexer" for hierarchy "CPU:inst|ALU:alu_0|multiplexer:multiplexer_0"
|
|
Info (12128): Elaborating entity "add_sub" for hierarchy "CPU:inst|ALU:alu_0|add_sub:add_sub_0"
|
|
Info (12128): Elaborating entity "comparator" for hierarchy "CPU:inst|ALU:alu_0|comparator:comparator_0"
|
|
Info (12128): Elaborating entity "logic_unit" for hierarchy "CPU:inst|ALU:alu_0|logic_unit:logic_unit_0"
|
|
Info (12128): Elaborating entity "shift_unit" for hierarchy "CPU:inst|ALU:alu_0|shift_unit:shift_unit_0"
|
|
Info (12128): Elaborating entity "register_file" for hierarchy "CPU:inst|register_file:register_file_0"
|
|
Info (12128): Elaborating entity "mux2x5" for hierarchy "CPU:inst|mux2x5:mux_aw"
|
|
Info (12128): Elaborating entity "mux2x32" for hierarchy "CPU:inst|mux2x32:mux_data"
|
|
Info (12128): Elaborating entity "extend" for hierarchy "CPU:inst|extend:extend_0"
|
|
Info (12128): Elaborating entity "ROM" for hierarchy "ROM:ROM_0"
|
|
Info (12128): Elaborating entity "ROM_Block" for hierarchy "ROM:ROM_0|ROM_Block:romblock" File: E:/cs208/vhdl/ROM.vhd Line: 33
|
|
Info (12128): Elaborating entity "altsyncram" for hierarchy "ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component" File: E:/cs208/vhdl/ROM_Block.vhd Line: 85
|
|
Info (12130): Elaborated megafunction instantiation "ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component" File: E:/cs208/vhdl/ROM_Block.vhd Line: 85
|
|
Info (12133): Instantiated megafunction "ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component" with the following parameter: File: E:/cs208/vhdl/ROM_Block.vhd Line: 85
|
|
Info (12134): Parameter "address_aclr_a" = "NONE"
|
|
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
|
|
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
|
|
Info (12134): Parameter "init_file" = "../quartus/ROM.hex"
|
|
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
|
|
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
|
|
Info (12134): Parameter "lpm_type" = "altsyncram"
|
|
Info (12134): Parameter "numwords_a" = "1024"
|
|
Info (12134): Parameter "operation_mode" = "ROM"
|
|
Info (12134): Parameter "outdata_aclr_a" = "NONE"
|
|
Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
|
|
Info (12134): Parameter "widthad_a" = "10"
|
|
Info (12134): Parameter "width_a" = "32"
|
|
Info (12134): Parameter "width_byteena_a" = "1"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_rna1.tdf
|
|
Info (12023): Found entity 1: altsyncram_rna1 File: E:/cs208/quartus/db/altsyncram_rna1.tdf Line: 27
|
|
Info (12128): Elaborating entity "altsyncram_rna1" for hierarchy "ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated" File: c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
|
|
Info (12128): Elaborating entity "RAM" for hierarchy "RAM:RAM_0"
|
|
Info (12128): Elaborating entity "buttons" for hierarchy "buttons:buttons_0"
|
|
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
|
|
Warning (13048): Converted tri-state node "rddata[31]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[30]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[29]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[28]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[27]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[26]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[25]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[24]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[23]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[22]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[21]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[20]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[19]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[18]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[17]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[16]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[15]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[14]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[13]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[12]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[11]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[10]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[9]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[8]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[7]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[6]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[5]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[4]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[3]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[2]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[1]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Warning (13048): Converted tri-state node "rddata[0]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "RAM:RAM_0|reg_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to SINGLE_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
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Info (286033): Parameter ADDRESS_ACLR_A set to NONE
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Info (286033): Parameter OUTDATA_ACLR_A set to NONE
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Info (286033): Parameter INDATA_ACLR_A set to NONE
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Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
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Info (286033): Parameter INIT_FILE set to db/GECKO.ram0_RAM_15119.hdl.mif
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Info (12130): Elaborated megafunction instantiation "RAM:RAM_0|altsyncram:reg_rtl_0"
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Info (12133): Instantiated megafunction "RAM:RAM_0|altsyncram:reg_rtl_0" with the following parameter:
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Info (12134): Parameter "OPERATION_MODE" = "SINGLE_PORT"
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Info (12134): Parameter "WIDTH_A" = "32"
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Info (12134): Parameter "WIDTHAD_A" = "10"
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Info (12134): Parameter "NUMWORDS_A" = "1024"
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Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
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Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
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Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
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Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
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Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
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Info (12134): Parameter "INIT_FILE" = "db/GECKO.ram0_RAM_15119.hdl.mif"
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Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_u781.tdf
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Info (12023): Found entity 1: altsyncram_u781 File: E:/cs208/quartus/db/altsyncram_u781.tdf Line: 27
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Info (13000): Registers with preset signals will power-up high File: E:/cs208/vhdl/LEDs.vhd Line: 90
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Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
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Info (286030): Timing-Driven Synthesis is running
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Info (17049): 17 registers lost all their fanouts during netlist optimizations.
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Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
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Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
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Info (21057): Implemented 3816 device resources after synthesis - the final resource count might be different
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Info (21058): Implemented 6 input pins
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Info (21059): Implemented 96 output pins
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Info (21061): Implemented 3650 logic cells
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Info (21064): Implemented 64 RAM segments
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Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 34 warnings
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Info: Peak virtual memory: 4843 megabytes
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Info: Processing ended: Wed Oct 24 12:06:43 2018
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Info: Elapsed time: 00:00:28
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Info: Total CPU time (on all processors): 00:00:39
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