java.lang.Integer 1610305946 false true false true GENERATION_ID java.lang.String false true false true UNIQUE_ID java.lang.String CYCLONEV false true false true DEVICE_FAMILY java.lang.String 5CSEMA4U23C6 false true false true DEVICE java.lang.String 6 false true false true DEVICE_SPEEDGRADE java.lang.Long -1 false true false true CLOCK_RATE clk java.lang.Integer -1 false true false true CLOCK_DOMAIN clk java.lang.Integer -1 false true false true RESET_DOMAIN clk java.lang.String Cyclone V false true false true DEVICE_FAMILY boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment DYNAMIC false true false true int 0 false true false true java.math.BigInteger 64 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true int 8 false true true true java.math.BigInteger false true false true com.altera.entityinterfaces.IConnectionPoint false true false true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false false true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 0 false false true true int 0 false false true true int 1 false true false true boolean false false true false true int 0 false true true true int 0 false true false true int 0 false false true true boolean false false true false true boolean false false true false true int 0 false false true true com.altera.sopcmodel.avalon.TimingUnits Cycles false false true true boolean false false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false false true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon false avalon_slave_address Input 4 address avalon_slave_write Input 1 write avalon_slave_writedata Input 32 writedata avalon_slave_read Input 1 read avalon_slave_readdata Output 32 readdata avalon_slave_waitrequest Output 1 waitrequest boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false rst_n Input 1 reset_n com.altera.entityinterfaces.IConnectionPoint false true false true int 0 false true false true com.altera.sopcmodel.avalon.EAddrBurstUnits SYMBOLS false true true true boolean false false true false true java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true int 8 false true true true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true true true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 32 false true false true int 0 false true true true int 0 false true true true int 0 false true true true int 1 false true true true boolean false false true false true boolean false false true false true int 0 false true true true com.altera.sopcmodel.avalon.TimingUnits Cycles false true true true int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon true avalon_master_address Output 32 address avalon_master_burstcount Output 5 burstcount avalon_master_read Output 1 read avalon_master_readdata Input 32 readdata avalon_master_readdatavalid Input 1 readdatavalid avalon_master_waitreq Input 1 waitrequest true address_span_extender_0 windowed_slave address_span_extender_0.windowed_slave 262144 262144 false hps_0_bridges f2h_sdram0_data hps_0_bridges.f2h_sdram0_data 262144 262144 com.altera.entityinterfaces.IConnectionPoint LCDController_0.avalon_slave false true true true java.lang.String clock_sink false true false true java.lang.String reset_sink false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false av_irq Output 1 irq java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true java.lang.String UNKNOWN false true true true boolean false false true true true conduit false lt24_cs_n Output 1 cs_n lt24_data Output 16 data lt24_lcd_on Output 1 lcd_on lt24_rd_n Output 1 rd_n lt24_reset_n Output 1 reset_n lt24_rs Output 1 rs lt24_wr_n Output 1 wr_n embeddedsw.CMacro.BURSTCOUNT_WIDTH 8 embeddedsw.CMacro.BYTEENABLE_WIDTH 4 embeddedsw.CMacro.CNTL_ADDRESS_WIDTH 1 embeddedsw.CMacro.DATA_WIDTH 32 embeddedsw.CMacro.MASTER_ADDRESS_WIDTH 32 embeddedsw.CMacro.MAX_BURST_BYTES 512 embeddedsw.CMacro.MAX_BURST_WORDS 128 embeddedsw.CMacro.SLAVE_ADDRESS_SHIFT 2 embeddedsw.CMacro.SLAVE_ADDRESS_WIDTH 16 embeddedsw.CMacro.SUB_WINDOW_COUNT 1 int 32 false true true true int 4 true true true true int 4 true true true true int 32 false true true true java.lang.String 4 gigabytes true true true true int 16 false true true true java.lang.String 256 kilobytes true true true true int 2 true true true true int 8 false true true true int 128 true true true true int 512 true true true true int 1 true true true true int 1 false true true true java.math.BigInteger 0 false true true true boolean false false true true true java.lang.String 256 kilobytes true true true true int 1 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clk Input 1 clk java.lang.String clock false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset Input 1 reset embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment DYNAMIC false true false true int 0 false true false true java.math.BigInteger 262144 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String clock false true true true java.lang.String reset false true true true int 8 false true true true java.math.BigInteger 0 false true false true com.altera.entityinterfaces.IConnectionPoint address_span_extender_0.expanded_master false true false true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false false true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 1 false true true true int 0 false false true true int 1 false true false true boolean false false true false true int 0 false false true true int 1 false true false true int 1 false false true true boolean false false true false true boolean false false true false true int 0 false false true true com.altera.sopcmodel.avalon.TimingUnits Cycles false false true true boolean false false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false false true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon false avs_s0_address Input 16 address avs_s0_read Input 1 read avs_s0_readdata Output 32 readdata avs_s0_write Input 1 write avs_s0_writedata Input 32 writedata avs_s0_readdatavalid Output 1 readdatavalid avs_s0_waitrequest Output 1 waitrequest avs_s0_byteenable Input 4 byteenable avs_s0_burstcount Input 8 burstcount com.altera.entityinterfaces.IConnectionPoint false true false true int 0 false true false true com.altera.sopcmodel.avalon.EAddrBurstUnits SYMBOLS false true true true boolean false false true false true java.lang.String clock false true true true java.lang.String reset false true true true int 8 false true true true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true true true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 32 false true false true int 0 false true true true int 0 false true true true int 0 false true true true int 1 false true true true boolean false false true false true boolean false false true false true int 0 false true true true com.altera.sopcmodel.avalon.TimingUnits Cycles false true true true int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon true avm_m0_address Output 32 address avm_m0_read Output 1 read avm_m0_waitrequest Input 1 waitrequest avm_m0_readdata Input 32 readdata avm_m0_write Output 1 write avm_m0_writedata Output 32 writedata avm_m0_readdatavalid Input 1 readdatavalid avm_m0_byteenable Output 4 byteenable avm_m0_burstcount Output 8 burstcount false hps_0_bridges f2h_sdram0_data hps_0_bridges.f2h_sdram0_data 0 4294967296 long 50000000 false true true true boolean true false true true true long 0 false true false true CLOCK_RATE clk_in com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true qsys.ui.export_name clk boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 50000000 true true false true clock false in_clk Input 1 clk qsys.ui.export_name reset java.lang.String false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_n Input 1 reset_n java.lang.String clk_in false true true true long 50000000 false true true true boolean true false true true true boolean true false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true clk_out Output 1 clk false nios2_gen2_0 clk nios2_gen2_0.clk false jtag_uart_0 clk jtag_uart_0.clk false onchip_memory2_0 clk1 onchip_memory2_0.clk1 false address_span_extender_0 clock address_span_extender_0.clock false LCDController_0 clock_sink LCDController_0.clock_sink false hps_0_bridges f2h_sdram0_clock hps_0_bridges.f2h_sdram0_clock java.lang.String false true true true java.lang.String clk_in_reset false true true true [Ljava.lang.String; clk_in_reset false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset true reset_n_out Output 1 reset_n cmsis.svd.file /opt/intelFPGA/18.1/ip/altera/hps/altera_hps/altera_hps.svd cmsis.svd.suffix hps postgeneration.simulation.init_file.param_name ABS_RAM_MEM_INIT_FILENAME postgeneration.simulation.init_file.type MEM_INIT java.lang.String 0010000110001 true true false true java.lang.String 0010001001001 true true false true java.lang.String true true false true java.lang.String 0010100110000 true true false true java.lang.String 0010011001000 true true false true java.lang.String 0000001000100 true true false true java.lang.String 0000000100100 true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String 0000000010000 true true false true java.lang.String 0000000001000 true true false true java.lang.String 0000000000000 true true false true java.lang.String 0000000000000 true true false true boolean true true true false true int 1 true true false true int 0 true true false true int 3 true true false true int 1 true true false true int 2 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 3 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 1 true true false true int 2 true true false true int 0 true true false true int 0 true true false true int 4 true true false true int 4 true true false true int 1 true true false true int 15 true true false true int 13 true true false true int 15 true true false true int 10 true true false true int 4 true true false true int 1 true true false true int 1 true true false true int 1 true true false true int 1 true true false true int 8 true true false true boolean false true true false true int 4 true true true true int 1 true true false true int 1 true true false true int 3 true true false true int 32 true true false true int 1 true true false true int 1 true true false true int 1 true true false true int 1 true true false true double 1.25 true true false true double 1250.0 true true false true int 20 true true false true int 14 true true false true int 6 true true false true int 6 true true false true int 3120 true true false true int 120 true true false true int 1 true true false true int 6 true true false true int 15 true true false true int 3 true true false true int 3 true true false true int 450 true true false true int 100000 true true false true int 1 true true false true int 7 true true false true boolean true true true false true boolean false true true false true boolean false true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 3 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 2 true true false true java.lang.String DDR3 true true false true int 0 true true false true int 0 true true false true boolean false true true false true boolean false true true false true java.lang.String Other false true true true java.lang.String DISCRETE false false true true boolean false true false true true java.lang.String 0000000000000000 false true false true java.lang.String 0x000000000000000000 false true false true boolean true false true false true int 1 false true true true java.lang.String 0 false true true true double 800.0 false true true true int 15 false true true true int 10 false true true true int 32 false true true true int 8 false true false true int 3 false true true true boolean true false true true true boolean true false true true true int 1 false true false true int 1 false true false true int 1 false true false true int 1 false true false true int 1 false true true true int 1 false true false true int 1 false true false true boolean false false true false true boolean true false true false true int 10 false true false true int 0 false true false true boolean false false true false true boolean true false true false true boolean false false true false true boolean false false true false true boolean false false true false true java.math.BigInteger 0 false true false true boolean false false true false true java.lang.String OTF false true true true java.lang.String Sequential false true true true java.lang.String Manual false true true true java.lang.String Normal false true true true java.lang.String DLL off false true true true java.lang.String RZQ/6 false true true true boolean true false true false true java.lang.String RZQ/6 false true true true java.lang.String Dynamic ODT off false true true true int 7 false true true true java.lang.String Disabled false true false true int 7 false true true true boolean true false true false true java.lang.String Leveling false true false true boolean false false true false true java.lang.String false false false true int 32 false false false true int 175 false true true true int 250 false true true true int 50 false true true true int 125 false true true true int 120 false true true true int 300 false true false true double 0.38 false true true true int 400 false true true true int 450 false true false true int 900 false true false true int 1200 false true false true double 0.25 false true true true double 0.35 false true false true double 0.38 false true true true double 0.2 false true true true double 0.2 false true true true int 500 false true true true int 200000 true true false true int 1 true true false true int 4 false true true true double 35.0 false true true true double 13.75 false true true true double 13.75 false true true true double 7.8 false true true true double 300.0 false true true true double 2.5 false true false true double 15.0 false true true true int 4 false true true true double 37.5 false true true true double 7.5 false true true true double 7.5 false true true true boolean false true true false true int 10 true true false true int 8 true true false true int 1 true true false true int 1 true true false true int 27 true false false true int 8 true true false true int 64 true false false true int 8 true true false true int 8 true true false true int 3 true true false true boolean false true true false true boolean false true true false true int 2 true true false true boolean true true true false true boolean false true true false true int 1 true true false true int 1 true true false true boolean false true true false true boolean false true true false true java.lang.String nextgen_v110 true true false true int 4 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 32 true true false true int 8 true true false true int 0 true true false true int 10 true true false true int 5 true true false true int 10 true true false true int 512 true true false true int 1 true true false true int 1 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true boolean false true true false true boolean false true true false true int 0 true true false true int 0 true true false true boolean false true true false true int 10 true true false true int 0 true true false true [Ljava.lang.String; Port 0 true true false true int 1 true true false true int 1 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 1 true true false true int 1 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 1 true true false true int 1 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 1 true true false true int 1 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 1 true true false true int 1 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 1 true true false true int 1 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true [Ljava.lang.String; None,None,None,None,None,None true true false true [Ljava.lang.String; None,None,None,None,None,None true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String BL_8 true true false true java.lang.String DWIDTH_32 true true false true java.lang.String SELF_RFSH_EXIT_CYCLES_512 true true false true java.lang.String STARVE_LIMIT_10 true true false true java.lang.String DDR3 true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String NO_CLR_INTR true true false true java.lang.String FALSE true true false true java.lang.String FALSE true true false true java.lang.String FALSE true true false true java.lang.String FALSE true true false true java.lang.String FALSE true true false true java.lang.String FALSE true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String CHIP_ROW_BANK_COL true true false true java.lang.String CTL_ECC_DISABLED true true false true java.lang.String CTL_ECC_RMW_DISABLED true true false true java.lang.String REGDIMM_DISABLED true true false true java.lang.String CTL_USR_REFRESH_DISABLED true true false true java.lang.String DATA_WIDTH_64_BIT true true false true java.lang.String BONDING_LATENCY_0 true true false true java.lang.String DFX_BYPASS_DISABLED true true false true java.lang.String MERGING_ENABLED true true false true java.lang.String ECC_DQ_WIDTH_0 true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String ENABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String GEN_DBE_DISABLED true true false true java.lang.String GEN_SBE_DISABLED true true false true java.lang.String FIFO_SET_2 true true false true java.lang.String ADDR_WIDTH_0 true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String AL_0 true true false true java.lang.String ADDR_WIDTH_3 true true false true java.lang.String MEM_IF_BURSTLENGTH_8 true true false true java.lang.String ADDR_WIDTH_10 true true false true java.lang.String MEM_IF_CS_PER_RANK_1 true true false true java.lang.String MEM_IF_CS_WIDTH_1 true true false true java.lang.String MEM_IF_DQ_PER_CHIP_8 true true false true java.lang.String DQS_WIDTH_4 true true false true java.lang.String MEM_IF_DWIDTH_32 true true false true java.lang.String DDR3_SDRAM true true false true java.lang.String ADDR_WIDTH_15 true true false true java.lang.String DDR3_1600_8_8_8 true true false true java.lang.String TCCD_4 true true false true java.lang.String TCL_7 true true false true java.lang.String TCWL_7 true true false true java.lang.String TFAW_15 true true false true java.lang.String TMRD_4 true true false true java.lang.String TRAS_14 true true false true java.lang.String TRC_20 true true false true java.lang.String TRCD_6 true true false true java.lang.String TRP_6 true true false true java.lang.String TRRD_3 true true false true java.lang.String TRTP_3 true true false true java.lang.String TWR_6 true true false true java.lang.String TWTR_4 true true false true java.lang.String MP_BL_8 true true false true java.lang.String DISABLED true true false true java.lang.String SLOW_EXIT true true false true java.lang.String PORT_32_BIT true true false true java.lang.String PORT_32_BIT true true false true java.lang.String PORT_32_BIT true true false true java.lang.String PORT_32_BIT true true false true java.lang.String PORT_32_BIT true true false true java.lang.String PORT_32_BIT true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true java.lang.String WEIGHT_0 true true false true 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java.lang.String AUTO false true true true double 0.0 false true false true double 0.0 false true false true double 0.0 false true false true double 0.0 false true false true double 0.0 false true false true double 0.0 false true false true double 0.0 true true true true double 0.0 true true true true double 0.0 true true true true double 0.0 true true true true double 0.0 true true true true double 0.0 true true true true boolean false false true false true boolean false false true false true double 0.6 false true true true double 0.6 false true true true double -0.01 false true true true double -0.01 true true false true double 0.01 false true true true double 0.01 true true false true double 0.05 false true false true double 0.0 true true false true double 0.02 false true true true double 0.02 false true true true double 0.0 false true true true double 0.02 false true true true double 0.0 false true true true java.lang.String Full false true false true double 400.0 false true true true boolean false false true true true boolean true true true false true java.lang.String AUTO false true false true boolean false true true false true boolean false true true false true boolean false true true false true java.lang.String AUTO false true false true int 1 true true false true int 1 true true false true int 1 true true false true int 2 true true false true int 2 true true false true int 30 true true false true int 6 true true false true int 2 true true false true int 1 true true false true int 1 true true false true int 8 true true false true int 64 true true false true int 1 true true false true int 4 true true false true int 6 true true false true int 6 true true false true int 0 true true false true int 0 true true false true int 1 true true false true boolean false false true false true java.lang.String CYCLONEV false true false true DEVICE_FAMILY java.lang.String CYCLONEV true true false true java.lang.String Cyclone V true true false true boolean false true true false true boolean true true true false true boolean false false true false true java.lang.String false true false true java.lang.String false true false true java.lang.String 7 false true false true boolean false false true false true boolean false false true false true boolean true true true false true boolean true false true false true boolean true false true false true boolean false false true false true boolean false false true false true java.lang.String DDR3 false true true true boolean true false true false true boolean false false true false true java.lang.String EXPORT false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false true true false true boolean false true true false true java.lang.String meminit false true false true int 7 true true false true int 6 true true false true java.lang.String HIGH true true false true int 8 true true false true java.lang.String None false true false true int 1 false false false true int 16 true true false true java.lang.String None false true false true int 1 false false false true boolean false false true false true boolean false false true false true java.lang.String {320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000} true true false true boolean false false true false true java.lang.String {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000} false false false true boolean false false true false true boolean false false true false true double 25.0 false true true true int 25000000 true true false true double 25.0 false true true true int 25000000 true true false true boolean false false true true true boolean false false true true true int 0 false true false true CLOCK_RATE f2h_sdram_ref_clock double 0.0 true true true true int 0 false true false true CLOCK_RATE f2h_periph_ref_clock double 0.0 true true true true int 0 false true true true int 2 false false true true int 2 false false true true int 1 false false true true int 1 false true true true int 1 false true true true double 925.0 true true true true int 925000000 true true false true boolean true false true true true double 800.0 false false true true int 800000000 true false false true int 1 false true true true int 1 false true true true boolean true false true false true int 0 false true true true int 1 false true true true int 0 false true true true double 100.0 false true true true int 100000000 true true false true double 100.0 false true true true int 100000000 true true false true double 100.0 false true true true int 100000000 true true false true double 200.0 false false true true int 200000000 true false false true double 12.5 false false true true int 12500000 true false false true double 400.0 false false true true int 400000000 true false false true double 250.0 false false true true int 250000000 true false false true double 250.0 false false true true int 250000000 true false false true double 200.0 false false true true int 200000000 true false false true double 200.0 false false true true int 200000000 true false false true double 100.0 false false true true int 100000000 true false false true double 100.0 false false true true int 100000000 true false false true int 32000 false false true true boolean false false true true true boolean false false true true true boolean false false true true true double 100.0 true false true true int 100000000 true true false true double 100.0 false false true true int 100000000 true true false true double 100.0 false false false true int 100000000 true true false true int 5 false false true true int 73 true true true true int 0 true true true true int 1850000000 true true false true double 1850.0 true true true true int 1 true true true true int 4 true true true true int 4 true true true true int 511 true true true true int 511 true true true true int 18 true true true true int 63 false false true true int 0 false false true true int 1600000000 true true false true double 1600.0 true true true true int 1 true true true true int 4 true true true true int 4 true true true true int 3 false false true true int 3 false false true true int 15 false false true true int 925000000 true true false true double 925.0 true true true true int 370000000 true true false true double 370.0 true true true true int 25000000 true true false true double 25.0 true true true true int 3613281 true true false true double 3.613281 true true true true int 3613281 true true false true double 3.613281 true true true true int 97368421 true true false true double 97.368421 true true true true int 231250000 true true false true double 231.25 true true true true int 462500000 true true false true double 462.5 true true true true int 925000000 true true false true double 925.0 true true true true int 185000000 true true false true double 185.0 true true true true int 92500000 true true false true double 92.5 true true true true int 25000000 true true false true double 25.0 true true true true int 12500000 true true false true double 12.5 true true true true int 25000000 true true false true double 25.0 true true true true int 25000000 true true false true double 25.0 true true true true int 97368421 true true false true double 97.368421 true true true true int 97368421 true true false true double 97.368421 true true true true int 39 true true true true int 0 true true true true int 1000000000 true true false true double 1000.0 true true true true int 511 true true true true int 511 true true true true int 511 true true true true int 511 true true true true int 9 true true true true int 511 true true true true int 79 false false true true int 1 false false true true int 1000000000 true true false true double 1000.0 true true true true int 3 false false true true int 3 false false true true int 1 false false true true int 19 false false true true int 4 false false true true int 9 false false true true int 1953125 true true false true double 1.953125 true true true true int 1953125 true true false true double 1.953125 true true true true int 100000000 true true false true double 100.0 true true true true int 4 true true true true int 4 true true true true int 4 true true true true int 4 true true true true int 16777215 true true true true int 0 false false true true int 0 false false true true int 1 false false true true int 1 false false true true int 6249 false false true true int 1953125 true true false true double 1.953125 true true true true int 1953125 true true false true double 1.953125 true true true true int 1953125 true true false true double 1.953125 true true true true int 6250000 true true false true double 6.25 true true true true int 6250000 true true false true double 6.25 true true true true int 6250000 true true false true double 6.25 true true true true int 6250000 true true false true double 6.25 true true true true int 5 true true true true int 1 false false true true int 1 false false true true int 0 true true true true int 0 true true true true int 1953125 true true false true double 1.953125 true true true true int 1953125 true true false true double 1.953125 true true true true int 488281 true true false true double 0.488281 true true true true int 3613281 true true false true double 3.613281 true true true true int 100000000 true true false true double 100.0 true true true true int 100000000 true true false true double 100.0 true true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false false true true boolean false false true true true boolean false false true false true boolean false false true true true boolean false false false false true int 1 false false false true boolean false false false false true int 0 false false false true int 0 false true true true int 0 false true true true java.lang.String false false true true true [Ljava.lang.String; f2h_sdram0 true true true true [Ljava.lang.String; Avalon-MM Bidirectional false true true true [Ljava.lang.Integer; 64 false true true true java.lang.String 1 true true false true java.lang.String 0x1 true true false true java.lang.String 0x1 true true false true java.lang.String 0x1 true true false true java.lang.String 0x111 true true false true boolean false false false false true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true [Ljava.lang.String; 0,1,2,3,4,5,6,7 true true true true [Ljava.lang.String; No,No,No,No,No,No,No,No false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false false true true boolean false false false true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true java.lang.String Unused false true true true java.lang.String N/A false true true true [Ljava.lang.String; RGMII0_TX_CLK,RGMII0_TXD0,RGMII0_TXD1,RGMII0_TXD2,RGMII0_TXD3,RGMII0_RXD0,RGMII0_MDIO,RGMII0_MDC ,RGMII0_RX_CTL,RGMII0_TX_CTL,RGMII0_RX_CLK,RGMII0_RXD1,RGMII0_RXD2,RGMII0_RXD3,NAND_ALE,NAND_CE,NAND_CLE,NAND_RE,NAND_RB,NAND_DQ0,NAND_DQ1,NAND_DQ2,NAND_DQ3,NAND_DQ4,NAND_DQ5,NAND_DQ6,NAND_DQ7,NAND_WP,NAND_WE,QSPI_IO0,QSPI_IO1,QSPI_IO2,QSPI_IO3,QSPI_SS0,QSPI_CLK,QSPI_SS1,SDMMC_CMD,SDMMC_PWREN,SDMMC_D0,SDMMC_D1,SDMMC_D4,SDMMC_D5,SDMMC_D6,SDMMC_D7,HPS_GPIO44,SDMMC_CCLK_OUT,SDMMC_D2,SDMMC_D3,TRACE_CLK,TRACE_D0,TRACE_D1,TRACE_D2,TRACE_D3,TRACE_D4,TRACE_D5,TRACE_D6,TRACE_D7,SPIM0_CLK,SPIM0_MOSI,SPIM0_MISO,SPIM0_SS0,UART0_RX,UART0_TX,I2C0_SDA,I2C0_SCL,CAN0_RX,CAN0_TX true true false true [Ljava.lang.String; ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, true true false true [Ljava.lang.String; GPIO00,GPIO01,GPIO02,GPIO03,GPIO04,GPIO05,GPIO06,GPIO07,GPIO08,GPIO09,GPIO10,GPIO11,GPIO12,GPIO13,GPIO14,GPIO15,GPIO16,GPIO17,GPIO18,GPIO19,GPIO20,GPIO21,GPIO22,GPIO23,GPIO24,GPIO25,GPIO26,GPIO27,GPIO28,GPIO29,GPIO30,GPIO31,GPIO32,GPIO33,GPIO34,GPIO35,GPIO36,GPIO37,GPIO38,GPIO39,GPIO40,GPIO41,GPIO42,GPIO43,GPIO44,GPIO45,GPIO46,GPIO47,GPIO48,GPIO49,GPIO50,GPIO51,GPIO52,GPIO53,GPIO54,GPIO55,GPIO56,GPIO57,GPIO58,GPIO59,GPIO60,GPIO61,GPIO62,GPIO63,GPIO64,GPIO65,GPIO66 true true false true [Ljava.lang.String; No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No false true false true [Ljava.lang.String; LOANIO00,LOANIO01,LOANIO02,LOANIO03,LOANIO04,LOANIO05,LOANIO06,LOANIO07,LOANIO08,LOANIO09,LOANIO10,LOANIO11,LOANIO12,LOANIO13,LOANIO14,LOANIO15,LOANIO16,LOANIO17,LOANIO18,LOANIO19,LOANIO20,LOANIO21,LOANIO22,LOANIO23,LOANIO24,LOANIO25,LOANIO26,LOANIO27,LOANIO28,LOANIO29,LOANIO30,LOANIO31,LOANIO32,LOANIO33,LOANIO34,LOANIO35,LOANIO36,LOANIO37,LOANIO38,LOANIO39,LOANIO40,LOANIO41,LOANIO42,LOANIO43,LOANIO44,LOANIO45,LOANIO46,LOANIO47,LOANIO48,LOANIO49,LOANIO50,LOANIO51,LOANIO52,LOANIO53,LOANIO54,LOANIO55,LOANIO56,LOANIO57,LOANIO58,LOANIO59,LOANIO60,LOANIO61,LOANIO62,LOANIO63,LOANIO64,LOANIO65,LOANIO66 true true false true boolean false true true false true [Ljava.lang.String; No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No false true false true [Ljava.lang.String; No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No true true false true [Ljava.lang.String; EMACIO0,EMACIO1,EMACIO2,EMACIO3,EMACIO4,EMACIO5,EMACIO6,EMACIO7,EMACIO8,EMACIO9,EMACIO10,EMACIO11,EMACIO12,EMACIO13,MIXED1IO0,MIXED1IO1,MIXED1IO2,MIXED1IO3,MIXED1IO4,MIXED1IO5,MIXED1IO6,MIXED1IO7,MIXED1IO8,MIXED1IO9,MIXED1IO10,MIXED1IO11,MIXED1IO12,MIXED1IO13,MIXED1IO14,MIXED1IO15,MIXED1IO16,MIXED1IO17,MIXED1IO18,MIXED1IO19,MIXED1IO20,MIXED1IO21,FLASHIO0,FLASHIO1,FLASHIO2,FLASHIO3,FLASHIO4,FLASHIO5,FLASHIO6,FLASHIO7,FLASHIO8,FLASHIO9,FLASHIO10,FLASHIO11,GENERALIO0,GENERALIO1,GENERALIO2,GENERALIO3,GENERALIO4,GENERALIO5,GENERALIO6,GENERALIO7,GENERALIO8,GENERALIO9,GENERALIO10,GENERALIO11,GENERALIO12,GENERALIO13,GENERALIO14,GENERALIO15,GENERALIO16,GENERALIO17,GENERALIO18 true true false true java.lang.String EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} true true false true java.lang.String EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} true true false true java.lang.String NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} true true false true java.lang.String QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} true true false true java.lang.String SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} true true false true java.lang.String USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} true true false true java.lang.String USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}} true true false true java.lang.String SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} true true false true java.lang.String SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} true true false true java.lang.String SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} true true false true java.lang.String SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} true true false true java.lang.String UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} true true false true java.lang.String UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} true true false true java.lang.String I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} true true false true java.lang.String I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} true true false true java.lang.String I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} true true false true java.lang.String I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} true true false true java.lang.String CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} true true false true java.lang.String CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} true true false true java.lang.String TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} true true false true int 100 false true false true CLOCK_RATE f2h_axi_clock int 100 false true false true CLOCK_RATE h2f_axi_clock int 100 false true false true CLOCK_RATE h2f_lw_axi_clock int 50000000 false true false true CLOCK_RATE f2h_sdram0_clock int 100 false true false true CLOCK_RATE f2h_sdram1_clock int 100 false true false true CLOCK_RATE f2h_sdram2_clock int 100 false true false true CLOCK_RATE f2h_sdram3_clock int 100 false true false true CLOCK_RATE f2h_sdram4_clock int 100 false true false true CLOCK_RATE f2h_sdram5_clock int 100 false true false true CLOCK_RATE h2f_cti_clock int 100 false true false true CLOCK_RATE h2f_tpiu_clock_in int 100 false true false true CLOCK_RATE h2f_debug_apb_clock int 100 false true false true CLOCK_RATE emac_ptp_ref_clock int 100 false true false true CLOCK_RATE emac0_rx_clk_in int 100 false true false true CLOCK_RATE emac0_tx_clk_in double 2.5 false false true true int 125 false false true true int 100 false true false true CLOCK_RATE emac1_rx_clk_in int 100 false true false true CLOCK_RATE emac1_tx_clk_in double 2.5 false false true true int 125 false false true true int 100 false false true true int 100 false true false true int 100 false true false true CLOCK_RATE usb0_clk_in int 100 false true false true CLOCK_RATE usb1_clk_in int 100 false false true true int 100 false false true true int 100 false true false true CLOCK_RATE spis0_sclk_in int 100 false true false true CLOCK_RATE spis1_sclk_in int 100 false true false true CLOCK_RATE i2c0_scl_in int 100 false false true true int 100 false true false true CLOCK_RATE i2c1_scl_in int 100 false false true true int 100 false true false true CLOCK_RATE i2c2_scl_in int 100 false false true true int 100 false true false true CLOCK_RATE i2c3_scl_in int 100 false false true true java.lang.String Cyclone V true true false true java.lang.String 5CSEMA4U23C6 false true false true DEVICE boolean false false true false true QUARTUS_INI hps_ip_enable_all_peripheral_fpga_interfaces boolean false false true false true QUARTUS_INI hps_ip_enable_emac0_peripheral_fpga_interface boolean false false true false true QUARTUS_INI hps_ip_enable_test_interface boolean false false true false true QUARTUS_INI hps_ip_fast_f2sdram_sim_model boolean false false true false true QUARTUS_INI hps_ip_suppress_sdram_synth boolean false false true false true QUARTUS_INI hps_ip_enable_low_speed_serial_fpga_interfaces boolean false false true false true QUARTUS_INI hps_ip_enable_bsel_csel boolean false false true false true QUARTUS_INI hps_ip_enable_f2sdram_bonding_out boolean false false true false true QUARTUS_INI hps_emif_pll java.lang.String DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output true true false true java.lang.String USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}} true true false true java.lang.String can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}} true true false true java.lang.String i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd} true true false true java.lang.String true true false true java.lang.String {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS} true true false true java.lang.String Cyclone V+5CSEMA4U23C6 true true false true java.lang.String 6 false true false true DEVICE_SPEEDGRADE java.lang.String UNKNOWN false true true true boolean false false true true true qsys.ui.export_name memory ui.blockdiagram.direction output java.lang.String false true true true java.lang.String false true true true java.lang.String UNKNOWN false true true true boolean false false true true true conduit false mem_a Output 15 mem_a mem_ba Output 3 mem_ba mem_ck Output 1 mem_ck mem_ck_n Output 1 mem_ck_n mem_cke Output 1 mem_cke mem_cs_n Output 1 mem_cs_n mem_ras_n Output 1 mem_ras_n mem_cas_n Output 1 mem_cas_n mem_we_n Output 1 mem_we_n mem_reset_n Output 1 mem_reset_n mem_dq Bidir 32 mem_dq mem_dqs Bidir 4 mem_dqs mem_dqs_n Bidir 4 mem_dqs_n mem_odt Output 1 mem_odt mem_dm Output 4 mem_dm oct_rzqin Input 1 oct_rzqin java.lang.String false true true true java.lang.String false true true true [Ljava.lang.String; none false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset true h2f_rst_n Output 1 reset_n boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 50000000 true true false true clock false f2h_sdram0_clk Input 1 clk embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment DYNAMIC false true false true int 0 false true false true java.math.BigInteger 4294967296 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String f2h_sdram0_clock false true true true java.lang.String h2f_reset false true true true int 8 false true true true java.math.BigInteger 0 false true false true com.altera.entityinterfaces.IConnectionPoint false true false true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false false true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 14 false true true true int 0 false false true true int 1 false true false true boolean false false true false true int 0 false false true true int 1 false true false true int 1 false false true true boolean false false true false true boolean false false true false true int 0 false false true true com.altera.sopcmodel.avalon.TimingUnits Cycles false false true true boolean false false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false false true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon false f2h_sdram0_ADDRESS Input 29 address f2h_sdram0_BURSTCOUNT Input 8 burstcount f2h_sdram0_WAITREQUEST Output 1 waitrequest f2h_sdram0_READDATA Output 64 readdata f2h_sdram0_READDATAVALID Output 1 readdatavalid f2h_sdram0_READ Input 1 read f2h_sdram0_WRITEDATA Input 64 writedata f2h_sdram0_BYTEENABLE Input 8 byteenable f2h_sdram0_WRITE Input 1 write postgeneration.simulation.init_file.param_name ABS_RAM_MEM_INIT_FILENAME postgeneration.simulation.init_file.type MEM_INIT java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true boolean false true true false true int 2 true true false true int 0 true true false true int 3 true true false true int 1 true true false true int 4 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 1 true true false true int 2 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 10 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 8 true true false true boolean true true true false true int 0 true true true true int 0 true true false true int -1 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 1 true true false true double 2.5 true true false true double 2500.0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 6 true true false true boolean true true true false true boolean false true true false true boolean false true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 3 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true boolean false true true false true boolean false true true false true java.lang.String Other false true true true java.lang.String DISCRETE false true true true boolean false true false true true java.lang.String 0000000000000000 false true true true java.lang.String 0x000000000000000000 false true true true boolean true false true true true int 1 false true true true java.lang.String 0 false true true true double 800.0 false true true true int 15 false true true true int 10 false true true true int 32 false true true true int 8 false true true true int 3 false true true true boolean true false true true true boolean true false true true true int 1 false true true true int 1 false true true true int 1 false true true true int 1 false true false true int 1 false true true true int 1 false true false true int 1 false true false true boolean false false true false true boolean true false true false true int 10 false true false true int 0 false true false true boolean false false true false true boolean true false true true true boolean false false true false true boolean false false true false true boolean false false true false true java.math.BigInteger 0 false true false true boolean false false true false true java.lang.String OTF false true false true java.lang.String Sequential false true true true java.lang.String Manual false true true true java.lang.String Normal false true true true java.lang.String DLL off false true true true java.lang.String RZQ/6 false true true true boolean true false true false true java.lang.String RZQ/6 false true true true java.lang.String Dynamic ODT off false true true true int 7 false true true true java.lang.String Disabled false true true true int 7 false true true true boolean true false true false true java.lang.String Leveling false true false true boolean false false true false true java.lang.String false true false true int 32 false true false true int 175 false true true true int 250 false true true true int 50 false true true true int 125 false true true true int 120 false true true true int 300 false true true true double 0.38 false true true true int 400 false true true true int 450 false true true true int 900 false true true true int 1200 false true true true double 0.25 false true true true double 0.35 false true true true double 0.38 false true true true double 0.2 false true true true double 0.2 false true true true int 500 false true true true int 499 true true false true int 2 true true false true int 4 false true true true double 35.0 false true true true double 13.75 false true true true double 13.75 false true true true double 7.8 false true true true double 300.0 false true true true double 2.5 false true false true double 15.0 false true true true int 4 false true true true double 37.5 false true true true double 7.5 false true true true double 7.5 false true true true boolean false true true false true int 8 true true false true int 32 true true false true int 4 true true false true int 0 true true false true int 0 true false true true int 0 true true false true int 0 true false true true int 8 true true false true int 2 true true false true int 0 true true false true boolean false true true false true boolean false true true false true int 4 true true false true boolean false true true false true boolean false true true false true int 0 true true false true int 0 true true false true boolean false true true false true boolean false true true false true java.lang.String nextgen_v110 true true false true int 4 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true boolean false true true false true boolean false true true false true int 0 true true false true int 0 true true false true boolean false true true false true int 0 true true false true int 0 true true false true [Ljava.lang.String; true true true true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true [Ljava.lang.String; 0,None,None,None,None,None true true true true [Ljava.lang.String; 0,None,None,None,None,None true true true true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String BL_8 true true false true java.lang.String DWIDTH_32 true true false true java.lang.String true true false true java.lang.String STARVE_LIMIT_32 true true false true java.lang.String DDR3 true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String NO_CLR_INTR true true false true java.lang.String FALSE true true false true java.lang.String FALSE true true false true java.lang.String FALSE true true false true java.lang.String FALSE true true false true java.lang.String FALSE true true false true java.lang.String FALSE true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String NOT_FULL true true false true java.lang.String FIFO_0 true true false true java.lang.String DISABLE true true false true java.lang.String FIFO_0 true true false true java.lang.String CHIP_BANK_ROW_COL true true false true java.lang.String CTL_ECC_DISABLED true true false true java.lang.String CTL_ECC_RMW_DISABLED true true false true java.lang.String REGDIMM_DISABLED true true false true java.lang.String CTL_USR_REFRESH_DISABLED true true false true java.lang.String DATA_WIDTH_64_BIT true true false true java.lang.String BONDING_LATENCY_0 true true false true java.lang.String DFX_BYPASS_DISABLED true true false true java.lang.String MERGING_ENABLED true true false true java.lang.String ECC_DQ_WIDTH_0 true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String 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true java.lang.String None false true true true int 1 false true true true java.lang.String instances {boot_from_fpga {entity_name cyclonev_hps_interface_boot_from_fpga location HPSINTERFACEBOOTFROMFPGA_X32_Y46_N111 signal_widths {boot_from_fpga_ready 1 boot_from_fpga_on_failure 1 bsel_en 1 csel_en 1 csel 2 bsel 3} signal_terminations {boot_from_fpga_ready {0:0 0} boot_from_fpga_on_failure {0:0 0} bsel_en {0:0 0} csel_en {0:0 0} csel {1:0 1} bsel {2:0 1}} parameters {} signal_default_terminations {boot_from_fpga_ready 0 boot_from_fpga_on_failure 0 bsel_en 0 csel_en 0 csel 0 bsel 0}} tpiu {entity_name cyclonev_hps_interface_tpiu_trace location HPSINTERFACETPIUTRACE_X32_Y18_N111 signal_widths {traceclk_ctl 1} parameters {} signal_terminations {traceclk_ctl {0:0 1}} signal_default_terminations {traceclk_ctl 1}} clocks_resets {entity_name cyclonev_hps_interface_clocks_resets location HPSINTERFACECLOCKSRESETS_X32_Y50_N111 signal_widths {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 1 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 1} signal_terminations {f2h_warm_rst_req_n {0:0 1} f2h_pending_rst_ack {0:0 1} f2h_sdram_ref_clk {} f2h_dbg_rst_req_n {0:0 1} f2h_cold_rst_req_n {0:0 1} f2h_periph_ref_clk {}} parameters {} signal_default_terminations {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 0 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 0}} @orderednames {clocks_resets debug_apb tpiu boot_from_fpga} debug_apb {entity_name cyclonev_hps_interface_dbg_apb location HPSINTERFACEDBGAPB_X32_Y53_N111 signal_widths {DBG_APB_DISABLE 1 P_CLK_EN 1} signal_terminations {DBG_APB_DISABLE {0:0 0} P_CLK_EN {0:0 0}} parameters {} signal_default_terminations {DBG_APB_DISABLE 0 P_CLK_EN 0}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {} properties {} bfm_types {} intermediate_wire_count 0 wires_to_fragments {} interfaces {@orderednames h2f_reset h2f_reset {properties {associatedResetSinks none synchronousEdges none} type reset direction Output signals {@orderednames h2f_rst_n h2f_rst_n {fragments {} properties {} internal_name h2f_rst_n width 1 instance_name clocks_resets direction Output role reset_n}}}} raw_assign_sim_style {} false true true true java.lang.String false true true true boolean false false true true true java.lang.String false true true true java.lang.String 5CSEMA4U23C6 false true false true DEVICE java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.String false true true true java.lang.String false true true true [Ljava.lang.String; none false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset true h2f_rst_n Output 1 reset_n postgeneration.simulation.init_file.param_name ABS_RAM_MEM_INIT_FILENAME postgeneration.simulation.init_file.type MEM_INIT java.lang.String instances {hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames hps_sdram_inst} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 0 wires_to_fragments {} interfaces {@orderednames memory memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}}} raw_assign_sim_style {} false true true true java.lang.String AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 100000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED f2h_sdram0 PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA4U23C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 120 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.6 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing Unused sdmmc_clk_hz 1953125 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode N/A NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 511 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x1 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.02 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 6.25 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 175 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.6 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 250 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 4 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing Unused desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 6250000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_7 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 1.953125 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x111 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 50 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {{Avalon-MM Bidirectional}} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 125 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 periph_nand_sdmmc_clk_mhz 1.953125 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000100100 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode N/A IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 6250000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN -0.01 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 6250000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode N/A S2FCLK_USER0CLK_FREQ_HZ 100000000 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 511 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x1 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 7 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode N/A hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 50000000 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 100.0 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/6 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.01 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 0 MEM_TCL 7 GPIO_Pin_Used_DERIVED false JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 120 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 488281 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable false desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width 64 dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.2 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 511 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 4 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 1.953125 PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 6.25 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.01 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 1.953125 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.325 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_15 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011001000 H2F_AXI_CLOCK_FREQ 100 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/6 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.5 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 37.5 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing Unused MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_7 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR Other device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing Unused CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_3 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 0 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 100.0 MR2_CWL 2 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 181 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 6.25 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 0 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 5 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 3 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR {Dynamic ODT off} TIMING_TDQSCK 400 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010100110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001001001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 8 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing Unused MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED -0.01 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 6 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 100 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.225 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} emac1_clk_mhz 1.953125 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.02 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 0 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.02 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 3 H2F_LW_AXI_CLOCK_FREQ 100 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 0 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 6250000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 1953125 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 2 periph_base_clk_mhz 100.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 7 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.35 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing Unused INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 desired_cfg_clk_hz 100000000 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 1953125 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 15 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 7 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 1953125 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 16777215 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0000000001000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x1 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode N/A quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 9 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 300.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 3 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 0 pin_muxing_check {Cyclone V+5CSEMA4U23C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 1953125 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 1 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 0.488281 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {}} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 7 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0000000010000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000001000100 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010000110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 6.25 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 1 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing Unused CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode N/A ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.38 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable false SDIO_Mode N/A desired_qspi_clk_mhz 400.0 MEM_TRFC 120 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2 false true true true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true java.lang.String true true false true boolean false true true false true int 2 true true false true int 0 true true false true int 3 true true false true int 1 true true false true int 4 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 1 true true false true int 2 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 10 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 8 true true false true boolean true true true false true int 0 true true true true int 0 true true false true int -1 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 1 true true false true int 1 true true false true double 2.5 true true false true double 2500.0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 6 true true false true boolean true true true false true boolean false true true false true boolean false true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 3 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true boolean false true true false true boolean false true true false true java.lang.String Other false true true true java.lang.String DISCRETE false true true true boolean false true false true true java.lang.String 0000000000000000 false true true true java.lang.String 0x000000000000000000 false true true true boolean true false true true true int 1 false true true true java.lang.String 0 false true true true double 800.0 false true true true int 15 false true true true int 10 false true true true int 32 false true true true int 8 false true true true int 3 false true true true boolean true false true true true boolean true false true true true int 1 false true true true int 1 false true true true int 1 false true true true int 1 false true false true int 1 false true true true int 1 false true false true int 1 false true false true boolean false false true false true boolean true false true false true int 10 false true false true int 0 false true false true boolean false false true false true boolean true false true true true boolean false false true false true boolean false false true false true boolean false false true false true java.math.BigInteger 0 false true false true boolean false false true false true java.lang.String OTF false true false true java.lang.String Sequential false true true true java.lang.String Manual false true true true java.lang.String Normal false true true true java.lang.String DLL off false true true true java.lang.String RZQ/6 false true true true boolean true false true false true java.lang.String RZQ/6 false true true true java.lang.String Dynamic ODT off false true true true int 7 false true true true java.lang.String Disabled false true true true int 7 false true true true boolean true false true false true java.lang.String Leveling false true false true boolean false false true false true java.lang.String false true false true int 32 false true false true int 175 false true true true int 250 false true true true int 50 false true true true int 125 false true true true int 120 false true true true int 300 false true true true double 0.38 false true true true int 400 false true true true int 450 false true true true int 900 false true true true int 1200 false true true true double 0.25 false true true true double 0.35 false true true true double 0.38 false true true true double 0.2 false true true true double 0.2 false true true true int 500 false true true true int 499 true true false true int 2 true true false true int 4 false true true true double 35.0 false true true true double 13.75 false true true true double 13.75 false true true true double 7.8 false true true true double 300.0 false true true true double 2.5 false true false true double 15.0 false true true true int 4 false true true true double 37.5 false true true true double 7.5 false true true true double 7.5 false true true true boolean false true true false true int 8 true true false true int 32 true true false true int 4 true true false true int 0 true true false true int 0 true false true true int 0 true true false true int 0 true false true true int 8 true true false true int 2 true true false true int 0 true true false true boolean false true true false true boolean false true true false true int 4 true true false true boolean false true true false true boolean false true true false true int 0 true true false true int 0 true true false true boolean false true true false true boolean false true true false true java.lang.String nextgen_v110 true true false true int 4 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true boolean false true true false true boolean false true true false true int 0 true true false true int 0 true true false true boolean false true true false true int 0 true true false true int 0 true true false true [Ljava.lang.String; true true true true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 5 true true false true int 5 true true false true int 5 true true false true int 5 true true false true [Ljava.lang.String; 0,None,None,None,None,None true true true true [Ljava.lang.String; 0,None,None,None,None,None true true true true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String BL_8 true true false true java.lang.String DWIDTH_32 true true false true java.lang.String true true false true java.lang.String STARVE_LIMIT_32 true true false true java.lang.String DDR3 true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String DISABLED true true false true java.lang.String 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true true false true double 0.0 true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true int 0 true true false true double 0.0 true true false true java.lang.String true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true int 0 true true false true double 0.0 true true false true java.lang.String true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true int 0 true true false true double 0.0 true true false true java.lang.String true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true int 0 true true false true double 0.0 true true false true java.lang.String true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true int 0 true true false true double 0.0 true true false true java.lang.String true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true int 0 true true false true double 0.0 true true false true java.lang.String true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true int 0 true true false true double 0.0 true true false true java.lang.String true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true int 0 true true false true double 0.0 true true false true java.lang.String true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true java.lang.String true true false true double 0.0 true true false true int 0 true true false true int 0 true true false true boolean false true true false true boolean false false true false true double 0.0 false true false true double 0.0 false true false true double 0.0 true true false true double 0.0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true double 0.0 false true false true java.lang.String false true false true int 0 false true false true java.lang.String false true false true int 0 false true false true int 0 false true false true double 0.0 true true false true java.lang.String true true false true int 0 true true false true java.lang.String true true false true int 0 true true false true int 0 true true false true java.lang.String true true false true boolean false true true false true double 0.0 true true false true double 0.0 true true false true java.lang.String Unknown true true false true boolean false true true false true java.lang.String Unknown true true false true double 0.0 true true false true double 0.0 true true false true double 0.0 true true false true double 0.0 true true false true double 0.0 true true false true java.lang.String Unknown true true false true boolean false true true false true boolean false true true false true boolean false false true false true boolean false false true false true int 10 false true false true boolean false false true false true int 8 false true false true boolean false false true false true java.lang.String None false true true true int 1 false true true true boolean false false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false true true false true boolean false false true false true int 0 false true false true boolean false true true false true boolean false false true false true int 8 false true false true boolean false true true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true java.lang.String 0_0000_0000_0000 false true false true java.lang.String 0_0000_0000_1000 false true false true int 35100 false true false true int 15000 false true false true boolean false false true false true int 350 false true false true boolean false false true false true java.lang.String false true false true java.lang.String MISSING_MODEL false true false true java.lang.String false true false true int 0 true true false true int 0 true true false true int 0 true true false true int 4 true true false true int 0 true true false true int 0 true true false true int 0 false true false true int 0 true true false true boolean false true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 2 true true false true int 9000 true true false true int 2 true true false true int 3 true true false true int 3 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true boolean false true true false true double 0.0 true true false true double 0.0 true true false true int -1 true true false true int -1 true true false true int -1 true true false true int -1 true true false true int -1 true true false true int -1 true true false true int -1 true true false true int -1 true true false true int -1 true true false true int -1 true true false true java.lang.String true true true true boolean false true true false true java.lang.String NIOS false true false true java.lang.String true true false true boolean false false true false true boolean false true true false true int 0 true true false true int 0 true true false true boolean false true true false true boolean false true true false true boolean false true true false true boolean false true true false true int 0 true true false true boolean true true true false true int 0 true true false true boolean false false true false true boolean false true true false true boolean false true true false true boolean false true true false true boolean false true true false true boolean false false true true true int 0 false true false true boolean false false true true true double 0.0 false true true true double 0.0 false true true true double 0.0 false true true true double 0.0 false true true true double 0.0 false true true true java.lang.String 1.5V DDR3 false true true true java.lang.String Top_Bottom false true true true boolean true false true true true java.lang.String INVERTED_DQS_BUS false true false true boolean false false true false true java.lang.String DIFFERENTIAL false true false true int 32 false true false true java.lang.String Skip false true true true int 32 false true false true int 13 true true false true int 8 false true false true boolean false false true true true java.lang.String INTERNAL_JTAG false true true true java.lang.String 1 false true true true java.lang.String AUTO false true true true double 2.0 false true true true double 1.0 false true true true double 2.0 false true true true double 1.0 false true true true double 2.0 true true true true double 1.0 true true true true double 2.0 true true true true double 1.0 true true true true double 0.0 false true true true double 0.0 false true true true double 0.0 false true true true double 0.0 false true true true double 0.0 true true true true double 0.0 true true true true double 0.0 true true true true double 0.0 true true true true java.lang.String AUTO false true true true double 0.0 false true true true double 0.0 false true true true double 0.0 false true true true double 0.0 false true true true double 0.0 false true true true double 0.0 false true true true double 0.0 true true true true double 0.0 true true true true double 0.0 true true true true double 0.0 true true true true double 0.0 true true true true double 0.0 true true true true boolean false false true false true boolean false false true false true double 0.6 false true true true double 0.6 false true true true double -0.01 false true true true double -0.01 true true false true double 0.01 false true true true double 0.01 true true false true double 0.05 false true true true double 0.05 true true false true double 0.02 false true true true double 0.02 false true true true double 0.0 false true true true double 0.02 false true true true double 0.0 false true true true java.lang.String Full false true true true double 400.0 false true true true boolean false false true false true boolean false true true false true java.lang.String AUTO false true false true boolean false true true false true boolean false true true false true boolean false true true false true java.lang.String AUTO false true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true int 0 true true false true boolean false false true false true java.lang.String CYCLONEV false true false true DEVICE_FAMILY java.lang.String true true false true java.lang.String true true false true boolean false true true false true boolean false true true false true boolean false false true false true java.lang.String false true false true java.lang.String false true false true java.lang.String 7 false true true true boolean false false true false true boolean false false true false true boolean false true true false true boolean true false true false true boolean true false true false true boolean false false true false true boolean false false true false true java.lang.String DDR3 false true true true boolean true false true false true boolean false false true true true java.lang.String EXPORT false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true boolean false true true false true boolean false true true false true java.lang.String meminit false true false true int 6 true true false true int 6 true true false true java.lang.String HIGH true true false true int 8 true true false true java.lang.String None false true true true int 1 false true true true int 14 true true false true java.lang.String None false true true true int 1 false true true true java.lang.String 5CSEMA4U23C6 false true false true DEVICE java.lang.String 6 false true false true DEVICE_SPEEDGRADE java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.String false true true true java.lang.String false true true true java.lang.String UNKNOWN false true true true boolean false false true true true conduit false mem_a Output 15 mem_a mem_ba Output 3 mem_ba mem_ck Output 1 mem_ck mem_ck_n Output 1 mem_ck_n mem_cke Output 1 mem_cke mem_cs_n Output 1 mem_cs_n mem_ras_n Output 1 mem_ras_n mem_cas_n Output 1 mem_cas_n mem_we_n Output 1 mem_we_n mem_reset_n Output 1 mem_reset_n mem_dq Bidir 32 mem_dq mem_dqs Bidir 4 mem_dqs mem_dqs_n Bidir 4 mem_dqs_n mem_odt Output 1 mem_odt mem_dm Output 4 mem_dm oct_rzqin Input 1 oct_rzqin java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.String clk false true true true java.lang.String false true true true [Ljava.lang.String; false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset true new_signal_13 Output 1 reset java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true new_signal_14 Output 1 clk false hps_0_bridges clock_sink hps_0_bridges.clock_sink false hps_0_arm_a9_0 clock_sink hps_0_arm_a9_0.clock_sink false hps_0_arm_a9_1 clock_sink hps_0_arm_a9_1.clock_sink false hps_0_arm_gic_0 clock_sink hps_0_arm_gic_0.clock_sink false hps_0_L2 clock_sink hps_0_L2.clock_sink false hps_0_sysmgr clock_sink hps_0_sysmgr.clock_sink false hps_0_rstmgr clock_sink hps_0_rstmgr.clock_sink false hps_0_fpgamgr clock_sink hps_0_fpgamgr.clock_sink false hps_0_l3regs clock_sink hps_0_l3regs.clock_sink false hps_0_sdrctl clock_sink hps_0_sdrctl.clock_sink false hps_0_axi_ocram clock_sink hps_0_axi_ocram.clock_sink false hps_0_axi_sdram clock_sink hps_0_axi_sdram.clock_sink false hps_0_scu clock_sink hps_0_scu.clock_sink embeddedsw.dts.compatible simple-bus embeddedsw.dts.group bridge embeddedsw.dts.name bridge embeddedsw.dts.vendor altr java.lang.String false true true true ADDRESS_MAP axi_f2h int 0 false true true true int 0 false true true true java.lang.String false false true true true [Ljava.lang.Integer; 64 false true true true [Ljava.lang.Integer; 1 false true true true boolean false false true true true boolean false false true true true int 50000000 false true false true CLOCK_RATE f2h_sdram0_clock int 100 false true false true CLOCK_RATE f2h_sdram1_clock int 100 false true false true CLOCK_RATE f2h_sdram2_clock int 100 false true false true CLOCK_RATE f2h_sdram3_clock int 100 false true false true CLOCK_RATE f2h_sdram4_clock int 100 false true false true CLOCK_RATE f2h_sdram5_clock java.lang.String UNKNOWN false true true true boolean false false true true true addressSpan 536870912 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 16 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 536870912 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 29 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 29 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp addressSpan 2097152 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 2097152 true true false true axi false axi_sig1_40 Input 1 awvalid axi_sig1_41 Output 1 awready axi_sig1_42 Input 12 awid axi_sig1_43 Input 21 awaddr axi_sig1_44 Input 4 awlen axi_sig1_45 Input 3 awsize axi_sig1_46 Input 2 awburst axi_sig1_47 Input 2 awlock axi_sig1_48 Input 4 awcache axi_sig1_49 Input 3 awprot axi_sig1_50 Input 1 awuser axi_sig1_51 Input 1 arvalid axi_sig1_52 Output 1 arready axi_sig1_53 Input 12 arid axi_sig1_54 Input 21 araddr axi_sig1_55 Input 4 arlen axi_sig1_56 Input 3 arsize axi_sig1_57 Input 2 arburst axi_sig1_58 Input 2 arlock axi_sig1_59 Input 4 arcache axi_sig1_60 Input 3 arprot axi_sig1_61 Input 1 aruser axi_sig1_62 Input 1 wvalid axi_sig1_63 Output 1 wready axi_sig1_64 Input 12 wid axi_sig1_65 Input 1 wlast axi_sig1_66 Input 32 wdata axi_sig1_67 Input 4 wstrb axi_sig1_68 Output 1 rvalid axi_sig1_69 Input 1 rready axi_sig1_70 Output 12 rid axi_sig1_71 Output 1 rlast axi_sig1_72 Output 2 rresp axi_sig1_73 Output 32 rdata axi_sig1_74 Output 1 bvalid axi_sig1_75 Input 1 bready axi_sig1_76 Output 12 bid axi_sig1_77 Output 2 bresp java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true axi true axi_master_sig Output 1 awvalid axi_master_sig_1 Input 1 awready axi_master_sig_2 Output 1 awid axi_master_sig_3 Output 32 awaddr axi_master_sig_4 Output 4 awlen axi_master_sig_5 Output 3 awsize axi_master_sig_6 Output 2 awburst axi_master_sig_7 Output 2 awlock axi_master_sig_8 Output 4 awcache axi_master_sig_9 Output 3 awprot axi_master_sig_10 Output 1 awuser axi_master_sig_11 Output 1 arvalid axi_master_sig_12 Input 1 arready axi_master_sig_14 Output 32 araddr axi_master_sig_15 Output 4 arlen axi_master_sig_16 Output 3 arsize axi_master_sig_17 Output 2 arburst axi_master_sig_18 Output 2 arlock axi_master_sig_19 Output 4 arcache axi_master_sig_20 Output 3 arprot axi_master_sig_21 Output 1 aruser axi_master_sig_13 Output 1 arid axi_master_sig_24 Input 1 bid axi_master_sig_25 Input 1 rid axi_master_sig_26 Output 1 wid axi_master_sig_27 Output 1 wvalid axi_master_sig_28 Input 1 wready axi_master_sig_29 Output 1 wlast axi_master_sig_30 Output 32 wdata axi_master_sig_31 Output 4 wstrb axi_master_sig_32 Input 1 rvalid axi_master_sig_33 Output 1 rready axi_master_sig_34 Input 1 rlast axi_master_sig_35 Input 2 rresp axi_master_sig_36 Input 32 rdata axi_master_sig_37 Input 1 bvalid axi_master_sig_38 Output 1 bready axi_master_sig_39 Input 2 bresp java.lang.String false true true true java.lang.String false true true true [Ljava.lang.String; none false true true true com.altera.sopcmodel.reset.Reset$Edges NONE false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset true h2f_rst_n Output 1 reset_n java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false new_signal_13 Input 1 reset boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false new_signal_14 Input 1 clk embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment DYNAMIC false true false true int 0 false true false true java.math.BigInteger 4294967296 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String f2h_sdram0_clock false true true true java.lang.String h2f_reset false true true true int 8 false true true true java.math.BigInteger false true false true com.altera.entityinterfaces.IConnectionPoint false true false true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false false true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 14 false true true true int 0 false false true true int 1 false true false true boolean false false true false true int 0 false false true true int 1 false true false true int 1 false false true true boolean false false true false true boolean false false true false true int 0 false false true true com.altera.sopcmodel.avalon.TimingUnits Cycles false false true true boolean false false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false false true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon false f2h_sdram0_ADDRESS Input 29 address f2h_sdram0_BURSTCOUNT Input 8 burstcount f2h_sdram0_WAITREQUEST Output 1 waitrequest f2h_sdram0_READDATA Output 64 readdata f2h_sdram0_READDATAVALID Output 1 readdatavalid f2h_sdram0_READ Input 1 read f2h_sdram0_WRITEDATA Input 64 writedata f2h_sdram0_BYTEENABLE Input 8 byteenable f2h_sdram0_WRITE Input 1 write boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 50000000 true true false true clock false f2h_sdram0_clk Input 1 clk embeddedsw.dts.compatible fixed-clock embeddedsw.dts.group clock embeddedsw.dts.vendor altr long 25000000 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.String clk false true true true java.lang.String false true true true [Ljava.lang.String; false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset true new_signal_13 Output 1 reset java.lang.String false true true true long 25000000 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true new_signal_14 Output 1 clk false hps_0_clkmgr eosc1 hps_0_clkmgr.eosc1 false hps_0_timer2 clock_sink hps_0_timer2.clock_sink false hps_0_timer3 clock_sink hps_0_timer3.clock_sink false hps_0_wd_timer0 clock_sink hps_0_wd_timer0.clock_sink embeddedsw.dts.compatible fixed-clock embeddedsw.dts.group clock embeddedsw.dts.vendor altr long 25000000 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.String clk false true true true java.lang.String false true true true [Ljava.lang.String; false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset true new_signal_13 Output 1 reset java.lang.String false true true true long 25000000 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true new_signal_14 Output 1 clk false hps_0_clkmgr eosc2 hps_0_clkmgr.eosc2 embeddedsw.dts.compatible fixed-clock embeddedsw.dts.group clock embeddedsw.dts.vendor altr long 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.String clk false true true true java.lang.String false true true true [Ljava.lang.String; false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset true new_signal_13 Output 1 reset java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true new_signal_14 Output 1 clk false hps_0_clkmgr f2s_periph_ref_clk hps_0_clkmgr.f2s_periph_ref_clk embeddedsw.dts.compatible fixed-clock embeddedsw.dts.group clock embeddedsw.dts.vendor altr long 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.String clk false true true true java.lang.String false true true true [Ljava.lang.String; false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset true new_signal_13 Output 1 reset java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true new_signal_14 Output 1 clk false hps_0_clkmgr f2s_sdram_ref_clk hps_0_clkmgr.f2s_sdram_ref_clk embeddedsw.dts.compatible arm,cortex-a9 embeddedsw.dts.group cpu embeddedsw.dts.name cortex-a9 embeddedsw.dts.vendor arm java.lang.String ]]> false true true true ADDRESS_MAP altera_axi_master java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true axi true new_signal Output 1 awvalid new_signal_1 Input 1 awready new_signal_2 Output 1 awid new_signal_3 Output 32 awaddr new_signal_4 Output 4 awlen new_signal_5 Output 3 awsize new_signal_6 Output 2 awburst new_signal_7 Output 2 awlock new_signal_8 Output 4 awcache new_signal_9 Output 3 awprot new_signal_10 Output 1 awuser new_signal_11 Output 1 arvalid new_signal_12 Input 1 arready new_signal_14 Output 32 araddr new_signal_15 Output 4 arlen new_signal_16 Output 3 arsize new_signal_17 Output 2 arburst new_signal_18 Output 2 arlock new_signal_19 Output 4 arcache new_signal_20 Output 3 arprot new_signal_21 Output 1 aruser new_signal_13 Output 1 arid new_signal_24 Input 1 bid new_signal_25 Input 1 rid new_signal_26 Output 1 wid new_signal_27 Output 1 wvalid new_signal_28 Input 1 wready new_signal_29 Output 1 wlast new_signal_30 Output 32 wdata new_signal_31 Output 4 wstrb new_signal_32 Input 1 rvalid new_signal_33 Output 1 rready new_signal_34 Input 1 rlast new_signal_35 Input 2 rresp new_signal_36 Input 32 rdata new_signal_37 Input 1 bvalid new_signal_38 Output 1 bready new_signal_39 Input 2 bresp false hps_0_arm_gic_0 axi_slave0 hps_0_arm_gic_0.axi_slave0 4294889472 4096 false hps_0_arm_gic_0 axi_slave1 hps_0_arm_gic_0.axi_slave1 4294885632 256 false hps_0_L2 axi_slave0 hps_0_L2.axi_slave0 4294897664 4096 false hps_0_dma axi_slave0 hps_0_dma.axi_slave0 4292874240 4096 false hps_0_sysmgr axi_slave0 hps_0_sysmgr.axi_slave0 4291854336 1024 false hps_0_clkmgr axi_slave0 hps_0_clkmgr.axi_slave0 4291837952 4096 false hps_0_rstmgr axi_slave0 hps_0_rstmgr.axi_slave0 4291842048 256 false hps_0_fpgamgr axi_slave0 hps_0_fpgamgr.axi_slave0 4285554688 4096 false hps_0_fpgamgr axi_slave1 hps_0_fpgamgr.axi_slave1 4290314240 256 false hps_0_uart0 axi_slave0 hps_0_uart0.axi_slave0 4290781184 256 false hps_0_uart1 axi_slave0 hps_0_uart1.axi_slave0 4290785280 256 false hps_0_timer0 axi_slave0 hps_0_timer0.axi_slave0 4290805760 256 false hps_0_timer1 axi_slave0 hps_0_timer1.axi_slave0 4290809856 256 false hps_0_timer2 axi_slave0 hps_0_timer2.axi_slave0 4291821568 256 false hps_0_timer3 axi_slave0 hps_0_timer3.axi_slave0 4291825664 256 false hps_0_wd_timer0 axi_slave0 hps_0_wd_timer0.axi_slave0 4291829760 256 false hps_0_wd_timer1 axi_slave0 hps_0_wd_timer1.axi_slave0 4291833856 256 false hps_0_gpio0 axi_slave0 hps_0_gpio0.axi_slave0 4285562880 256 false hps_0_gpio1 axi_slave0 hps_0_gpio1.axi_slave0 4285566976 256 false hps_0_gpio2 axi_slave0 hps_0_gpio2.axi_slave0 4285571072 256 false hps_0_i2c0 axi_slave0 hps_0_i2c0.axi_slave0 4290789376 256 false hps_0_i2c1 axi_slave0 hps_0_i2c1.axi_slave0 4290793472 256 false hps_0_i2c2 axi_slave0 hps_0_i2c2.axi_slave0 4290797568 256 false hps_0_i2c3 axi_slave0 hps_0_i2c3.axi_slave0 4290801664 256 false hps_0_nand0 axi_slave0 hps_0_nand0.axi_slave0 4287627264 65536 false hps_0_nand0 axi_slave1 hps_0_nand0.axi_slave1 4290248704 65536 false hps_0_spim0 axi_slave0 hps_0_spim0.axi_slave0 4293918720 256 false hps_0_spim1 axi_slave0 hps_0_spim1.axi_slave0 4293922816 256 false hps_0_qspi axi_slave0 hps_0_qspi.axi_slave0 4285550592 256 false hps_0_qspi axi_slave1 hps_0_qspi.axi_slave1 4288675840 256 false hps_0_sdmmc axi_slave0 hps_0_sdmmc.axi_slave0 4285546496 4096 false hps_0_usb0 axi_slave0 hps_0_usb0.axi_slave0 4289724416 262144 false hps_0_usb1 axi_slave0 hps_0_usb1.axi_slave0 4289986560 262144 false hps_0_gmac0 axi_slave0 hps_0_gmac0.axi_slave0 4285530112 8192 false hps_0_gmac1 axi_slave0 hps_0_gmac1.axi_slave0 4285538304 8192 false hps_0_dcan0 axi_slave0 hps_0_dcan0.axi_slave0 4290772992 4096 false hps_0_dcan1 axi_slave0 hps_0_dcan1.axi_slave0 4290777088 4096 false hps_0_l3regs axi_slave0 hps_0_l3regs.axi_slave0 4286578688 4096 false hps_0_sdrctl axi_slave0 hps_0_sdrctl.axi_slave0 4290924544 4096 false hps_0_axi_ocram axi_slave0 hps_0_axi_ocram.axi_slave0 4294901760 65536 false hps_0_axi_sdram axi_slave0 hps_0_axi_sdram.axi_slave0 0 2147483648 false hps_0_timer axi_slave0 hps_0_timer.axi_slave0 4294886912 256 false hps_0_scu axi_slave0 hps_0_scu.axi_slave0 4294885376 256 java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false new_signal_22 Input 1 reset boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false new_signal_23 Input 1 clk embeddedsw.dts.compatible arm,cortex-a9 embeddedsw.dts.group cpu embeddedsw.dts.name cortex-a9 embeddedsw.dts.vendor arm java.lang.String ]]> false true true true ADDRESS_MAP altera_axi_master java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true axi true new_signal Output 1 awvalid new_signal_1 Input 1 awready new_signal_2 Output 1 awid new_signal_3 Output 32 awaddr new_signal_4 Output 4 awlen new_signal_5 Output 3 awsize new_signal_6 Output 2 awburst new_signal_7 Output 2 awlock new_signal_8 Output 4 awcache new_signal_9 Output 3 awprot new_signal_10 Output 1 awuser new_signal_11 Output 1 arvalid new_signal_12 Input 1 arready new_signal_14 Output 32 araddr new_signal_15 Output 4 arlen new_signal_16 Output 3 arsize new_signal_17 Output 2 arburst new_signal_18 Output 2 arlock new_signal_19 Output 4 arcache new_signal_20 Output 3 arprot new_signal_21 Output 1 aruser new_signal_13 Output 1 arid new_signal_24 Input 1 bid new_signal_25 Input 1 rid new_signal_26 Output 1 wid new_signal_27 Output 1 wvalid new_signal_28 Input 1 wready new_signal_29 Output 1 wlast new_signal_30 Output 32 wdata new_signal_31 Output 4 wstrb new_signal_32 Input 1 rvalid new_signal_33 Output 1 rready new_signal_34 Input 1 rlast new_signal_35 Input 2 rresp new_signal_36 Input 32 rdata new_signal_37 Input 1 bvalid new_signal_38 Output 1 bready new_signal_39 Input 2 bresp false hps_0_arm_gic_0 axi_slave0 hps_0_arm_gic_0.axi_slave0 4294889472 4096 false hps_0_arm_gic_0 axi_slave1 hps_0_arm_gic_0.axi_slave1 4294885632 256 false hps_0_L2 axi_slave0 hps_0_L2.axi_slave0 4294897664 4096 false hps_0_dma axi_slave0 hps_0_dma.axi_slave0 4292874240 4096 false hps_0_sysmgr axi_slave0 hps_0_sysmgr.axi_slave0 4291854336 1024 false hps_0_clkmgr axi_slave0 hps_0_clkmgr.axi_slave0 4291837952 4096 false hps_0_rstmgr axi_slave0 hps_0_rstmgr.axi_slave0 4291842048 256 false hps_0_fpgamgr axi_slave0 hps_0_fpgamgr.axi_slave0 4285554688 4096 false hps_0_fpgamgr axi_slave1 hps_0_fpgamgr.axi_slave1 4290314240 256 false hps_0_uart0 axi_slave0 hps_0_uart0.axi_slave0 4290781184 256 false hps_0_uart1 axi_slave0 hps_0_uart1.axi_slave0 4290785280 256 false hps_0_timer0 axi_slave0 hps_0_timer0.axi_slave0 4290805760 256 false hps_0_timer1 axi_slave0 hps_0_timer1.axi_slave0 4290809856 256 false hps_0_timer2 axi_slave0 hps_0_timer2.axi_slave0 4291821568 256 false hps_0_timer3 axi_slave0 hps_0_timer3.axi_slave0 4291825664 256 false hps_0_wd_timer0 axi_slave0 hps_0_wd_timer0.axi_slave0 4291829760 256 false hps_0_wd_timer1 axi_slave0 hps_0_wd_timer1.axi_slave0 4291833856 256 false hps_0_gpio0 axi_slave0 hps_0_gpio0.axi_slave0 4285562880 256 false hps_0_gpio1 axi_slave0 hps_0_gpio1.axi_slave0 4285566976 256 false hps_0_gpio2 axi_slave0 hps_0_gpio2.axi_slave0 4285571072 256 false hps_0_i2c0 axi_slave0 hps_0_i2c0.axi_slave0 4290789376 256 false hps_0_i2c1 axi_slave0 hps_0_i2c1.axi_slave0 4290793472 256 false hps_0_i2c2 axi_slave0 hps_0_i2c2.axi_slave0 4290797568 256 false hps_0_i2c3 axi_slave0 hps_0_i2c3.axi_slave0 4290801664 256 false hps_0_nand0 axi_slave0 hps_0_nand0.axi_slave0 4287627264 65536 false hps_0_nand0 axi_slave1 hps_0_nand0.axi_slave1 4290248704 65536 false hps_0_spim0 axi_slave0 hps_0_spim0.axi_slave0 4293918720 256 false hps_0_spim1 axi_slave0 hps_0_spim1.axi_slave0 4293922816 256 false hps_0_qspi axi_slave0 hps_0_qspi.axi_slave0 4285550592 256 false hps_0_qspi axi_slave1 hps_0_qspi.axi_slave1 4288675840 256 false hps_0_sdmmc axi_slave0 hps_0_sdmmc.axi_slave0 4285546496 4096 false hps_0_usb0 axi_slave0 hps_0_usb0.axi_slave0 4289724416 262144 false hps_0_usb1 axi_slave0 hps_0_usb1.axi_slave0 4289986560 262144 false hps_0_gmac0 axi_slave0 hps_0_gmac0.axi_slave0 4285530112 8192 false hps_0_gmac1 axi_slave0 hps_0_gmac1.axi_slave0 4285538304 8192 false hps_0_dcan0 axi_slave0 hps_0_dcan0.axi_slave0 4290772992 4096 false hps_0_dcan1 axi_slave0 hps_0_dcan1.axi_slave0 4290777088 4096 false hps_0_l3regs axi_slave0 hps_0_l3regs.axi_slave0 4286578688 4096 false hps_0_sdrctl axi_slave0 hps_0_sdrctl.axi_slave0 4290924544 4096 false hps_0_axi_ocram axi_slave0 hps_0_axi_ocram.axi_slave0 4294901760 65536 false hps_0_axi_sdram axi_slave0 hps_0_axi_sdram.axi_slave0 0 2147483648 false hps_0_timer axi_slave0 hps_0_timer.axi_slave0 4294886912 256 false hps_0_scu axi_slave0 hps_0_scu.axi_slave0 4294885376 256 java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false new_signal_22 Input 1 reset boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false new_signal_23 Input 1 clk embeddedsw.dts.compatible arm,cortex-a9-gic embeddedsw.dts.group intc embeddedsw.dts.name cortex-a9-gic embeddedsw.dts.vendor arm java.math.BigInteger 8192 false true false true INTERRUPTS_USED arm_gic_ppi java.math.BigInteger 0 false true false true INTERRUPTS_USED irq_rx_offset_0 java.math.BigInteger 64 false true false true INTERRUPTS_USED irq_rx_offset_32 java.math.BigInteger 0 false true false true INTERRUPTS_USED f2h_irq_0_irq_rx_offset_40 java.math.BigInteger 0 false true false true INTERRUPTS_USED f2h_irq_32_irq_rx_offset_72 java.math.BigInteger 2569078785 false true false true INTERRUPTS_USED irq_rx_offset_104 java.math.BigInteger 1070366985 false true false true INTERRUPTS_USED irq_rx_offset_136 java.math.BigInteger 639 false true false true INTERRUPTS_USED irq_rx_offset_166 java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false new_signal_2 Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false new_signal_3 Input 1 reset embeddedsw.dts.irq.rx_offset 0 embeddedsw.dts.irq.rx_type arm_gic_ppi com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String clock_sink false true false true java.lang.String reset_sink false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt true ppi_irq_siq Input 16 irq false hps_0_timer interrupt_sender hps_0_timer.interrupt_sender 13 embeddedsw.dts.irq.rx_offset 0 embeddedsw.dts.irq.rx_type arm_gic_spi com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String clock_sink false true false true java.lang.String reset_sink false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt true irq_siq_0 Input 32 irq embeddedsw.dts.irq.rx_offset 32 embeddedsw.dts.irq.rx_type arm_gic_spi com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String clock_sink false true false true java.lang.String reset_sink false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt true irq_siq_32 Input 8 irq false hps_0_L2 interrupt_sender hps_0_L2.interrupt_sender 6 embeddedsw.dts.irq.rx_offset 40 embeddedsw.dts.irq.rx_type arm_gic_spi com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String clock_sink false true false true java.lang.String reset_sink false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt true irq_siq_40 Input 32 irq embeddedsw.dts.irq.rx_offset 72 embeddedsw.dts.irq.rx_type arm_gic_spi com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String clock_sink false true false true java.lang.String reset_sink false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt true irq_siq_72 Input 32 irq embeddedsw.dts.irq.rx_offset 104 embeddedsw.dts.irq.rx_type arm_gic_spi com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String clock_sink false true false true java.lang.String reset_sink false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt true irq_siq_104 Input 32 irq false hps_0_dma interrupt_sender hps_0_dma.interrupt_sender 0 false hps_0_usb0 interrupt_sender hps_0_usb0.interrupt_sender 21 false hps_0_usb1 interrupt_sender hps_0_usb1.interrupt_sender 24 false hps_0_gmac0 interrupt_sender hps_0_gmac0.interrupt_sender 11 false hps_0_gmac1 interrupt_sender hps_0_gmac1.interrupt_sender 16 false hps_0_dcan0 interrupt_sender0 hps_0_dcan0.interrupt_sender0 27 false hps_0_dcan0 interrupt_sender1 hps_0_dcan0.interrupt_sender1 28 false hps_0_dcan1 interrupt_sender0 hps_0_dcan1.interrupt_sender0 31 embeddedsw.dts.irq.rx_offset 136 embeddedsw.dts.irq.rx_type arm_gic_spi com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String clock_sink false true false true java.lang.String reset_sink false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt true irq_siq_136 Input 32 irq false hps_0_uart0 interrupt_sender hps_0_uart0.interrupt_sender 26 false hps_0_uart1 interrupt_sender hps_0_uart1.interrupt_sender 27 false hps_0_gpio0 interrupt_sender hps_0_gpio0.interrupt_sender 28 false hps_0_gpio1 interrupt_sender hps_0_gpio1.interrupt_sender 29 false hps_0_i2c0 interrupt_sender hps_0_i2c0.interrupt_sender 22 false hps_0_i2c1 interrupt_sender hps_0_i2c1.interrupt_sender 23 false hps_0_i2c2 interrupt_sender hps_0_i2c2.interrupt_sender 24 false hps_0_i2c3 interrupt_sender hps_0_i2c3.interrupt_sender 25 false hps_0_nand0 interrupt_sender hps_0_nand0.interrupt_sender 8 false hps_0_spim0 interrupt_sender hps_0_spim0.interrupt_sender 18 false hps_0_spim1 interrupt_sender hps_0_spim1.interrupt_sender 19 false hps_0_qspi interrupt_sender hps_0_qspi.interrupt_sender 15 false hps_0_sdmmc interrupt_sender hps_0_sdmmc.interrupt_sender 3 false hps_0_dcan1 interrupt_sender1 hps_0_dcan1.interrupt_sender1 0 embeddedsw.dts.irq.rx_offset 166 embeddedsw.dts.irq.rx_type arm_gic_spi com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String clock_sink false true false true java.lang.String reset_sink false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt true irq_siq_192 Input 14 irq false hps_0_fpgamgr interrupt_sender hps_0_fpgamgr.interrupt_sender 9 false hps_0_timer0 interrupt_sender hps_0_timer0.interrupt_sender 1 false hps_0_timer1 interrupt_sender hps_0_timer1.interrupt_sender 2 false hps_0_timer2 interrupt_sender hps_0_timer2.interrupt_sender 3 false hps_0_timer3 interrupt_sender hps_0_timer3.interrupt_sender 4 false hps_0_wd_timer0 interrupt_sender hps_0_wd_timer0.interrupt_sender 5 false hps_0_wd_timer1 interrupt_sender hps_0_wd_timer1.interrupt_sender 6 false hps_0_gpio2 interrupt_sender hps_0_gpio2.interrupt_sender 0 addressSpan 4096 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4096 true true false true axi false axi_slave0_signal_40 Input 1 awvalid axi_slave0_signal_41 Output 1 awready axi_slave0_signal_42 Input 12 awid axi_slave0_signal_43 Input 12 awaddr axi_slave0_signal_44 Input 4 awlen axi_slave0_signal_45 Input 3 awsize axi_slave0_signal_46 Input 2 awburst axi_slave0_signal_47 Input 2 awlock axi_slave0_signal_48 Input 4 awcache axi_slave0_signal_49 Input 3 awprot axi_slave0_signal_50 Input 1 awuser axi_slave0_signal_51 Input 1 arvalid axi_slave0_signal_52 Output 1 arready axi_slave0_signal_53 Input 12 arid axi_slave0_signal_54 Input 12 araddr axi_slave0_signal_55 Input 4 arlen axi_slave0_signal_56 Input 3 arsize axi_slave0_signal_57 Input 2 arburst axi_slave0_signal_58 Input 2 arlock axi_slave0_signal_59 Input 4 arcache axi_slave0_signal_60 Input 3 arprot axi_slave0_signal_61 Input 1 aruser axi_slave0_signal_62 Input 1 wvalid axi_slave0_signal_63 Output 1 wready axi_slave0_signal_64 Input 12 wid axi_slave0_signal_65 Input 1 wlast axi_slave0_signal_66 Input 32 wdata axi_slave0_signal_67 Input 4 wstrb axi_slave0_signal_68 Output 1 rvalid axi_slave0_signal_69 Input 1 rready axi_slave0_signal_70 Output 12 rid axi_slave0_signal_71 Output 1 rlast axi_slave0_signal_72 Output 2 rresp axi_slave0_signal_73 Output 32 rdata axi_slave0_signal_74 Output 1 bvalid axi_slave0_signal_75 Input 1 bready axi_slave0_signal_76 Output 12 bid axi_slave0_signal_77 Output 2 bresp addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_slave1_signal_40 Input 1 awvalid axi_slave1_signal_41 Output 1 awready axi_slave1_signal_42 Input 12 awid axi_slave1_signal_43 Input 8 awaddr axi_slave1_signal_44 Input 4 awlen axi_slave1_signal_45 Input 3 awsize axi_slave1_signal_46 Input 2 awburst axi_slave1_signal_47 Input 2 awlock axi_slave1_signal_48 Input 4 awcache axi_slave1_signal_49 Input 3 awprot axi_slave1_signal_50 Input 1 awuser axi_slave1_signal_51 Input 1 arvalid axi_slave1_signal_52 Output 1 arready axi_slave1_signal_53 Input 12 arid axi_slave1_signal_54 Input 8 araddr axi_slave1_signal_55 Input 4 arlen axi_slave1_signal_56 Input 3 arsize axi_slave1_signal_57 Input 2 arburst axi_slave1_signal_58 Input 2 arlock axi_slave1_signal_59 Input 4 arcache axi_slave1_signal_60 Input 3 arprot axi_slave1_signal_61 Input 1 aruser axi_slave1_signal_62 Input 1 wvalid axi_slave1_signal_63 Output 1 wready axi_slave1_signal_64 Input 12 wid axi_slave1_signal_65 Input 1 wlast axi_slave1_signal_66 Input 32 wdata axi_slave1_signal_67 Input 4 wstrb axi_slave1_signal_68 Output 1 rvalid axi_slave1_signal_69 Input 1 rready axi_slave1_signal_70 Output 12 rid axi_slave1_signal_71 Output 1 rlast axi_slave1_signal_72 Output 2 rresp axi_slave1_signal_73 Output 32 rdata axi_slave1_signal_74 Output 1 bvalid axi_slave1_signal_75 Input 1 bready axi_slave1_signal_76 Output 12 bid axi_slave1_signal_77 Output 2 bresp embeddedsw.dts.compatible arm,pl310-cache embeddedsw.dts.group L2-cache embeddedsw.dts.name pl310-cache embeddedsw.dts.params.cache-level 2 embeddedsw.dts.vendor arm java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 4096 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4096 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 12 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 12 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible arm,pl330 arm,primecell embeddedsw.dts.group dma embeddedsw.dts.name pl330 embeddedsw.dts.params.#dma-cells 1 embeddedsw.dts.params.#dma-channels 8 embeddedsw.dts.params.#dma-requests 32 embeddedsw.dts.params.clock-names apb_pclk embeddedsw.dts.params.copy-align 3 embeddedsw.dts.params.nr-irqs 9 embeddedsw.dts.params.nr-valid-peri 9 embeddedsw.dts.vendor arm java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false apb_pclk_clk Input 1 clk java.lang.String apb_pclk false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 4096 java.lang.String apb_pclk false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4096 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 12 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 12 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible altr,sys-mgr syscon embeddedsw.dts.group sysmgr embeddedsw.dts.name sys-mgr embeddedsw.dts.params.cpu1-start-addr 4291854532 embeddedsw.dts.vendor altr long 4291854532 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset addressSpan 1024 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 1024 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 10 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 10 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible altr,clk-mgr embeddedsw.dts.group clkmgr embeddedsw.dts.name clk-mgr embeddedsw.dts.vendor altr boolean false false true false true boolean false false true true true java.lang.String true true false true boolean false false true false true java.lang.String {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000} false true false true boolean false false true false true boolean false false true false true double 25.0 false true true true int 0 true true false true double 25.0 false true true true int 0 true true false true boolean false false true true true boolean false false true true true int 0 false true false true CLOCK_RATE f2h_sdram_ref_clock double 0.0 true true true true int 0 false true false true CLOCK_RATE f2h_periph_ref_clock double 0.0 true true true true int 0 false true true true int 2 false true true true int 2 false true true true int 1 false true true true int 1 false true true true int 1 false true true true double 0.0 true true true true int 0 true true false true boolean true false true true true double 800.0 false true true true int 0 true true false true int 1 false true true true int 1 false true true true boolean true false true false true int 0 false true true true int 1 false true true true int 0 false true true true double 100.0 false true true true int 0 true true false true double 100.0 false true true true int 0 true true false true double 100.0 false true true true int 0 true true false true double 200.0 false true true true int 0 true true false true double 12.5 false true true true int 0 true true false true double 400.0 false true true true int 0 true true false true double 250.0 false true true true int 0 true true false true double 250.0 false true true true int 0 true true false true double 200.0 false true true true int 0 true true false true double 200.0 false true true true int 0 true true false true double 100.0 false true true true int 0 true true false true double 100.0 false true true true int 0 true true false true int 32000 false true true true boolean false false true true true boolean false false true true true boolean false false true true true double 0.0 true true true true int 0 true true false true double 100.0 false true true true int 0 true true false true double 100.0 false true false true int 0 true true false true int 5 false true true true int 0 true true true true int 0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 63 false true true true int 0 false true true true int 0 true true false true double 0.0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 3 false true true true int 3 false true true true int 15 false true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true true true int 0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 79 false true true true int 1 false true true true int 0 true true false true double 0.0 true true true true int 3 false true true true int 3 false true true true int 1 false true true true int 19 false true true true int 4 false true true true int 9 false true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 0 true true true true int 1 true true true true int 0 false true true true int 0 false true true true int 1 false true true true int 1 false true true true int 6249 false true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true true true int 1 false true true true int 1 false true true true int 0 true true true true int 0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true int 0 true true false true double 0.0 true true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false eosc1_clk Input 1 clk java.lang.String eosc1 false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false eosc2_clk Input 1 clk boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false f2s_periph_ref_clk_clk Input 1 clk boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false f2s_sdram_ref_clk_clk Input 1 clk java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true emac0_clk_clk Output 1 clk false hps_0_gmac0 clock_sink hps_0_gmac0.clock_sink java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true emac1_clk_clk Output 1 clk false hps_0_gmac1 clock_sink hps_0_gmac1.clock_sink java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true can0_clk_clk Output 1 clk false hps_0_dcan0 clock_sink hps_0_dcan0.clock_sink java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true can1_clk_clk Output 1 clk false hps_0_dcan1 clock_sink hps_0_dcan1.clock_sink java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true nand_clk_clk Output 1 clk false hps_0_nand0 clock_sink hps_0_nand0.clock_sink java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true l4_sp_clk_clk Output 1 clk false hps_0_uart0 clock_sink hps_0_uart0.clock_sink false hps_0_uart1 clock_sink hps_0_uart1.clock_sink false hps_0_timer0 clock_sink hps_0_timer0.clock_sink false hps_0_timer1 clock_sink hps_0_timer1.clock_sink false hps_0_i2c0 clock_sink hps_0_i2c0.clock_sink false hps_0_i2c1 clock_sink hps_0_i2c1.clock_sink false hps_0_i2c2 clock_sink hps_0_i2c2.clock_sink false hps_0_i2c3 clock_sink hps_0_i2c3.clock_sink java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true l4_mp_clk_clk Output 1 clk false hps_0_gpio0 clock_sink hps_0_gpio0.clock_sink false hps_0_gpio1 clock_sink hps_0_gpio1.clock_sink false hps_0_gpio2 clock_sink hps_0_gpio2.clock_sink false hps_0_sdmmc biu hps_0_sdmmc.biu java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true l4_main_clk_clk Output 1 clk false hps_0_dma apb_pclk hps_0_dma.apb_pclk java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true per_base_clk_clk Output 1 clk false hps_0_wd_timer1 clock_sink hps_0_wd_timer1.clock_sink java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true mpu_periph_clk_clk Output 1 clk false hps_0_timer clock_sink hps_0_timer.clock_sink java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true usb_mp_clk_clk Output 1 clk false hps_0_usb0 clock_sink hps_0_usb0.clock_sink false hps_0_usb1 clock_sink hps_0_usb1.clock_sink java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true sdmmc_clk_clk Output 1 clk false hps_0_sdmmc ciu hps_0_sdmmc.ciu java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true qspi_clk_clk Output 1 clk false hps_0_qspi clock_sink hps_0_qspi.clock_sink java.lang.String false true true true long 0 false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock true spi_m_clk_clk Output 1 clk false hps_0_spim0 clock_sink hps_0_spim0.clock_sink false hps_0_spim1 clock_sink hps_0_spim1.clock_sink addressSpan 4096 java.lang.String eosc1 false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4096 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 12 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 12 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible altr,rst-mgr syscon embeddedsw.dts.group rstmgr embeddedsw.dts.name rst-mgr embeddedsw.dts.params.#reset-cells 1 embeddedsw.dts.params.altr,modrst-offset 16 embeddedsw.dts.vendor altr int 16 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible altr,fpga-mgr altr,socfpga-fpga-mgr embeddedsw.dts.group fpgamgr embeddedsw.dts.name fpga-mgr embeddedsw.dts.params.transport mmio embeddedsw.dts.vendor altr java.lang.String altr,fpga-mgr altr,socfpga-fpga-mgr false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 4096 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4096 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 12 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 12 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig1_40 Input 1 awvalid axi_sig1_41 Output 1 awready axi_sig1_42 Input 12 awid axi_sig1_43 Input 8 awaddr axi_sig1_44 Input 4 awlen axi_sig1_45 Input 3 awsize axi_sig1_46 Input 2 awburst axi_sig1_47 Input 2 awlock axi_sig1_48 Input 4 awcache axi_sig1_49 Input 3 awprot axi_sig1_50 Input 1 awuser axi_sig1_51 Input 1 arvalid axi_sig1_52 Output 1 arready axi_sig1_53 Input 12 arid axi_sig1_54 Input 8 araddr axi_sig1_55 Input 4 arlen axi_sig1_56 Input 3 arsize axi_sig1_57 Input 2 arburst axi_sig1_58 Input 2 arlock axi_sig1_59 Input 4 arcache axi_sig1_60 Input 3 arprot axi_sig1_61 Input 1 aruser axi_sig1_62 Input 1 wvalid axi_sig1_63 Output 1 wready axi_sig1_64 Input 12 wid axi_sig1_65 Input 1 wlast axi_sig1_66 Input 32 wdata axi_sig1_67 Input 4 wstrb axi_sig1_68 Output 1 rvalid axi_sig1_69 Input 1 rready axi_sig1_70 Output 12 rid axi_sig1_71 Output 1 rlast axi_sig1_72 Output 2 rresp axi_sig1_73 Output 32 rdata axi_sig1_74 Output 1 bvalid axi_sig1_75 Input 1 bready axi_sig1_76 Output 12 bid axi_sig1_77 Output 2 bresp embeddedsw.CMacro.FIFO_DEPTH 128 embeddedsw.CMacro.FIFO_HWFC 0 embeddedsw.CMacro.FIFO_MODE 1 embeddedsw.CMacro.FIFO_SWFC 0 embeddedsw.CMacro.FREQ 100000000 embeddedsw.dts.compatible snps,dw-apb-uart embeddedsw.dts.group serial embeddedsw.dts.name dw-apb-uart embeddedsw.dts.params.reg-io-width 4 embeddedsw.dts.params.reg-shift 2 embeddedsw.dts.params.status disabled embeddedsw.dts.vendor snps boolean false false true true true double 100.0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 embeddedsw.configuration.isPrintableDevice 1 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.CMacro.FIFO_DEPTH 128 embeddedsw.CMacro.FIFO_HWFC 0 embeddedsw.CMacro.FIFO_MODE 1 embeddedsw.CMacro.FIFO_SWFC 0 embeddedsw.CMacro.FREQ 100000000 embeddedsw.dts.compatible snps,dw-apb-uart embeddedsw.dts.group serial embeddedsw.dts.name dw-apb-uart embeddedsw.dts.params.reg-io-width 4 embeddedsw.dts.params.reg-shift 2 embeddedsw.dts.params.status disabled embeddedsw.dts.vendor snps boolean false false true true true double 100.0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 embeddedsw.configuration.isPrintableDevice 1 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-apb-timer-sp embeddedsw.dts.group timer embeddedsw.dts.name dw-apb-timer-sp embeddedsw.dts.params.clock-names timer embeddedsw.dts.vendor snps java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-apb-timer-sp embeddedsw.dts.group timer embeddedsw.dts.name dw-apb-timer-sp embeddedsw.dts.params.clock-names timer embeddedsw.dts.vendor snps java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-apb-timer-osc embeddedsw.dts.group timer embeddedsw.dts.name dw-apb-timer-osc embeddedsw.dts.params.clock-names timer embeddedsw.dts.vendor snps java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-apb-timer-osc embeddedsw.dts.group timer embeddedsw.dts.name dw-apb-timer-osc embeddedsw.dts.params.clock-names timer embeddedsw.dts.vendor snps java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-wdt embeddedsw.dts.group timer embeddedsw.dts.name dw-wdt embeddedsw.dts.params.clock-names timer embeddedsw.dts.vendor snps java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-wdt embeddedsw.dts.group timer embeddedsw.dts.name dw-wdt embeddedsw.dts.params.clock-names timer embeddedsw.dts.vendor snps java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-gpio embeddedsw.dts.group gpio embeddedsw.dts.name dw-gpio embeddedsw.dts.vendor snps int 1 false true true true int 29 false true true true int 0 false true true true int 0 false true true true int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-gpio embeddedsw.dts.group gpio embeddedsw.dts.name dw-gpio embeddedsw.dts.vendor snps int 1 false true true true int 29 false true true true int 0 false true true true int 0 false true true true int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-gpio embeddedsw.dts.group gpio embeddedsw.dts.name dw-gpio embeddedsw.dts.vendor snps int 1 false true true true int 27 false true true true int 0 false true true true int 0 false true true true int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,designware-i2c embeddedsw.dts.group i2c embeddedsw.dts.name designware-i2c embeddedsw.dts.params.emptyfifo_hold_master 1 embeddedsw.dts.params.status disabled embeddedsw.dts.vendor snps boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,designware-i2c embeddedsw.dts.group i2c embeddedsw.dts.name designware-i2c embeddedsw.dts.params.emptyfifo_hold_master 1 embeddedsw.dts.params.status disabled embeddedsw.dts.vendor snps boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,designware-i2c embeddedsw.dts.group i2c embeddedsw.dts.name designware-i2c embeddedsw.dts.params.emptyfifo_hold_master 1 embeddedsw.dts.params.status disabled embeddedsw.dts.vendor snps boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,designware-i2c embeddedsw.dts.group i2c embeddedsw.dts.name designware-i2c embeddedsw.dts.params.emptyfifo_hold_master 1 embeddedsw.dts.params.status disabled embeddedsw.dts.vendor snps boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible denali,denali-nand-dt embeddedsw.dts.group flash embeddedsw.dts.name nand embeddedsw.dts.params.#address-cells 1 embeddedsw.dts.params.#size-cells 1 embeddedsw.dts.params.reg-names "nand_data", "denali_reg" embeddedsw.dts.params.status disabled embeddedsw.dts.vendor denali boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 65536 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 65536 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 16 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 16 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp addressSpan 65536 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 65536 true true false true axi false axi_sig1_40 Input 1 awvalid axi_sig1_41 Output 1 awready axi_sig1_42 Input 12 awid axi_sig1_43 Input 16 awaddr axi_sig1_44 Input 4 awlen axi_sig1_45 Input 3 awsize axi_sig1_46 Input 2 awburst axi_sig1_47 Input 2 awlock axi_sig1_48 Input 4 awcache axi_sig1_49 Input 3 awprot axi_sig1_50 Input 1 awuser axi_sig1_51 Input 1 arvalid axi_sig1_52 Output 1 arready axi_sig1_53 Input 12 arid axi_sig1_54 Input 16 araddr axi_sig1_55 Input 4 arlen axi_sig1_56 Input 3 arsize axi_sig1_57 Input 2 arburst axi_sig1_58 Input 2 arlock axi_sig1_59 Input 4 arcache axi_sig1_60 Input 3 arprot axi_sig1_61 Input 1 aruser axi_sig1_62 Input 1 wvalid axi_sig1_63 Output 1 wready axi_sig1_64 Input 12 wid axi_sig1_65 Input 1 wlast axi_sig1_66 Input 32 wdata axi_sig1_67 Input 4 wstrb axi_sig1_68 Output 1 rvalid axi_sig1_69 Input 1 rready axi_sig1_70 Output 12 rid axi_sig1_71 Output 1 rlast axi_sig1_72 Output 2 rresp axi_sig1_73 Output 32 rdata axi_sig1_74 Output 1 bvalid axi_sig1_75 Input 1 bready axi_sig1_76 Output 12 bid axi_sig1_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-spi-mmio snps,dw-apb-ssi embeddedsw.dts.group spi embeddedsw.dts.name dw-spi-mmio embeddedsw.dts.params.#address-cells 1 embeddedsw.dts.params.#size-cells 0 embeddedsw.dts.params.bus-num 0 embeddedsw.dts.params.num-chipselect 4 embeddedsw.dts.params.status disabled embeddedsw.dts.vendor snps boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dw-spi-mmio snps,dw-apb-ssi embeddedsw.dts.group spi embeddedsw.dts.name dw-spi-mmio embeddedsw.dts.params.#address-cells 1 embeddedsw.dts.params.#size-cells 0 embeddedsw.dts.params.bus-num 0 embeddedsw.dts.params.num-chipselect 4 embeddedsw.dts.params.status disabled embeddedsw.dts.vendor snps boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible cadence,qspi cdns,qspi-nor embeddedsw.dts.group flash embeddedsw.dts.name qspi embeddedsw.dts.params.bus-num 2 embeddedsw.dts.params.fifo-depth 128 embeddedsw.dts.params.num-chipselect 4 embeddedsw.dts.params.status disabled embeddedsw.dts.vendor cadence boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig1_40 Input 1 awvalid axi_sig1_41 Output 1 awready axi_sig1_42 Input 12 awid axi_sig1_43 Input 8 awaddr axi_sig1_44 Input 4 awlen axi_sig1_45 Input 3 awsize axi_sig1_46 Input 2 awburst axi_sig1_47 Input 2 awlock axi_sig1_48 Input 4 awcache axi_sig1_49 Input 3 awprot axi_sig1_50 Input 1 awuser axi_sig1_51 Input 1 arvalid axi_sig1_52 Output 1 arready axi_sig1_53 Input 12 arid axi_sig1_54 Input 8 araddr axi_sig1_55 Input 4 arlen axi_sig1_56 Input 3 arsize axi_sig1_57 Input 2 arburst axi_sig1_58 Input 2 arlock axi_sig1_59 Input 4 arcache axi_sig1_60 Input 3 arprot axi_sig1_61 Input 1 aruser axi_sig1_62 Input 1 wvalid axi_sig1_63 Output 1 wready axi_sig1_64 Input 12 wid axi_sig1_65 Input 1 wlast axi_sig1_66 Input 32 wdata axi_sig1_67 Input 4 wstrb axi_sig1_68 Output 1 rvalid axi_sig1_69 Input 1 rready axi_sig1_70 Output 12 rid axi_sig1_71 Output 1 rlast axi_sig1_72 Output 2 rresp axi_sig1_73 Output 32 rdata axi_sig1_74 Output 1 bvalid axi_sig1_75 Input 1 bready axi_sig1_76 Output 12 bid axi_sig1_77 Output 2 bresp embeddedsw.dts.compatible altr,socfpga-dw-mshc embeddedsw.dts.group flash embeddedsw.dts.name mmc embeddedsw.dts.params.fifo-depth 1024 embeddedsw.dts.params.num-slots 1 embeddedsw.dts.params.status disabled embeddedsw.dts.vendor snps boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false biu_clk Input 1 clk boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false ciu_clk Input 1 clk java.lang.String biu false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 4096 java.lang.String biu false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4096 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 12 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 12 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dwc-otg snps,dwc2 embeddedsw.dts.group usb embeddedsw.dts.name dwc-otg embeddedsw.dts.params.clock-names otg embeddedsw.dts.params.dev-nperio-tx-fifo-size 4096 embeddedsw.dts.params.dev-perio-tx-fifo-size ]]> embeddedsw.dts.params.dev-rx-fifo-size 512 embeddedsw.dts.params.dev-tx-fifo-size ]]> embeddedsw.dts.params.dma-mask 268435455 embeddedsw.dts.params.enable-dynamic-fifo 1 embeddedsw.dts.params.host-nperio-tx-fifo-size 0xa00 embeddedsw.dts.params.host-perio-tx-fifo-size 0xa00 embeddedsw.dts.params.host-rx-fifo-size 0xa00 embeddedsw.dts.params.phy-names usb2-phy embeddedsw.dts.params.status disabled embeddedsw.dts.params.ulpi-ddr 0 embeddedsw.dts.params.voltage-switch 0 embeddedsw.dts.vendor snps boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 262144 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 262144 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 18 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 18 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible snps,dwc-otg snps,dwc2 embeddedsw.dts.group usb embeddedsw.dts.name dwc-otg embeddedsw.dts.params.clock-names otg embeddedsw.dts.params.dev-nperio-tx-fifo-size 4096 embeddedsw.dts.params.dev-perio-tx-fifo-size ]]> embeddedsw.dts.params.dev-rx-fifo-size 512 embeddedsw.dts.params.dev-tx-fifo-size ]]> embeddedsw.dts.params.dma-mask 268435455 embeddedsw.dts.params.enable-dynamic-fifo 1 embeddedsw.dts.params.host-nperio-tx-fifo-size 0xa00 embeddedsw.dts.params.host-perio-tx-fifo-size 0xa00 embeddedsw.dts.params.host-rx-fifo-size 0xa00 embeddedsw.dts.params.phy-names usb2-phy embeddedsw.dts.params.status disabled embeddedsw.dts.params.ulpi-ddr 0 embeddedsw.dts.params.voltage-switch 0 embeddedsw.dts.vendor snps boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 262144 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 262144 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 18 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 18 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac embeddedsw.dts.group ethernet embeddedsw.dts.name dwmac embeddedsw.dts.params.clock-names stmmaceth embeddedsw.dts.params.interrupt-names macirq embeddedsw.dts.params.rx-fifo-depth 4096 embeddedsw.dts.params.snps,multicast-filter-bins 256 embeddedsw.dts.params.snps,perfect-filter-entries 128 embeddedsw.dts.params.status disabled embeddedsw.dts.params.tx-fifo-depth 4096 embeddedsw.dts.vendor synopsys boolean false false true true true java.lang.String altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac false true true true int 4096 false true true true int 4096 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 8192 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 8192 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 13 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 13 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac embeddedsw.dts.group ethernet embeddedsw.dts.name dwmac embeddedsw.dts.params.clock-names stmmaceth embeddedsw.dts.params.interrupt-names macirq embeddedsw.dts.params.rx-fifo-depth 4096 embeddedsw.dts.params.snps,multicast-filter-bins 256 embeddedsw.dts.params.snps,perfect-filter-entries 128 embeddedsw.dts.params.status disabled embeddedsw.dts.params.tx-fifo-depth 4096 embeddedsw.dts.vendor synopsys boolean false false true true true java.lang.String altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac false true true true int 4096 false true true true int 4096 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 8192 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 8192 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 13 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 13 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible bosch,d_can embeddedsw.dts.group can embeddedsw.dts.name dcan embeddedsw.dts.params.status disabled embeddedsw.dts.vendor bosch boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender0 Output 1 irq com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender1 Output 1 irq addressSpan 4096 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4096 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 12 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 12 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible bosch,d_can embeddedsw.dts.group can embeddedsw.dts.name dcan embeddedsw.dts.params.status disabled embeddedsw.dts.vendor bosch boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender0 Output 1 irq com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender1 Output 1 irq addressSpan 4096 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4096 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 12 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 12 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible altr,l3regs syscon embeddedsw.dts.group rl3regs embeddedsw.dts.name l3regs embeddedsw.dts.vendor altr java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset addressSpan 4096 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4096 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 12 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 12 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible altr,sdr-ctl syscon embeddedsw.dts.group sdr-ctl embeddedsw.dts.name sdr-ctl embeddedsw.dts.vendor altr java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset addressSpan 4096 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 4096 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 12 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 12 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.CMacro.SIZE_MULTIPLE 1 embeddedsw.CMacro.SIZE_VALUE embeddedsw.CMacro.WRITABLE 1 embeddedsw.dts.group memory embeddedsw.dts.name ocram embeddedsw.dts.vendor altr embeddedsw.memoryInfo.GENERATE_DAT_SYM 0 embeddedsw.memoryInfo.GENERATE_HEX 0 embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH 16 java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset addressSpan 65536 embeddedsw.configuration.isMemoryDevice 1 embeddedsw.configuration.isNonVolatileStorage 0 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 65536 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 16 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 16 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.CMacro.SIZE_MULTIPLE 1 embeddedsw.CMacro.SIZE_VALUE embeddedsw.CMacro.WRITABLE 1 embeddedsw.dts.group memory embeddedsw.dts.name ocram embeddedsw.dts.vendor altr embeddedsw.memoryInfo.GENERATE_DAT_SYM 0 embeddedsw.memoryInfo.GENERATE_HEX 0 embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH 31 java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset addressSpan -2147483648 embeddedsw.configuration.isMemoryDevice 1 embeddedsw.configuration.isNonVolatileStorage 0 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 2147483648 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 31 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 31 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible arm,cortex-a9-twd-timer embeddedsw.dts.group timer embeddedsw.dts.name cortex-a9-twd-timer embeddedsw.dts.vendor arm java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset embeddedsw.dts.irq.tx_mask 0xf00 com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String false true false true java.lang.String false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false interrupt_sender Output 1 irq addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.dts.compatible arm,cortex-a9-scu embeddedsw.dts.group scu embeddedsw.dts.name corex-a9-scu embeddedsw.dts.vendor arm java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clock_sink_clk Input 1 clk java.lang.String clock_sink false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_sink_rst Input 1 reset addressSpan 256 java.lang.String clock_sink false true true true java.lang.String reset_sink false true true true boolean true false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true false true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true java.lang.Integer 1 false true true true com.altera.entityinterfaces.IConnectionPoint false true true true java.lang.String UNKNOWN false true true true boolean false false true true true java.math.BigInteger 256 true true false true axi false axi_sig0_40 Input 1 awvalid axi_sig0_41 Output 1 awready axi_sig0_42 Input 12 awid axi_sig0_43 Input 8 awaddr axi_sig0_44 Input 4 awlen axi_sig0_45 Input 3 awsize axi_sig0_46 Input 2 awburst axi_sig0_47 Input 2 awlock axi_sig0_48 Input 4 awcache axi_sig0_49 Input 3 awprot axi_sig0_50 Input 1 awuser axi_sig0_51 Input 1 arvalid axi_sig0_52 Output 1 arready axi_sig0_53 Input 12 arid axi_sig0_54 Input 8 araddr axi_sig0_55 Input 4 arlen axi_sig0_56 Input 3 arsize axi_sig0_57 Input 2 arburst axi_sig0_58 Input 2 arlock axi_sig0_59 Input 4 arcache axi_sig0_60 Input 3 arprot axi_sig0_61 Input 1 aruser axi_sig0_62 Input 1 wvalid axi_sig0_63 Output 1 wready axi_sig0_64 Input 12 wid axi_sig0_65 Input 1 wlast axi_sig0_66 Input 32 wdata axi_sig0_67 Input 4 wstrb axi_sig0_68 Output 1 rvalid axi_sig0_69 Input 1 rready axi_sig0_70 Output 12 rid axi_sig0_71 Output 1 rlast axi_sig0_72 Output 2 rresp axi_sig0_73 Output 32 rdata axi_sig0_74 Output 1 bvalid axi_sig0_75 Input 1 bready axi_sig0_76 Output 12 bid axi_sig0_77 Output 2 bresp embeddedsw.CMacro.READ_DEPTH 64 embeddedsw.CMacro.READ_THRESHOLD 8 embeddedsw.CMacro.WRITE_DEPTH 64 embeddedsw.CMacro.WRITE_THRESHOLD 8 embeddedsw.dts.compatible altr,juart-1.0 embeddedsw.dts.group serial embeddedsw.dts.name juart embeddedsw.dts.vendor altr boolean false false true false true int 0 false true false true int 64 false true true true int 8 false true true true java.lang.String false false false true java.lang.String NO_INTERACTIVE_WINDOWS false true false true boolean false false true true true boolean false false true true true boolean false false true false true int 64 false true true true int 8 false true true true long 50000000 false true false true CLOCK_RATE clk java.lang.String 2.0 false true false true AVALON_SPEC boolean false true true false true boolean false true true false true boolean false true true false true java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 50000000 true true false true clock false clk Input 1 clk java.lang.String clk false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false rst_n Input 1 reset_n embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 0 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 1 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment NATIVE false true false true int 0 false true false true java.math.BigInteger 2 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true java.math.BigInteger false true false true com.altera.entityinterfaces.IConnectionPoint false true false true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false false true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 0 false false true true int 0 false false true true int 1 false true false true boolean true false true false true int 0 false true true true int 1 false true false true int 1 false false true true boolean false false true false true boolean false false true false true int 0 false false true true com.altera.sopcmodel.avalon.TimingUnits Cycles false false true true boolean false false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false false true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon false av_chipselect Input 1 chipselect av_address Input 1 address av_read_n Input 1 read_n av_readdata Output 32 readdata av_write_n Input 1 write_n av_writedata Input 32 writedata av_waitrequest Output 1 waitrequest com.altera.entityinterfaces.IConnectionPoint jtag_uart_0.avalon_jtag_slave false true true true java.lang.String clk false true false true java.lang.String reset false true false true java.lang.Integer false true true true com.altera.entityinterfaces.IConnectionPoint false true true true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme NONE false true false true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt false av_irq Output 1 irq debug.hostConnection type jtag id 70:34|110:135 embeddedsw.CMacro.BIG_ENDIAN 0 embeddedsw.CMacro.BREAK_ADDR 0x00008820 embeddedsw.CMacro.CPU_ARCH_NIOS2_R1 embeddedsw.CMacro.CPU_FREQ 50000000u embeddedsw.CMacro.CPU_ID_SIZE 1 embeddedsw.CMacro.CPU_ID_VALUE 0x00000000 embeddedsw.CMacro.CPU_IMPLEMENTATION "fast" embeddedsw.CMacro.DATA_ADDR_WIDTH 19 embeddedsw.CMacro.DCACHE_BYPASS_MASK 0x80000000 embeddedsw.CMacro.DCACHE_LINE_SIZE 32 embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2 5 embeddedsw.CMacro.DCACHE_SIZE 2048 embeddedsw.CMacro.EXCEPTION_ADDR 0x00000020 embeddedsw.CMacro.FLASH_ACCELERATOR_LINES 0 embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE 0 embeddedsw.CMacro.FLUSHDA_SUPPORTED embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT 0 embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT 1 embeddedsw.CMacro.HARDWARE_MULX_PRESENT 0 embeddedsw.CMacro.HAS_DEBUG_CORE 1 embeddedsw.CMacro.HAS_DEBUG_STUB embeddedsw.CMacro.HAS_EXTRA_EXCEPTION_INFO embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION embeddedsw.CMacro.HAS_JMPI_INSTRUCTION embeddedsw.CMacro.ICACHE_LINE_SIZE 32 embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2 5 embeddedsw.CMacro.ICACHE_SIZE 8192 embeddedsw.CMacro.INITDA_SUPPORTED embeddedsw.CMacro.INST_ADDR_WIDTH 16 embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS 0 embeddedsw.CMacro.OCI_VERSION 1 embeddedsw.CMacro.RESET_ADDR 0x00000000 embeddedsw.configuration.DataCacheVictimBufImpl ram embeddedsw.configuration.HDLSimCachesCleared 1 embeddedsw.configuration.breakOffset 32 embeddedsw.configuration.breakSlave nios2_gen2_0.debug_mem_slave embeddedsw.configuration.cpuArchitecture Nios II embeddedsw.configuration.exceptionOffset 32 embeddedsw.configuration.exceptionSlave onchip_memory2_0.s1 embeddedsw.configuration.resetOffset 0 embeddedsw.configuration.resetSlave onchip_memory2_0.s1 embeddedsw.dts.compatible altr,nios2-1.1 embeddedsw.dts.group cpu embeddedsw.dts.name nios2 embeddedsw.dts.params.altr,exception-addr 0x00000020 embeddedsw.dts.params.altr,has-initda 1 embeddedsw.dts.params.altr,has-mul 1 embeddedsw.dts.params.altr,implementation "fast" embeddedsw.dts.params.altr,reset-addr 0x00000000 embeddedsw.dts.params.clock-frequency 50000000u embeddedsw.dts.params.dcache-line-size 32 embeddedsw.dts.params.dcache-size 2048 embeddedsw.dts.params.icache-line-size 32 embeddedsw.dts.params.icache-size 8192 embeddedsw.dts.vendor altr boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true true true boolean false false true true true boolean false false true false true boolean false false true false true boolean true false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true int 1 false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean true false true false true int 0 false false true true int 0 false true true true boolean true false true true true boolean false false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean true false true false true boolean true false true false true boolean false false true false true boolean false false true false true boolean false false false true true boolean false false true true true boolean false false true true true boolean true false false true true boolean false false true true true boolean true false true true true boolean false false true false true boolean false false true false true int 0 false true true true int 8 false false true true int 8 false false true true int 0 false false true true int 0 false true true true int 32 false true true true int 0 false true true true int 32 false true false true java.lang.String false true false true java.lang.String false true false true java.lang.String onchip_memory2_0.s1 false true true true java.lang.String None false false true true java.lang.String onchip_memory2_0.s1 false true true true java.lang.String None false true false true java.lang.String Internal false true true true java.lang.String Dynamic false true true true int 8 false true true true int 1 false true false true boolean false true true false true java.lang.String fast_le_shift true true false true java.lang.String mul_fast32 true true false true int 0 false true true true int 2 false false true true int 0 false false true true int 1 false false true true java.lang.String no_div false true true true int 12 false false true true int 12 false false true true int 4 false false true true int 6 false false true true int 7 false false true true int 16 false false true true int 8 false false true true java.lang.String Fast false true true true int 8192 false true true true int 2 false false true true int 0 false true true true java.lang.String Automatic false true false true java.lang.String Automatic false true false true int 0 false true true true java.lang.String None false true true true java.lang.String false false true true true java.lang.String ram false true true true int 2048 false true true true java.lang.String Automatic false true false true java.lang.String Automatic false true false true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true true true boolean true false true false true boolean true false true false true boolean true false true false true boolean true false true false true boolean true false true false true boolean true false true false true java.lang.String Automatic false true false true java.lang.String Automatic false true false true boolean false false true false true java.lang.String Automatic false true false true java.lang.String Automatic false true false true boolean false false true false true boolean false false true false true boolean true false true true true boolean true false true false true boolean false false true true true boolean false false true false true int 0 false true false true java.lang.String _128 false false true true int 0 false true true true int 0 false true true true java.lang.String none false true true true java.lang.String onchip_trace false false true true boolean false false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 false true false true long 0 false true false true int 0 true true true true int 32 true true true true int 34848 true true false true int 0 true true true true java.lang.String false true true false true int 2048 true true false true java.lang.String nios2_gen2_0.debug_mem_slave true true false true int 32 true true false true boolean false true true false true boolean true true true false true java.lang.String "synthesis translate_on" true true false true java.lang.String "synthesis translate_off" true true false true boolean false true true false true boolean false true true false true boolean false true true false true boolean false true true false true int 16 false true false true ADDRESS_WIDTH instruction_master int 1 false true false true ADDRESS_WIDTH flash_instruction_master int 19 false true false true ADDRESS_WIDTH data_master int 1 false true false true ADDRESS_WIDTH tightly_coupled_data_master_0 int 1 false true false true ADDRESS_WIDTH tightly_coupled_data_master_1 int 1 false true false true ADDRESS_WIDTH tightly_coupled_data_master_2 int 1 false true false true ADDRESS_WIDTH tightly_coupled_data_master_3 int 1 false true false true ADDRESS_WIDTH tightly_coupled_instruction_master_0 int 1 false true false true ADDRESS_WIDTH tightly_coupled_instruction_master_1 int 1 false true false true ADDRESS_WIDTH tightly_coupled_instruction_master_2 int 1 false true false true ADDRESS_WIDTH tightly_coupled_instruction_master_3 int 1 false true false true ADDRESS_WIDTH data_master_high_performance int 1 false true false true ADDRESS_WIDTH instruction_master_high_performance java.lang.String ]]> false true false true ADDRESS_MAP instruction_master java.lang.String false true false true ADDRESS_MAP flash_instruction_master java.lang.String ]]> false true false true ADDRESS_MAP data_master java.lang.String false true false true ADDRESS_MAP tightly_coupled_data_master_0 java.lang.String false true false true ADDRESS_MAP tightly_coupled_data_master_1 java.lang.String false true false true ADDRESS_MAP tightly_coupled_data_master_2 java.lang.String false true false true ADDRESS_MAP tightly_coupled_data_master_3 java.lang.String false true false true ADDRESS_MAP tightly_coupled_instruction_master_0 java.lang.String false true false true ADDRESS_MAP tightly_coupled_instruction_master_1 java.lang.String false true false true ADDRESS_MAP tightly_coupled_instruction_master_2 java.lang.String false true false true ADDRESS_MAP tightly_coupled_instruction_master_3 java.lang.String false true false true ADDRESS_MAP data_master_high_performance java.lang.String false true false true ADDRESS_MAP instruction_master_high_performance long 50000000 false true false true CLOCK_RATE clk java.lang.String CYCLONEV false true false true DEVICE_FAMILY long 6 false true false true INTERRUPTS_USED irq java.lang.String ]]> false true false true CUSTOM_INSTRUCTION_SLAVES custom_instruction_master java.lang.String ]]> false true false true CUSTOM_INSTRUCTION_SLAVES custom_instruction_master_a java.lang.String ]]> false true false true CUSTOM_INSTRUCTION_SLAVES custom_instruction_master_b java.lang.String ]]> false true false true CUSTOM_INSTRUCTION_SLAVES custom_instruction_master_c java.lang.String ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 false true false true DEVICE_FEATURES java.lang.String 5CSEMA4U23C6 false true false true DEVICE java.lang.String 6 false true false true DEVICE_SPEEDGRADE java.lang.Integer 1 false true false true CLOCK_DOMAIN clk java.lang.Integer 1 false true false true RESET_DOMAIN clk java.lang.String UNKNOWN false true true true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true java.lang.Boolean true true true false true java.lang.Long 50000000 true true false true clock false clk Input 1 clk java.lang.String clk false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset_n Input 1 reset_n reset_req Input 1 reset_req debug.providesServices master com.altera.entityinterfaces.IConnectionPoint false true false true int 1 false true false true com.altera.sopcmodel.avalon.EAddrBurstUnits SYMBOLS false true true true boolean false false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true boolean true false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true true true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 32 false true false true int 0 false true true true int 0 false true true true int 0 false true true true int 1 false true true true boolean false false true false true boolean false false true false true int 0 false true true true com.altera.sopcmodel.avalon.TimingUnits Cycles false true true true int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon true d_address Output 19 address d_byteenable Output 4 byteenable d_read Output 1 read d_readdata Input 32 readdata d_waitrequest Input 1 waitrequest d_write Output 1 write d_writedata Output 32 writedata d_readdatavalid Input 1 readdatavalid debug_mem_slave_debugaccess_to_roms Output 1 debugaccess false jtag_uart_0 avalon_jtag_slave jtag_uart_0.avalon_jtag_slave 36928 8 false LCDController_0 avalon_slave LCDController_0.avalon_slave 36864 64 false nios2_gen2_0 debug_mem_slave nios2_gen2_0.debug_mem_slave 34816 2048 false onchip_memory2_0 s1 onchip_memory2_0.s1 0 32000 true address_span_extender_0 windowed_slave address_span_extender_0.windowed_slave 262144 262144 false hps_0_bridges f2h_sdram0_data hps_0_bridges.f2h_sdram0_data 262144 262144 com.altera.entityinterfaces.IConnectionPoint false true false true int 1 false true false true com.altera.sopcmodel.avalon.EAddrBurstUnits SYMBOLS false true true true boolean true false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true boolean false false true false true boolean false false true true true boolean false false true true true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean true false true true true int 32 false true false true int 0 false true true true int 0 false true true true int 0 false true true true int 1 false true true true boolean false false true false true boolean false false true false true int 0 false true true true com.altera.sopcmodel.avalon.TimingUnits Cycles false true true true int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon true i_address Output 16 address i_read Output 1 read i_readdata Input 32 readdata i_waitrequest Input 1 waitrequest i_readdatavalid Input 1 readdatavalid false nios2_gen2_0 debug_mem_slave nios2_gen2_0.debug_mem_slave 34816 2048 false onchip_memory2_0 s1 onchip_memory2_0.s1 0 32000 com.altera.entityinterfaces.IConnectionPoint nios2_gen2_0.data_master false true true true java.lang.String clk false true false true java.lang.String reset false true false true java.lang.String false true false true com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme INDIVIDUAL_REQUESTS false true true true java.lang.String UNKNOWN false true true true boolean false false true true true interrupt true irq Input 32 irq false jtag_uart_0 irq jtag_uart_0.irq 1 false LCDController_0 irq LCDController_0.irq 2 java.lang.String clk false true true true java.lang.String false true true true [Ljava.lang.String; none false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset true debug_reset_request Output 1 reset embeddedsw.configuration.hideDevice 1 qsys.ui.connect instruction_master,data_master com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment DYNAMIC false true false true int 0 false true false true java.math.BigInteger 2048 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String clk false true true true java.lang.String reset false true true true int 8 false true true true java.math.BigInteger 0 false true false true com.altera.entityinterfaces.IConnectionPoint false true false true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 0 false true true true int 0 false false true true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true false true boolean false false true true true int 0 false false true true int 0 false false true true int 1 false true false true boolean false false true false true int 0 false true true true int 1 false true false true int 1 false false true true boolean true false true false true boolean false false true false true int 0 false false true true com.altera.sopcmodel.avalon.TimingUnits Cycles false false true true boolean false false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false false true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon false debug_mem_slave_address Input 9 address debug_mem_slave_byteenable Input 4 byteenable debug_mem_slave_debugaccess Input 1 debugaccess debug_mem_slave_read Input 1 read debug_mem_slave_readdata Output 32 readdata debug_mem_slave_waitrequest Output 1 waitrequest debug_mem_slave_write Input 1 write debug_mem_slave_writedata Input 32 writedata java.lang.String true true false true int 8 false true false true int 0 false false true true boolean false false true false true int 8 false true false true int 0 true true false true boolean false false true false true java.lang.String UNKNOWN false true true true boolean false false true true true nios_custom_instruction true dummy_ci_port Output 1 readra embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 embeddedsw.CMacro.CONTENTS_INFO "" embeddedsw.CMacro.DUAL_PORT 0 embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE AUTO embeddedsw.CMacro.INIT_CONTENTS_FILE system_onchip_memory2_0 embeddedsw.CMacro.INIT_MEM_CONTENT 1 embeddedsw.CMacro.INSTANCE_ID NONE embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED 0 embeddedsw.CMacro.RAM_BLOCK_TYPE AUTO embeddedsw.CMacro.READ_DURING_WRITE_MODE DONT_CARE embeddedsw.CMacro.SINGLE_CLOCK_OP 0 embeddedsw.CMacro.SIZE_MULTIPLE 1 embeddedsw.CMacro.SIZE_VALUE 32000 embeddedsw.CMacro.WRITABLE 1 embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR SIM_DIR embeddedsw.memoryInfo.GENERATE_DAT_SYM 1 embeddedsw.memoryInfo.GENERATE_HEX 1 embeddedsw.memoryInfo.HAS_BYTE_LANE 0 embeddedsw.memoryInfo.HEX_INSTALL_DIR QPF_DIR embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH 32 embeddedsw.memoryInfo.MEM_INIT_FILENAME system_onchip_memory2_0 postgeneration.simulation.init_file.param_name INIT_FILE postgeneration.simulation.init_file.type MEM_INIT boolean false false true true true java.lang.String AUTO false true true true int 32 false true true true int 32 false true false true boolean false false true true true boolean false false false true true boolean false true true false true boolean true false true true true java.lang.String onchip_mem.hex false false true true boolean false false true true true java.lang.String NONE false false true true long 32000 false true true true java.lang.String DONT_CARE false false true true boolean false false true false true int 0 false true false true boolean false false false true true boolean false true true false true int 1 false true true true int 1 false false true true boolean false false true true true boolean false false false false true boolean false false false true true boolean true false true true true boolean false false true true true boolean true false true true true java.lang.String system_onchip_memory2_0 false true false true UNIQUE_ID java.lang.String CYCLONEV false true false true DEVICE_FAMILY java.lang.String ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 false true false true DEVICE_FEATURES int 13 true true false true int 13 true true false true int 32 true true false true int 32 true true false true java.lang.String Automatic true true false true boolean false true true false true java.lang.String system_onchip_memory2_0.hex true true false true boolean false false true true true boolean false false true false true java.lang.String false true false true java.lang.String UNKNOWN false true true true boolean false false true true true clock false clk Input 1 clk embeddedsw.configuration.isFlash 0 embeddedsw.configuration.isMemoryDevice 1 embeddedsw.configuration.isNonVolatileStorage 0 embeddedsw.configuration.isPrintableDevice 0 com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment DYNAMIC false true false true int 0 false true false true java.math.BigInteger 32000 true true false true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.lang.String clk1 false true true true java.lang.String reset1 false true true true int 8 false true true true java.math.BigInteger false true false true com.altera.entityinterfaces.IConnectionPoint false true false true boolean false false true true true com.altera.sopcmodel.avalon.EAddrBurstUnits WORDS false true true true boolean false false true false true java.math.BigInteger 32000 false true true true int 0 false true true true boolean false false true false true boolean false false true false true boolean false false true false true boolean true false true false true boolean false false true false true boolean false false true true true int 0 false false true true int 0 false false true true int 1 false true false true boolean false false true false true int 1 false true true true int 0 false true false true int 0 false true true true boolean false false true false true boolean false false true false true int 0 false true true true com.altera.sopcmodel.avalon.TimingUnits Cycles false true true true boolean false false true false true boolean false false true false true int 0 false true false true int 0 false true false true int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true avalon false address Input 13 address clken Input 1 clken chipselect Input 1 chipselect write Input 1 write readdata Output 32 readdata writedata Input 32 writedata byteenable Input 4 byteenable java.lang.String clk1 false true true true com.altera.sopcmodel.reset.Reset$Edges DEASSERT false true true true java.lang.String UNKNOWN false true true true boolean false false true true true reset false reset Input 1 reset reset_req Input 1 reset_req java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_bridges reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_bridges clock_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_arm_a9_0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_arm_a9_0 clock_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_arm_a9_1 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_arm_a9_1 clock_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_arm_gic_0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_arm_gic_0 clock_sink int 1 false true true true java.math.BigInteger 0xfffed000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_arm_gic_0 axi_slave0 int 1 false true true true java.math.BigInteger 0xfffed000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_arm_gic_0 axi_slave0 int 1 false true true true java.math.BigInteger 0xfffec100 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_arm_gic_0 axi_slave1 int 1 false true true true java.math.BigInteger 0xfffec100 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_arm_gic_0 axi_slave1 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_L2 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_L2 clock_sink int 1 false true true true java.math.BigInteger 0xfffef000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_L2 axi_slave0 int 1 false true true true java.math.BigInteger 0xfffef000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_L2 axi_slave0 int 6 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_32 hps_0_L2 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_dma reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_main_clk hps_0_dma apb_pclk int 1 false true true true java.math.BigInteger 0xffe01000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_dma axi_slave0 int 1 false true true true java.math.BigInteger 0xffe01000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_dma axi_slave0 int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_104 hps_0_dma interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_sysmgr reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_sysmgr clock_sink int 1 false true true true java.math.BigInteger 0xffd08000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_sysmgr axi_slave0 int 1 false true true true java.math.BigInteger 0xffd08000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_sysmgr axi_slave0 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_clkmgr reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_eosc1 clk hps_0_clkmgr eosc1 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_eosc2 clk hps_0_clkmgr eosc2 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_f2s_periph_ref_clk clk hps_0_clkmgr f2s_periph_ref_clk java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_f2s_sdram_ref_clk clk hps_0_clkmgr f2s_sdram_ref_clk int 1 false true true true java.math.BigInteger 0xffd04000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_clkmgr axi_slave0 int 1 false true true true java.math.BigInteger 0xffd04000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_clkmgr axi_slave0 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_rstmgr reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_rstmgr clock_sink int 1 false true true true java.math.BigInteger 0xffd05000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_rstmgr axi_slave0 int 1 false true true true java.math.BigInteger 0xffd05000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_rstmgr axi_slave0 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_fpgamgr reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_fpgamgr clock_sink int 1 false true true true java.math.BigInteger 0xff706000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_fpgamgr axi_slave0 int 1 false true true true java.math.BigInteger 0xff706000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_fpgamgr axi_slave0 int 1 false true true true java.math.BigInteger 0xffb90000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_fpgamgr axi_slave1 int 1 false true true true java.math.BigInteger 0xffb90000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_fpgamgr axi_slave1 int 9 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_166 hps_0_fpgamgr interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_uart0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_sp_clk hps_0_uart0 clock_sink int 1 false true true true java.math.BigInteger 0xffc02000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_uart0 axi_slave0 int 1 false true true true java.math.BigInteger 0xffc02000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_uart0 axi_slave0 int 26 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_uart0 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_uart1 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_sp_clk hps_0_uart1 clock_sink int 1 false true true true java.math.BigInteger 0xffc03000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_uart1 axi_slave0 int 1 false true true true java.math.BigInteger 0xffc03000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_uart1 axi_slave0 int 27 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_uart1 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_timer0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_sp_clk hps_0_timer0 clock_sink int 1 false true true true java.math.BigInteger 0xffc08000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_timer0 axi_slave0 int 1 false true true true java.math.BigInteger 0xffc08000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_timer0 axi_slave0 int 1 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_166 hps_0_timer0 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_timer1 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_sp_clk hps_0_timer1 clock_sink int 1 false true true true java.math.BigInteger 0xffc09000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_timer1 axi_slave0 int 1 false true true true java.math.BigInteger 0xffc09000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_timer1 axi_slave0 int 2 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_166 hps_0_timer1 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_eosc1 clk_reset hps_0_timer2 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_eosc1 clk hps_0_timer2 clock_sink int 1 false true true true java.math.BigInteger 0xffd00000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_timer2 axi_slave0 int 1 false true true true java.math.BigInteger 0xffd00000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_timer2 axi_slave0 int 3 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_166 hps_0_timer2 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_eosc1 clk_reset hps_0_timer3 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_eosc1 clk hps_0_timer3 clock_sink int 1 false true true true java.math.BigInteger 0xffd01000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_timer3 axi_slave0 int 1 false true true true java.math.BigInteger 0xffd01000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_timer3 axi_slave0 int 4 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_166 hps_0_timer3 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_eosc1 clk_reset hps_0_wd_timer0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_eosc1 clk hps_0_wd_timer0 clock_sink int 1 false true true true java.math.BigInteger 0xffd02000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_wd_timer0 axi_slave0 int 1 false true true true java.math.BigInteger 0xffd02000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_wd_timer0 axi_slave0 int 5 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_166 hps_0_wd_timer0 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_wd_timer1 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr per_base_clk hps_0_wd_timer1 clock_sink int 1 false true true true java.math.BigInteger 0xffd03000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_wd_timer1 axi_slave0 int 1 false true true true java.math.BigInteger 0xffd03000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_wd_timer1 axi_slave0 int 6 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_166 hps_0_wd_timer1 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_gpio0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_mp_clk hps_0_gpio0 clock_sink int 1 false true true true java.math.BigInteger 0xff708000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_gpio0 axi_slave0 int 1 false true true true java.math.BigInteger 0xff708000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_gpio0 axi_slave0 int 28 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_gpio0 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_gpio1 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_mp_clk hps_0_gpio1 clock_sink int 1 false true true true java.math.BigInteger 0xff709000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_gpio1 axi_slave0 int 1 false true true true java.math.BigInteger 0xff709000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_gpio1 axi_slave0 int 29 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_gpio1 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_gpio2 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_mp_clk hps_0_gpio2 clock_sink int 1 false true true true java.math.BigInteger 0xff70a000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_gpio2 axi_slave0 int 1 false true true true java.math.BigInteger 0xff70a000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_gpio2 axi_slave0 int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_166 hps_0_gpio2 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_i2c0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_sp_clk hps_0_i2c0 clock_sink int 1 false true true true java.math.BigInteger 0xffc04000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_i2c0 axi_slave0 int 1 false true true true java.math.BigInteger 0xffc04000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_i2c0 axi_slave0 int 22 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_i2c0 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_i2c1 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_sp_clk hps_0_i2c1 clock_sink int 1 false true true true java.math.BigInteger 0xffc05000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_i2c1 axi_slave0 int 1 false true true true java.math.BigInteger 0xffc05000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_i2c1 axi_slave0 int 23 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_i2c1 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_i2c2 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_sp_clk hps_0_i2c2 clock_sink int 1 false true true true java.math.BigInteger 0xffc06000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_i2c2 axi_slave0 int 1 false true true true java.math.BigInteger 0xffc06000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_i2c2 axi_slave0 int 24 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_i2c2 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_i2c3 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_sp_clk hps_0_i2c3 clock_sink int 1 false true true true java.math.BigInteger 0xffc07000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_i2c3 axi_slave0 int 1 false true true true java.math.BigInteger 0xffc07000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_i2c3 axi_slave0 int 25 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_i2c3 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_nand0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr nand_clk hps_0_nand0 clock_sink int 1 false true true true java.math.BigInteger 0xff900000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_nand0 axi_slave0 int 1 false true true true java.math.BigInteger 0xff900000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_nand0 axi_slave0 int 1 false true true true java.math.BigInteger 0xffb80000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_nand0 axi_slave1 int 1 false true true true java.math.BigInteger 0xffb80000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_nand0 axi_slave1 int 8 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_nand0 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_spim0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr spi_m_clk hps_0_spim0 clock_sink int 1 false true true true java.math.BigInteger 0xfff00000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_spim0 axi_slave0 int 1 false true true true java.math.BigInteger 0xfff00000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_spim0 axi_slave0 int 18 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_spim0 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_spim1 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr spi_m_clk hps_0_spim1 clock_sink int 1 false true true true java.math.BigInteger 0xfff01000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_spim1 axi_slave0 int 1 false true true true java.math.BigInteger 0xfff01000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_spim1 axi_slave0 int 19 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_spim1 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_qspi reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr qspi_clk hps_0_qspi clock_sink int 1 false true true true java.math.BigInteger 0xff705000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_qspi axi_slave0 int 1 false true true true java.math.BigInteger 0xff705000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_qspi axi_slave0 int 1 false true true true java.math.BigInteger 0xffa00000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_qspi axi_slave1 int 1 false true true true java.math.BigInteger 0xffa00000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_qspi axi_slave1 int 15 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_qspi interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_sdmmc reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr l4_mp_clk hps_0_sdmmc biu java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr sdmmc_clk hps_0_sdmmc ciu int 1 false true true true java.math.BigInteger 0xff704000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_sdmmc axi_slave0 int 1 false true true true java.math.BigInteger 0xff704000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_sdmmc axi_slave0 int 3 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_sdmmc interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_usb0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr usb_mp_clk hps_0_usb0 clock_sink int 1 false true true true java.math.BigInteger 0xffb00000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_usb0 axi_slave0 int 1 false true true true java.math.BigInteger 0xffb00000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_usb0 axi_slave0 int 21 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_104 hps_0_usb0 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_usb1 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr usb_mp_clk hps_0_usb1 clock_sink int 1 false true true true java.math.BigInteger 0xffb40000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_usb1 axi_slave0 int 1 false true true true java.math.BigInteger 0xffb40000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_usb1 axi_slave0 int 24 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_104 hps_0_usb1 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_gmac0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr emac0_clk hps_0_gmac0 clock_sink int 1 false true true true java.math.BigInteger 0xff700000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_gmac0 axi_slave0 int 1 false true true true java.math.BigInteger 0xff700000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_gmac0 axi_slave0 int 11 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_104 hps_0_gmac0 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_gmac1 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr emac1_clk hps_0_gmac1 clock_sink int 1 false true true true java.math.BigInteger 0xff702000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_gmac1 axi_slave0 int 1 false true true true java.math.BigInteger 0xff702000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_gmac1 axi_slave0 int 16 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_104 hps_0_gmac1 interrupt_sender java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_dcan0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr can0_clk hps_0_dcan0 clock_sink int 1 false true true true java.math.BigInteger 0xffc00000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_dcan0 axi_slave0 int 1 false true true true java.math.BigInteger 0xffc00000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_dcan0 axi_slave0 int 27 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_104 hps_0_dcan0 interrupt_sender0 int 28 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_104 hps_0_dcan0 interrupt_sender1 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_dcan1 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr can1_clk hps_0_dcan1 clock_sink int 1 false true true true java.math.BigInteger 0xffc01000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_dcan1 axi_slave0 int 1 false true true true java.math.BigInteger 0xffc01000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_dcan1 axi_slave0 int 31 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_104 hps_0_dcan1 interrupt_sender0 int 0 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 irq_rx_offset_136 hps_0_dcan1 interrupt_sender1 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_l3regs reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_l3regs clock_sink int 1 false true true true java.math.BigInteger 0xff800000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_l3regs axi_slave0 int 1 false true true true java.math.BigInteger 0xff800000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_l3regs axi_slave0 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_sdrctl reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_sdrctl clock_sink int 1 false true true true java.math.BigInteger 0xffc25000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_sdrctl axi_slave0 int 1 false true true true java.math.BigInteger 0xffc25000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_sdrctl axi_slave0 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_axi_ocram reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_axi_ocram clock_sink int 1 false true true true java.math.BigInteger 0xffff0000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_axi_ocram axi_slave0 int 1 false true true true java.math.BigInteger 0xffff0000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_axi_ocram axi_slave0 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_axi_sdram reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_axi_sdram clock_sink int 1 false true true true java.math.BigInteger 0x0000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_axi_sdram axi_slave0 int 1 false true true true java.math.BigInteger 0x0000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_axi_sdram axi_slave0 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_timer reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clkmgr mpu_periph_clk hps_0_timer clock_sink int 1 false true true true java.math.BigInteger 0xfffec600 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_timer axi_slave0 int 1 false true true true java.math.BigInteger 0xfffec600 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_timer axi_slave0 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk_reset hps_0_scu reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_clk_0 clk hps_0_scu clock_sink int 1 false true true true java.math.BigInteger 0xfffec000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_0 altera_axi_master hps_0_scu axi_slave0 int 1 false true true true java.math.BigInteger 0xfffec000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_a9_1 altera_axi_master hps_0_scu axi_slave0 int 13 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_arm_gic_0 arm_gic_ppi hps_0_timer interrupt_sender int 1 false true true true java.math.BigInteger 0x00040000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true LCDController_0 avalon_master address_span_extender_0 windowed_slave int 1 false true true true java.math.BigInteger 0x9040 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 data_master jtag_uart_0 avalon_jtag_slave int 1 false true true true java.math.BigInteger 0x9000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 data_master LCDController_0 avalon_slave int 1 false true true true java.math.BigInteger 0x8800 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 data_master nios2_gen2_0 debug_mem_slave int 1 false true true true java.math.BigInteger 0x0000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 data_master onchip_memory2_0 s1 int 1 false true true true java.math.BigInteger 0x00040000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 data_master address_span_extender_0 windowed_slave int 1 false true true true java.math.BigInteger 0x0000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true address_span_extender_0 expanded_master hps_0_bridges f2h_sdram0_data int 1 false true true true java.math.BigInteger 0x8800 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 instruction_master nios2_gen2_0 debug_mem_slave int 1 false true true true java.math.BigInteger 0x0000 false true true true boolean false false true true true java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 instruction_master onchip_memory2_0 s1 java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk nios2_gen2_0 clk java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk jtag_uart_0 clk java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk onchip_memory2_0 clk1 java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk address_span_extender_0 clock java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk LCDController_0 clock_sink java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk hps_0_bridges f2h_sdram0_clock int 1 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 irq jtag_uart_0 irq int 2 false true true true java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 irq LCDController_0 irq java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk_reset jtag_uart_0 reset java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk_reset nios2_gen2_0 reset java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk_reset address_span_extender_0 reset java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk_reset onchip_memory2_0 reset1 java.lang.String UNKNOWN false true true true boolean false false true true true clk_0 clk_reset LCDController_0 reset_sink java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 debug_reset_request nios2_gen2_0 reset java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 debug_reset_request jtag_uart_0 reset java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 debug_reset_request address_span_extender_0 reset java.lang.String UNKNOWN false true true true boolean false false true true true nios2_gen2_0 debug_reset_request onchip_memory2_0 reset1 java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_bridges h2f_reset nios2_gen2_0 reset java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_bridges h2f_reset address_span_extender_0 reset java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_bridges h2f_reset jtag_uart_0 reset java.lang.String UNKNOWN false true true true boolean false false true true true hps_0_bridges h2f_reset onchip_memory2_0 reset1 1 LCDController com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule LCDController 1.0 7 avalon_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Avalon Memory Mapped Slave 18.1 53 clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Input 18.1 47 reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Input 18.1 4 avalon_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Avalon Memory Mapped Master 18.1 34 interrupt_sender com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Interrupt Sender 18.1 3 conduit_end com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Conduit 18.1 1 altera_address_span_extender com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Address Span Extender 18.1 1 clock_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Clock Source 18.1 1 clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Input 18.1 1 reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Input 18.1 1 clock_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Output 18.1 1 reset_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Output 18.1 1 altera_hps com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Arria V/Cyclone V Hard Processor System 18.1 9 reset_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Output 18.1 1 altera_interface_generator com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule altera_interface_generator 18.1 1 altera_hps_io com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule altera_hps_io 18.1 1 hps_clk_src com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule HPS clk src 18.1 19 clock_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Output 18.1 1 hps_bridge_avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule HPS Bridge Avalon 18.1 45 altera_axi_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint AXI Slave 18.1 3 altera_axi_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint AXI Master 18.1 4 hps_virt_clk com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule HPS Virtual Clock 18.1 2 arm_a9 com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule ARM A9 18.1 1 arm_gic com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule ARM GIC 18.1 9 interrupt_receiver com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Interrupt Receiver 18.1 1 arm_pl310_L2 com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule ARM pl310 cache 18.1 1 arm_pl330_dma com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule ARM pl330 dma 18.1 1 altera_sysmgr com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Altera System Manager 18.1 1 asimov_clkmgr com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Altera Clock Manager 18.1 1 altera_rstmgr com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Altera Reset Manager 18.1 1 altera_fpgamgr com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Altera FPGA Manager 18.1 2 snps_uart com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Synopsys UART 18.1 2 dw_apb_timer_sp com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Synopsys SP Timer 18.1 2 dw_apb_timer_osc com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Synopsys OCS Timer 18.1 2 dw_wd_timer com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Synopsys WatchDog Timer 18.1 3 dw_gpio com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Synopsys GPIO 18.1 4 designware_i2c com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Synopsys I2C 18.1 1 denali_nand com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Denali NAND 18.1 2 spi com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Synopsys SPI 18.1 1 cadence_qspi com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Cadence QSPI 18.1 1 sdmmc com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Synopsys SDMMC 18.1 2 usb com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Synopsys USB 18.1 2 stmmac com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Synopsys GMAC 18.1 2 bosch_dcan com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Bosch DCAN 18.1 1 altera_l3regs com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Altera HPS L3 Registers 18.1 1 altera_sdrctl com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Altera SDRAM Controller 18.1 1 axi_ocram com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule HPS On Chip RAM 18.1 1 axi_sdram com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule SDRAM connected to HPS 18.1 1 arm_internal_timer com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule ARM internal timer 18.1 1 scu com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule ARM Snoop Control Unit 18.1 1 altera_avalon_jtag_uart com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule JTAG UART Intel FPGA IP 18.1 1 altera_nios2_gen2 com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Nios II Processor 18.1 1 nios_custom_instruction_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Custom Instruction Master 18.1 1 altera_avalon_onchip_memory2 com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule On-Chip Memory (RAM or ROM) Intel FPGA IP 18.1 55 reset com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Reset Connection 18.1 52 clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Clock Connection 18.1 95 avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Avalon Memory Mapped Connection 18.1 34 interrupt com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Interrupt Connection 18.1 18.1 625