library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;


entity PixTrans_tb is
end PixTrans_tb;

architecture test of PixTrans_tb is
    constant CLK_PERIOD : time := 20 ns;
    constant N_LED_MAX : integer := 255;

    constant MAX_H : natural := 4;
    constant MAX_W : natural := 4;

    constant ACTUAL_H : natural := 2;
    constant ACTUAL_W : natural := 2;

    signal clk : std_logic := '0';
    signal rst_n : std_logic;

    signal fifo_empty, lcd_req : std_logic;
    signal fifo_q : std_logic_vector(31 downto 0);
    signal w, h : natural;

begin

    w <= ACTUAL_W;
    h <= ACTUAL_H;

    -- Instantiate DUT
    dut : entity work.PixTrans
    generic map (
        MAX_H => MAX_H,
        MAX_W => MAX_W
    )
    port map(
        clk => clk,
        rst_n => rst_n,
        lcd_req => lcd_req,
        fifo_q => fifo_q,
        fifo_empty => fifo_empty,
        w => w,
        h => h
    );

    -- Clocking process
    clk_generation : process
    begin
        clk <= not clk;
        wait for CLK_PERIOD / 2;
    end process;

    -- Testbench
    tb : process 

        procedure getPixel is
        begin
            wait until rising_edge(clk);
            lcd_req <= '1';
            wait for CLK_PERIOD;
            wait until rising_edge(clk);
            lcd_req <= '0';
            wait for CLK_PERIOD*3;
        end procedure getPixel;
    begin
        -- Just let the FIFO interface always provide data
        fifo_q <= X"FFFF" & X"F0F0";
        fifo_empty <= '0';
        lcd_req <= '0';

        -- Reset
        rst_n <= '0';
        wait for CLK_PERIOD * 2.5;
        rst_n <= '1';
        wait for CLK_PERIOD * 2;

        -- Get some pixels
        for i in 1 to MAX_H*MAX_W loop
            report "hello";
            getPixel;
        end loop;
        
        -- Test finished
        wait;

    end process;

end;