library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;


entity LCDDriver_tb is
end LCDDriver_tb;

architecture test of LCDDriver_tb is
    constant CLK_PERIOD : time := 20 ns;
    constant N_LED_MAX : integer := 255;

    signal clk   : std_logic := '0';
    signal rst_n : std_logic := '1';

    signal data_in      : std_logic_vector(15 downto 0) := (others=> '0');
    signal empty_in     : std_logic := '1';
    signal refresh_in   : std_logic := '0';

    signal cmd_en_in    : std_logic := '0';
    signal cmd_dcx_in   : std_logic := '0';
    signal cmd_data_in  : std_logic_vector(7 downto 0) := (others => '0');

    signal m_finished_in  : std_logic := '0';

    signal data_out   : std_logic_vector(15 downto 0);
    signal rd_n       : std_logic;
    signal wr_n       : std_logic;
    signal rs         : std_logic;
    signal cs_n       : std_logic;

    signal lcd_rdreq  : std_logic;
    signal rdreq_cnt  : integer := 0;

    signal busy : std_logic;

begin
    -- Instantiate DUT
    dut : entity work.LCDDriver
    generic map (
        F_CLK => 50000000
    )
    port map(
        clk             => clk,
        rst_n           => rst_n,
        data_in         => data_in,
        empty_in        => empty_in,
        refresh_in      => refresh_in,

        cmd_en_in       => cmd_en_in,
        cmd_dcx_in      => cmd_dcx_in,
        cmd_data_in     => cmd_data_in,

        m_finished_in   => m_finished_in,

        data_out        => data_out,
        rd_n            => rd_n,
        wr_n            => wr_n,
        rs              => rs,
        cs_n            => cs_n,

        lcd_rdreq       => lcd_rdreq,

        busy            => busy
    );

    -- Clocking process
    clk_generation : process
    begin
        clk <= not clk;
        wait for CLK_PERIOD / 2;
    end process;

    process (lcd_rdreq) begin
        if rising_edge(lcd_rdreq) then
            if (rdreq_cnt = 0) then 
                data_in <= "1111111111111111";
            elsif (rdreq_cnt = 1) then
                data_in <= "1111000000001111";
            elsif (rdreq_cnt = 2) then
                data_in <= "1111111100000000";
            elsif (rdreq_cnt = 3) then
                data_in <= "0000000011111111";
            else 
                data_in <= "0000000000000000";
            end if;
            rdreq_cnt <= rdreq_cnt + 1;
        end if;
    end process;

    tb : process 
        procedure wait_ready is
            begin
                if busy = '1' then
                    wait until busy = '0';
                end if;
        end procedure wait_ready;

        procedure finish is
        begin
            wait until falling_edge(clk);
            wait_ready;
            wait; 
        end procedure finish ;

    begin
        -- Reset
        rst_n <= '0';
        wait for CLK_PERIOD * 2.5;
        rst_n <= '1';
        wait for CLK_PERIOD * 2;
        wait_ready;

        -- Test CMD
        cmd_en_in <= '1';
        cmd_dcx_in <= '1';
        cmd_data_in <= "11010011";
        wait for CLK_PERIOD * 2.5;
        cmd_en_in <= '0';

        wait_ready;

        -- Test REFRESH
        refresh_in <= '1';
        wait for CLK_PERIOD * 2.5;
        refresh_in <= '0';
        wait for CLK_PERIOD * 4;
        empty_in <= '0';
        wait until rdreq_cnt = 4;
        empty_in <= '1';
        --m_finished_in   => m_finished_in,
        wait_ready;

        
        -- Test finished
        finish;

    end process;

end;