library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;


entity LCDAvalonMaster_tb is
end LCDAvalonMaster_tb;

architecture test of LCDAvalonMaster_tb is
    constant CLK_PERIOD : time := 20 ns;
    constant N_LED_MAX : integer := 255;

    -- 20 = 1 full burst + 1 non full burst
    constant NWORDS : natural := 20;

    constant NWORDS_MAX :natural := (320*240)/2;

    signal clk : std_logic := '0';
    signal rst_n : std_logic;
    signal waitreq, readdatavalid, refresh, fifo_almost_empty : std_logic;
    signal readdata    : std_logic_vector(31 downto 0);
    signal baseaddress : std_logic_vector(31 downto 0);
    signal nwords_sig  : std_logic_vector(integer(floor(log2(real(NWORDS_MAX)))) downto 0);

begin

    nwords_sig <= std_logic_vector(to_unsigned(NWORDS, nwords_sig'length));

    -- Instantiate DUT
    dut : entity work.LCDAvalonMaster
    generic map (
        NWORDS_MAX => NWORDS_MAX
    )
    port map(
        clk => clk,
        rst_n => rst_n,
        waitreq => waitreq,
        readdatavalid => readdatavalid,
        refresh => refresh,
        fifo_almost_empty => fifo_almost_empty,
        readdata => readdata,
        baseaddress => baseaddress,
        nwords => nwords_sig
    );

    -- Clocking process
    clk_generation : process
    begin
        clk <= not clk;
        wait for CLK_PERIOD / 2;
    end process;

    -- Testbench
    tb : process 
    begin
        while true loop
            -- Dummy signals from bus
            readdata <= X"12341234";
            readdatavalid <= '0';
            waitreq <= '1';
            baseaddress <= X"10000000";
            fifo_almost_empty <= '0';

            -- Reset
            rst_n <= '0';
            wait for CLK_PERIOD * 2.5;
            rst_n <= '1';
            wait for CLK_PERIOD * 2;

            -- Initiate a refresh cycle
            wait until rising_edge(clk);
            refresh <= '1';
            wait for CLK_PERIOD;
            refresh <= '0';

            -- Wait until bus grant
            wait for CLK_PERIOD * 3;
            waitreq <= '0';
            wait for CLK_PERIOD;
            
            -- Emulate that new read data is valid each cycle of the burst
            readdatavalid <= '1';
            for i in 1 to 16 loop
                wait for CLK_PERIOD;
            end loop;
            readdatavalid <= '0';

            wait for CLK_PERIOD * 5;

            -- Assert fifo_almost empty; should repromt another transfer
            fifo_almost_empty <= '1';
            wait for CLK_period;
            fifo_almost_empty <= '0';
            wait for CLK_PERIOD * 2;
            
            readdatavalid <= '1';
            for i in 1 to 16 loop
                wait for CLK_PERIOD;
            end loop;

            -- Test finished
            wait for CLK_PERIOD * 5;
        end loop;

    end process;

end;