|GECKO
row1[0] <= out_LEDs[0].DB_MAX_OUTPUT_PORT_TYPE
row1[1] <= out_LEDs[1].DB_MAX_OUTPUT_PORT_TYPE
row1[2] <= out_LEDs[2].DB_MAX_OUTPUT_PORT_TYPE
row1[3] <= out_LEDs[3].DB_MAX_OUTPUT_PORT_TYPE
row1[4] <= out_LEDs[4].DB_MAX_OUTPUT_PORT_TYPE
row1[5] <= out_LEDs[5].DB_MAX_OUTPUT_PORT_TYPE
row1[6] <= out_LEDs[6].DB_MAX_OUTPUT_PORT_TYPE
row1[7] <= out_LEDs[7].DB_MAX_OUTPUT_PORT_TYPE
row1[8] <= out_LEDs[8].DB_MAX_OUTPUT_PORT_TYPE
row1[9] <= out_LEDs[9].DB_MAX_OUTPUT_PORT_TYPE
row1[10] <= out_LEDs[10].DB_MAX_OUTPUT_PORT_TYPE
row1[11] <= out_LEDs[11].DB_MAX_OUTPUT_PORT_TYPE
clk => LEDs:LEDs_0.clk
clk => CPU:inst.clk
clk => ROM:ROM_0.clk
clk => RAM:RAM_0.clk
clk => buttons:buttons_0.clk
reset_n => LEDs:LEDs_0.reset_n
reset_n => CPU:inst.reset_n
reset_n => buttons:buttons_0.reset_n
in_buttons[0] => buttons:buttons_0.buttons[0]
in_buttons[1] => buttons:buttons_0.buttons[1]
in_buttons[2] => buttons:buttons_0.buttons[2]
in_buttons[3] => buttons:buttons_0.buttons[3]
row2[0] <= out_LEDs[12].DB_MAX_OUTPUT_PORT_TYPE
row2[1] <= out_LEDs[13].DB_MAX_OUTPUT_PORT_TYPE
row2[2] <= out_LEDs[14].DB_MAX_OUTPUT_PORT_TYPE
row2[3] <= out_LEDs[15].DB_MAX_OUTPUT_PORT_TYPE
row2[4] <= out_LEDs[16].DB_MAX_OUTPUT_PORT_TYPE
row2[5] <= out_LEDs[17].DB_MAX_OUTPUT_PORT_TYPE
row2[6] <= out_LEDs[18].DB_MAX_OUTPUT_PORT_TYPE
row2[7] <= out_LEDs[19].DB_MAX_OUTPUT_PORT_TYPE
row2[8] <= out_LEDs[20].DB_MAX_OUTPUT_PORT_TYPE
row2[9] <= out_LEDs[21].DB_MAX_OUTPUT_PORT_TYPE
row2[10] <= out_LEDs[22].DB_MAX_OUTPUT_PORT_TYPE
row2[11] <= out_LEDs[23].DB_MAX_OUTPUT_PORT_TYPE
row3[0] <= out_LEDs[24].DB_MAX_OUTPUT_PORT_TYPE
row3[1] <= out_LEDs[25].DB_MAX_OUTPUT_PORT_TYPE
row3[2] <= out_LEDs[26].DB_MAX_OUTPUT_PORT_TYPE
row3[3] <= out_LEDs[27].DB_MAX_OUTPUT_PORT_TYPE
row3[4] <= out_LEDs[28].DB_MAX_OUTPUT_PORT_TYPE
row3[5] <= out_LEDs[29].DB_MAX_OUTPUT_PORT_TYPE
row3[6] <= out_LEDs[30].DB_MAX_OUTPUT_PORT_TYPE
row3[7] <= out_LEDs[31].DB_MAX_OUTPUT_PORT_TYPE
row3[8] <= out_LEDs[32].DB_MAX_OUTPUT_PORT_TYPE
row3[9] <= out_LEDs[33].DB_MAX_OUTPUT_PORT_TYPE
row3[10] <= out_LEDs[34].DB_MAX_OUTPUT_PORT_TYPE
row3[11] <= out_LEDs[35].DB_MAX_OUTPUT_PORT_TYPE
row4[0] <= out_LEDs[36].DB_MAX_OUTPUT_PORT_TYPE
row4[1] <= out_LEDs[37].DB_MAX_OUTPUT_PORT_TYPE
row4[2] <= out_LEDs[38].DB_MAX_OUTPUT_PORT_TYPE
row4[3] <= out_LEDs[39].DB_MAX_OUTPUT_PORT_TYPE
row4[4] <= out_LEDs[40].DB_MAX_OUTPUT_PORT_TYPE
row4[5] <= out_LEDs[41].DB_MAX_OUTPUT_PORT_TYPE
row4[6] <= out_LEDs[42].DB_MAX_OUTPUT_PORT_TYPE
row4[7] <= out_LEDs[43].DB_MAX_OUTPUT_PORT_TYPE
row4[8] <= out_LEDs[44].DB_MAX_OUTPUT_PORT_TYPE
row4[9] <= out_LEDs[45].DB_MAX_OUTPUT_PORT_TYPE
row4[10] <= out_LEDs[46].DB_MAX_OUTPUT_PORT_TYPE
row4[11] <= out_LEDs[47].DB_MAX_OUTPUT_PORT_TYPE
row5[0] <= out_LEDs[48].DB_MAX_OUTPUT_PORT_TYPE
row5[1] <= out_LEDs[49].DB_MAX_OUTPUT_PORT_TYPE
row5[2] <= out_LEDs[50].DB_MAX_OUTPUT_PORT_TYPE
row5[3] <= out_LEDs[51].DB_MAX_OUTPUT_PORT_TYPE
row5[4] <= out_LEDs[52].DB_MAX_OUTPUT_PORT_TYPE
row5[5] <= out_LEDs[53].DB_MAX_OUTPUT_PORT_TYPE
row5[6] <= out_LEDs[54].DB_MAX_OUTPUT_PORT_TYPE
row5[7] <= out_LEDs[55].DB_MAX_OUTPUT_PORT_TYPE
row5[8] <= out_LEDs[56].DB_MAX_OUTPUT_PORT_TYPE
row5[9] <= out_LEDs[57].DB_MAX_OUTPUT_PORT_TYPE
row5[10] <= out_LEDs[58].DB_MAX_OUTPUT_PORT_TYPE
row5[11] <= out_LEDs[59].DB_MAX_OUTPUT_PORT_TYPE
row6[0] <= out_LEDs[60].DB_MAX_OUTPUT_PORT_TYPE
row6[1] <= out_LEDs[61].DB_MAX_OUTPUT_PORT_TYPE
row6[2] <= out_LEDs[62].DB_MAX_OUTPUT_PORT_TYPE
row6[3] <= out_LEDs[63].DB_MAX_OUTPUT_PORT_TYPE
row6[4] <= out_LEDs[64].DB_MAX_OUTPUT_PORT_TYPE
row6[5] <= out_LEDs[65].DB_MAX_OUTPUT_PORT_TYPE
row6[6] <= out_LEDs[66].DB_MAX_OUTPUT_PORT_TYPE
row6[7] <= out_LEDs[67].DB_MAX_OUTPUT_PORT_TYPE
row6[8] <= out_LEDs[68].DB_MAX_OUTPUT_PORT_TYPE
row6[9] <= out_LEDs[69].DB_MAX_OUTPUT_PORT_TYPE
row6[10] <= out_LEDs[70].DB_MAX_OUTPUT_PORT_TYPE
row6[11] <= out_LEDs[71].DB_MAX_OUTPUT_PORT_TYPE
row7[0] <= out_LEDs[72].DB_MAX_OUTPUT_PORT_TYPE
row7[1] <= out_LEDs[73].DB_MAX_OUTPUT_PORT_TYPE
row7[2] <= out_LEDs[74].DB_MAX_OUTPUT_PORT_TYPE
row7[3] <= out_LEDs[75].DB_MAX_OUTPUT_PORT_TYPE
row7[4] <= out_LEDs[76].DB_MAX_OUTPUT_PORT_TYPE
row7[5] <= out_LEDs[77].DB_MAX_OUTPUT_PORT_TYPE
row7[6] <= out_LEDs[78].DB_MAX_OUTPUT_PORT_TYPE
row7[7] <= out_LEDs[79].DB_MAX_OUTPUT_PORT_TYPE
row7[8] <= out_LEDs[80].DB_MAX_OUTPUT_PORT_TYPE
row7[9] <= out_LEDs[81].DB_MAX_OUTPUT_PORT_TYPE
row7[10] <= out_LEDs[82].DB_MAX_OUTPUT_PORT_TYPE
row7[11] <= out_LEDs[83].DB_MAX_OUTPUT_PORT_TYPE
row8[0] <= out_LEDs[84].DB_MAX_OUTPUT_PORT_TYPE
row8[1] <= out_LEDs[85].DB_MAX_OUTPUT_PORT_TYPE
row8[2] <= out_LEDs[86].DB_MAX_OUTPUT_PORT_TYPE
row8[3] <= out_LEDs[87].DB_MAX_OUTPUT_PORT_TYPE
row8[4] <= out_LEDs[88].DB_MAX_OUTPUT_PORT_TYPE
row8[5] <= out_LEDs[89].DB_MAX_OUTPUT_PORT_TYPE
row8[6] <= out_LEDs[90].DB_MAX_OUTPUT_PORT_TYPE
row8[7] <= out_LEDs[91].DB_MAX_OUTPUT_PORT_TYPE
row8[8] <= out_LEDs[92].DB_MAX_OUTPUT_PORT_TYPE
row8[9] <= out_LEDs[93].DB_MAX_OUTPUT_PORT_TYPE
row8[10] <= out_LEDs[94].DB_MAX_OUTPUT_PORT_TYPE
row8[11] <= out_LEDs[95].DB_MAX_OUTPUT_PORT_TYPE


|GECKO|LEDs:LEDs_0
clk => duty_cycle[0].CLK
clk => duty_cycle[1].CLK
clk => duty_cycle[2].CLK
clk => duty_cycle[3].CLK
clk => duty_cycle[4].CLK
clk => duty_cycle[5].CLK
clk => duty_cycle[6].CLK
clk => duty_cycle[7].CLK
clk => LEDs_reg[0].CLK
clk => LEDs_reg[1].CLK
clk => LEDs_reg[2].CLK
clk => LEDs_reg[3].CLK
clk => LEDs_reg[4].CLK
clk => LEDs_reg[5].CLK
clk => LEDs_reg[6].CLK
clk => LEDs_reg[7].CLK
clk => LEDs_reg[8].CLK
clk => LEDs_reg[9].CLK
clk => LEDs_reg[10].CLK
clk => LEDs_reg[11].CLK
clk => LEDs_reg[12].CLK
clk => LEDs_reg[13].CLK
clk => LEDs_reg[14].CLK
clk => LEDs_reg[15].CLK
clk => LEDs_reg[16].CLK
clk => LEDs_reg[17].CLK
clk => LEDs_reg[18].CLK
clk => LEDs_reg[19].CLK
clk => LEDs_reg[20].CLK
clk => LEDs_reg[21].CLK
clk => LEDs_reg[22].CLK
clk => LEDs_reg[23].CLK
clk => LEDs_reg[24].CLK
clk => LEDs_reg[25].CLK
clk => LEDs_reg[26].CLK
clk => LEDs_reg[27].CLK
clk => LEDs_reg[28].CLK
clk => LEDs_reg[29].CLK
clk => LEDs_reg[30].CLK
clk => LEDs_reg[31].CLK
clk => LEDs_reg[32].CLK
clk => LEDs_reg[33].CLK
clk => LEDs_reg[34].CLK
clk => LEDs_reg[35].CLK
clk => LEDs_reg[36].CLK
clk => LEDs_reg[37].CLK
clk => LEDs_reg[38].CLK
clk => LEDs_reg[39].CLK
clk => LEDs_reg[40].CLK
clk => LEDs_reg[41].CLK
clk => LEDs_reg[42].CLK
clk => LEDs_reg[43].CLK
clk => LEDs_reg[44].CLK
clk => LEDs_reg[45].CLK
clk => LEDs_reg[46].CLK
clk => LEDs_reg[47].CLK
clk => LEDs_reg[48].CLK
clk => LEDs_reg[49].CLK
clk => LEDs_reg[50].CLK
clk => LEDs_reg[51].CLK
clk => LEDs_reg[52].CLK
clk => LEDs_reg[53].CLK
clk => LEDs_reg[54].CLK
clk => LEDs_reg[55].CLK
clk => LEDs_reg[56].CLK
clk => LEDs_reg[57].CLK
clk => LEDs_reg[58].CLK
clk => LEDs_reg[59].CLK
clk => LEDs_reg[60].CLK
clk => LEDs_reg[61].CLK
clk => LEDs_reg[62].CLK
clk => LEDs_reg[63].CLK
clk => LEDs_reg[64].CLK
clk => LEDs_reg[65].CLK
clk => LEDs_reg[66].CLK
clk => LEDs_reg[67].CLK
clk => LEDs_reg[68].CLK
clk => LEDs_reg[69].CLK
clk => LEDs_reg[70].CLK
clk => LEDs_reg[71].CLK
clk => LEDs_reg[72].CLK
clk => LEDs_reg[73].CLK
clk => LEDs_reg[74].CLK
clk => LEDs_reg[75].CLK
clk => LEDs_reg[76].CLK
clk => LEDs_reg[77].CLK
clk => LEDs_reg[78].CLK
clk => LEDs_reg[79].CLK
clk => LEDs_reg[80].CLK
clk => LEDs_reg[81].CLK
clk => LEDs_reg[82].CLK
clk => LEDs_reg[83].CLK
clk => LEDs_reg[84].CLK
clk => LEDs_reg[85].CLK
clk => LEDs_reg[86].CLK
clk => LEDs_reg[87].CLK
clk => LEDs_reg[88].CLK
clk => LEDs_reg[89].CLK
clk => LEDs_reg[90].CLK
clk => LEDs_reg[91].CLK
clk => LEDs_reg[92].CLK
clk => LEDs_reg[93].CLK
clk => LEDs_reg[94].CLK
clk => LEDs_reg[95].CLK
clk => counter[0].CLK
clk => counter[1].CLK
clk => counter[2].CLK
clk => counter[3].CLK
clk => counter[4].CLK
clk => counter[5].CLK
clk => counter[6].CLK
clk => counter[7].CLK
clk => reg_address[0].CLK
clk => reg_address[1].CLK
clk => reg_read.CLK
reset_n => duty_cycle[0].PRESET
reset_n => duty_cycle[1].PRESET
reset_n => duty_cycle[2].PRESET
reset_n => duty_cycle[3].PRESET
reset_n => duty_cycle[4].ACLR
reset_n => duty_cycle[5].ACLR
reset_n => duty_cycle[6].ACLR
reset_n => duty_cycle[7].ACLR
reset_n => LEDs_reg[0].ACLR
reset_n => LEDs_reg[1].ACLR
reset_n => LEDs_reg[2].ACLR
reset_n => LEDs_reg[3].ACLR
reset_n => LEDs_reg[4].ACLR
reset_n => LEDs_reg[5].ACLR
reset_n => LEDs_reg[6].ACLR
reset_n => LEDs_reg[7].ACLR
reset_n => LEDs_reg[8].ACLR
reset_n => LEDs_reg[9].ACLR
reset_n => LEDs_reg[10].ACLR
reset_n => LEDs_reg[11].ACLR
reset_n => LEDs_reg[12].ACLR
reset_n => LEDs_reg[13].ACLR
reset_n => LEDs_reg[14].ACLR
reset_n => LEDs_reg[15].ACLR
reset_n => LEDs_reg[16].ACLR
reset_n => LEDs_reg[17].ACLR
reset_n => LEDs_reg[18].ACLR
reset_n => LEDs_reg[19].ACLR
reset_n => LEDs_reg[20].ACLR
reset_n => LEDs_reg[21].ACLR
reset_n => LEDs_reg[22].ACLR
reset_n => LEDs_reg[23].ACLR
reset_n => LEDs_reg[24].ACLR
reset_n => LEDs_reg[25].ACLR
reset_n => LEDs_reg[26].ACLR
reset_n => LEDs_reg[27].ACLR
reset_n => LEDs_reg[28].ACLR
reset_n => LEDs_reg[29].ACLR
reset_n => LEDs_reg[30].ACLR
reset_n => LEDs_reg[31].ACLR
reset_n => LEDs_reg[32].ACLR
reset_n => LEDs_reg[33].ACLR
reset_n => LEDs_reg[34].ACLR
reset_n => LEDs_reg[35].ACLR
reset_n => LEDs_reg[36].ACLR
reset_n => LEDs_reg[37].ACLR
reset_n => LEDs_reg[38].ACLR
reset_n => LEDs_reg[39].ACLR
reset_n => LEDs_reg[40].ACLR
reset_n => LEDs_reg[41].ACLR
reset_n => LEDs_reg[42].ACLR
reset_n => LEDs_reg[43].ACLR
reset_n => LEDs_reg[44].ACLR
reset_n => LEDs_reg[45].ACLR
reset_n => LEDs_reg[46].ACLR
reset_n => LEDs_reg[47].ACLR
reset_n => LEDs_reg[48].ACLR
reset_n => LEDs_reg[49].ACLR
reset_n => LEDs_reg[50].ACLR
reset_n => LEDs_reg[51].ACLR
reset_n => LEDs_reg[52].ACLR
reset_n => LEDs_reg[53].ACLR
reset_n => LEDs_reg[54].ACLR
reset_n => LEDs_reg[55].ACLR
reset_n => LEDs_reg[56].ACLR
reset_n => LEDs_reg[57].ACLR
reset_n => LEDs_reg[58].ACLR
reset_n => LEDs_reg[59].ACLR
reset_n => LEDs_reg[60].ACLR
reset_n => LEDs_reg[61].ACLR
reset_n => LEDs_reg[62].ACLR
reset_n => LEDs_reg[63].ACLR
reset_n => LEDs_reg[64].ACLR
reset_n => LEDs_reg[65].ACLR
reset_n => LEDs_reg[66].ACLR
reset_n => LEDs_reg[67].ACLR
reset_n => LEDs_reg[68].ACLR
reset_n => LEDs_reg[69].ACLR
reset_n => LEDs_reg[70].ACLR
reset_n => LEDs_reg[71].ACLR
reset_n => LEDs_reg[72].ACLR
reset_n => LEDs_reg[73].ACLR
reset_n => LEDs_reg[74].ACLR
reset_n => LEDs_reg[75].ACLR
reset_n => LEDs_reg[76].ACLR
reset_n => LEDs_reg[77].ACLR
reset_n => LEDs_reg[78].ACLR
reset_n => LEDs_reg[79].ACLR
reset_n => LEDs_reg[80].ACLR
reset_n => LEDs_reg[81].ACLR
reset_n => LEDs_reg[82].ACLR
reset_n => LEDs_reg[83].ACLR
reset_n => LEDs_reg[84].ACLR
reset_n => LEDs_reg[85].ACLR
reset_n => LEDs_reg[86].ACLR
reset_n => LEDs_reg[87].ACLR
reset_n => LEDs_reg[88].ACLR
reset_n => LEDs_reg[89].ACLR
reset_n => LEDs_reg[90].ACLR
reset_n => LEDs_reg[91].ACLR
reset_n => LEDs_reg[92].ACLR
reset_n => LEDs_reg[93].ACLR
reset_n => LEDs_reg[94].ACLR
reset_n => LEDs_reg[95].ACLR
reset_n => counter[0].ACLR
reset_n => counter[1].ACLR
reset_n => counter[2].ACLR
reset_n => counter[3].ACLR
reset_n => counter[4].ACLR
reset_n => counter[5].ACLR
reset_n => counter[6].ACLR
reset_n => counter[7].ACLR
reset_n => reg_address[0].ACLR
reset_n => reg_address[1].ACLR
reset_n => reg_read.ACLR
cs => reg_read.IN0
cs => process_3.IN0
read => reg_read.IN1
write => process_3.IN1
address[0] => Mux32.IN1
address[0] => Mux33.IN1
address[0] => Mux34.IN1
address[0] => Mux35.IN1
address[0] => Mux36.IN1
address[0] => Mux37.IN1
address[0] => Mux38.IN1
address[0] => Mux39.IN1
address[0] => Mux40.IN1
address[0] => Mux41.IN1
address[0] => Mux42.IN1
address[0] => Mux43.IN1
address[0] => Mux44.IN1
address[0] => Mux45.IN1
address[0] => Mux46.IN1
address[0] => Mux47.IN1
address[0] => Mux48.IN1
address[0] => Mux49.IN1
address[0] => Mux50.IN1
address[0] => Mux51.IN1
address[0] => Mux52.IN1
address[0] => Mux53.IN1
address[0] => Mux54.IN1
address[0] => Mux55.IN1
address[0] => Mux56.IN1
address[0] => Mux57.IN1
address[0] => Mux58.IN1
address[0] => Mux59.IN1
address[0] => Mux60.IN1
address[0] => Mux61.IN1
address[0] => Mux62.IN1
address[0] => Mux63.IN1
address[0] => Mux64.IN1
address[0] => Mux65.IN1
address[0] => Mux66.IN1
address[0] => Mux67.IN1
address[0] => Mux68.IN1
address[0] => Mux69.IN1
address[0] => Mux70.IN1
address[0] => Mux71.IN1
address[0] => Mux72.IN1
address[0] => Mux73.IN1
address[0] => Mux74.IN1
address[0] => Mux75.IN1
address[0] => Mux76.IN1
address[0] => Mux77.IN1
address[0] => Mux78.IN1
address[0] => Mux79.IN1
address[0] => Mux80.IN1
address[0] => Mux81.IN1
address[0] => Mux82.IN1
address[0] => Mux83.IN1
address[0] => Mux84.IN1
address[0] => Mux85.IN1
address[0] => Mux86.IN1
address[0] => Mux87.IN1
address[0] => Mux88.IN1
address[0] => Mux89.IN1
address[0] => Mux90.IN1
address[0] => Mux91.IN1
address[0] => Mux92.IN1
address[0] => Mux93.IN1
address[0] => Mux94.IN1
address[0] => Mux95.IN1
address[0] => Mux96.IN1
address[0] => Mux97.IN1
address[0] => Mux98.IN1
address[0] => Mux99.IN1
address[0] => Mux100.IN1
address[0] => Mux101.IN1
address[0] => Mux102.IN1
address[0] => Mux103.IN1
address[0] => Mux104.IN1
address[0] => Mux105.IN1
address[0] => Mux106.IN1
address[0] => Mux107.IN1
address[0] => Mux108.IN1
address[0] => Mux109.IN1
address[0] => Mux110.IN1
address[0] => Mux111.IN1
address[0] => Mux112.IN1
address[0] => Mux113.IN1
address[0] => Mux114.IN1
address[0] => Mux115.IN1
address[0] => Mux116.IN1
address[0] => Mux117.IN1
address[0] => Mux118.IN1
address[0] => Mux119.IN1
address[0] => Mux120.IN1
address[0] => Mux121.IN1
address[0] => Mux122.IN1
address[0] => Mux123.IN1
address[0] => Mux124.IN1
address[0] => Mux125.IN1
address[0] => Mux126.IN1
address[0] => Mux127.IN1
address[0] => Mux128.IN1
address[0] => Mux129.IN1
address[0] => Mux130.IN1
address[0] => Mux131.IN1
address[0] => Mux132.IN1
address[0] => Mux133.IN1
address[0] => Mux134.IN1
address[0] => Mux135.IN1
address[0] => reg_address[0].DATAIN
address[0] => Equal0.IN1
address[1] => Mux32.IN0
address[1] => Mux33.IN0
address[1] => Mux34.IN0
address[1] => Mux35.IN0
address[1] => Mux36.IN0
address[1] => Mux37.IN0
address[1] => Mux38.IN0
address[1] => Mux39.IN0
address[1] => Mux40.IN0
address[1] => Mux41.IN0
address[1] => Mux42.IN0
address[1] => Mux43.IN0
address[1] => Mux44.IN0
address[1] => Mux45.IN0
address[1] => Mux46.IN0
address[1] => Mux47.IN0
address[1] => Mux48.IN0
address[1] => Mux49.IN0
address[1] => Mux50.IN0
address[1] => Mux51.IN0
address[1] => Mux52.IN0
address[1] => Mux53.IN0
address[1] => Mux54.IN0
address[1] => Mux55.IN0
address[1] => Mux56.IN0
address[1] => Mux57.IN0
address[1] => Mux58.IN0
address[1] => Mux59.IN0
address[1] => Mux60.IN0
address[1] => Mux61.IN0
address[1] => Mux62.IN0
address[1] => Mux63.IN0
address[1] => Mux64.IN0
address[1] => Mux65.IN0
address[1] => Mux66.IN0
address[1] => Mux67.IN0
address[1] => Mux68.IN0
address[1] => Mux69.IN0
address[1] => Mux70.IN0
address[1] => Mux71.IN0
address[1] => Mux72.IN0
address[1] => Mux73.IN0
address[1] => Mux74.IN0
address[1] => Mux75.IN0
address[1] => Mux76.IN0
address[1] => Mux77.IN0
address[1] => Mux78.IN0
address[1] => Mux79.IN0
address[1] => Mux80.IN0
address[1] => Mux81.IN0
address[1] => Mux82.IN0
address[1] => Mux83.IN0
address[1] => Mux84.IN0
address[1] => Mux85.IN0
address[1] => Mux86.IN0
address[1] => Mux87.IN0
address[1] => Mux88.IN0
address[1] => Mux89.IN0
address[1] => Mux90.IN0
address[1] => Mux91.IN0
address[1] => Mux92.IN0
address[1] => Mux93.IN0
address[1] => Mux94.IN0
address[1] => Mux95.IN0
address[1] => Mux96.IN0
address[1] => Mux97.IN0
address[1] => Mux98.IN0
address[1] => Mux99.IN0
address[1] => Mux100.IN0
address[1] => Mux101.IN0
address[1] => Mux102.IN0
address[1] => Mux103.IN0
address[1] => Mux104.IN0
address[1] => Mux105.IN0
address[1] => Mux106.IN0
address[1] => Mux107.IN0
address[1] => Mux108.IN0
address[1] => Mux109.IN0
address[1] => Mux110.IN0
address[1] => Mux111.IN0
address[1] => Mux112.IN0
address[1] => Mux113.IN0
address[1] => Mux114.IN0
address[1] => Mux115.IN0
address[1] => Mux116.IN0
address[1] => Mux117.IN0
address[1] => Mux118.IN0
address[1] => Mux119.IN0
address[1] => Mux120.IN0
address[1] => Mux121.IN0
address[1] => Mux122.IN0
address[1] => Mux123.IN0
address[1] => Mux124.IN0
address[1] => Mux125.IN0
address[1] => Mux126.IN0
address[1] => Mux127.IN0
address[1] => Mux128.IN0
address[1] => Mux129.IN0
address[1] => Mux130.IN0
address[1] => Mux131.IN0
address[1] => Mux132.IN0
address[1] => Mux133.IN0
address[1] => Mux134.IN0
address[1] => Mux135.IN0
address[1] => reg_address[1].DATAIN
address[1] => Equal0.IN0
rddata[0] <= rddata[0].DB_MAX_OUTPUT_PORT_TYPE
rddata[1] <= rddata[1].DB_MAX_OUTPUT_PORT_TYPE
rddata[2] <= rddata[2].DB_MAX_OUTPUT_PORT_TYPE
rddata[3] <= rddata[3].DB_MAX_OUTPUT_PORT_TYPE
rddata[4] <= rddata[4].DB_MAX_OUTPUT_PORT_TYPE
rddata[5] <= rddata[5].DB_MAX_OUTPUT_PORT_TYPE
rddata[6] <= rddata[6].DB_MAX_OUTPUT_PORT_TYPE
rddata[7] <= rddata[7].DB_MAX_OUTPUT_PORT_TYPE
rddata[8] <= rddata[8].DB_MAX_OUTPUT_PORT_TYPE
rddata[9] <= rddata[9].DB_MAX_OUTPUT_PORT_TYPE
rddata[10] <= rddata[10].DB_MAX_OUTPUT_PORT_TYPE
rddata[11] <= rddata[11].DB_MAX_OUTPUT_PORT_TYPE
rddata[12] <= rddata[12].DB_MAX_OUTPUT_PORT_TYPE
rddata[13] <= rddata[13].DB_MAX_OUTPUT_PORT_TYPE
rddata[14] <= rddata[14].DB_MAX_OUTPUT_PORT_TYPE
rddata[15] <= rddata[15].DB_MAX_OUTPUT_PORT_TYPE
rddata[16] <= rddata[16].DB_MAX_OUTPUT_PORT_TYPE
rddata[17] <= rddata[17].DB_MAX_OUTPUT_PORT_TYPE
rddata[18] <= rddata[18].DB_MAX_OUTPUT_PORT_TYPE
rddata[19] <= rddata[19].DB_MAX_OUTPUT_PORT_TYPE
rddata[20] <= rddata[20].DB_MAX_OUTPUT_PORT_TYPE
rddata[21] <= rddata[21].DB_MAX_OUTPUT_PORT_TYPE
rddata[22] <= rddata[22].DB_MAX_OUTPUT_PORT_TYPE
rddata[23] <= rddata[23].DB_MAX_OUTPUT_PORT_TYPE
rddata[24] <= rddata[24].DB_MAX_OUTPUT_PORT_TYPE
rddata[25] <= rddata[25].DB_MAX_OUTPUT_PORT_TYPE
rddata[26] <= rddata[26].DB_MAX_OUTPUT_PORT_TYPE
rddata[27] <= rddata[27].DB_MAX_OUTPUT_PORT_TYPE
rddata[28] <= rddata[28].DB_MAX_OUTPUT_PORT_TYPE
rddata[29] <= rddata[29].DB_MAX_OUTPUT_PORT_TYPE
rddata[30] <= rddata[30].DB_MAX_OUTPUT_PORT_TYPE
rddata[31] <= rddata[31].DB_MAX_OUTPUT_PORT_TYPE
wrdata[0] => Mux63.IN2
wrdata[0] => Mux95.IN2
wrdata[0] => Mux127.IN2
wrdata[0] => Mux135.IN2
wrdata[1] => Mux62.IN2
wrdata[1] => Mux94.IN2
wrdata[1] => Mux126.IN2
wrdata[1] => Mux134.IN2
wrdata[2] => Mux61.IN2
wrdata[2] => Mux93.IN2
wrdata[2] => Mux125.IN2
wrdata[2] => Mux133.IN2
wrdata[3] => Mux60.IN2
wrdata[3] => Mux92.IN2
wrdata[3] => Mux124.IN2
wrdata[3] => Mux132.IN2
wrdata[4] => Mux59.IN2
wrdata[4] => Mux91.IN2
wrdata[4] => Mux123.IN2
wrdata[4] => Mux131.IN2
wrdata[5] => Mux58.IN2
wrdata[5] => Mux90.IN2
wrdata[5] => Mux122.IN2
wrdata[5] => Mux130.IN2
wrdata[6] => Mux57.IN2
wrdata[6] => Mux89.IN2
wrdata[6] => Mux121.IN2
wrdata[6] => Mux129.IN2
wrdata[7] => Mux56.IN2
wrdata[7] => Mux88.IN2
wrdata[7] => Mux120.IN2
wrdata[7] => Mux128.IN2
wrdata[8] => Mux55.IN2
wrdata[8] => Mux87.IN2
wrdata[8] => Mux119.IN2
wrdata[9] => Mux54.IN2
wrdata[9] => Mux86.IN2
wrdata[9] => Mux118.IN2
wrdata[10] => Mux53.IN2
wrdata[10] => Mux85.IN2
wrdata[10] => Mux117.IN2
wrdata[11] => Mux52.IN2
wrdata[11] => Mux84.IN2
wrdata[11] => Mux116.IN2
wrdata[12] => Mux51.IN2
wrdata[12] => Mux83.IN2
wrdata[12] => Mux115.IN2
wrdata[13] => Mux50.IN2
wrdata[13] => Mux82.IN2
wrdata[13] => Mux114.IN2
wrdata[14] => Mux49.IN2
wrdata[14] => Mux81.IN2
wrdata[14] => Mux113.IN2
wrdata[15] => Mux48.IN2
wrdata[15] => Mux80.IN2
wrdata[15] => Mux112.IN2
wrdata[16] => Mux47.IN2
wrdata[16] => Mux79.IN2
wrdata[16] => Mux111.IN2
wrdata[17] => Mux46.IN2
wrdata[17] => Mux78.IN2
wrdata[17] => Mux110.IN2
wrdata[18] => Mux45.IN2
wrdata[18] => Mux77.IN2
wrdata[18] => Mux109.IN2
wrdata[19] => Mux44.IN2
wrdata[19] => Mux76.IN2
wrdata[19] => Mux108.IN2
wrdata[20] => Mux43.IN2
wrdata[20] => Mux75.IN2
wrdata[20] => Mux107.IN2
wrdata[21] => Mux42.IN2
wrdata[21] => Mux74.IN2
wrdata[21] => Mux106.IN2
wrdata[22] => Mux41.IN2
wrdata[22] => Mux73.IN2
wrdata[22] => Mux105.IN2
wrdata[23] => Mux40.IN2
wrdata[23] => Mux72.IN2
wrdata[23] => Mux104.IN2
wrdata[24] => Mux39.IN2
wrdata[24] => Mux71.IN2
wrdata[24] => Mux103.IN2
wrdata[25] => Mux38.IN2
wrdata[25] => Mux70.IN2
wrdata[25] => Mux102.IN2
wrdata[26] => Mux37.IN2
wrdata[26] => Mux69.IN2
wrdata[26] => Mux101.IN2
wrdata[27] => Mux36.IN2
wrdata[27] => Mux68.IN2
wrdata[27] => Mux100.IN2
wrdata[28] => Mux35.IN2
wrdata[28] => Mux67.IN2
wrdata[28] => Mux99.IN2
wrdata[29] => Mux34.IN2
wrdata[29] => Mux66.IN2
wrdata[29] => Mux98.IN2
wrdata[30] => Mux33.IN2
wrdata[30] => Mux65.IN2
wrdata[30] => Mux97.IN2
wrdata[31] => Mux32.IN2
wrdata[31] => Mux64.IN2
wrdata[31] => Mux96.IN2
LEDs[0] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[1] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[2] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[3] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[4] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[5] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[6] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[7] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[8] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[9] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[10] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[11] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[12] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[13] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[14] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[15] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[16] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[17] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[18] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[19] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[20] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[21] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[22] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[23] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[24] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[25] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[26] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[27] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[28] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[29] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[30] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[31] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[32] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[33] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[34] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[35] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[36] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[37] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[38] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[39] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[40] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[41] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[42] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[43] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[44] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[45] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[46] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[47] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[48] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[49] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[50] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[51] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[52] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[53] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[54] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[55] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[56] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[57] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[58] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[59] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[60] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[61] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[62] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[63] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[64] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[65] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[66] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[67] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[68] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[69] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[70] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[71] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[72] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[73] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[74] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[75] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[76] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[77] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[78] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[79] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[80] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[81] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[82] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[83] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[84] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[85] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[86] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[87] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[88] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[89] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[90] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[91] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[92] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[93] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[94] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE
LEDs[95] <= LEDs_FPGA4U.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|decoder:decoder_0
address[0] => LessThan0.IN32
address[0] => LessThan1.IN32
address[0] => LessThan2.IN32
address[0] => LessThan3.IN32
address[0] => LessThan4.IN32
address[1] => LessThan0.IN31
address[1] => LessThan1.IN31
address[1] => LessThan2.IN31
address[1] => LessThan3.IN31
address[1] => LessThan4.IN31
address[2] => LessThan0.IN30
address[2] => LessThan1.IN30
address[2] => LessThan2.IN30
address[2] => LessThan3.IN30
address[2] => LessThan4.IN30
address[3] => LessThan0.IN29
address[3] => LessThan1.IN29
address[3] => LessThan2.IN29
address[3] => LessThan3.IN29
address[3] => LessThan4.IN29
address[4] => LessThan0.IN28
address[4] => LessThan1.IN28
address[4] => LessThan2.IN28
address[4] => LessThan3.IN28
address[4] => LessThan4.IN28
address[5] => LessThan0.IN27
address[5] => LessThan1.IN27
address[5] => LessThan2.IN27
address[5] => LessThan3.IN27
address[5] => LessThan4.IN27
address[6] => LessThan0.IN26
address[6] => LessThan1.IN26
address[6] => LessThan2.IN26
address[6] => LessThan3.IN26
address[6] => LessThan4.IN26
address[7] => LessThan0.IN25
address[7] => LessThan1.IN25
address[7] => LessThan2.IN25
address[7] => LessThan3.IN25
address[7] => LessThan4.IN25
address[8] => LessThan0.IN24
address[8] => LessThan1.IN24
address[8] => LessThan2.IN24
address[8] => LessThan3.IN24
address[8] => LessThan4.IN24
address[9] => LessThan0.IN23
address[9] => LessThan1.IN23
address[9] => LessThan2.IN23
address[9] => LessThan3.IN23
address[9] => LessThan4.IN23
address[10] => LessThan0.IN22
address[10] => LessThan1.IN22
address[10] => LessThan2.IN22
address[10] => LessThan3.IN22
address[10] => LessThan4.IN22
address[11] => LessThan0.IN21
address[11] => LessThan1.IN21
address[11] => LessThan2.IN21
address[11] => LessThan3.IN21
address[11] => LessThan4.IN21
address[12] => LessThan0.IN20
address[12] => LessThan1.IN20
address[12] => LessThan2.IN20
address[12] => LessThan3.IN20
address[12] => LessThan4.IN20
address[13] => LessThan0.IN19
address[13] => LessThan1.IN19
address[13] => LessThan2.IN19
address[13] => LessThan3.IN19
address[13] => LessThan4.IN19
address[14] => LessThan0.IN18
address[14] => LessThan1.IN18
address[14] => LessThan2.IN18
address[14] => LessThan3.IN18
address[14] => LessThan4.IN18
address[15] => LessThan0.IN17
address[15] => LessThan1.IN17
address[15] => LessThan2.IN17
address[15] => LessThan3.IN17
address[15] => LessThan4.IN17
cs_LEDS <= cs_LEDS.DB_MAX_OUTPUT_PORT_TYPE
cs_RAM <= cs_RAM.DB_MAX_OUTPUT_PORT_TYPE
cs_ROM <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
cs_buttons <= cs_buttons.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst
write <= controller:controller_0.write
clk => controller:controller_0.clk
clk => IR:IR_0.clk
clk => PC:PC_0.clk
clk => register_file:register_file_0.clk
reset_n => controller:controller_0.reset_n
reset_n => PC:PC_0.reset_n
rddata[0] => IR:IR_0.D[0]
rddata[0] => mux2x32:mux_mem.i1[0]
rddata[1] => IR:IR_0.D[1]
rddata[1] => mux2x32:mux_mem.i1[1]
rddata[2] => IR:IR_0.D[2]
rddata[2] => mux2x32:mux_mem.i1[2]
rddata[3] => IR:IR_0.D[3]
rddata[3] => mux2x32:mux_mem.i1[3]
rddata[4] => IR:IR_0.D[4]
rddata[4] => mux2x32:mux_mem.i1[4]
rddata[5] => IR:IR_0.D[5]
rddata[5] => mux2x32:mux_mem.i1[5]
rddata[6] => IR:IR_0.D[6]
rddata[6] => mux2x32:mux_mem.i1[6]
rddata[7] => IR:IR_0.D[7]
rddata[7] => mux2x32:mux_mem.i1[7]
rddata[8] => IR:IR_0.D[8]
rddata[8] => mux2x32:mux_mem.i1[8]
rddata[9] => IR:IR_0.D[9]
rddata[9] => mux2x32:mux_mem.i1[9]
rddata[10] => IR:IR_0.D[10]
rddata[10] => mux2x32:mux_mem.i1[10]
rddata[11] => IR:IR_0.D[11]
rddata[11] => mux2x32:mux_mem.i1[11]
rddata[12] => IR:IR_0.D[12]
rddata[12] => mux2x32:mux_mem.i1[12]
rddata[13] => IR:IR_0.D[13]
rddata[13] => mux2x32:mux_mem.i1[13]
rddata[14] => IR:IR_0.D[14]
rddata[14] => mux2x32:mux_mem.i1[14]
rddata[15] => IR:IR_0.D[15]
rddata[15] => mux2x32:mux_mem.i1[15]
rddata[16] => IR:IR_0.D[16]
rddata[16] => mux2x32:mux_mem.i1[16]
rddata[17] => IR:IR_0.D[17]
rddata[17] => mux2x32:mux_mem.i1[17]
rddata[18] => IR:IR_0.D[18]
rddata[18] => mux2x32:mux_mem.i1[18]
rddata[19] => IR:IR_0.D[19]
rddata[19] => mux2x32:mux_mem.i1[19]
rddata[20] => IR:IR_0.D[20]
rddata[20] => mux2x32:mux_mem.i1[20]
rddata[21] => IR:IR_0.D[21]
rddata[21] => mux2x32:mux_mem.i1[21]
rddata[22] => IR:IR_0.D[22]
rddata[22] => mux2x32:mux_mem.i1[22]
rddata[23] => IR:IR_0.D[23]
rddata[23] => mux2x32:mux_mem.i1[23]
rddata[24] => IR:IR_0.D[24]
rddata[24] => mux2x32:mux_mem.i1[24]
rddata[25] => IR:IR_0.D[25]
rddata[25] => mux2x32:mux_mem.i1[25]
rddata[26] => IR:IR_0.D[26]
rddata[26] => mux2x32:mux_mem.i1[26]
rddata[27] => IR:IR_0.D[27]
rddata[27] => mux2x32:mux_mem.i1[27]
rddata[28] => IR:IR_0.D[28]
rddata[28] => mux2x32:mux_mem.i1[28]
rddata[29] => IR:IR_0.D[29]
rddata[29] => mux2x32:mux_mem.i1[29]
rddata[30] => IR:IR_0.D[30]
rddata[30] => mux2x32:mux_mem.i1[30]
rddata[31] => IR:IR_0.D[31]
rddata[31] => mux2x32:mux_mem.i1[31]
read <= controller:controller_0.read
address[0] <= mux2x16:mux_addr.o[0]
address[1] <= mux2x16:mux_addr.o[1]
address[2] <= mux2x16:mux_addr.o[2]
address[3] <= mux2x16:mux_addr.o[3]
address[4] <= mux2x16:mux_addr.o[4]
address[5] <= mux2x16:mux_addr.o[5]
address[6] <= mux2x16:mux_addr.o[6]
address[7] <= mux2x16:mux_addr.o[7]
address[8] <= mux2x16:mux_addr.o[8]
address[9] <= mux2x16:mux_addr.o[9]
address[10] <= mux2x16:mux_addr.o[10]
address[11] <= mux2x16:mux_addr.o[11]
address[12] <= mux2x16:mux_addr.o[12]
address[13] <= mux2x16:mux_addr.o[13]
address[14] <= mux2x16:mux_addr.o[14]
address[15] <= mux2x16:mux_addr.o[15]
wrdata[0] <= b[0].DB_MAX_OUTPUT_PORT_TYPE
wrdata[1] <= b[1].DB_MAX_OUTPUT_PORT_TYPE
wrdata[2] <= b[2].DB_MAX_OUTPUT_PORT_TYPE
wrdata[3] <= b[3].DB_MAX_OUTPUT_PORT_TYPE
wrdata[4] <= b[4].DB_MAX_OUTPUT_PORT_TYPE
wrdata[5] <= b[5].DB_MAX_OUTPUT_PORT_TYPE
wrdata[6] <= b[6].DB_MAX_OUTPUT_PORT_TYPE
wrdata[7] <= b[7].DB_MAX_OUTPUT_PORT_TYPE
wrdata[8] <= b[8].DB_MAX_OUTPUT_PORT_TYPE
wrdata[9] <= b[9].DB_MAX_OUTPUT_PORT_TYPE
wrdata[10] <= b[10].DB_MAX_OUTPUT_PORT_TYPE
wrdata[11] <= b[11].DB_MAX_OUTPUT_PORT_TYPE
wrdata[12] <= b[12].DB_MAX_OUTPUT_PORT_TYPE
wrdata[13] <= b[13].DB_MAX_OUTPUT_PORT_TYPE
wrdata[14] <= b[14].DB_MAX_OUTPUT_PORT_TYPE
wrdata[15] <= b[15].DB_MAX_OUTPUT_PORT_TYPE
wrdata[16] <= b[16].DB_MAX_OUTPUT_PORT_TYPE
wrdata[17] <= b[17].DB_MAX_OUTPUT_PORT_TYPE
wrdata[18] <= b[18].DB_MAX_OUTPUT_PORT_TYPE
wrdata[19] <= b[19].DB_MAX_OUTPUT_PORT_TYPE
wrdata[20] <= b[20].DB_MAX_OUTPUT_PORT_TYPE
wrdata[21] <= b[21].DB_MAX_OUTPUT_PORT_TYPE
wrdata[22] <= b[22].DB_MAX_OUTPUT_PORT_TYPE
wrdata[23] <= b[23].DB_MAX_OUTPUT_PORT_TYPE
wrdata[24] <= b[24].DB_MAX_OUTPUT_PORT_TYPE
wrdata[25] <= b[25].DB_MAX_OUTPUT_PORT_TYPE
wrdata[26] <= b[26].DB_MAX_OUTPUT_PORT_TYPE
wrdata[27] <= b[27].DB_MAX_OUTPUT_PORT_TYPE
wrdata[28] <= b[28].DB_MAX_OUTPUT_PORT_TYPE
wrdata[29] <= b[29].DB_MAX_OUTPUT_PORT_TYPE
wrdata[30] <= b[30].DB_MAX_OUTPUT_PORT_TYPE
wrdata[31] <= b[31].DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|controller:controller_0
clk => s_cur~1.DATAIN
reset_n => s_cur~3.DATAIN
op[0] => Equal1.IN5
op[0] => Equal5.IN5
op[0] => Equal6.IN1
op[0] => Equal10.IN1
op[0] => Equal11.IN3
op[0] => Equal13.IN1
op[0] => Equal14.IN3
op[0] => Equal16.IN2
op[0] => Equal17.IN3
op[0] => Equal18.IN4
op[0] => Equal20.IN1
op[0] => Equal21.IN3
op[0] => Equal23.IN2
op[0] => Equal24.IN4
op[0] => Equal26.IN2
op[0] => Equal27.IN4
op[0] => Equal36.IN2
op[0] => Equal38.IN3
op[0] => Equal40.IN3
op[0] => Equal44.IN4
op[0] => Equal45.IN5
op[0] => Equal46.IN5
op[1] => Equal1.IN4
op[1] => Equal5.IN4
op[1] => Equal6.IN5
op[1] => Equal10.IN5
op[1] => Equal11.IN2
op[1] => Equal13.IN5
op[1] => Equal14.IN2
op[1] => Equal16.IN5
op[1] => Equal17.IN5
op[1] => Equal18.IN3
op[1] => Equal20.IN5
op[1] => Equal21.IN2
op[1] => Equal23.IN5
op[1] => Equal24.IN3
op[1] => Equal26.IN5
op[1] => Equal27.IN3
op[1] => Equal36.IN1
op[1] => Equal38.IN2
op[1] => Equal40.IN2
op[1] => Equal44.IN3
op[1] => Equal45.IN4
op[1] => Equal46.IN2
op[2] => Equal1.IN3
op[2] => Equal5.IN3
op[2] => Equal6.IN0
op[2] => Equal10.IN4
op[2] => Equal11.IN1
op[2] => Equal13.IN4
op[2] => Equal14.IN1
op[2] => Equal16.IN4
op[2] => Equal17.IN4
op[2] => Equal18.IN2
op[2] => Equal20.IN4
op[2] => Equal21.IN1
op[2] => Equal23.IN4
op[2] => Equal24.IN2
op[2] => Equal26.IN4
op[2] => Equal27.IN2
op[2] => Equal36.IN5
op[2] => Equal38.IN5
op[2] => Equal40.IN5
op[2] => Equal44.IN5
op[2] => Equal45.IN3
op[2] => Equal46.IN4
op[3] => Equal1.IN2
op[3] => Equal5.IN2
op[3] => Equal6.IN4
op[3] => Equal10.IN0
op[3] => Equal11.IN0
op[3] => Equal13.IN3
op[3] => Equal14.IN5
op[3] => Equal16.IN1
op[3] => Equal17.IN2
op[3] => Equal18.IN1
op[3] => Equal20.IN3
op[3] => Equal21.IN5
op[3] => Equal23.IN1
op[3] => Equal24.IN1
op[3] => Equal26.IN3
op[3] => Equal27.IN5
op[3] => Equal36.IN4
op[3] => Equal38.IN1
op[3] => Equal40.IN4
op[3] => Equal44.IN2
op[3] => Equal45.IN1
op[3] => Equal46.IN1
op[4] => Equal1.IN1
op[4] => Equal5.IN1
op[4] => Equal6.IN3
op[4] => Equal10.IN3
op[4] => Equal11.IN5
op[4] => Equal13.IN0
op[4] => Equal14.IN0
op[4] => Equal16.IN0
op[4] => Equal17.IN1
op[4] => Equal18.IN0
op[4] => Equal20.IN2
op[4] => Equal21.IN4
op[4] => Equal23.IN3
op[4] => Equal24.IN5
op[4] => Equal26.IN1
op[4] => Equal27.IN1
op[4] => Equal36.IN3
op[4] => Equal38.IN4
op[4] => Equal40.IN1
op[4] => Equal44.IN1
op[4] => Equal45.IN2
op[4] => Equal46.IN3
op[5] => Equal1.IN0
op[5] => Equal5.IN0
op[5] => Equal6.IN2
op[5] => Equal10.IN2
op[5] => Equal11.IN4
op[5] => Equal13.IN2
op[5] => Equal14.IN4
op[5] => Equal16.IN3
op[5] => Equal17.IN0
op[5] => Equal18.IN5
op[5] => Equal20.IN0
op[5] => Equal21.IN0
op[5] => Equal23.IN0
op[5] => Equal24.IN0
op[5] => Equal26.IN0
op[5] => Equal27.IN0
op[5] => Equal36.IN0
op[5] => Equal38.IN0
op[5] => Equal40.IN0
op[5] => Equal44.IN0
op[5] => Equal45.IN0
op[5] => Equal46.IN0
opx[0] => Equal0.IN2
opx[0] => Equal2.IN5
opx[0] => Equal3.IN5
opx[0] => Equal4.IN5
opx[0] => Equal7.IN5
opx[0] => Equal8.IN4
opx[0] => Equal9.IN5
opx[0] => Equal12.IN3
opx[0] => Equal15.IN3
opx[0] => Equal19.IN4
opx[0] => Equal22.IN3
opx[0] => Equal25.IN4
opx[0] => Equal28.IN4
opx[0] => Equal29.IN5
opx[0] => Equal30.IN1
opx[0] => Equal31.IN5
opx[0] => Equal32.IN3
opx[0] => Equal33.IN5
opx[0] => Equal34.IN2
opx[0] => Equal35.IN3
opx[0] => Equal37.IN1
opx[0] => Equal39.IN2
opx[0] => Equal41.IN2
opx[0] => Equal42.IN5
opx[0] => Equal43.IN5
opx[1] => Equal0.IN1
opx[1] => Equal2.IN2
opx[1] => Equal3.IN3
opx[1] => Equal4.IN1
opx[1] => Equal7.IN4
opx[1] => Equal8.IN5
opx[1] => Equal9.IN4
opx[1] => Equal12.IN2
opx[1] => Equal15.IN2
opx[1] => Equal19.IN3
opx[1] => Equal22.IN2
opx[1] => Equal25.IN3
opx[1] => Equal28.IN3
opx[1] => Equal29.IN4
opx[1] => Equal30.IN5
opx[1] => Equal31.IN4
opx[1] => Equal32.IN5
opx[1] => Equal33.IN4
opx[1] => Equal34.IN5
opx[1] => Equal35.IN5
opx[1] => Equal37.IN5
opx[1] => Equal39.IN5
opx[1] => Equal41.IN5
opx[1] => Equal42.IN1
opx[1] => Equal43.IN2
opx[2] => Equal0.IN5
opx[2] => Equal2.IN4
opx[2] => Equal3.IN4
opx[2] => Equal4.IN4
opx[2] => Equal7.IN2
opx[2] => Equal8.IN3
opx[2] => Equal9.IN3
opx[2] => Equal12.IN1
opx[2] => Equal15.IN1
opx[2] => Equal19.IN2
opx[2] => Equal22.IN1
opx[2] => Equal25.IN2
opx[2] => Equal28.IN2
opx[2] => Equal29.IN0
opx[2] => Equal30.IN0
opx[2] => Equal31.IN2
opx[2] => Equal32.IN2
opx[2] => Equal33.IN1
opx[2] => Equal34.IN1
opx[2] => Equal35.IN4
opx[2] => Equal37.IN4
opx[2] => Equal39.IN4
opx[2] => Equal41.IN4
opx[2] => Equal42.IN0
opx[2] => Equal43.IN1
opx[3] => Equal0.IN0
opx[3] => Equal2.IN3
opx[3] => Equal3.IN2
opx[3] => Equal4.IN3
opx[3] => Equal7.IN3
opx[3] => Equal8.IN2
opx[3] => Equal9.IN2
opx[3] => Equal12.IN0
opx[3] => Equal15.IN5
opx[3] => Equal19.IN1
opx[3] => Equal22.IN5
opx[3] => Equal25.IN1
opx[3] => Equal28.IN5
opx[3] => Equal29.IN3
opx[3] => Equal30.IN4
opx[3] => Equal31.IN1
opx[3] => Equal32.IN1
opx[3] => Equal33.IN3
opx[3] => Equal34.IN4
opx[3] => Equal35.IN2
opx[3] => Equal37.IN3
opx[3] => Equal39.IN1
opx[3] => Equal41.IN3
opx[3] => Equal42.IN4
opx[3] => Equal43.IN0
opx[4] => Equal0.IN4
opx[4] => Equal2.IN1
opx[4] => Equal3.IN1
opx[4] => Equal4.IN2
opx[4] => Equal7.IN1
opx[4] => Equal8.IN1
opx[4] => Equal9.IN1
opx[4] => Equal12.IN5
opx[4] => Equal15.IN0
opx[4] => Equal19.IN0
opx[4] => Equal22.IN4
opx[4] => Equal25.IN5
opx[4] => Equal28.IN1
opx[4] => Equal29.IN2
opx[4] => Equal30.IN3
opx[4] => Equal31.IN3
opx[4] => Equal32.IN4
opx[4] => Equal33.IN2
opx[4] => Equal34.IN3
opx[4] => Equal35.IN1
opx[4] => Equal37.IN2
opx[4] => Equal39.IN3
opx[4] => Equal41.IN1
opx[4] => Equal42.IN3
opx[4] => Equal43.IN4
opx[5] => Equal0.IN3
opx[5] => Equal2.IN0
opx[5] => Equal3.IN0
opx[5] => Equal4.IN0
opx[5] => Equal7.IN0
opx[5] => Equal8.IN0
opx[5] => Equal9.IN0
opx[5] => Equal12.IN4
opx[5] => Equal15.IN4
opx[5] => Equal19.IN5
opx[5] => Equal22.IN0
opx[5] => Equal25.IN0
opx[5] => Equal28.IN0
opx[5] => Equal29.IN1
opx[5] => Equal30.IN2
opx[5] => Equal31.IN0
opx[5] => Equal32.IN0
opx[5] => Equal33.IN0
opx[5] => Equal34.IN0
opx[5] => Equal35.IN0
opx[5] => Equal37.IN0
opx[5] => Equal39.IN0
opx[5] => Equal41.IN0
opx[5] => Equal42.IN2
opx[5] => Equal43.IN3
branch_op <= branch_op.DB_MAX_OUTPUT_PORT_TYPE
imm_signed <= imm_signed.DB_MAX_OUTPUT_PORT_TYPE
ir_en <= ir_en.DB_MAX_OUTPUT_PORT_TYPE
pc_add_imm <= pc_add_imm.DB_MAX_OUTPUT_PORT_TYPE
pc_en <= pc_en.DB_MAX_OUTPUT_PORT_TYPE
pc_sel_a <= pc_sel_a.DB_MAX_OUTPUT_PORT_TYPE
pc_sel_imm <= pc_sel_imm.DB_MAX_OUTPUT_PORT_TYPE
rf_wren <= rf_wren.DB_MAX_OUTPUT_PORT_TYPE
sel_addr <= sel_addr.DB_MAX_OUTPUT_PORT_TYPE
sel_b <= sel_b.DB_MAX_OUTPUT_PORT_TYPE
sel_mem <= sel_mem.DB_MAX_OUTPUT_PORT_TYPE
sel_pc <= sel_pc.DB_MAX_OUTPUT_PORT_TYPE
sel_ra <= sel_ra.DB_MAX_OUTPUT_PORT_TYPE
sel_rC <= sel_rC.DB_MAX_OUTPUT_PORT_TYPE
read <= read.DB_MAX_OUTPUT_PORT_TYPE
write <= write.DB_MAX_OUTPUT_PORT_TYPE
op_alu[0] <= op_alu.DB_MAX_OUTPUT_PORT_TYPE
op_alu[1] <= op_alu.DB_MAX_OUTPUT_PORT_TYPE
op_alu[2] <= op_alu.DB_MAX_OUTPUT_PORT_TYPE
op_alu[3] <= op_alu.DB_MAX_OUTPUT_PORT_TYPE
op_alu[4] <= op_alu.DB_MAX_OUTPUT_PORT_TYPE
op_alu[5] <= op_alu.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|IR:IR_0
clk => sq[0].CLK
clk => sq[1].CLK
clk => sq[2].CLK
clk => sq[3].CLK
clk => sq[4].CLK
clk => sq[5].CLK
clk => sq[6].CLK
clk => sq[7].CLK
clk => sq[8].CLK
clk => sq[9].CLK
clk => sq[10].CLK
clk => sq[11].CLK
clk => sq[12].CLK
clk => sq[13].CLK
clk => sq[14].CLK
clk => sq[15].CLK
clk => sq[16].CLK
clk => sq[17].CLK
clk => sq[18].CLK
clk => sq[19].CLK
clk => sq[20].CLK
clk => sq[21].CLK
clk => sq[22].CLK
clk => sq[23].CLK
clk => sq[24].CLK
clk => sq[25].CLK
clk => sq[26].CLK
clk => sq[27].CLK
clk => sq[28].CLK
clk => sq[29].CLK
clk => sq[30].CLK
clk => sq[31].CLK
enable => sq[0].ENA
enable => sq[1].ENA
enable => sq[2].ENA
enable => sq[3].ENA
enable => sq[4].ENA
enable => sq[5].ENA
enable => sq[6].ENA
enable => sq[7].ENA
enable => sq[8].ENA
enable => sq[9].ENA
enable => sq[10].ENA
enable => sq[11].ENA
enable => sq[12].ENA
enable => sq[13].ENA
enable => sq[14].ENA
enable => sq[15].ENA
enable => sq[16].ENA
enable => sq[17].ENA
enable => sq[18].ENA
enable => sq[19].ENA
enable => sq[20].ENA
enable => sq[21].ENA
enable => sq[22].ENA
enable => sq[23].ENA
enable => sq[24].ENA
enable => sq[25].ENA
enable => sq[26].ENA
enable => sq[27].ENA
enable => sq[28].ENA
enable => sq[29].ENA
enable => sq[30].ENA
enable => sq[31].ENA
D[0] => sq[0].DATAIN
D[1] => sq[1].DATAIN
D[2] => sq[2].DATAIN
D[3] => sq[3].DATAIN
D[4] => sq[4].DATAIN
D[5] => sq[5].DATAIN
D[6] => sq[6].DATAIN
D[7] => sq[7].DATAIN
D[8] => sq[8].DATAIN
D[9] => sq[9].DATAIN
D[10] => sq[10].DATAIN
D[11] => sq[11].DATAIN
D[12] => sq[12].DATAIN
D[13] => sq[13].DATAIN
D[14] => sq[14].DATAIN
D[15] => sq[15].DATAIN
D[16] => sq[16].DATAIN
D[17] => sq[17].DATAIN
D[18] => sq[18].DATAIN
D[19] => sq[19].DATAIN
D[20] => sq[20].DATAIN
D[21] => sq[21].DATAIN
D[22] => sq[22].DATAIN
D[23] => sq[23].DATAIN
D[24] => sq[24].DATAIN
D[25] => sq[25].DATAIN
D[26] => sq[26].DATAIN
D[27] => sq[27].DATAIN
D[28] => sq[28].DATAIN
D[29] => sq[29].DATAIN
D[30] => sq[30].DATAIN
D[31] => sq[31].DATAIN
Q[0] <= sq[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= sq[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= sq[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= sq[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= sq[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= sq[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= sq[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= sq[7].DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= sq[8].DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= sq[9].DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= sq[10].DB_MAX_OUTPUT_PORT_TYPE
Q[11] <= sq[11].DB_MAX_OUTPUT_PORT_TYPE
Q[12] <= sq[12].DB_MAX_OUTPUT_PORT_TYPE
Q[13] <= sq[13].DB_MAX_OUTPUT_PORT_TYPE
Q[14] <= sq[14].DB_MAX_OUTPUT_PORT_TYPE
Q[15] <= sq[15].DB_MAX_OUTPUT_PORT_TYPE
Q[16] <= sq[16].DB_MAX_OUTPUT_PORT_TYPE
Q[17] <= sq[17].DB_MAX_OUTPUT_PORT_TYPE
Q[18] <= sq[18].DB_MAX_OUTPUT_PORT_TYPE
Q[19] <= sq[19].DB_MAX_OUTPUT_PORT_TYPE
Q[20] <= sq[20].DB_MAX_OUTPUT_PORT_TYPE
Q[21] <= sq[21].DB_MAX_OUTPUT_PORT_TYPE
Q[22] <= sq[22].DB_MAX_OUTPUT_PORT_TYPE
Q[23] <= sq[23].DB_MAX_OUTPUT_PORT_TYPE
Q[24] <= sq[24].DB_MAX_OUTPUT_PORT_TYPE
Q[25] <= sq[25].DB_MAX_OUTPUT_PORT_TYPE
Q[26] <= sq[26].DB_MAX_OUTPUT_PORT_TYPE
Q[27] <= sq[27].DB_MAX_OUTPUT_PORT_TYPE
Q[28] <= sq[28].DB_MAX_OUTPUT_PORT_TYPE
Q[29] <= sq[29].DB_MAX_OUTPUT_PORT_TYPE
Q[30] <= sq[30].DB_MAX_OUTPUT_PORT_TYPE
Q[31] <= sq[31].DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|mux2x16:mux_addr
i0[0] => o.DATAB
i0[1] => o.DATAB
i0[2] => o.DATAB
i0[3] => o.DATAB
i0[4] => o.DATAB
i0[5] => o.DATAB
i0[6] => o.DATAB
i0[7] => o.DATAB
i0[8] => o.DATAB
i0[9] => o.DATAB
i0[10] => o.DATAB
i0[11] => o.DATAB
i0[12] => o.DATAB
i0[13] => o.DATAB
i0[14] => o.DATAB
i0[15] => o.DATAB
i1[0] => o.DATAA
i1[1] => o.DATAA
i1[2] => o.DATAA
i1[3] => o.DATAA
i1[4] => o.DATAA
i1[5] => o.DATAA
i1[6] => o.DATAA
i1[7] => o.DATAA
i1[8] => o.DATAA
i1[9] => o.DATAA
i1[10] => o.DATAA
i1[11] => o.DATAA
i1[12] => o.DATAA
i1[13] => o.DATAA
i1[14] => o.DATAA
i1[15] => o.DATAA
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
o[0] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[1] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[2] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[3] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[4] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[5] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[6] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[7] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[8] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[9] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[10] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[11] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[12] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[13] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[14] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[15] <= o.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|PC:PC_0
clk => n_addr[0].CLK
clk => n_addr[1].CLK
clk => n_addr[2].CLK
clk => n_addr[3].CLK
clk => n_addr[4].CLK
clk => n_addr[5].CLK
clk => n_addr[6].CLK
clk => n_addr[7].CLK
clk => n_addr[8].CLK
clk => n_addr[9].CLK
clk => n_addr[10].CLK
clk => n_addr[11].CLK
clk => n_addr[12].CLK
clk => n_addr[13].CLK
clk => n_addr[14].CLK
clk => n_addr[15].CLK
clk => n_addr[16].CLK
clk => n_addr[17].CLK
clk => n_addr[18].CLK
clk => n_addr[19].CLK
clk => n_addr[20].CLK
clk => n_addr[21].CLK
clk => n_addr[22].CLK
clk => n_addr[23].CLK
clk => n_addr[24].CLK
clk => n_addr[25].CLK
clk => n_addr[26].CLK
clk => n_addr[27].CLK
clk => n_addr[28].CLK
clk => n_addr[29].CLK
clk => n_addr[30].CLK
clk => n_addr[31].CLK
reset_n => n_addr[0].ACLR
reset_n => n_addr[1].ACLR
reset_n => n_addr[2].ACLR
reset_n => n_addr[3].ACLR
reset_n => n_addr[4].ACLR
reset_n => n_addr[5].ACLR
reset_n => n_addr[6].ACLR
reset_n => n_addr[7].ACLR
reset_n => n_addr[8].ACLR
reset_n => n_addr[9].ACLR
reset_n => n_addr[10].ACLR
reset_n => n_addr[11].ACLR
reset_n => n_addr[12].ACLR
reset_n => n_addr[13].ACLR
reset_n => n_addr[14].ACLR
reset_n => n_addr[15].ACLR
reset_n => n_addr[16].ACLR
reset_n => n_addr[17].ACLR
reset_n => n_addr[18].ACLR
reset_n => n_addr[19].ACLR
reset_n => n_addr[20].ACLR
reset_n => n_addr[21].ACLR
reset_n => n_addr[22].ACLR
reset_n => n_addr[23].ACLR
reset_n => n_addr[24].ACLR
reset_n => n_addr[25].ACLR
reset_n => n_addr[26].ACLR
reset_n => n_addr[27].ACLR
reset_n => n_addr[28].ACLR
reset_n => n_addr[29].ACLR
reset_n => n_addr[30].ACLR
reset_n => n_addr[31].ACLR
en => n_addr[31].ENA
en => n_addr[30].ENA
en => n_addr[29].ENA
en => n_addr[28].ENA
en => n_addr[27].ENA
en => n_addr[26].ENA
en => n_addr[25].ENA
en => n_addr[24].ENA
en => n_addr[23].ENA
en => n_addr[22].ENA
en => n_addr[21].ENA
en => n_addr[20].ENA
en => n_addr[19].ENA
en => n_addr[18].ENA
en => n_addr[17].ENA
en => n_addr[16].ENA
en => n_addr[15].ENA
en => n_addr[14].ENA
en => n_addr[13].ENA
en => n_addr[12].ENA
en => n_addr[11].ENA
en => n_addr[10].ENA
en => n_addr[9].ENA
en => n_addr[8].ENA
en => n_addr[7].ENA
en => n_addr[6].ENA
en => n_addr[5].ENA
en => n_addr[4].ENA
en => n_addr[3].ENA
en => n_addr[2].ENA
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_a => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
sel_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
add_imm => n_addr.OUTPUTSELECT
imm[0] => Add0.IN33
imm[0] => n_addr.DATAB
imm[1] => Add0.IN32
imm[1] => n_addr.DATAB
imm[2] => Add0.IN31
imm[2] => n_addr.DATAB
imm[3] => Add0.IN30
imm[3] => n_addr.DATAB
imm[4] => Add0.IN29
imm[4] => n_addr.DATAB
imm[5] => Add0.IN28
imm[5] => n_addr.DATAB
imm[6] => Add0.IN27
imm[6] => n_addr.DATAB
imm[7] => Add0.IN26
imm[7] => n_addr.DATAB
imm[8] => Add0.IN25
imm[8] => n_addr.DATAB
imm[9] => Add0.IN24
imm[9] => n_addr.DATAB
imm[10] => Add0.IN23
imm[10] => n_addr.DATAB
imm[11] => Add0.IN22
imm[11] => n_addr.DATAB
imm[12] => Add0.IN21
imm[12] => n_addr.DATAB
imm[13] => Add0.IN20
imm[13] => n_addr.DATAB
imm[14] => Add0.IN19
imm[15] => Add0.IN2
imm[15] => Add0.IN3
imm[15] => Add0.IN4
imm[15] => Add0.IN5
imm[15] => Add0.IN6
imm[15] => Add0.IN7
imm[15] => Add0.IN8
imm[15] => Add0.IN9
imm[15] => Add0.IN10
imm[15] => Add0.IN11
imm[15] => Add0.IN12
imm[15] => Add0.IN13
imm[15] => Add0.IN14
imm[15] => Add0.IN15
imm[15] => Add0.IN16
imm[15] => Add0.IN17
imm[15] => Add0.IN18
a[0] => ~NO_FANOUT~
a[1] => ~NO_FANOUT~
a[2] => n_addr.DATAB
a[3] => n_addr.DATAB
a[4] => n_addr.DATAB
a[5] => n_addr.DATAB
a[6] => n_addr.DATAB
a[7] => n_addr.DATAB
a[8] => n_addr.DATAB
a[9] => n_addr.DATAB
a[10] => n_addr.DATAB
a[11] => n_addr.DATAB
a[12] => n_addr.DATAB
a[13] => n_addr.DATAB
a[14] => n_addr.DATAB
a[15] => n_addr.DATAB
addr[0] <= n_addr[0].DB_MAX_OUTPUT_PORT_TYPE
addr[1] <= n_addr[1].DB_MAX_OUTPUT_PORT_TYPE
addr[2] <= n_addr[2].DB_MAX_OUTPUT_PORT_TYPE
addr[3] <= n_addr[3].DB_MAX_OUTPUT_PORT_TYPE
addr[4] <= n_addr[4].DB_MAX_OUTPUT_PORT_TYPE
addr[5] <= n_addr[5].DB_MAX_OUTPUT_PORT_TYPE
addr[6] <= n_addr[6].DB_MAX_OUTPUT_PORT_TYPE
addr[7] <= n_addr[7].DB_MAX_OUTPUT_PORT_TYPE
addr[8] <= n_addr[8].DB_MAX_OUTPUT_PORT_TYPE
addr[9] <= n_addr[9].DB_MAX_OUTPUT_PORT_TYPE
addr[10] <= n_addr[10].DB_MAX_OUTPUT_PORT_TYPE
addr[11] <= n_addr[11].DB_MAX_OUTPUT_PORT_TYPE
addr[12] <= n_addr[12].DB_MAX_OUTPUT_PORT_TYPE
addr[13] <= n_addr[13].DB_MAX_OUTPUT_PORT_TYPE
addr[14] <= n_addr[14].DB_MAX_OUTPUT_PORT_TYPE
addr[15] <= n_addr[15].DB_MAX_OUTPUT_PORT_TYPE
addr[16] <= <GND>
addr[17] <= <GND>
addr[18] <= <GND>
addr[19] <= <GND>
addr[20] <= <GND>
addr[21] <= <GND>
addr[22] <= <GND>
addr[23] <= <GND>
addr[24] <= <GND>
addr[25] <= <GND>
addr[26] <= <GND>
addr[27] <= <GND>
addr[28] <= <GND>
addr[29] <= <GND>
addr[30] <= <GND>
addr[31] <= <GND>


|GECKO|CPU:inst|ALU:alu_0
s[0] <= multiplexer:multiplexer_0.o[0]
s[1] <= multiplexer:multiplexer_0.o[1]
s[2] <= multiplexer:multiplexer_0.o[2]
s[3] <= multiplexer:multiplexer_0.o[3]
s[4] <= multiplexer:multiplexer_0.o[4]
s[5] <= multiplexer:multiplexer_0.o[5]
s[6] <= multiplexer:multiplexer_0.o[6]
s[7] <= multiplexer:multiplexer_0.o[7]
s[8] <= multiplexer:multiplexer_0.o[8]
s[9] <= multiplexer:multiplexer_0.o[9]
s[10] <= multiplexer:multiplexer_0.o[10]
s[11] <= multiplexer:multiplexer_0.o[11]
s[12] <= multiplexer:multiplexer_0.o[12]
s[13] <= multiplexer:multiplexer_0.o[13]
s[14] <= multiplexer:multiplexer_0.o[14]
s[15] <= multiplexer:multiplexer_0.o[15]
s[16] <= multiplexer:multiplexer_0.o[16]
s[17] <= multiplexer:multiplexer_0.o[17]
s[18] <= multiplexer:multiplexer_0.o[18]
s[19] <= multiplexer:multiplexer_0.o[19]
s[20] <= multiplexer:multiplexer_0.o[20]
s[21] <= multiplexer:multiplexer_0.o[21]
s[22] <= multiplexer:multiplexer_0.o[22]
s[23] <= multiplexer:multiplexer_0.o[23]
s[24] <= multiplexer:multiplexer_0.o[24]
s[25] <= multiplexer:multiplexer_0.o[25]
s[26] <= multiplexer:multiplexer_0.o[26]
s[27] <= multiplexer:multiplexer_0.o[27]
s[28] <= multiplexer:multiplexer_0.o[28]
s[29] <= multiplexer:multiplexer_0.o[29]
s[30] <= multiplexer:multiplexer_0.o[30]
s[31] <= multiplexer:multiplexer_0.o[31]
op[0] => comparator:comparator_0.op[0]
op[0] => logic_unit:logic_unit_0.op[0]
op[0] => shift_unit:shift_unit_0.op[0]
op[1] => comparator:comparator_0.op[1]
op[1] => logic_unit:logic_unit_0.op[1]
op[1] => shift_unit:shift_unit_0.op[1]
op[2] => comparator:comparator_0.op[2]
op[2] => shift_unit:shift_unit_0.op[2]
op[3] => add_sub:add_sub_0.sub_mode
op[4] => multiplexer:multiplexer_0.sel[0]
op[5] => multiplexer:multiplexer_0.sel[1]
a[0] => add_sub:add_sub_0.a[0]
a[0] => logic_unit:logic_unit_0.a[0]
a[0] => shift_unit:shift_unit_0.a[0]
a[1] => add_sub:add_sub_0.a[1]
a[1] => logic_unit:logic_unit_0.a[1]
a[1] => shift_unit:shift_unit_0.a[1]
a[2] => add_sub:add_sub_0.a[2]
a[2] => logic_unit:logic_unit_0.a[2]
a[2] => shift_unit:shift_unit_0.a[2]
a[3] => add_sub:add_sub_0.a[3]
a[3] => logic_unit:logic_unit_0.a[3]
a[3] => shift_unit:shift_unit_0.a[3]
a[4] => add_sub:add_sub_0.a[4]
a[4] => logic_unit:logic_unit_0.a[4]
a[4] => shift_unit:shift_unit_0.a[4]
a[5] => add_sub:add_sub_0.a[5]
a[5] => logic_unit:logic_unit_0.a[5]
a[5] => shift_unit:shift_unit_0.a[5]
a[6] => add_sub:add_sub_0.a[6]
a[6] => logic_unit:logic_unit_0.a[6]
a[6] => shift_unit:shift_unit_0.a[6]
a[7] => add_sub:add_sub_0.a[7]
a[7] => logic_unit:logic_unit_0.a[7]
a[7] => shift_unit:shift_unit_0.a[7]
a[8] => add_sub:add_sub_0.a[8]
a[8] => logic_unit:logic_unit_0.a[8]
a[8] => shift_unit:shift_unit_0.a[8]
a[9] => add_sub:add_sub_0.a[9]
a[9] => logic_unit:logic_unit_0.a[9]
a[9] => shift_unit:shift_unit_0.a[9]
a[10] => add_sub:add_sub_0.a[10]
a[10] => logic_unit:logic_unit_0.a[10]
a[10] => shift_unit:shift_unit_0.a[10]
a[11] => add_sub:add_sub_0.a[11]
a[11] => logic_unit:logic_unit_0.a[11]
a[11] => shift_unit:shift_unit_0.a[11]
a[12] => add_sub:add_sub_0.a[12]
a[12] => logic_unit:logic_unit_0.a[12]
a[12] => shift_unit:shift_unit_0.a[12]
a[13] => add_sub:add_sub_0.a[13]
a[13] => logic_unit:logic_unit_0.a[13]
a[13] => shift_unit:shift_unit_0.a[13]
a[14] => add_sub:add_sub_0.a[14]
a[14] => logic_unit:logic_unit_0.a[14]
a[14] => shift_unit:shift_unit_0.a[14]
a[15] => add_sub:add_sub_0.a[15]
a[15] => logic_unit:logic_unit_0.a[15]
a[15] => shift_unit:shift_unit_0.a[15]
a[16] => add_sub:add_sub_0.a[16]
a[16] => logic_unit:logic_unit_0.a[16]
a[16] => shift_unit:shift_unit_0.a[16]
a[17] => add_sub:add_sub_0.a[17]
a[17] => logic_unit:logic_unit_0.a[17]
a[17] => shift_unit:shift_unit_0.a[17]
a[18] => add_sub:add_sub_0.a[18]
a[18] => logic_unit:logic_unit_0.a[18]
a[18] => shift_unit:shift_unit_0.a[18]
a[19] => add_sub:add_sub_0.a[19]
a[19] => logic_unit:logic_unit_0.a[19]
a[19] => shift_unit:shift_unit_0.a[19]
a[20] => add_sub:add_sub_0.a[20]
a[20] => logic_unit:logic_unit_0.a[20]
a[20] => shift_unit:shift_unit_0.a[20]
a[21] => add_sub:add_sub_0.a[21]
a[21] => logic_unit:logic_unit_0.a[21]
a[21] => shift_unit:shift_unit_0.a[21]
a[22] => add_sub:add_sub_0.a[22]
a[22] => logic_unit:logic_unit_0.a[22]
a[22] => shift_unit:shift_unit_0.a[22]
a[23] => add_sub:add_sub_0.a[23]
a[23] => logic_unit:logic_unit_0.a[23]
a[23] => shift_unit:shift_unit_0.a[23]
a[24] => add_sub:add_sub_0.a[24]
a[24] => logic_unit:logic_unit_0.a[24]
a[24] => shift_unit:shift_unit_0.a[24]
a[25] => add_sub:add_sub_0.a[25]
a[25] => logic_unit:logic_unit_0.a[25]
a[25] => shift_unit:shift_unit_0.a[25]
a[26] => add_sub:add_sub_0.a[26]
a[26] => logic_unit:logic_unit_0.a[26]
a[26] => shift_unit:shift_unit_0.a[26]
a[27] => add_sub:add_sub_0.a[27]
a[27] => logic_unit:logic_unit_0.a[27]
a[27] => shift_unit:shift_unit_0.a[27]
a[28] => add_sub:add_sub_0.a[28]
a[28] => logic_unit:logic_unit_0.a[28]
a[28] => shift_unit:shift_unit_0.a[28]
a[29] => add_sub:add_sub_0.a[29]
a[29] => logic_unit:logic_unit_0.a[29]
a[29] => shift_unit:shift_unit_0.a[29]
a[30] => add_sub:add_sub_0.a[30]
a[30] => logic_unit:logic_unit_0.a[30]
a[30] => shift_unit:shift_unit_0.a[30]
a[31] => add_sub:add_sub_0.a[31]
a[31] => comparator:comparator_0.a_31
a[31] => logic_unit:logic_unit_0.a[31]
a[31] => shift_unit:shift_unit_0.a[31]
b[0] => add_sub:add_sub_0.b[0]
b[0] => logic_unit:logic_unit_0.b[0]
b[0] => shift_unit:shift_unit_0.b[0]
b[1] => add_sub:add_sub_0.b[1]
b[1] => logic_unit:logic_unit_0.b[1]
b[1] => shift_unit:shift_unit_0.b[1]
b[2] => add_sub:add_sub_0.b[2]
b[2] => logic_unit:logic_unit_0.b[2]
b[2] => shift_unit:shift_unit_0.b[2]
b[3] => add_sub:add_sub_0.b[3]
b[3] => logic_unit:logic_unit_0.b[3]
b[3] => shift_unit:shift_unit_0.b[3]
b[4] => add_sub:add_sub_0.b[4]
b[4] => logic_unit:logic_unit_0.b[4]
b[4] => shift_unit:shift_unit_0.b[4]
b[5] => add_sub:add_sub_0.b[5]
b[5] => logic_unit:logic_unit_0.b[5]
b[6] => add_sub:add_sub_0.b[6]
b[6] => logic_unit:logic_unit_0.b[6]
b[7] => add_sub:add_sub_0.b[7]
b[7] => logic_unit:logic_unit_0.b[7]
b[8] => add_sub:add_sub_0.b[8]
b[8] => logic_unit:logic_unit_0.b[8]
b[9] => add_sub:add_sub_0.b[9]
b[9] => logic_unit:logic_unit_0.b[9]
b[10] => add_sub:add_sub_0.b[10]
b[10] => logic_unit:logic_unit_0.b[10]
b[11] => add_sub:add_sub_0.b[11]
b[11] => logic_unit:logic_unit_0.b[11]
b[12] => add_sub:add_sub_0.b[12]
b[12] => logic_unit:logic_unit_0.b[12]
b[13] => add_sub:add_sub_0.b[13]
b[13] => logic_unit:logic_unit_0.b[13]
b[14] => add_sub:add_sub_0.b[14]
b[14] => logic_unit:logic_unit_0.b[14]
b[15] => add_sub:add_sub_0.b[15]
b[15] => logic_unit:logic_unit_0.b[15]
b[16] => add_sub:add_sub_0.b[16]
b[16] => logic_unit:logic_unit_0.b[16]
b[17] => add_sub:add_sub_0.b[17]
b[17] => logic_unit:logic_unit_0.b[17]
b[18] => add_sub:add_sub_0.b[18]
b[18] => logic_unit:logic_unit_0.b[18]
b[19] => add_sub:add_sub_0.b[19]
b[19] => logic_unit:logic_unit_0.b[19]
b[20] => add_sub:add_sub_0.b[20]
b[20] => logic_unit:logic_unit_0.b[20]
b[21] => add_sub:add_sub_0.b[21]
b[21] => logic_unit:logic_unit_0.b[21]
b[22] => add_sub:add_sub_0.b[22]
b[22] => logic_unit:logic_unit_0.b[22]
b[23] => add_sub:add_sub_0.b[23]
b[23] => logic_unit:logic_unit_0.b[23]
b[24] => add_sub:add_sub_0.b[24]
b[24] => logic_unit:logic_unit_0.b[24]
b[25] => add_sub:add_sub_0.b[25]
b[25] => logic_unit:logic_unit_0.b[25]
b[26] => add_sub:add_sub_0.b[26]
b[26] => logic_unit:logic_unit_0.b[26]
b[27] => add_sub:add_sub_0.b[27]
b[27] => logic_unit:logic_unit_0.b[27]
b[28] => add_sub:add_sub_0.b[28]
b[28] => logic_unit:logic_unit_0.b[28]
b[29] => add_sub:add_sub_0.b[29]
b[29] => logic_unit:logic_unit_0.b[29]
b[30] => add_sub:add_sub_0.b[30]
b[30] => logic_unit:logic_unit_0.b[30]
b[31] => add_sub:add_sub_0.b[31]
b[31] => comparator:comparator_0.b_31
b[31] => logic_unit:logic_unit_0.b[31]


|GECKO|CPU:inst|ALU:alu_0|multiplexer:multiplexer_0
i0[0] => o.DATAA
i0[0] => o.DATAB
i0[1] => o.DATAA
i0[1] => o.DATAB
i0[2] => o.DATAA
i0[2] => o.DATAB
i0[3] => o.DATAA
i0[3] => o.DATAB
i0[4] => o.DATAA
i0[4] => o.DATAB
i0[5] => o.DATAA
i0[5] => o.DATAB
i0[6] => o.DATAA
i0[6] => o.DATAB
i0[7] => o.DATAA
i0[7] => o.DATAB
i0[8] => o.DATAA
i0[8] => o.DATAB
i0[9] => o.DATAA
i0[9] => o.DATAB
i0[10] => o.DATAA
i0[10] => o.DATAB
i0[11] => o.DATAA
i0[11] => o.DATAB
i0[12] => o.DATAA
i0[12] => o.DATAB
i0[13] => o.DATAA
i0[13] => o.DATAB
i0[14] => o.DATAA
i0[14] => o.DATAB
i0[15] => o.DATAA
i0[15] => o.DATAB
i0[16] => o.DATAA
i0[16] => o.DATAB
i0[17] => o.DATAA
i0[17] => o.DATAB
i0[18] => o.DATAA
i0[18] => o.DATAB
i0[19] => o.DATAA
i0[19] => o.DATAB
i0[20] => o.DATAA
i0[20] => o.DATAB
i0[21] => o.DATAA
i0[21] => o.DATAB
i0[22] => o.DATAA
i0[22] => o.DATAB
i0[23] => o.DATAA
i0[23] => o.DATAB
i0[24] => o.DATAA
i0[24] => o.DATAB
i0[25] => o.DATAA
i0[25] => o.DATAB
i0[26] => o.DATAA
i0[26] => o.DATAB
i0[27] => o.DATAA
i0[27] => o.DATAB
i0[28] => o.DATAA
i0[28] => o.DATAB
i0[29] => o.DATAA
i0[29] => o.DATAB
i0[30] => o.DATAA
i0[30] => o.DATAB
i0[31] => o.DATAA
i0[31] => o.DATAB
i1[0] => o.DATAB
i1[1] => o.DATAB
i1[2] => o.DATAB
i1[3] => o.DATAB
i1[4] => o.DATAB
i1[5] => o.DATAB
i1[6] => o.DATAB
i1[7] => o.DATAB
i1[8] => o.DATAB
i1[9] => o.DATAB
i1[10] => o.DATAB
i1[11] => o.DATAB
i1[12] => o.DATAB
i1[13] => o.DATAB
i1[14] => o.DATAB
i1[15] => o.DATAB
i1[16] => o.DATAB
i1[17] => o.DATAB
i1[18] => o.DATAB
i1[19] => o.DATAB
i1[20] => o.DATAB
i1[21] => o.DATAB
i1[22] => o.DATAB
i1[23] => o.DATAB
i1[24] => o.DATAB
i1[25] => o.DATAB
i1[26] => o.DATAB
i1[27] => o.DATAB
i1[28] => o.DATAB
i1[29] => o.DATAB
i1[30] => o.DATAB
i1[31] => o.DATAB
i2[0] => o.DATAB
i2[1] => o.DATAB
i2[2] => o.DATAB
i2[3] => o.DATAB
i2[4] => o.DATAB
i2[5] => o.DATAB
i2[6] => o.DATAB
i2[7] => o.DATAB
i2[8] => o.DATAB
i2[9] => o.DATAB
i2[10] => o.DATAB
i2[11] => o.DATAB
i2[12] => o.DATAB
i2[13] => o.DATAB
i2[14] => o.DATAB
i2[15] => o.DATAB
i2[16] => o.DATAB
i2[17] => o.DATAB
i2[18] => o.DATAB
i2[19] => o.DATAB
i2[20] => o.DATAB
i2[21] => o.DATAB
i2[22] => o.DATAB
i2[23] => o.DATAB
i2[24] => o.DATAB
i2[25] => o.DATAB
i2[26] => o.DATAB
i2[27] => o.DATAB
i2[28] => o.DATAB
i2[29] => o.DATAB
i2[30] => o.DATAB
i2[31] => o.DATAB
i3[0] => o.DATAB
i3[1] => o.DATAB
i3[2] => o.DATAB
i3[3] => o.DATAB
i3[4] => o.DATAB
i3[5] => o.DATAB
i3[6] => o.DATAB
i3[7] => o.DATAB
i3[8] => o.DATAB
i3[9] => o.DATAB
i3[10] => o.DATAB
i3[11] => o.DATAB
i3[12] => o.DATAB
i3[13] => o.DATAB
i3[14] => o.DATAB
i3[15] => o.DATAB
i3[16] => o.DATAB
i3[17] => o.DATAB
i3[18] => o.DATAB
i3[19] => o.DATAB
i3[20] => o.DATAB
i3[21] => o.DATAB
i3[22] => o.DATAB
i3[23] => o.DATAB
i3[24] => o.DATAB
i3[25] => o.DATAB
i3[26] => o.DATAB
i3[27] => o.DATAB
i3[28] => o.DATAB
i3[29] => o.DATAB
i3[30] => o.DATAB
i3[31] => o.DATAB
sel[0] => Equal0.IN1
sel[0] => Equal1.IN0
sel[0] => Equal2.IN1
sel[0] => Equal3.IN1
sel[1] => Equal0.IN0
sel[1] => Equal1.IN1
sel[1] => Equal2.IN0
sel[1] => Equal3.IN0
o[0] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[1] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[2] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[3] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[4] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[5] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[6] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[7] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[8] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[9] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[10] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[11] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[12] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[13] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[14] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[15] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[16] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[17] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[18] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[19] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[20] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[21] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[22] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[23] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[24] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[25] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[26] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[27] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[28] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[29] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[30] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[31] <= o.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|ALU:alu_0|add_sub:add_sub_0
a[0] => Add0.IN32
a[1] => Add0.IN31
a[2] => Add0.IN30
a[3] => Add0.IN29
a[4] => Add0.IN28
a[5] => Add0.IN27
a[6] => Add0.IN26
a[7] => Add0.IN25
a[8] => Add0.IN24
a[9] => Add0.IN23
a[10] => Add0.IN22
a[11] => Add0.IN21
a[12] => Add0.IN20
a[13] => Add0.IN19
a[14] => Add0.IN18
a[15] => Add0.IN17
a[16] => Add0.IN16
a[17] => Add0.IN15
a[18] => Add0.IN14
a[19] => Add0.IN13
a[20] => Add0.IN12
a[21] => Add0.IN11
a[22] => Add0.IN10
a[23] => Add0.IN9
a[24] => Add0.IN8
a[25] => Add0.IN7
a[26] => Add0.IN6
a[27] => Add0.IN5
a[28] => Add0.IN4
a[29] => Add0.IN3
a[30] => Add0.IN2
a[31] => Add0.IN1
b[0] => bsub[0].IN0
b[1] => bsub[1].IN0
b[2] => bsub[2].IN0
b[3] => bsub[3].IN0
b[4] => bsub[4].IN0
b[5] => bsub[5].IN0
b[6] => bsub[6].IN0
b[7] => bsub[7].IN0
b[8] => bsub[8].IN0
b[9] => bsub[9].IN0
b[10] => bsub[10].IN0
b[11] => bsub[11].IN0
b[12] => bsub[12].IN0
b[13] => bsub[13].IN0
b[14] => bsub[14].IN0
b[15] => bsub[15].IN0
b[16] => bsub[16].IN0
b[17] => bsub[17].IN0
b[18] => bsub[18].IN0
b[19] => bsub[19].IN0
b[20] => bsub[20].IN0
b[21] => bsub[21].IN0
b[22] => bsub[22].IN0
b[23] => bsub[23].IN0
b[24] => bsub[24].IN0
b[25] => bsub[25].IN0
b[26] => bsub[26].IN0
b[27] => bsub[27].IN0
b[28] => bsub[28].IN0
b[29] => bsub[29].IN0
b[30] => bsub[30].IN0
b[31] => bsub[31].IN0
sub_mode => bsub[0].IN1
sub_mode => bsub[1].IN1
sub_mode => bsub[2].IN1
sub_mode => bsub[3].IN1
sub_mode => bsub[4].IN1
sub_mode => bsub[5].IN1
sub_mode => bsub[6].IN1
sub_mode => bsub[7].IN1
sub_mode => bsub[8].IN1
sub_mode => bsub[9].IN1
sub_mode => bsub[10].IN1
sub_mode => bsub[11].IN1
sub_mode => bsub[12].IN1
sub_mode => bsub[13].IN1
sub_mode => bsub[14].IN1
sub_mode => bsub[15].IN1
sub_mode => bsub[16].IN1
sub_mode => bsub[17].IN1
sub_mode => bsub[18].IN1
sub_mode => bsub[19].IN1
sub_mode => bsub[20].IN1
sub_mode => bsub[21].IN1
sub_mode => bsub[22].IN1
sub_mode => bsub[23].IN1
sub_mode => bsub[24].IN1
sub_mode => bsub[25].IN1
sub_mode => bsub[26].IN1
sub_mode => bsub[27].IN1
sub_mode => bsub[28].IN1
sub_mode => bsub[29].IN1
sub_mode => bsub[30].IN1
sub_mode => bsub[31].IN1
sub_mode => Add1.IN66
carry <= Add1.DB_MAX_OUTPUT_PORT_TYPE
zero <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
r[0] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[1] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[2] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[3] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[4] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[5] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[6] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[7] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[8] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[9] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[10] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[11] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[12] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[13] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[14] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[15] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[16] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[17] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[18] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[19] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[20] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[21] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[22] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[23] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[24] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[25] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[26] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[27] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[28] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[29] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[30] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
r[31] <= Add1.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|ALU:alu_0|comparator:comparator_0
a_31 => r.IN0
a_31 => r.IN0
a_31 => r.IN0
b_31 => r.IN1
b_31 => r.IN1
b_31 => r.IN1
diff_31 => r.IN0
carry => r.IN0
carry => r.IN0
zero => r.DATAA
zero => r.IN1
zero => r.IN1
zero => r.IN1
zero => r.DATAB
op[0] => Equal0.IN0
op[0] => Equal1.IN2
op[0] => Equal2.IN2
op[0] => Equal3.IN1
op[0] => Equal4.IN2
op[1] => Equal0.IN2
op[1] => Equal1.IN0
op[1] => Equal2.IN1
op[1] => Equal3.IN2
op[1] => Equal4.IN1
op[2] => Equal0.IN1
op[2] => Equal1.IN1
op[2] => Equal2.IN0
op[2] => Equal3.IN0
op[2] => Equal4.IN0
r <= r.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|ALU:alu_0|logic_unit:logic_unit_0
a[0] => r.IN0
a[0] => r.IN0
a[0] => r.IN0
a[0] => r.IN0
a[1] => r.IN0
a[1] => r.IN0
a[1] => r.IN0
a[1] => r.IN0
a[2] => r.IN0
a[2] => r.IN0
a[2] => r.IN0
a[2] => r.IN0
a[3] => r.IN0
a[3] => r.IN0
a[3] => r.IN0
a[3] => r.IN0
a[4] => r.IN0
a[4] => r.IN0
a[4] => r.IN0
a[4] => r.IN0
a[5] => r.IN0
a[5] => r.IN0
a[5] => r.IN0
a[5] => r.IN0
a[6] => r.IN0
a[6] => r.IN0
a[6] => r.IN0
a[6] => r.IN0
a[7] => r.IN0
a[7] => r.IN0
a[7] => r.IN0
a[7] => r.IN0
a[8] => r.IN0
a[8] => r.IN0
a[8] => r.IN0
a[8] => r.IN0
a[9] => r.IN0
a[9] => r.IN0
a[9] => r.IN0
a[9] => r.IN0
a[10] => r.IN0
a[10] => r.IN0
a[10] => r.IN0
a[10] => r.IN0
a[11] => r.IN0
a[11] => r.IN0
a[11] => r.IN0
a[11] => r.IN0
a[12] => r.IN0
a[12] => r.IN0
a[12] => r.IN0
a[12] => r.IN0
a[13] => r.IN0
a[13] => r.IN0
a[13] => r.IN0
a[13] => r.IN0
a[14] => r.IN0
a[14] => r.IN0
a[14] => r.IN0
a[14] => r.IN0
a[15] => r.IN0
a[15] => r.IN0
a[15] => r.IN0
a[15] => r.IN0
a[16] => r.IN0
a[16] => r.IN0
a[16] => r.IN0
a[16] => r.IN0
a[17] => r.IN0
a[17] => r.IN0
a[17] => r.IN0
a[17] => r.IN0
a[18] => r.IN0
a[18] => r.IN0
a[18] => r.IN0
a[18] => r.IN0
a[19] => r.IN0
a[19] => r.IN0
a[19] => r.IN0
a[19] => r.IN0
a[20] => r.IN0
a[20] => r.IN0
a[20] => r.IN0
a[20] => r.IN0
a[21] => r.IN0
a[21] => r.IN0
a[21] => r.IN0
a[21] => r.IN0
a[22] => r.IN0
a[22] => r.IN0
a[22] => r.IN0
a[22] => r.IN0
a[23] => r.IN0
a[23] => r.IN0
a[23] => r.IN0
a[23] => r.IN0
a[24] => r.IN0
a[24] => r.IN0
a[24] => r.IN0
a[24] => r.IN0
a[25] => r.IN0
a[25] => r.IN0
a[25] => r.IN0
a[25] => r.IN0
a[26] => r.IN0
a[26] => r.IN0
a[26] => r.IN0
a[26] => r.IN0
a[27] => r.IN0
a[27] => r.IN0
a[27] => r.IN0
a[27] => r.IN0
a[28] => r.IN0
a[28] => r.IN0
a[28] => r.IN0
a[28] => r.IN0
a[29] => r.IN0
a[29] => r.IN0
a[29] => r.IN0
a[29] => r.IN0
a[30] => r.IN0
a[30] => r.IN0
a[30] => r.IN0
a[30] => r.IN0
a[31] => r.IN0
a[31] => r.IN0
a[31] => r.IN0
a[31] => r.IN0
b[0] => r.IN1
b[0] => r.IN1
b[0] => r.IN1
b[0] => r.IN1
b[1] => r.IN1
b[1] => r.IN1
b[1] => r.IN1
b[1] => r.IN1
b[2] => r.IN1
b[2] => r.IN1
b[2] => r.IN1
b[2] => r.IN1
b[3] => r.IN1
b[3] => r.IN1
b[3] => r.IN1
b[3] => r.IN1
b[4] => r.IN1
b[4] => r.IN1
b[4] => r.IN1
b[4] => r.IN1
b[5] => r.IN1
b[5] => r.IN1
b[5] => r.IN1
b[5] => r.IN1
b[6] => r.IN1
b[6] => r.IN1
b[6] => r.IN1
b[6] => r.IN1
b[7] => r.IN1
b[7] => r.IN1
b[7] => r.IN1
b[7] => r.IN1
b[8] => r.IN1
b[8] => r.IN1
b[8] => r.IN1
b[8] => r.IN1
b[9] => r.IN1
b[9] => r.IN1
b[9] => r.IN1
b[9] => r.IN1
b[10] => r.IN1
b[10] => r.IN1
b[10] => r.IN1
b[10] => r.IN1
b[11] => r.IN1
b[11] => r.IN1
b[11] => r.IN1
b[11] => r.IN1
b[12] => r.IN1
b[12] => r.IN1
b[12] => r.IN1
b[12] => r.IN1
b[13] => r.IN1
b[13] => r.IN1
b[13] => r.IN1
b[13] => r.IN1
b[14] => r.IN1
b[14] => r.IN1
b[14] => r.IN1
b[14] => r.IN1
b[15] => r.IN1
b[15] => r.IN1
b[15] => r.IN1
b[15] => r.IN1
b[16] => r.IN1
b[16] => r.IN1
b[16] => r.IN1
b[16] => r.IN1
b[17] => r.IN1
b[17] => r.IN1
b[17] => r.IN1
b[17] => r.IN1
b[18] => r.IN1
b[18] => r.IN1
b[18] => r.IN1
b[18] => r.IN1
b[19] => r.IN1
b[19] => r.IN1
b[19] => r.IN1
b[19] => r.IN1
b[20] => r.IN1
b[20] => r.IN1
b[20] => r.IN1
b[20] => r.IN1
b[21] => r.IN1
b[21] => r.IN1
b[21] => r.IN1
b[21] => r.IN1
b[22] => r.IN1
b[22] => r.IN1
b[22] => r.IN1
b[22] => r.IN1
b[23] => r.IN1
b[23] => r.IN1
b[23] => r.IN1
b[23] => r.IN1
b[24] => r.IN1
b[24] => r.IN1
b[24] => r.IN1
b[24] => r.IN1
b[25] => r.IN1
b[25] => r.IN1
b[25] => r.IN1
b[25] => r.IN1
b[26] => r.IN1
b[26] => r.IN1
b[26] => r.IN1
b[26] => r.IN1
b[27] => r.IN1
b[27] => r.IN1
b[27] => r.IN1
b[27] => r.IN1
b[28] => r.IN1
b[28] => r.IN1
b[28] => r.IN1
b[28] => r.IN1
b[29] => r.IN1
b[29] => r.IN1
b[29] => r.IN1
b[29] => r.IN1
b[30] => r.IN1
b[30] => r.IN1
b[30] => r.IN1
b[30] => r.IN1
b[31] => r.IN1
b[31] => r.IN1
b[31] => r.IN1
b[31] => r.IN1
op[0] => Equal0.IN0
op[0] => Equal1.IN1
op[0] => Equal2.IN1
op[1] => Equal0.IN1
op[1] => Equal1.IN0
op[1] => Equal2.IN0
r[0] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[1] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[2] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[3] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[4] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[5] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[6] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[7] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[8] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[9] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[10] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[11] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[12] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[13] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[14] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[15] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[16] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[17] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[18] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[19] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[20] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[21] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[22] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[23] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[24] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[25] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[26] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[27] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[28] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[29] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[30] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[31] <= r.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0
a[0] => v.DATAB
a[0] => v.DATAA
a[0] => v.DATAA
a[1] => v.DATAB
a[1] => v.DATAA
a[1] => v.DATAA
a[1] => v.DATAA
a[1] => v.DATAB
a[2] => v.DATAB
a[2] => v.DATAA
a[2] => v.DATAA
a[2] => v.DATAB
a[3] => v.DATAB
a[3] => v.DATAA
a[3] => v.DATAA
a[3] => v.DATAB
a[4] => v.DATAB
a[4] => v.DATAA
a[4] => v.DATAA
a[4] => v.DATAB
a[5] => v.DATAB
a[5] => v.DATAA
a[5] => v.DATAA
a[5] => v.DATAB
a[6] => v.DATAB
a[6] => v.DATAA
a[6] => v.DATAA
a[6] => v.DATAB
a[7] => v.DATAB
a[7] => v.DATAA
a[7] => v.DATAA
a[7] => v.DATAB
a[8] => v.DATAB
a[8] => v.DATAA
a[8] => v.DATAA
a[8] => v.DATAB
a[9] => v.DATAB
a[9] => v.DATAA
a[9] => v.DATAA
a[9] => v.DATAB
a[10] => v.DATAB
a[10] => v.DATAA
a[10] => v.DATAA
a[10] => v.DATAB
a[11] => v.DATAB
a[11] => v.DATAA
a[11] => v.DATAA
a[11] => v.DATAB
a[12] => v.DATAB
a[12] => v.DATAA
a[12] => v.DATAA
a[12] => v.DATAB
a[13] => v.DATAB
a[13] => v.DATAA
a[13] => v.DATAA
a[13] => v.DATAB
a[14] => v.DATAB
a[14] => v.DATAA
a[14] => v.DATAA
a[14] => v.DATAB
a[15] => v.DATAB
a[15] => v.DATAA
a[15] => v.DATAA
a[15] => v.DATAB
a[16] => v.DATAB
a[16] => v.DATAA
a[16] => v.DATAA
a[16] => v.DATAB
a[17] => v.DATAB
a[17] => v.DATAA
a[17] => v.DATAA
a[17] => v.DATAB
a[18] => v.DATAB
a[18] => v.DATAA
a[18] => v.DATAA
a[18] => v.DATAB
a[19] => v.DATAB
a[19] => v.DATAA
a[19] => v.DATAA
a[19] => v.DATAB
a[20] => v.DATAB
a[20] => v.DATAA
a[20] => v.DATAA
a[20] => v.DATAB
a[21] => v.DATAB
a[21] => v.DATAA
a[21] => v.DATAA
a[21] => v.DATAB
a[22] => v.DATAB
a[22] => v.DATAA
a[22] => v.DATAA
a[22] => v.DATAB
a[23] => v.DATAB
a[23] => v.DATAA
a[23] => v.DATAA
a[23] => v.DATAB
a[24] => v.DATAB
a[24] => v.DATAA
a[24] => v.DATAA
a[24] => v.DATAB
a[25] => v.DATAB
a[25] => v.DATAA
a[25] => v.DATAA
a[25] => v.DATAB
a[26] => v.DATAB
a[26] => v.DATAA
a[26] => v.DATAA
a[26] => v.DATAB
a[27] => v.DATAB
a[27] => v.DATAA
a[27] => v.DATAA
a[27] => v.DATAB
a[28] => v.DATAB
a[28] => v.DATAA
a[28] => v.DATAA
a[28] => v.DATAB
a[29] => v.DATAB
a[29] => v.DATAA
a[29] => v.DATAA
a[29] => v.DATAB
a[30] => v.DATAB
a[30] => v.DATAA
a[30] => v.DATAA
a[30] => v.DATAB
a[31] => v.DATAA
a[31] => v.DATAA
a[31] => v.DATAA
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => v.DATAB
a[31] => \shift_ar:v[30].DATAB
a[31] => \shift_ar:v[29].DATAB
a[31] => \shift_ar:v[28].DATAB
a[31] => \shift_ar:v[27].DATAB
a[31] => \shift_ar:v[26].DATAB
a[31] => \shift_ar:v[25].DATAB
a[31] => \shift_ar:v[24].DATAB
a[31] => \shift_ar:v[23].DATAB
a[31] => \shift_ar:v[22].DATAB
a[31] => \shift_ar:v[21].DATAB
a[31] => \shift_ar:v[20].DATAB
a[31] => \shift_ar:v[19].DATAB
a[31] => \shift_ar:v[18].DATAB
a[31] => \shift_ar:v[17].DATAB
a[31] => \shift_ar:v[16].DATAB
a[31] => \shift_ar:v[15].DATAB
a[31] => r.DATAB
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[0] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[1] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[2] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[3] => v.OUTPUTSELECT
b[4] => \shift_l:v[31].OUTPUTSELECT
b[4] => \shift_l:v[30].OUTPUTSELECT
b[4] => \shift_l:v[29].OUTPUTSELECT
b[4] => \shift_l:v[28].OUTPUTSELECT
b[4] => \shift_l:v[27].OUTPUTSELECT
b[4] => \shift_l:v[26].OUTPUTSELECT
b[4] => \shift_l:v[25].OUTPUTSELECT
b[4] => \shift_l:v[24].OUTPUTSELECT
b[4] => \shift_l:v[23].OUTPUTSELECT
b[4] => \shift_l:v[22].OUTPUTSELECT
b[4] => \shift_l:v[21].OUTPUTSELECT
b[4] => \shift_l:v[20].OUTPUTSELECT
b[4] => \shift_l:v[19].OUTPUTSELECT
b[4] => \shift_l:v[18].OUTPUTSELECT
b[4] => \shift_l:v[17].OUTPUTSELECT
b[4] => \shift_l:v[16].OUTPUTSELECT
b[4] => \shift_l:v[15].OUTPUTSELECT
b[4] => \shift_l:v[14].OUTPUTSELECT
b[4] => \shift_l:v[13].OUTPUTSELECT
b[4] => \shift_l:v[12].OUTPUTSELECT
b[4] => \shift_l:v[11].OUTPUTSELECT
b[4] => \shift_l:v[10].OUTPUTSELECT
b[4] => \shift_l:v[9].OUTPUTSELECT
b[4] => \shift_l:v[8].OUTPUTSELECT
b[4] => \shift_l:v[7].OUTPUTSELECT
b[4] => \shift_l:v[6].OUTPUTSELECT
b[4] => \shift_l:v[5].OUTPUTSELECT
b[4] => \shift_l:v[4].OUTPUTSELECT
b[4] => \shift_l:v[3].OUTPUTSELECT
b[4] => \shift_l:v[2].OUTPUTSELECT
b[4] => \shift_l:v[1].OUTPUTSELECT
b[4] => \shift_l:v[0].OUTPUTSELECT
b[4] => \shift_r:v[31].OUTPUTSELECT
b[4] => \shift_r:v[30].OUTPUTSELECT
b[4] => \shift_r:v[29].OUTPUTSELECT
b[4] => \shift_r:v[28].OUTPUTSELECT
b[4] => \shift_r:v[27].OUTPUTSELECT
b[4] => \shift_r:v[26].OUTPUTSELECT
b[4] => \shift_r:v[25].OUTPUTSELECT
b[4] => \shift_r:v[24].OUTPUTSELECT
b[4] => \shift_r:v[23].OUTPUTSELECT
b[4] => \shift_r:v[22].OUTPUTSELECT
b[4] => \shift_r:v[21].OUTPUTSELECT
b[4] => \shift_r:v[20].OUTPUTSELECT
b[4] => \shift_r:v[19].OUTPUTSELECT
b[4] => \shift_r:v[18].OUTPUTSELECT
b[4] => \shift_r:v[17].OUTPUTSELECT
b[4] => \shift_r:v[16].OUTPUTSELECT
b[4] => \shift_r:v[15].OUTPUTSELECT
b[4] => \shift_r:v[14].OUTPUTSELECT
b[4] => \shift_r:v[13].OUTPUTSELECT
b[4] => \shift_r:v[12].OUTPUTSELECT
b[4] => \shift_r:v[11].OUTPUTSELECT
b[4] => \shift_r:v[10].OUTPUTSELECT
b[4] => \shift_r:v[9].OUTPUTSELECT
b[4] => \shift_r:v[8].OUTPUTSELECT
b[4] => \shift_r:v[7].OUTPUTSELECT
b[4] => \shift_r:v[6].OUTPUTSELECT
b[4] => \shift_r:v[5].OUTPUTSELECT
b[4] => \shift_r:v[4].OUTPUTSELECT
b[4] => \shift_r:v[3].OUTPUTSELECT
b[4] => \shift_r:v[2].OUTPUTSELECT
b[4] => \shift_r:v[1].OUTPUTSELECT
b[4] => \shift_r:v[0].OUTPUTSELECT
b[4] => \shift_ar:v[30].OUTPUTSELECT
b[4] => \shift_ar:v[29].OUTPUTSELECT
b[4] => \shift_ar:v[28].OUTPUTSELECT
b[4] => \shift_ar:v[27].OUTPUTSELECT
b[4] => \shift_ar:v[26].OUTPUTSELECT
b[4] => \shift_ar:v[25].OUTPUTSELECT
b[4] => \shift_ar:v[24].OUTPUTSELECT
b[4] => \shift_ar:v[23].OUTPUTSELECT
b[4] => \shift_ar:v[22].OUTPUTSELECT
b[4] => \shift_ar:v[21].OUTPUTSELECT
b[4] => \shift_ar:v[20].OUTPUTSELECT
b[4] => \shift_ar:v[19].OUTPUTSELECT
b[4] => \shift_ar:v[18].OUTPUTSELECT
b[4] => \shift_ar:v[17].OUTPUTSELECT
b[4] => \shift_ar:v[16].OUTPUTSELECT
b[4] => \shift_ar:v[15].OUTPUTSELECT
b[4] => \shift_ar:v[14].OUTPUTSELECT
b[4] => \shift_ar:v[13].OUTPUTSELECT
b[4] => \shift_ar:v[12].OUTPUTSELECT
b[4] => \shift_ar:v[11].OUTPUTSELECT
b[4] => \shift_ar:v[10].OUTPUTSELECT
b[4] => \shift_ar:v[9].OUTPUTSELECT
b[4] => \shift_ar:v[8].OUTPUTSELECT
b[4] => \shift_ar:v[7].OUTPUTSELECT
b[4] => \shift_ar:v[6].OUTPUTSELECT
b[4] => \shift_ar:v[5].OUTPUTSELECT
b[4] => \shift_ar:v[4].OUTPUTSELECT
b[4] => \shift_ar:v[3].OUTPUTSELECT
b[4] => \shift_ar:v[2].OUTPUTSELECT
b[4] => \shift_ar:v[1].OUTPUTSELECT
b[4] => \shift_ar:v[0].OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => r.OUTPUTSELECT
op[0] => Equal0.IN2
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => v.OUTPUTSELECT
op[1] => Equal0.IN1
op[2] => Equal0.IN0
r[0] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[1] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[2] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[3] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[4] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[5] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[6] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[7] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[8] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[9] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[10] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[11] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[12] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[13] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[14] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[15] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[16] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[17] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[18] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[19] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[20] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[21] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[22] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[23] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[24] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[25] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[26] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[27] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[28] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[29] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[30] <= r.DB_MAX_OUTPUT_PORT_TYPE
r[31] <= r.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|register_file:register_file_0
clk => reg[31][0].CLK
clk => reg[31][1].CLK
clk => reg[31][2].CLK
clk => reg[31][3].CLK
clk => reg[31][4].CLK
clk => reg[31][5].CLK
clk => reg[31][6].CLK
clk => reg[31][7].CLK
clk => reg[31][8].CLK
clk => reg[31][9].CLK
clk => reg[31][10].CLK
clk => reg[31][11].CLK
clk => reg[31][12].CLK
clk => reg[31][13].CLK
clk => reg[31][14].CLK
clk => reg[31][15].CLK
clk => reg[31][16].CLK
clk => reg[31][17].CLK
clk => reg[31][18].CLK
clk => reg[31][19].CLK
clk => reg[31][20].CLK
clk => reg[31][21].CLK
clk => reg[31][22].CLK
clk => reg[31][23].CLK
clk => reg[31][24].CLK
clk => reg[31][25].CLK
clk => reg[31][26].CLK
clk => reg[31][27].CLK
clk => reg[31][28].CLK
clk => reg[31][29].CLK
clk => reg[31][30].CLK
clk => reg[31][31].CLK
clk => reg[30][0].CLK
clk => reg[30][1].CLK
clk => reg[30][2].CLK
clk => reg[30][3].CLK
clk => reg[30][4].CLK
clk => reg[30][5].CLK
clk => reg[30][6].CLK
clk => reg[30][7].CLK
clk => reg[30][8].CLK
clk => reg[30][9].CLK
clk => reg[30][10].CLK
clk => reg[30][11].CLK
clk => reg[30][12].CLK
clk => reg[30][13].CLK
clk => reg[30][14].CLK
clk => reg[30][15].CLK
clk => reg[30][16].CLK
clk => reg[30][17].CLK
clk => reg[30][18].CLK
clk => reg[30][19].CLK
clk => reg[30][20].CLK
clk => reg[30][21].CLK
clk => reg[30][22].CLK
clk => reg[30][23].CLK
clk => reg[30][24].CLK
clk => reg[30][25].CLK
clk => reg[30][26].CLK
clk => reg[30][27].CLK
clk => reg[30][28].CLK
clk => reg[30][29].CLK
clk => reg[30][30].CLK
clk => reg[30][31].CLK
clk => reg[29][0].CLK
clk => reg[29][1].CLK
clk => reg[29][2].CLK
clk => reg[29][3].CLK
clk => reg[29][4].CLK
clk => reg[29][5].CLK
clk => reg[29][6].CLK
clk => reg[29][7].CLK
clk => reg[29][8].CLK
clk => reg[29][9].CLK
clk => reg[29][10].CLK
clk => reg[29][11].CLK
clk => reg[29][12].CLK
clk => reg[29][13].CLK
clk => reg[29][14].CLK
clk => reg[29][15].CLK
clk => reg[29][16].CLK
clk => reg[29][17].CLK
clk => reg[29][18].CLK
clk => reg[29][19].CLK
clk => reg[29][20].CLK
clk => reg[29][21].CLK
clk => reg[29][22].CLK
clk => reg[29][23].CLK
clk => reg[29][24].CLK
clk => reg[29][25].CLK
clk => reg[29][26].CLK
clk => reg[29][27].CLK
clk => reg[29][28].CLK
clk => reg[29][29].CLK
clk => reg[29][30].CLK
clk => reg[29][31].CLK
clk => reg[28][0].CLK
clk => reg[28][1].CLK
clk => reg[28][2].CLK
clk => reg[28][3].CLK
clk => reg[28][4].CLK
clk => reg[28][5].CLK
clk => reg[28][6].CLK
clk => reg[28][7].CLK
clk => reg[28][8].CLK
clk => reg[28][9].CLK
clk => reg[28][10].CLK
clk => reg[28][11].CLK
clk => reg[28][12].CLK
clk => reg[28][13].CLK
clk => reg[28][14].CLK
clk => reg[28][15].CLK
clk => reg[28][16].CLK
clk => reg[28][17].CLK
clk => reg[28][18].CLK
clk => reg[28][19].CLK
clk => reg[28][20].CLK
clk => reg[28][21].CLK
clk => reg[28][22].CLK
clk => reg[28][23].CLK
clk => reg[28][24].CLK
clk => reg[28][25].CLK
clk => reg[28][26].CLK
clk => reg[28][27].CLK
clk => reg[28][28].CLK
clk => reg[28][29].CLK
clk => reg[28][30].CLK
clk => reg[28][31].CLK
clk => reg[27][0].CLK
clk => reg[27][1].CLK
clk => reg[27][2].CLK
clk => reg[27][3].CLK
clk => reg[27][4].CLK
clk => reg[27][5].CLK
clk => reg[27][6].CLK
clk => reg[27][7].CLK
clk => reg[27][8].CLK
clk => reg[27][9].CLK
clk => reg[27][10].CLK
clk => reg[27][11].CLK
clk => reg[27][12].CLK
clk => reg[27][13].CLK
clk => reg[27][14].CLK
clk => reg[27][15].CLK
clk => reg[27][16].CLK
clk => reg[27][17].CLK
clk => reg[27][18].CLK
clk => reg[27][19].CLK
clk => reg[27][20].CLK
clk => reg[27][21].CLK
clk => reg[27][22].CLK
clk => reg[27][23].CLK
clk => reg[27][24].CLK
clk => reg[27][25].CLK
clk => reg[27][26].CLK
clk => reg[27][27].CLK
clk => reg[27][28].CLK
clk => reg[27][29].CLK
clk => reg[27][30].CLK
clk => reg[27][31].CLK
clk => reg[26][0].CLK
clk => reg[26][1].CLK
clk => reg[26][2].CLK
clk => reg[26][3].CLK
clk => reg[26][4].CLK
clk => reg[26][5].CLK
clk => reg[26][6].CLK
clk => reg[26][7].CLK
clk => reg[26][8].CLK
clk => reg[26][9].CLK
clk => reg[26][10].CLK
clk => reg[26][11].CLK
clk => reg[26][12].CLK
clk => reg[26][13].CLK
clk => reg[26][14].CLK
clk => reg[26][15].CLK
clk => reg[26][16].CLK
clk => reg[26][17].CLK
clk => reg[26][18].CLK
clk => reg[26][19].CLK
clk => reg[26][20].CLK
clk => reg[26][21].CLK
clk => reg[26][22].CLK
clk => reg[26][23].CLK
clk => reg[26][24].CLK
clk => reg[26][25].CLK
clk => reg[26][26].CLK
clk => reg[26][27].CLK
clk => reg[26][28].CLK
clk => reg[26][29].CLK
clk => reg[26][30].CLK
clk => reg[26][31].CLK
clk => reg[25][0].CLK
clk => reg[25][1].CLK
clk => reg[25][2].CLK
clk => reg[25][3].CLK
clk => reg[25][4].CLK
clk => reg[25][5].CLK
clk => reg[25][6].CLK
clk => reg[25][7].CLK
clk => reg[25][8].CLK
clk => reg[25][9].CLK
clk => reg[25][10].CLK
clk => reg[25][11].CLK
clk => reg[25][12].CLK
clk => reg[25][13].CLK
clk => reg[25][14].CLK
clk => reg[25][15].CLK
clk => reg[25][16].CLK
clk => reg[25][17].CLK
clk => reg[25][18].CLK
clk => reg[25][19].CLK
clk => reg[25][20].CLK
clk => reg[25][21].CLK
clk => reg[25][22].CLK
clk => reg[25][23].CLK
clk => reg[25][24].CLK
clk => reg[25][25].CLK
clk => reg[25][26].CLK
clk => reg[25][27].CLK
clk => reg[25][28].CLK
clk => reg[25][29].CLK
clk => reg[25][30].CLK
clk => reg[25][31].CLK
clk => reg[24][0].CLK
clk => reg[24][1].CLK
clk => reg[24][2].CLK
clk => reg[24][3].CLK
clk => reg[24][4].CLK
clk => reg[24][5].CLK
clk => reg[24][6].CLK
clk => reg[24][7].CLK
clk => reg[24][8].CLK
clk => reg[24][9].CLK
clk => reg[24][10].CLK
clk => reg[24][11].CLK
clk => reg[24][12].CLK
clk => reg[24][13].CLK
clk => reg[24][14].CLK
clk => reg[24][15].CLK
clk => reg[24][16].CLK
clk => reg[24][17].CLK
clk => reg[24][18].CLK
clk => reg[24][19].CLK
clk => reg[24][20].CLK
clk => reg[24][21].CLK
clk => reg[24][22].CLK
clk => reg[24][23].CLK
clk => reg[24][24].CLK
clk => reg[24][25].CLK
clk => reg[24][26].CLK
clk => reg[24][27].CLK
clk => reg[24][28].CLK
clk => reg[24][29].CLK
clk => reg[24][30].CLK
clk => reg[24][31].CLK
clk => reg[23][0].CLK
clk => reg[23][1].CLK
clk => reg[23][2].CLK
clk => reg[23][3].CLK
clk => reg[23][4].CLK
clk => reg[23][5].CLK
clk => reg[23][6].CLK
clk => reg[23][7].CLK
clk => reg[23][8].CLK
clk => reg[23][9].CLK
clk => reg[23][10].CLK
clk => reg[23][11].CLK
clk => reg[23][12].CLK
clk => reg[23][13].CLK
clk => reg[23][14].CLK
clk => reg[23][15].CLK
clk => reg[23][16].CLK
clk => reg[23][17].CLK
clk => reg[23][18].CLK
clk => reg[23][19].CLK
clk => reg[23][20].CLK
clk => reg[23][21].CLK
clk => reg[23][22].CLK
clk => reg[23][23].CLK
clk => reg[23][24].CLK
clk => reg[23][25].CLK
clk => reg[23][26].CLK
clk => reg[23][27].CLK
clk => reg[23][28].CLK
clk => reg[23][29].CLK
clk => reg[23][30].CLK
clk => reg[23][31].CLK
clk => reg[22][0].CLK
clk => reg[22][1].CLK
clk => reg[22][2].CLK
clk => reg[22][3].CLK
clk => reg[22][4].CLK
clk => reg[22][5].CLK
clk => reg[22][6].CLK
clk => reg[22][7].CLK
clk => reg[22][8].CLK
clk => reg[22][9].CLK
clk => reg[22][10].CLK
clk => reg[22][11].CLK
clk => reg[22][12].CLK
clk => reg[22][13].CLK
clk => reg[22][14].CLK
clk => reg[22][15].CLK
clk => reg[22][16].CLK
clk => reg[22][17].CLK
clk => reg[22][18].CLK
clk => reg[22][19].CLK
clk => reg[22][20].CLK
clk => reg[22][21].CLK
clk => reg[22][22].CLK
clk => reg[22][23].CLK
clk => reg[22][24].CLK
clk => reg[22][25].CLK
clk => reg[22][26].CLK
clk => reg[22][27].CLK
clk => reg[22][28].CLK
clk => reg[22][29].CLK
clk => reg[22][30].CLK
clk => reg[22][31].CLK
clk => reg[21][0].CLK
clk => reg[21][1].CLK
clk => reg[21][2].CLK
clk => reg[21][3].CLK
clk => reg[21][4].CLK
clk => reg[21][5].CLK
clk => reg[21][6].CLK
clk => reg[21][7].CLK
clk => reg[21][8].CLK
clk => reg[21][9].CLK
clk => reg[21][10].CLK
clk => reg[21][11].CLK
clk => reg[21][12].CLK
clk => reg[21][13].CLK
clk => reg[21][14].CLK
clk => reg[21][15].CLK
clk => reg[21][16].CLK
clk => reg[21][17].CLK
clk => reg[21][18].CLK
clk => reg[21][19].CLK
clk => reg[21][20].CLK
clk => reg[21][21].CLK
clk => reg[21][22].CLK
clk => reg[21][23].CLK
clk => reg[21][24].CLK
clk => reg[21][25].CLK
clk => reg[21][26].CLK
clk => reg[21][27].CLK
clk => reg[21][28].CLK
clk => reg[21][29].CLK
clk => reg[21][30].CLK
clk => reg[21][31].CLK
clk => reg[20][0].CLK
clk => reg[20][1].CLK
clk => reg[20][2].CLK
clk => reg[20][3].CLK
clk => reg[20][4].CLK
clk => reg[20][5].CLK
clk => reg[20][6].CLK
clk => reg[20][7].CLK
clk => reg[20][8].CLK
clk => reg[20][9].CLK
clk => reg[20][10].CLK
clk => reg[20][11].CLK
clk => reg[20][12].CLK
clk => reg[20][13].CLK
clk => reg[20][14].CLK
clk => reg[20][15].CLK
clk => reg[20][16].CLK
clk => reg[20][17].CLK
clk => reg[20][18].CLK
clk => reg[20][19].CLK
clk => reg[20][20].CLK
clk => reg[20][21].CLK
clk => reg[20][22].CLK
clk => reg[20][23].CLK
clk => reg[20][24].CLK
clk => reg[20][25].CLK
clk => reg[20][26].CLK
clk => reg[20][27].CLK
clk => reg[20][28].CLK
clk => reg[20][29].CLK
clk => reg[20][30].CLK
clk => reg[20][31].CLK
clk => reg[19][0].CLK
clk => reg[19][1].CLK
clk => reg[19][2].CLK
clk => reg[19][3].CLK
clk => reg[19][4].CLK
clk => reg[19][5].CLK
clk => reg[19][6].CLK
clk => reg[19][7].CLK
clk => reg[19][8].CLK
clk => reg[19][9].CLK
clk => reg[19][10].CLK
clk => reg[19][11].CLK
clk => reg[19][12].CLK
clk => reg[19][13].CLK
clk => reg[19][14].CLK
clk => reg[19][15].CLK
clk => reg[19][16].CLK
clk => reg[19][17].CLK
clk => reg[19][18].CLK
clk => reg[19][19].CLK
clk => reg[19][20].CLK
clk => reg[19][21].CLK
clk => reg[19][22].CLK
clk => reg[19][23].CLK
clk => reg[19][24].CLK
clk => reg[19][25].CLK
clk => reg[19][26].CLK
clk => reg[19][27].CLK
clk => reg[19][28].CLK
clk => reg[19][29].CLK
clk => reg[19][30].CLK
clk => reg[19][31].CLK
clk => reg[18][0].CLK
clk => reg[18][1].CLK
clk => reg[18][2].CLK
clk => reg[18][3].CLK
clk => reg[18][4].CLK
clk => reg[18][5].CLK
clk => reg[18][6].CLK
clk => reg[18][7].CLK
clk => reg[18][8].CLK
clk => reg[18][9].CLK
clk => reg[18][10].CLK
clk => reg[18][11].CLK
clk => reg[18][12].CLK
clk => reg[18][13].CLK
clk => reg[18][14].CLK
clk => reg[18][15].CLK
clk => reg[18][16].CLK
clk => reg[18][17].CLK
clk => reg[18][18].CLK
clk => reg[18][19].CLK
clk => reg[18][20].CLK
clk => reg[18][21].CLK
clk => reg[18][22].CLK
clk => reg[18][23].CLK
clk => reg[18][24].CLK
clk => reg[18][25].CLK
clk => reg[18][26].CLK
clk => reg[18][27].CLK
clk => reg[18][28].CLK
clk => reg[18][29].CLK
clk => reg[18][30].CLK
clk => reg[18][31].CLK
clk => reg[17][0].CLK
clk => reg[17][1].CLK
clk => reg[17][2].CLK
clk => reg[17][3].CLK
clk => reg[17][4].CLK
clk => reg[17][5].CLK
clk => reg[17][6].CLK
clk => reg[17][7].CLK
clk => reg[17][8].CLK
clk => reg[17][9].CLK
clk => reg[17][10].CLK
clk => reg[17][11].CLK
clk => reg[17][12].CLK
clk => reg[17][13].CLK
clk => reg[17][14].CLK
clk => reg[17][15].CLK
clk => reg[17][16].CLK
clk => reg[17][17].CLK
clk => reg[17][18].CLK
clk => reg[17][19].CLK
clk => reg[17][20].CLK
clk => reg[17][21].CLK
clk => reg[17][22].CLK
clk => reg[17][23].CLK
clk => reg[17][24].CLK
clk => reg[17][25].CLK
clk => reg[17][26].CLK
clk => reg[17][27].CLK
clk => reg[17][28].CLK
clk => reg[17][29].CLK
clk => reg[17][30].CLK
clk => reg[17][31].CLK
clk => reg[16][0].CLK
clk => reg[16][1].CLK
clk => reg[16][2].CLK
clk => reg[16][3].CLK
clk => reg[16][4].CLK
clk => reg[16][5].CLK
clk => reg[16][6].CLK
clk => reg[16][7].CLK
clk => reg[16][8].CLK
clk => reg[16][9].CLK
clk => reg[16][10].CLK
clk => reg[16][11].CLK
clk => reg[16][12].CLK
clk => reg[16][13].CLK
clk => reg[16][14].CLK
clk => reg[16][15].CLK
clk => reg[16][16].CLK
clk => reg[16][17].CLK
clk => reg[16][18].CLK
clk => reg[16][19].CLK
clk => reg[16][20].CLK
clk => reg[16][21].CLK
clk => reg[16][22].CLK
clk => reg[16][23].CLK
clk => reg[16][24].CLK
clk => reg[16][25].CLK
clk => reg[16][26].CLK
clk => reg[16][27].CLK
clk => reg[16][28].CLK
clk => reg[16][29].CLK
clk => reg[16][30].CLK
clk => reg[16][31].CLK
clk => reg[15][0].CLK
clk => reg[15][1].CLK
clk => reg[15][2].CLK
clk => reg[15][3].CLK
clk => reg[15][4].CLK
clk => reg[15][5].CLK
clk => reg[15][6].CLK
clk => reg[15][7].CLK
clk => reg[15][8].CLK
clk => reg[15][9].CLK
clk => reg[15][10].CLK
clk => reg[15][11].CLK
clk => reg[15][12].CLK
clk => reg[15][13].CLK
clk => reg[15][14].CLK
clk => reg[15][15].CLK
clk => reg[15][16].CLK
clk => reg[15][17].CLK
clk => reg[15][18].CLK
clk => reg[15][19].CLK
clk => reg[15][20].CLK
clk => reg[15][21].CLK
clk => reg[15][22].CLK
clk => reg[15][23].CLK
clk => reg[15][24].CLK
clk => reg[15][25].CLK
clk => reg[15][26].CLK
clk => reg[15][27].CLK
clk => reg[15][28].CLK
clk => reg[15][29].CLK
clk => reg[15][30].CLK
clk => reg[15][31].CLK
clk => reg[14][0].CLK
clk => reg[14][1].CLK
clk => reg[14][2].CLK
clk => reg[14][3].CLK
clk => reg[14][4].CLK
clk => reg[14][5].CLK
clk => reg[14][6].CLK
clk => reg[14][7].CLK
clk => reg[14][8].CLK
clk => reg[14][9].CLK
clk => reg[14][10].CLK
clk => reg[14][11].CLK
clk => reg[14][12].CLK
clk => reg[14][13].CLK
clk => reg[14][14].CLK
clk => reg[14][15].CLK
clk => reg[14][16].CLK
clk => reg[14][17].CLK
clk => reg[14][18].CLK
clk => reg[14][19].CLK
clk => reg[14][20].CLK
clk => reg[14][21].CLK
clk => reg[14][22].CLK
clk => reg[14][23].CLK
clk => reg[14][24].CLK
clk => reg[14][25].CLK
clk => reg[14][26].CLK
clk => reg[14][27].CLK
clk => reg[14][28].CLK
clk => reg[14][29].CLK
clk => reg[14][30].CLK
clk => reg[14][31].CLK
clk => reg[13][0].CLK
clk => reg[13][1].CLK
clk => reg[13][2].CLK
clk => reg[13][3].CLK
clk => reg[13][4].CLK
clk => reg[13][5].CLK
clk => reg[13][6].CLK
clk => reg[13][7].CLK
clk => reg[13][8].CLK
clk => reg[13][9].CLK
clk => reg[13][10].CLK
clk => reg[13][11].CLK
clk => reg[13][12].CLK
clk => reg[13][13].CLK
clk => reg[13][14].CLK
clk => reg[13][15].CLK
clk => reg[13][16].CLK
clk => reg[13][17].CLK
clk => reg[13][18].CLK
clk => reg[13][19].CLK
clk => reg[13][20].CLK
clk => reg[13][21].CLK
clk => reg[13][22].CLK
clk => reg[13][23].CLK
clk => reg[13][24].CLK
clk => reg[13][25].CLK
clk => reg[13][26].CLK
clk => reg[13][27].CLK
clk => reg[13][28].CLK
clk => reg[13][29].CLK
clk => reg[13][30].CLK
clk => reg[13][31].CLK
clk => reg[12][0].CLK
clk => reg[12][1].CLK
clk => reg[12][2].CLK
clk => reg[12][3].CLK
clk => reg[12][4].CLK
clk => reg[12][5].CLK
clk => reg[12][6].CLK
clk => reg[12][7].CLK
clk => reg[12][8].CLK
clk => reg[12][9].CLK
clk => reg[12][10].CLK
clk => reg[12][11].CLK
clk => reg[12][12].CLK
clk => reg[12][13].CLK
clk => reg[12][14].CLK
clk => reg[12][15].CLK
clk => reg[12][16].CLK
clk => reg[12][17].CLK
clk => reg[12][18].CLK
clk => reg[12][19].CLK
clk => reg[12][20].CLK
clk => reg[12][21].CLK
clk => reg[12][22].CLK
clk => reg[12][23].CLK
clk => reg[12][24].CLK
clk => reg[12][25].CLK
clk => reg[12][26].CLK
clk => reg[12][27].CLK
clk => reg[12][28].CLK
clk => reg[12][29].CLK
clk => reg[12][30].CLK
clk => reg[12][31].CLK
clk => reg[11][0].CLK
clk => reg[11][1].CLK
clk => reg[11][2].CLK
clk => reg[11][3].CLK
clk => reg[11][4].CLK
clk => reg[11][5].CLK
clk => reg[11][6].CLK
clk => reg[11][7].CLK
clk => reg[11][8].CLK
clk => reg[11][9].CLK
clk => reg[11][10].CLK
clk => reg[11][11].CLK
clk => reg[11][12].CLK
clk => reg[11][13].CLK
clk => reg[11][14].CLK
clk => reg[11][15].CLK
clk => reg[11][16].CLK
clk => reg[11][17].CLK
clk => reg[11][18].CLK
clk => reg[11][19].CLK
clk => reg[11][20].CLK
clk => reg[11][21].CLK
clk => reg[11][22].CLK
clk => reg[11][23].CLK
clk => reg[11][24].CLK
clk => reg[11][25].CLK
clk => reg[11][26].CLK
clk => reg[11][27].CLK
clk => reg[11][28].CLK
clk => reg[11][29].CLK
clk => reg[11][30].CLK
clk => reg[11][31].CLK
clk => reg[10][0].CLK
clk => reg[10][1].CLK
clk => reg[10][2].CLK
clk => reg[10][3].CLK
clk => reg[10][4].CLK
clk => reg[10][5].CLK
clk => reg[10][6].CLK
clk => reg[10][7].CLK
clk => reg[10][8].CLK
clk => reg[10][9].CLK
clk => reg[10][10].CLK
clk => reg[10][11].CLK
clk => reg[10][12].CLK
clk => reg[10][13].CLK
clk => reg[10][14].CLK
clk => reg[10][15].CLK
clk => reg[10][16].CLK
clk => reg[10][17].CLK
clk => reg[10][18].CLK
clk => reg[10][19].CLK
clk => reg[10][20].CLK
clk => reg[10][21].CLK
clk => reg[10][22].CLK
clk => reg[10][23].CLK
clk => reg[10][24].CLK
clk => reg[10][25].CLK
clk => reg[10][26].CLK
clk => reg[10][27].CLK
clk => reg[10][28].CLK
clk => reg[10][29].CLK
clk => reg[10][30].CLK
clk => reg[10][31].CLK
clk => reg[9][0].CLK
clk => reg[9][1].CLK
clk => reg[9][2].CLK
clk => reg[9][3].CLK
clk => reg[9][4].CLK
clk => reg[9][5].CLK
clk => reg[9][6].CLK
clk => reg[9][7].CLK
clk => reg[9][8].CLK
clk => reg[9][9].CLK
clk => reg[9][10].CLK
clk => reg[9][11].CLK
clk => reg[9][12].CLK
clk => reg[9][13].CLK
clk => reg[9][14].CLK
clk => reg[9][15].CLK
clk => reg[9][16].CLK
clk => reg[9][17].CLK
clk => reg[9][18].CLK
clk => reg[9][19].CLK
clk => reg[9][20].CLK
clk => reg[9][21].CLK
clk => reg[9][22].CLK
clk => reg[9][23].CLK
clk => reg[9][24].CLK
clk => reg[9][25].CLK
clk => reg[9][26].CLK
clk => reg[9][27].CLK
clk => reg[9][28].CLK
clk => reg[9][29].CLK
clk => reg[9][30].CLK
clk => reg[9][31].CLK
clk => reg[8][0].CLK
clk => reg[8][1].CLK
clk => reg[8][2].CLK
clk => reg[8][3].CLK
clk => reg[8][4].CLK
clk => reg[8][5].CLK
clk => reg[8][6].CLK
clk => reg[8][7].CLK
clk => reg[8][8].CLK
clk => reg[8][9].CLK
clk => reg[8][10].CLK
clk => reg[8][11].CLK
clk => reg[8][12].CLK
clk => reg[8][13].CLK
clk => reg[8][14].CLK
clk => reg[8][15].CLK
clk => reg[8][16].CLK
clk => reg[8][17].CLK
clk => reg[8][18].CLK
clk => reg[8][19].CLK
clk => reg[8][20].CLK
clk => reg[8][21].CLK
clk => reg[8][22].CLK
clk => reg[8][23].CLK
clk => reg[8][24].CLK
clk => reg[8][25].CLK
clk => reg[8][26].CLK
clk => reg[8][27].CLK
clk => reg[8][28].CLK
clk => reg[8][29].CLK
clk => reg[8][30].CLK
clk => reg[8][31].CLK
clk => reg[7][0].CLK
clk => reg[7][1].CLK
clk => reg[7][2].CLK
clk => reg[7][3].CLK
clk => reg[7][4].CLK
clk => reg[7][5].CLK
clk => reg[7][6].CLK
clk => reg[7][7].CLK
clk => reg[7][8].CLK
clk => reg[7][9].CLK
clk => reg[7][10].CLK
clk => reg[7][11].CLK
clk => reg[7][12].CLK
clk => reg[7][13].CLK
clk => reg[7][14].CLK
clk => reg[7][15].CLK
clk => reg[7][16].CLK
clk => reg[7][17].CLK
clk => reg[7][18].CLK
clk => reg[7][19].CLK
clk => reg[7][20].CLK
clk => reg[7][21].CLK
clk => reg[7][22].CLK
clk => reg[7][23].CLK
clk => reg[7][24].CLK
clk => reg[7][25].CLK
clk => reg[7][26].CLK
clk => reg[7][27].CLK
clk => reg[7][28].CLK
clk => reg[7][29].CLK
clk => reg[7][30].CLK
clk => reg[7][31].CLK
clk => reg[6][0].CLK
clk => reg[6][1].CLK
clk => reg[6][2].CLK
clk => reg[6][3].CLK
clk => reg[6][4].CLK
clk => reg[6][5].CLK
clk => reg[6][6].CLK
clk => reg[6][7].CLK
clk => reg[6][8].CLK
clk => reg[6][9].CLK
clk => reg[6][10].CLK
clk => reg[6][11].CLK
clk => reg[6][12].CLK
clk => reg[6][13].CLK
clk => reg[6][14].CLK
clk => reg[6][15].CLK
clk => reg[6][16].CLK
clk => reg[6][17].CLK
clk => reg[6][18].CLK
clk => reg[6][19].CLK
clk => reg[6][20].CLK
clk => reg[6][21].CLK
clk => reg[6][22].CLK
clk => reg[6][23].CLK
clk => reg[6][24].CLK
clk => reg[6][25].CLK
clk => reg[6][26].CLK
clk => reg[6][27].CLK
clk => reg[6][28].CLK
clk => reg[6][29].CLK
clk => reg[6][30].CLK
clk => reg[6][31].CLK
clk => reg[5][0].CLK
clk => reg[5][1].CLK
clk => reg[5][2].CLK
clk => reg[5][3].CLK
clk => reg[5][4].CLK
clk => reg[5][5].CLK
clk => reg[5][6].CLK
clk => reg[5][7].CLK
clk => reg[5][8].CLK
clk => reg[5][9].CLK
clk => reg[5][10].CLK
clk => reg[5][11].CLK
clk => reg[5][12].CLK
clk => reg[5][13].CLK
clk => reg[5][14].CLK
clk => reg[5][15].CLK
clk => reg[5][16].CLK
clk => reg[5][17].CLK
clk => reg[5][18].CLK
clk => reg[5][19].CLK
clk => reg[5][20].CLK
clk => reg[5][21].CLK
clk => reg[5][22].CLK
clk => reg[5][23].CLK
clk => reg[5][24].CLK
clk => reg[5][25].CLK
clk => reg[5][26].CLK
clk => reg[5][27].CLK
clk => reg[5][28].CLK
clk => reg[5][29].CLK
clk => reg[5][30].CLK
clk => reg[5][31].CLK
clk => reg[4][0].CLK
clk => reg[4][1].CLK
clk => reg[4][2].CLK
clk => reg[4][3].CLK
clk => reg[4][4].CLK
clk => reg[4][5].CLK
clk => reg[4][6].CLK
clk => reg[4][7].CLK
clk => reg[4][8].CLK
clk => reg[4][9].CLK
clk => reg[4][10].CLK
clk => reg[4][11].CLK
clk => reg[4][12].CLK
clk => reg[4][13].CLK
clk => reg[4][14].CLK
clk => reg[4][15].CLK
clk => reg[4][16].CLK
clk => reg[4][17].CLK
clk => reg[4][18].CLK
clk => reg[4][19].CLK
clk => reg[4][20].CLK
clk => reg[4][21].CLK
clk => reg[4][22].CLK
clk => reg[4][23].CLK
clk => reg[4][24].CLK
clk => reg[4][25].CLK
clk => reg[4][26].CLK
clk => reg[4][27].CLK
clk => reg[4][28].CLK
clk => reg[4][29].CLK
clk => reg[4][30].CLK
clk => reg[4][31].CLK
clk => reg[3][0].CLK
clk => reg[3][1].CLK
clk => reg[3][2].CLK
clk => reg[3][3].CLK
clk => reg[3][4].CLK
clk => reg[3][5].CLK
clk => reg[3][6].CLK
clk => reg[3][7].CLK
clk => reg[3][8].CLK
clk => reg[3][9].CLK
clk => reg[3][10].CLK
clk => reg[3][11].CLK
clk => reg[3][12].CLK
clk => reg[3][13].CLK
clk => reg[3][14].CLK
clk => reg[3][15].CLK
clk => reg[3][16].CLK
clk => reg[3][17].CLK
clk => reg[3][18].CLK
clk => reg[3][19].CLK
clk => reg[3][20].CLK
clk => reg[3][21].CLK
clk => reg[3][22].CLK
clk => reg[3][23].CLK
clk => reg[3][24].CLK
clk => reg[3][25].CLK
clk => reg[3][26].CLK
clk => reg[3][27].CLK
clk => reg[3][28].CLK
clk => reg[3][29].CLK
clk => reg[3][30].CLK
clk => reg[3][31].CLK
clk => reg[2][0].CLK
clk => reg[2][1].CLK
clk => reg[2][2].CLK
clk => reg[2][3].CLK
clk => reg[2][4].CLK
clk => reg[2][5].CLK
clk => reg[2][6].CLK
clk => reg[2][7].CLK
clk => reg[2][8].CLK
clk => reg[2][9].CLK
clk => reg[2][10].CLK
clk => reg[2][11].CLK
clk => reg[2][12].CLK
clk => reg[2][13].CLK
clk => reg[2][14].CLK
clk => reg[2][15].CLK
clk => reg[2][16].CLK
clk => reg[2][17].CLK
clk => reg[2][18].CLK
clk => reg[2][19].CLK
clk => reg[2][20].CLK
clk => reg[2][21].CLK
clk => reg[2][22].CLK
clk => reg[2][23].CLK
clk => reg[2][24].CLK
clk => reg[2][25].CLK
clk => reg[2][26].CLK
clk => reg[2][27].CLK
clk => reg[2][28].CLK
clk => reg[2][29].CLK
clk => reg[2][30].CLK
clk => reg[2][31].CLK
clk => reg[1][0].CLK
clk => reg[1][1].CLK
clk => reg[1][2].CLK
clk => reg[1][3].CLK
clk => reg[1][4].CLK
clk => reg[1][5].CLK
clk => reg[1][6].CLK
clk => reg[1][7].CLK
clk => reg[1][8].CLK
clk => reg[1][9].CLK
clk => reg[1][10].CLK
clk => reg[1][11].CLK
clk => reg[1][12].CLK
clk => reg[1][13].CLK
clk => reg[1][14].CLK
clk => reg[1][15].CLK
clk => reg[1][16].CLK
clk => reg[1][17].CLK
clk => reg[1][18].CLK
clk => reg[1][19].CLK
clk => reg[1][20].CLK
clk => reg[1][21].CLK
clk => reg[1][22].CLK
clk => reg[1][23].CLK
clk => reg[1][24].CLK
clk => reg[1][25].CLK
clk => reg[1][26].CLK
clk => reg[1][27].CLK
clk => reg[1][28].CLK
clk => reg[1][29].CLK
clk => reg[1][30].CLK
clk => reg[1][31].CLK
clk => reg[0][0].CLK
clk => reg[0][1].CLK
clk => reg[0][2].CLK
clk => reg[0][3].CLK
clk => reg[0][4].CLK
clk => reg[0][5].CLK
clk => reg[0][6].CLK
clk => reg[0][7].CLK
clk => reg[0][8].CLK
clk => reg[0][9].CLK
clk => reg[0][10].CLK
clk => reg[0][11].CLK
clk => reg[0][12].CLK
clk => reg[0][13].CLK
clk => reg[0][14].CLK
clk => reg[0][15].CLK
clk => reg[0][16].CLK
clk => reg[0][17].CLK
clk => reg[0][18].CLK
clk => reg[0][19].CLK
clk => reg[0][20].CLK
clk => reg[0][21].CLK
clk => reg[0][22].CLK
clk => reg[0][23].CLK
clk => reg[0][24].CLK
clk => reg[0][25].CLK
clk => reg[0][26].CLK
clk => reg[0][27].CLK
clk => reg[0][28].CLK
clk => reg[0][29].CLK
clk => reg[0][30].CLK
clk => reg[0][31].CLK
aa[0] => Mux0.IN4
aa[0] => Mux1.IN4
aa[0] => Mux2.IN4
aa[0] => Mux3.IN4
aa[0] => Mux4.IN4
aa[0] => Mux5.IN4
aa[0] => Mux6.IN4
aa[0] => Mux7.IN4
aa[0] => Mux8.IN4
aa[0] => Mux9.IN4
aa[0] => Mux10.IN4
aa[0] => Mux11.IN4
aa[0] => Mux12.IN4
aa[0] => Mux13.IN4
aa[0] => Mux14.IN4
aa[0] => Mux15.IN4
aa[0] => Mux16.IN4
aa[0] => Mux17.IN4
aa[0] => Mux18.IN4
aa[0] => Mux19.IN4
aa[0] => Mux20.IN4
aa[0] => Mux21.IN4
aa[0] => Mux22.IN4
aa[0] => Mux23.IN4
aa[0] => Mux24.IN4
aa[0] => Mux25.IN4
aa[0] => Mux26.IN4
aa[0] => Mux27.IN4
aa[0] => Mux28.IN4
aa[0] => Mux29.IN4
aa[0] => Mux30.IN4
aa[0] => Mux31.IN4
aa[1] => Mux0.IN3
aa[1] => Mux1.IN3
aa[1] => Mux2.IN3
aa[1] => Mux3.IN3
aa[1] => Mux4.IN3
aa[1] => Mux5.IN3
aa[1] => Mux6.IN3
aa[1] => Mux7.IN3
aa[1] => Mux8.IN3
aa[1] => Mux9.IN3
aa[1] => Mux10.IN3
aa[1] => Mux11.IN3
aa[1] => Mux12.IN3
aa[1] => Mux13.IN3
aa[1] => Mux14.IN3
aa[1] => Mux15.IN3
aa[1] => Mux16.IN3
aa[1] => Mux17.IN3
aa[1] => Mux18.IN3
aa[1] => Mux19.IN3
aa[1] => Mux20.IN3
aa[1] => Mux21.IN3
aa[1] => Mux22.IN3
aa[1] => Mux23.IN3
aa[1] => Mux24.IN3
aa[1] => Mux25.IN3
aa[1] => Mux26.IN3
aa[1] => Mux27.IN3
aa[1] => Mux28.IN3
aa[1] => Mux29.IN3
aa[1] => Mux30.IN3
aa[1] => Mux31.IN3
aa[2] => Mux0.IN2
aa[2] => Mux1.IN2
aa[2] => Mux2.IN2
aa[2] => Mux3.IN2
aa[2] => Mux4.IN2
aa[2] => Mux5.IN2
aa[2] => Mux6.IN2
aa[2] => Mux7.IN2
aa[2] => Mux8.IN2
aa[2] => Mux9.IN2
aa[2] => Mux10.IN2
aa[2] => Mux11.IN2
aa[2] => Mux12.IN2
aa[2] => Mux13.IN2
aa[2] => Mux14.IN2
aa[2] => Mux15.IN2
aa[2] => Mux16.IN2
aa[2] => Mux17.IN2
aa[2] => Mux18.IN2
aa[2] => Mux19.IN2
aa[2] => Mux20.IN2
aa[2] => Mux21.IN2
aa[2] => Mux22.IN2
aa[2] => Mux23.IN2
aa[2] => Mux24.IN2
aa[2] => Mux25.IN2
aa[2] => Mux26.IN2
aa[2] => Mux27.IN2
aa[2] => Mux28.IN2
aa[2] => Mux29.IN2
aa[2] => Mux30.IN2
aa[2] => Mux31.IN2
aa[3] => Mux0.IN1
aa[3] => Mux1.IN1
aa[3] => Mux2.IN1
aa[3] => Mux3.IN1
aa[3] => Mux4.IN1
aa[3] => Mux5.IN1
aa[3] => Mux6.IN1
aa[3] => Mux7.IN1
aa[3] => Mux8.IN1
aa[3] => Mux9.IN1
aa[3] => Mux10.IN1
aa[3] => Mux11.IN1
aa[3] => Mux12.IN1
aa[3] => Mux13.IN1
aa[3] => Mux14.IN1
aa[3] => Mux15.IN1
aa[3] => Mux16.IN1
aa[3] => Mux17.IN1
aa[3] => Mux18.IN1
aa[3] => Mux19.IN1
aa[3] => Mux20.IN1
aa[3] => Mux21.IN1
aa[3] => Mux22.IN1
aa[3] => Mux23.IN1
aa[3] => Mux24.IN1
aa[3] => Mux25.IN1
aa[3] => Mux26.IN1
aa[3] => Mux27.IN1
aa[3] => Mux28.IN1
aa[3] => Mux29.IN1
aa[3] => Mux30.IN1
aa[3] => Mux31.IN1
aa[4] => Mux0.IN0
aa[4] => Mux1.IN0
aa[4] => Mux2.IN0
aa[4] => Mux3.IN0
aa[4] => Mux4.IN0
aa[4] => Mux5.IN0
aa[4] => Mux6.IN0
aa[4] => Mux7.IN0
aa[4] => Mux8.IN0
aa[4] => Mux9.IN0
aa[4] => Mux10.IN0
aa[4] => Mux11.IN0
aa[4] => Mux12.IN0
aa[4] => Mux13.IN0
aa[4] => Mux14.IN0
aa[4] => Mux15.IN0
aa[4] => Mux16.IN0
aa[4] => Mux17.IN0
aa[4] => Mux18.IN0
aa[4] => Mux19.IN0
aa[4] => Mux20.IN0
aa[4] => Mux21.IN0
aa[4] => Mux22.IN0
aa[4] => Mux23.IN0
aa[4] => Mux24.IN0
aa[4] => Mux25.IN0
aa[4] => Mux26.IN0
aa[4] => Mux27.IN0
aa[4] => Mux28.IN0
aa[4] => Mux29.IN0
aa[4] => Mux30.IN0
aa[4] => Mux31.IN0
ab[0] => Mux32.IN4
ab[0] => Mux33.IN4
ab[0] => Mux34.IN4
ab[0] => Mux35.IN4
ab[0] => Mux36.IN4
ab[0] => Mux37.IN4
ab[0] => Mux38.IN4
ab[0] => Mux39.IN4
ab[0] => Mux40.IN4
ab[0] => Mux41.IN4
ab[0] => Mux42.IN4
ab[0] => Mux43.IN4
ab[0] => Mux44.IN4
ab[0] => Mux45.IN4
ab[0] => Mux46.IN4
ab[0] => Mux47.IN4
ab[0] => Mux48.IN4
ab[0] => Mux49.IN4
ab[0] => Mux50.IN4
ab[0] => Mux51.IN4
ab[0] => Mux52.IN4
ab[0] => Mux53.IN4
ab[0] => Mux54.IN4
ab[0] => Mux55.IN4
ab[0] => Mux56.IN4
ab[0] => Mux57.IN4
ab[0] => Mux58.IN4
ab[0] => Mux59.IN4
ab[0] => Mux60.IN4
ab[0] => Mux61.IN4
ab[0] => Mux62.IN4
ab[0] => Mux63.IN4
ab[1] => Mux32.IN3
ab[1] => Mux33.IN3
ab[1] => Mux34.IN3
ab[1] => Mux35.IN3
ab[1] => Mux36.IN3
ab[1] => Mux37.IN3
ab[1] => Mux38.IN3
ab[1] => Mux39.IN3
ab[1] => Mux40.IN3
ab[1] => Mux41.IN3
ab[1] => Mux42.IN3
ab[1] => Mux43.IN3
ab[1] => Mux44.IN3
ab[1] => Mux45.IN3
ab[1] => Mux46.IN3
ab[1] => Mux47.IN3
ab[1] => Mux48.IN3
ab[1] => Mux49.IN3
ab[1] => Mux50.IN3
ab[1] => Mux51.IN3
ab[1] => Mux52.IN3
ab[1] => Mux53.IN3
ab[1] => Mux54.IN3
ab[1] => Mux55.IN3
ab[1] => Mux56.IN3
ab[1] => Mux57.IN3
ab[1] => Mux58.IN3
ab[1] => Mux59.IN3
ab[1] => Mux60.IN3
ab[1] => Mux61.IN3
ab[1] => Mux62.IN3
ab[1] => Mux63.IN3
ab[2] => Mux32.IN2
ab[2] => Mux33.IN2
ab[2] => Mux34.IN2
ab[2] => Mux35.IN2
ab[2] => Mux36.IN2
ab[2] => Mux37.IN2
ab[2] => Mux38.IN2
ab[2] => Mux39.IN2
ab[2] => Mux40.IN2
ab[2] => Mux41.IN2
ab[2] => Mux42.IN2
ab[2] => Mux43.IN2
ab[2] => Mux44.IN2
ab[2] => Mux45.IN2
ab[2] => Mux46.IN2
ab[2] => Mux47.IN2
ab[2] => Mux48.IN2
ab[2] => Mux49.IN2
ab[2] => Mux50.IN2
ab[2] => Mux51.IN2
ab[2] => Mux52.IN2
ab[2] => Mux53.IN2
ab[2] => Mux54.IN2
ab[2] => Mux55.IN2
ab[2] => Mux56.IN2
ab[2] => Mux57.IN2
ab[2] => Mux58.IN2
ab[2] => Mux59.IN2
ab[2] => Mux60.IN2
ab[2] => Mux61.IN2
ab[2] => Mux62.IN2
ab[2] => Mux63.IN2
ab[3] => Mux32.IN1
ab[3] => Mux33.IN1
ab[3] => Mux34.IN1
ab[3] => Mux35.IN1
ab[3] => Mux36.IN1
ab[3] => Mux37.IN1
ab[3] => Mux38.IN1
ab[3] => Mux39.IN1
ab[3] => Mux40.IN1
ab[3] => Mux41.IN1
ab[3] => Mux42.IN1
ab[3] => Mux43.IN1
ab[3] => Mux44.IN1
ab[3] => Mux45.IN1
ab[3] => Mux46.IN1
ab[3] => Mux47.IN1
ab[3] => Mux48.IN1
ab[3] => Mux49.IN1
ab[3] => Mux50.IN1
ab[3] => Mux51.IN1
ab[3] => Mux52.IN1
ab[3] => Mux53.IN1
ab[3] => Mux54.IN1
ab[3] => Mux55.IN1
ab[3] => Mux56.IN1
ab[3] => Mux57.IN1
ab[3] => Mux58.IN1
ab[3] => Mux59.IN1
ab[3] => Mux60.IN1
ab[3] => Mux61.IN1
ab[3] => Mux62.IN1
ab[3] => Mux63.IN1
ab[4] => Mux32.IN0
ab[4] => Mux33.IN0
ab[4] => Mux34.IN0
ab[4] => Mux35.IN0
ab[4] => Mux36.IN0
ab[4] => Mux37.IN0
ab[4] => Mux38.IN0
ab[4] => Mux39.IN0
ab[4] => Mux40.IN0
ab[4] => Mux41.IN0
ab[4] => Mux42.IN0
ab[4] => Mux43.IN0
ab[4] => Mux44.IN0
ab[4] => Mux45.IN0
ab[4] => Mux46.IN0
ab[4] => Mux47.IN0
ab[4] => Mux48.IN0
ab[4] => Mux49.IN0
ab[4] => Mux50.IN0
ab[4] => Mux51.IN0
ab[4] => Mux52.IN0
ab[4] => Mux53.IN0
ab[4] => Mux54.IN0
ab[4] => Mux55.IN0
ab[4] => Mux56.IN0
ab[4] => Mux57.IN0
ab[4] => Mux58.IN0
ab[4] => Mux59.IN0
ab[4] => Mux60.IN0
ab[4] => Mux61.IN0
ab[4] => Mux62.IN0
ab[4] => Mux63.IN0
aw[0] => Decoder0.IN4
aw[1] => Decoder0.IN3
aw[2] => Decoder0.IN2
aw[3] => Decoder0.IN1
aw[4] => Decoder0.IN0
wren => reg[31][10].ENA
wren => reg[31][9].ENA
wren => reg[31][8].ENA
wren => reg[31][7].ENA
wren => reg[31][6].ENA
wren => reg[31][5].ENA
wren => reg[31][4].ENA
wren => reg[31][3].ENA
wren => reg[31][2].ENA
wren => reg[31][1].ENA
wren => reg[31][0].ENA
wren => reg[31][11].ENA
wren => reg[31][12].ENA
wren => reg[31][13].ENA
wren => reg[31][14].ENA
wren => reg[31][15].ENA
wren => reg[31][16].ENA
wren => reg[31][17].ENA
wren => reg[31][18].ENA
wren => reg[31][19].ENA
wren => reg[31][20].ENA
wren => reg[31][21].ENA
wren => reg[31][22].ENA
wren => reg[31][23].ENA
wren => reg[31][24].ENA
wren => reg[31][25].ENA
wren => reg[31][26].ENA
wren => reg[31][27].ENA
wren => reg[31][28].ENA
wren => reg[31][29].ENA
wren => reg[31][30].ENA
wren => reg[31][31].ENA
wren => reg[30][0].ENA
wren => reg[30][1].ENA
wren => reg[30][2].ENA
wren => reg[30][3].ENA
wren => reg[30][4].ENA
wren => reg[30][5].ENA
wren => reg[30][6].ENA
wren => reg[30][7].ENA
wren => reg[30][8].ENA
wren => reg[30][9].ENA
wren => reg[30][10].ENA
wren => reg[30][11].ENA
wren => reg[30][12].ENA
wren => reg[30][13].ENA
wren => reg[30][14].ENA
wren => reg[30][15].ENA
wren => reg[30][16].ENA
wren => reg[30][17].ENA
wren => reg[30][18].ENA
wren => reg[30][19].ENA
wren => reg[30][20].ENA
wren => reg[30][21].ENA
wren => reg[30][22].ENA
wren => reg[30][23].ENA
wren => reg[30][24].ENA
wren => reg[30][25].ENA
wren => reg[30][26].ENA
wren => reg[30][27].ENA
wren => reg[30][28].ENA
wren => reg[30][29].ENA
wren => reg[30][30].ENA
wren => reg[30][31].ENA
wren => reg[29][0].ENA
wren => reg[29][1].ENA
wren => reg[29][2].ENA
wren => reg[29][3].ENA
wren => reg[29][4].ENA
wren => reg[29][5].ENA
wren => reg[29][6].ENA
wren => reg[29][7].ENA
wren => reg[29][8].ENA
wren => reg[29][9].ENA
wren => reg[29][10].ENA
wren => reg[29][11].ENA
wren => reg[29][12].ENA
wren => reg[29][13].ENA
wren => reg[29][14].ENA
wren => reg[29][15].ENA
wren => reg[29][16].ENA
wren => reg[29][17].ENA
wren => reg[29][18].ENA
wren => reg[29][19].ENA
wren => reg[29][20].ENA
wren => reg[29][21].ENA
wren => reg[29][22].ENA
wren => reg[29][23].ENA
wren => reg[29][24].ENA
wren => reg[29][25].ENA
wren => reg[29][26].ENA
wren => reg[29][27].ENA
wren => reg[29][28].ENA
wren => reg[29][29].ENA
wren => reg[29][30].ENA
wren => reg[29][31].ENA
wren => reg[28][0].ENA
wren => reg[28][1].ENA
wren => reg[28][2].ENA
wren => reg[28][3].ENA
wren => reg[28][4].ENA
wren => reg[28][5].ENA
wren => reg[28][6].ENA
wren => reg[28][7].ENA
wren => reg[28][8].ENA
wren => reg[28][9].ENA
wren => reg[28][10].ENA
wren => reg[28][11].ENA
wren => reg[28][12].ENA
wren => reg[28][13].ENA
wren => reg[28][14].ENA
wren => reg[28][15].ENA
wren => reg[28][16].ENA
wren => reg[28][17].ENA
wren => reg[28][18].ENA
wren => reg[28][19].ENA
wren => reg[28][20].ENA
wren => reg[28][21].ENA
wren => reg[28][22].ENA
wren => reg[28][23].ENA
wren => reg[28][24].ENA
wren => reg[28][25].ENA
wren => reg[28][26].ENA
wren => reg[28][27].ENA
wren => reg[28][28].ENA
wren => reg[28][29].ENA
wren => reg[28][30].ENA
wren => reg[28][31].ENA
wren => reg[27][0].ENA
wren => reg[27][1].ENA
wren => reg[27][2].ENA
wren => reg[27][3].ENA
wren => reg[27][4].ENA
wren => reg[27][5].ENA
wren => reg[27][6].ENA
wren => reg[27][7].ENA
wren => reg[27][8].ENA
wren => reg[27][9].ENA
wren => reg[27][10].ENA
wren => reg[27][11].ENA
wren => reg[27][12].ENA
wren => reg[27][13].ENA
wren => reg[27][14].ENA
wren => reg[27][15].ENA
wren => reg[27][16].ENA
wren => reg[27][17].ENA
wren => reg[27][18].ENA
wren => reg[27][19].ENA
wren => reg[27][20].ENA
wren => reg[27][21].ENA
wren => reg[27][22].ENA
wren => reg[27][23].ENA
wren => reg[27][24].ENA
wren => reg[27][25].ENA
wren => reg[27][26].ENA
wren => reg[27][27].ENA
wren => reg[27][28].ENA
wren => reg[27][29].ENA
wren => reg[27][30].ENA
wren => reg[27][31].ENA
wren => reg[26][0].ENA
wren => reg[26][1].ENA
wren => reg[26][2].ENA
wren => reg[26][3].ENA
wren => reg[26][4].ENA
wren => reg[26][5].ENA
wren => reg[26][6].ENA
wren => reg[26][7].ENA
wren => reg[26][8].ENA
wren => reg[26][9].ENA
wren => reg[26][10].ENA
wren => reg[26][11].ENA
wren => reg[26][12].ENA
wren => reg[26][13].ENA
wren => reg[26][14].ENA
wren => reg[26][15].ENA
wren => reg[26][16].ENA
wren => reg[26][17].ENA
wren => reg[26][18].ENA
wren => reg[26][19].ENA
wren => reg[26][20].ENA
wren => reg[26][21].ENA
wren => reg[26][22].ENA
wren => reg[26][23].ENA
wren => reg[26][24].ENA
wren => reg[26][25].ENA
wren => reg[26][26].ENA
wren => reg[26][27].ENA
wren => reg[26][28].ENA
wren => reg[26][29].ENA
wren => reg[26][30].ENA
wren => reg[26][31].ENA
wren => reg[25][0].ENA
wren => reg[25][1].ENA
wren => reg[25][2].ENA
wren => reg[25][3].ENA
wren => reg[25][4].ENA
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wren => reg[4][13].ENA
wren => reg[4][14].ENA
wren => reg[4][15].ENA
wren => reg[4][16].ENA
wren => reg[4][17].ENA
wren => reg[4][18].ENA
wren => reg[4][19].ENA
wren => reg[4][20].ENA
wren => reg[4][21].ENA
wren => reg[4][22].ENA
wren => reg[4][23].ENA
wren => reg[4][24].ENA
wren => reg[4][25].ENA
wren => reg[4][26].ENA
wren => reg[4][27].ENA
wren => reg[4][28].ENA
wren => reg[4][29].ENA
wren => reg[4][30].ENA
wren => reg[4][31].ENA
wren => reg[3][0].ENA
wren => reg[3][1].ENA
wren => reg[3][2].ENA
wren => reg[3][3].ENA
wren => reg[3][4].ENA
wren => reg[3][5].ENA
wren => reg[3][6].ENA
wren => reg[3][7].ENA
wren => reg[3][8].ENA
wren => reg[3][9].ENA
wren => reg[3][10].ENA
wren => reg[3][11].ENA
wren => reg[3][12].ENA
wren => reg[3][13].ENA
wren => reg[3][14].ENA
wren => reg[3][15].ENA
wren => reg[3][16].ENA
wren => reg[3][17].ENA
wren => reg[3][18].ENA
wren => reg[3][19].ENA
wren => reg[3][20].ENA
wren => reg[3][21].ENA
wren => reg[3][22].ENA
wren => reg[3][23].ENA
wren => reg[3][24].ENA
wren => reg[3][25].ENA
wren => reg[3][26].ENA
wren => reg[3][27].ENA
wren => reg[3][28].ENA
wren => reg[3][29].ENA
wren => reg[3][30].ENA
wren => reg[3][31].ENA
wren => reg[2][0].ENA
wren => reg[2][1].ENA
wren => reg[2][2].ENA
wren => reg[2][3].ENA
wren => reg[2][4].ENA
wren => reg[2][5].ENA
wren => reg[2][6].ENA
wren => reg[2][7].ENA
wren => reg[2][8].ENA
wren => reg[2][9].ENA
wren => reg[2][10].ENA
wren => reg[2][11].ENA
wren => reg[2][12].ENA
wren => reg[2][13].ENA
wren => reg[2][14].ENA
wren => reg[2][15].ENA
wren => reg[2][16].ENA
wren => reg[2][17].ENA
wren => reg[2][18].ENA
wren => reg[2][19].ENA
wren => reg[2][20].ENA
wren => reg[2][21].ENA
wren => reg[2][22].ENA
wren => reg[2][23].ENA
wren => reg[2][24].ENA
wren => reg[2][25].ENA
wren => reg[2][26].ENA
wren => reg[2][27].ENA
wren => reg[2][28].ENA
wren => reg[2][29].ENA
wren => reg[2][30].ENA
wren => reg[2][31].ENA
wren => reg[1][0].ENA
wren => reg[1][1].ENA
wren => reg[1][2].ENA
wren => reg[1][3].ENA
wren => reg[1][4].ENA
wren => reg[1][5].ENA
wren => reg[1][6].ENA
wren => reg[1][7].ENA
wren => reg[1][8].ENA
wren => reg[1][9].ENA
wren => reg[1][10].ENA
wren => reg[1][11].ENA
wren => reg[1][12].ENA
wren => reg[1][13].ENA
wren => reg[1][14].ENA
wren => reg[1][15].ENA
wren => reg[1][16].ENA
wren => reg[1][17].ENA
wren => reg[1][18].ENA
wren => reg[1][19].ENA
wren => reg[1][20].ENA
wren => reg[1][21].ENA
wren => reg[1][22].ENA
wren => reg[1][23].ENA
wren => reg[1][24].ENA
wren => reg[1][25].ENA
wren => reg[1][26].ENA
wren => reg[1][27].ENA
wren => reg[1][28].ENA
wren => reg[1][29].ENA
wren => reg[1][30].ENA
wren => reg[1][31].ENA
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[0] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[1] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[2] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[3] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[4] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[5] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[6] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[7] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[8] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[9] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[10] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[11] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[12] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[13] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[14] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[15] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[16] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[17] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[18] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[19] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[20] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[21] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[22] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[23] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[24] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[25] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[26] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[27] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[28] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[29] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[30] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
wrdata[31] => reg.DATAB
a[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE
a[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE
a[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE
a[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE
a[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE
a[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE
a[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE
a[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE
a[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE
a[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE
a[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE
a[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE
a[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE
a[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE
a[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE
a[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE
a[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
a[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
a[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
a[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
a[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
a[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
a[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
a[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
a[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
a[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
a[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
a[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
a[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
a[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
a[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
a[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
b[0] <= Mux63.DB_MAX_OUTPUT_PORT_TYPE
b[1] <= Mux62.DB_MAX_OUTPUT_PORT_TYPE
b[2] <= Mux61.DB_MAX_OUTPUT_PORT_TYPE
b[3] <= Mux60.DB_MAX_OUTPUT_PORT_TYPE
b[4] <= Mux59.DB_MAX_OUTPUT_PORT_TYPE
b[5] <= Mux58.DB_MAX_OUTPUT_PORT_TYPE
b[6] <= Mux57.DB_MAX_OUTPUT_PORT_TYPE
b[7] <= Mux56.DB_MAX_OUTPUT_PORT_TYPE
b[8] <= Mux55.DB_MAX_OUTPUT_PORT_TYPE
b[9] <= Mux54.DB_MAX_OUTPUT_PORT_TYPE
b[10] <= Mux53.DB_MAX_OUTPUT_PORT_TYPE
b[11] <= Mux52.DB_MAX_OUTPUT_PORT_TYPE
b[12] <= Mux51.DB_MAX_OUTPUT_PORT_TYPE
b[13] <= Mux50.DB_MAX_OUTPUT_PORT_TYPE
b[14] <= Mux49.DB_MAX_OUTPUT_PORT_TYPE
b[15] <= Mux48.DB_MAX_OUTPUT_PORT_TYPE
b[16] <= Mux47.DB_MAX_OUTPUT_PORT_TYPE
b[17] <= Mux46.DB_MAX_OUTPUT_PORT_TYPE
b[18] <= Mux45.DB_MAX_OUTPUT_PORT_TYPE
b[19] <= Mux44.DB_MAX_OUTPUT_PORT_TYPE
b[20] <= Mux43.DB_MAX_OUTPUT_PORT_TYPE
b[21] <= Mux42.DB_MAX_OUTPUT_PORT_TYPE
b[22] <= Mux41.DB_MAX_OUTPUT_PORT_TYPE
b[23] <= Mux40.DB_MAX_OUTPUT_PORT_TYPE
b[24] <= Mux39.DB_MAX_OUTPUT_PORT_TYPE
b[25] <= Mux38.DB_MAX_OUTPUT_PORT_TYPE
b[26] <= Mux37.DB_MAX_OUTPUT_PORT_TYPE
b[27] <= Mux36.DB_MAX_OUTPUT_PORT_TYPE
b[28] <= Mux35.DB_MAX_OUTPUT_PORT_TYPE
b[29] <= Mux34.DB_MAX_OUTPUT_PORT_TYPE
b[30] <= Mux33.DB_MAX_OUTPUT_PORT_TYPE
b[31] <= Mux32.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|mux2x5:mux_aw
i0[0] => o.DATAB
i0[1] => o.DATAB
i0[2] => o.DATAB
i0[3] => o.DATAB
i0[4] => o.DATAB
i1[0] => o.DATAA
i1[1] => o.DATAA
i1[2] => o.DATAA
i1[3] => o.DATAA
i1[4] => o.DATAA
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
o[0] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[1] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[2] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[3] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[4] <= o.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|mux2x5:mux_ra
i0[0] => o.DATAB
i0[1] => o.DATAB
i0[2] => o.DATAB
i0[3] => o.DATAB
i0[4] => o.DATAB
i1[0] => o.DATAA
i1[1] => o.DATAA
i1[2] => o.DATAA
i1[3] => o.DATAA
i1[4] => o.DATAA
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
o[0] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[1] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[2] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[3] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[4] <= o.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|mux2x32:mux_data
i0[0] => o.DATAB
i0[1] => o.DATAB
i0[2] => o.DATAB
i0[3] => o.DATAB
i0[4] => o.DATAB
i0[5] => o.DATAB
i0[6] => o.DATAB
i0[7] => o.DATAB
i0[8] => o.DATAB
i0[9] => o.DATAB
i0[10] => o.DATAB
i0[11] => o.DATAB
i0[12] => o.DATAB
i0[13] => o.DATAB
i0[14] => o.DATAB
i0[15] => o.DATAB
i0[16] => o.DATAB
i0[17] => o.DATAB
i0[18] => o.DATAB
i0[19] => o.DATAB
i0[20] => o.DATAB
i0[21] => o.DATAB
i0[22] => o.DATAB
i0[23] => o.DATAB
i0[24] => o.DATAB
i0[25] => o.DATAB
i0[26] => o.DATAB
i0[27] => o.DATAB
i0[28] => o.DATAB
i0[29] => o.DATAB
i0[30] => o.DATAB
i0[31] => o.DATAB
i1[0] => o.DATAA
i1[1] => o.DATAA
i1[2] => o.DATAA
i1[3] => o.DATAA
i1[4] => o.DATAA
i1[5] => o.DATAA
i1[6] => o.DATAA
i1[7] => o.DATAA
i1[8] => o.DATAA
i1[9] => o.DATAA
i1[10] => o.DATAA
i1[11] => o.DATAA
i1[12] => o.DATAA
i1[13] => o.DATAA
i1[14] => o.DATAA
i1[15] => o.DATAA
i1[16] => o.DATAA
i1[17] => o.DATAA
i1[18] => o.DATAA
i1[19] => o.DATAA
i1[20] => o.DATAA
i1[21] => o.DATAA
i1[22] => o.DATAA
i1[23] => o.DATAA
i1[24] => o.DATAA
i1[25] => o.DATAA
i1[26] => o.DATAA
i1[27] => o.DATAA
i1[28] => o.DATAA
i1[29] => o.DATAA
i1[30] => o.DATAA
i1[31] => o.DATAA
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
o[0] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[1] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[2] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[3] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[4] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[5] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[6] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[7] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[8] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[9] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[10] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[11] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[12] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[13] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[14] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[15] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[16] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[17] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[18] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[19] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[20] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[21] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[22] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[23] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[24] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[25] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[26] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[27] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[28] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[29] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[30] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[31] <= o.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|mux2x32:mux_mem
i0[0] => o.DATAB
i0[1] => o.DATAB
i0[2] => o.DATAB
i0[3] => o.DATAB
i0[4] => o.DATAB
i0[5] => o.DATAB
i0[6] => o.DATAB
i0[7] => o.DATAB
i0[8] => o.DATAB
i0[9] => o.DATAB
i0[10] => o.DATAB
i0[11] => o.DATAB
i0[12] => o.DATAB
i0[13] => o.DATAB
i0[14] => o.DATAB
i0[15] => o.DATAB
i0[16] => o.DATAB
i0[17] => o.DATAB
i0[18] => o.DATAB
i0[19] => o.DATAB
i0[20] => o.DATAB
i0[21] => o.DATAB
i0[22] => o.DATAB
i0[23] => o.DATAB
i0[24] => o.DATAB
i0[25] => o.DATAB
i0[26] => o.DATAB
i0[27] => o.DATAB
i0[28] => o.DATAB
i0[29] => o.DATAB
i0[30] => o.DATAB
i0[31] => o.DATAB
i1[0] => o.DATAA
i1[1] => o.DATAA
i1[2] => o.DATAA
i1[3] => o.DATAA
i1[4] => o.DATAA
i1[5] => o.DATAA
i1[6] => o.DATAA
i1[7] => o.DATAA
i1[8] => o.DATAA
i1[9] => o.DATAA
i1[10] => o.DATAA
i1[11] => o.DATAA
i1[12] => o.DATAA
i1[13] => o.DATAA
i1[14] => o.DATAA
i1[15] => o.DATAA
i1[16] => o.DATAA
i1[17] => o.DATAA
i1[18] => o.DATAA
i1[19] => o.DATAA
i1[20] => o.DATAA
i1[21] => o.DATAA
i1[22] => o.DATAA
i1[23] => o.DATAA
i1[24] => o.DATAA
i1[25] => o.DATAA
i1[26] => o.DATAA
i1[27] => o.DATAA
i1[28] => o.DATAA
i1[29] => o.DATAA
i1[30] => o.DATAA
i1[31] => o.DATAA
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
o[0] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[1] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[2] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[3] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[4] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[5] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[6] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[7] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[8] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[9] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[10] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[11] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[12] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[13] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[14] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[15] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[16] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[17] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[18] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[19] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[20] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[21] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[22] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[23] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[24] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[25] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[26] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[27] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[28] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[29] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[30] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[31] <= o.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|mux2x32:mux_b
i0[0] => o.DATAB
i0[1] => o.DATAB
i0[2] => o.DATAB
i0[3] => o.DATAB
i0[4] => o.DATAB
i0[5] => o.DATAB
i0[6] => o.DATAB
i0[7] => o.DATAB
i0[8] => o.DATAB
i0[9] => o.DATAB
i0[10] => o.DATAB
i0[11] => o.DATAB
i0[12] => o.DATAB
i0[13] => o.DATAB
i0[14] => o.DATAB
i0[15] => o.DATAB
i0[16] => o.DATAB
i0[17] => o.DATAB
i0[18] => o.DATAB
i0[19] => o.DATAB
i0[20] => o.DATAB
i0[21] => o.DATAB
i0[22] => o.DATAB
i0[23] => o.DATAB
i0[24] => o.DATAB
i0[25] => o.DATAB
i0[26] => o.DATAB
i0[27] => o.DATAB
i0[28] => o.DATAB
i0[29] => o.DATAB
i0[30] => o.DATAB
i0[31] => o.DATAB
i1[0] => o.DATAA
i1[1] => o.DATAA
i1[2] => o.DATAA
i1[3] => o.DATAA
i1[4] => o.DATAA
i1[5] => o.DATAA
i1[6] => o.DATAA
i1[7] => o.DATAA
i1[8] => o.DATAA
i1[9] => o.DATAA
i1[10] => o.DATAA
i1[11] => o.DATAA
i1[12] => o.DATAA
i1[13] => o.DATAA
i1[14] => o.DATAA
i1[15] => o.DATAA
i1[16] => o.DATAA
i1[17] => o.DATAA
i1[18] => o.DATAA
i1[19] => o.DATAA
i1[20] => o.DATAA
i1[21] => o.DATAA
i1[22] => o.DATAA
i1[23] => o.DATAA
i1[24] => o.DATAA
i1[25] => o.DATAA
i1[26] => o.DATAA
i1[27] => o.DATAA
i1[28] => o.DATAA
i1[29] => o.DATAA
i1[30] => o.DATAA
i1[31] => o.DATAA
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
sel => o.OUTPUTSELECT
o[0] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[1] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[2] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[3] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[4] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[5] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[6] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[7] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[8] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[9] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[10] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[11] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[12] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[13] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[14] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[15] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[16] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[17] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[18] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[19] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[20] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[21] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[22] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[23] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[24] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[25] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[26] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[27] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[28] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[29] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[30] <= o.DB_MAX_OUTPUT_PORT_TYPE
o[31] <= o.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|CPU:inst|extend:extend_0
imm16[0] => imm32[0].DATAIN
imm16[1] => imm32[1].DATAIN
imm16[2] => imm32[2].DATAIN
imm16[3] => imm32[3].DATAIN
imm16[4] => imm32[4].DATAIN
imm16[5] => imm32[5].DATAIN
imm16[6] => imm32[6].DATAIN
imm16[7] => imm32[7].DATAIN
imm16[8] => imm32[8].DATAIN
imm16[9] => imm32[9].DATAIN
imm16[10] => imm32[10].DATAIN
imm16[11] => imm32[11].DATAIN
imm16[12] => imm32[12].DATAIN
imm16[13] => imm32[13].DATAIN
imm16[14] => imm32[14].DATAIN
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32.DATAA
imm16[15] => imm32[15].DATAIN
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
signed => imm32.OUTPUTSELECT
imm32[0] <= imm16[0].DB_MAX_OUTPUT_PORT_TYPE
imm32[1] <= imm16[1].DB_MAX_OUTPUT_PORT_TYPE
imm32[2] <= imm16[2].DB_MAX_OUTPUT_PORT_TYPE
imm32[3] <= imm16[3].DB_MAX_OUTPUT_PORT_TYPE
imm32[4] <= imm16[4].DB_MAX_OUTPUT_PORT_TYPE
imm32[5] <= imm16[5].DB_MAX_OUTPUT_PORT_TYPE
imm32[6] <= imm16[6].DB_MAX_OUTPUT_PORT_TYPE
imm32[7] <= imm16[7].DB_MAX_OUTPUT_PORT_TYPE
imm32[8] <= imm16[8].DB_MAX_OUTPUT_PORT_TYPE
imm32[9] <= imm16[9].DB_MAX_OUTPUT_PORT_TYPE
imm32[10] <= imm16[10].DB_MAX_OUTPUT_PORT_TYPE
imm32[11] <= imm16[11].DB_MAX_OUTPUT_PORT_TYPE
imm32[12] <= imm16[12].DB_MAX_OUTPUT_PORT_TYPE
imm32[13] <= imm16[13].DB_MAX_OUTPUT_PORT_TYPE
imm32[14] <= imm16[14].DB_MAX_OUTPUT_PORT_TYPE
imm32[15] <= imm16[15].DB_MAX_OUTPUT_PORT_TYPE
imm32[16] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[17] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[18] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[19] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[20] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[21] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[22] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[23] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[24] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[25] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[26] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[27] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[28] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[29] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[30] <= imm32.DB_MAX_OUTPUT_PORT_TYPE
imm32[31] <= imm32.DB_MAX_OUTPUT_PORT_TYPE


|GECKO|ROM:ROM_0
clk => ROM_Block:romblock.clock
clk => reg_read.CLK
cs => reg_read.IN0
read => reg_read.IN1
address[0] => ROM_Block:romblock.address[0]
address[1] => ROM_Block:romblock.address[1]
address[2] => ROM_Block:romblock.address[2]
address[3] => ROM_Block:romblock.address[3]
address[4] => ROM_Block:romblock.address[4]
address[5] => ROM_Block:romblock.address[5]
address[6] => ROM_Block:romblock.address[6]
address[7] => ROM_Block:romblock.address[7]
address[8] => ROM_Block:romblock.address[8]
address[9] => ROM_Block:romblock.address[9]
rddata[0] <= rddata[0].DB_MAX_OUTPUT_PORT_TYPE
rddata[1] <= rddata[1].DB_MAX_OUTPUT_PORT_TYPE
rddata[2] <= rddata[2].DB_MAX_OUTPUT_PORT_TYPE
rddata[3] <= rddata[3].DB_MAX_OUTPUT_PORT_TYPE
rddata[4] <= rddata[4].DB_MAX_OUTPUT_PORT_TYPE
rddata[5] <= rddata[5].DB_MAX_OUTPUT_PORT_TYPE
rddata[6] <= rddata[6].DB_MAX_OUTPUT_PORT_TYPE
rddata[7] <= rddata[7].DB_MAX_OUTPUT_PORT_TYPE
rddata[8] <= rddata[8].DB_MAX_OUTPUT_PORT_TYPE
rddata[9] <= rddata[9].DB_MAX_OUTPUT_PORT_TYPE
rddata[10] <= rddata[10].DB_MAX_OUTPUT_PORT_TYPE
rddata[11] <= rddata[11].DB_MAX_OUTPUT_PORT_TYPE
rddata[12] <= rddata[12].DB_MAX_OUTPUT_PORT_TYPE
rddata[13] <= rddata[13].DB_MAX_OUTPUT_PORT_TYPE
rddata[14] <= rddata[14].DB_MAX_OUTPUT_PORT_TYPE
rddata[15] <= rddata[15].DB_MAX_OUTPUT_PORT_TYPE
rddata[16] <= rddata[16].DB_MAX_OUTPUT_PORT_TYPE
rddata[17] <= rddata[17].DB_MAX_OUTPUT_PORT_TYPE
rddata[18] <= rddata[18].DB_MAX_OUTPUT_PORT_TYPE
rddata[19] <= rddata[19].DB_MAX_OUTPUT_PORT_TYPE
rddata[20] <= rddata[20].DB_MAX_OUTPUT_PORT_TYPE
rddata[21] <= rddata[21].DB_MAX_OUTPUT_PORT_TYPE
rddata[22] <= rddata[22].DB_MAX_OUTPUT_PORT_TYPE
rddata[23] <= rddata[23].DB_MAX_OUTPUT_PORT_TYPE
rddata[24] <= rddata[24].DB_MAX_OUTPUT_PORT_TYPE
rddata[25] <= rddata[25].DB_MAX_OUTPUT_PORT_TYPE
rddata[26] <= rddata[26].DB_MAX_OUTPUT_PORT_TYPE
rddata[27] <= rddata[27].DB_MAX_OUTPUT_PORT_TYPE
rddata[28] <= rddata[28].DB_MAX_OUTPUT_PORT_TYPE
rddata[29] <= rddata[29].DB_MAX_OUTPUT_PORT_TYPE
rddata[30] <= rddata[30].DB_MAX_OUTPUT_PORT_TYPE
rddata[31] <= rddata[31].DB_MAX_OUTPUT_PORT_TYPE


|GECKO|ROM:ROM_0|ROM_Block:romblock
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]
q[12] <= altsyncram:altsyncram_component.q_a[12]
q[13] <= altsyncram:altsyncram_component.q_a[13]
q[14] <= altsyncram:altsyncram_component.q_a[14]
q[15] <= altsyncram:altsyncram_component.q_a[15]
q[16] <= altsyncram:altsyncram_component.q_a[16]
q[17] <= altsyncram:altsyncram_component.q_a[17]
q[18] <= altsyncram:altsyncram_component.q_a[18]
q[19] <= altsyncram:altsyncram_component.q_a[19]
q[20] <= altsyncram:altsyncram_component.q_a[20]
q[21] <= altsyncram:altsyncram_component.q_a[21]
q[22] <= altsyncram:altsyncram_component.q_a[22]
q[23] <= altsyncram:altsyncram_component.q_a[23]
q[24] <= altsyncram:altsyncram_component.q_a[24]
q[25] <= altsyncram:altsyncram_component.q_a[25]
q[26] <= altsyncram:altsyncram_component.q_a[26]
q[27] <= altsyncram:altsyncram_component.q_a[27]
q[28] <= altsyncram:altsyncram_component.q_a[28]
q[29] <= altsyncram:altsyncram_component.q_a[29]
q[30] <= altsyncram:altsyncram_component.q_a[30]
q[31] <= altsyncram:altsyncram_component.q_a[31]


|GECKO|ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_a[16] => ~NO_FANOUT~
data_a[17] => ~NO_FANOUT~
data_a[18] => ~NO_FANOUT~
data_a[19] => ~NO_FANOUT~
data_a[20] => ~NO_FANOUT~
data_a[21] => ~NO_FANOUT~
data_a[22] => ~NO_FANOUT~
data_a[23] => ~NO_FANOUT~
data_a[24] => ~NO_FANOUT~
data_a[25] => ~NO_FANOUT~
data_a[26] => ~NO_FANOUT~
data_a[27] => ~NO_FANOUT~
data_a[28] => ~NO_FANOUT~
data_a[29] => ~NO_FANOUT~
data_a[30] => ~NO_FANOUT~
data_a[31] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_rna1:auto_generated.address_a[0]
address_a[1] => altsyncram_rna1:auto_generated.address_a[1]
address_a[2] => altsyncram_rna1:auto_generated.address_a[2]
address_a[3] => altsyncram_rna1:auto_generated.address_a[3]
address_a[4] => altsyncram_rna1:auto_generated.address_a[4]
address_a[5] => altsyncram_rna1:auto_generated.address_a[5]
address_a[6] => altsyncram_rna1:auto_generated.address_a[6]
address_a[7] => altsyncram_rna1:auto_generated.address_a[7]
address_a[8] => altsyncram_rna1:auto_generated.address_a[8]
address_a[9] => altsyncram_rna1:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_rna1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_rna1:auto_generated.q_a[0]
q_a[1] <= altsyncram_rna1:auto_generated.q_a[1]
q_a[2] <= altsyncram_rna1:auto_generated.q_a[2]
q_a[3] <= altsyncram_rna1:auto_generated.q_a[3]
q_a[4] <= altsyncram_rna1:auto_generated.q_a[4]
q_a[5] <= altsyncram_rna1:auto_generated.q_a[5]
q_a[6] <= altsyncram_rna1:auto_generated.q_a[6]
q_a[7] <= altsyncram_rna1:auto_generated.q_a[7]
q_a[8] <= altsyncram_rna1:auto_generated.q_a[8]
q_a[9] <= altsyncram_rna1:auto_generated.q_a[9]
q_a[10] <= altsyncram_rna1:auto_generated.q_a[10]
q_a[11] <= altsyncram_rna1:auto_generated.q_a[11]
q_a[12] <= altsyncram_rna1:auto_generated.q_a[12]
q_a[13] <= altsyncram_rna1:auto_generated.q_a[13]
q_a[14] <= altsyncram_rna1:auto_generated.q_a[14]
q_a[15] <= altsyncram_rna1:auto_generated.q_a[15]
q_a[16] <= altsyncram_rna1:auto_generated.q_a[16]
q_a[17] <= altsyncram_rna1:auto_generated.q_a[17]
q_a[18] <= altsyncram_rna1:auto_generated.q_a[18]
q_a[19] <= altsyncram_rna1:auto_generated.q_a[19]
q_a[20] <= altsyncram_rna1:auto_generated.q_a[20]
q_a[21] <= altsyncram_rna1:auto_generated.q_a[21]
q_a[22] <= altsyncram_rna1:auto_generated.q_a[22]
q_a[23] <= altsyncram_rna1:auto_generated.q_a[23]
q_a[24] <= altsyncram_rna1:auto_generated.q_a[24]
q_a[25] <= altsyncram_rna1:auto_generated.q_a[25]
q_a[26] <= altsyncram_rna1:auto_generated.q_a[26]
q_a[27] <= altsyncram_rna1:auto_generated.q_a[27]
q_a[28] <= altsyncram_rna1:auto_generated.q_a[28]
q_a[29] <= altsyncram_rna1:auto_generated.q_a[29]
q_a[30] <= altsyncram_rna1:auto_generated.q_a[30]
q_a[31] <= altsyncram_rna1:auto_generated.q_a[31]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|GECKO|ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_a[8] => ram_block1a23.PORTAADDR8
address_a[8] => ram_block1a24.PORTAADDR8
address_a[8] => ram_block1a25.PORTAADDR8
address_a[8] => ram_block1a26.PORTAADDR8
address_a[8] => ram_block1a27.PORTAADDR8
address_a[8] => ram_block1a28.PORTAADDR8
address_a[8] => ram_block1a29.PORTAADDR8
address_a[8] => ram_block1a30.PORTAADDR8
address_a[8] => ram_block1a31.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[9] => ram_block1a16.PORTAADDR9
address_a[9] => ram_block1a17.PORTAADDR9
address_a[9] => ram_block1a18.PORTAADDR9
address_a[9] => ram_block1a19.PORTAADDR9
address_a[9] => ram_block1a20.PORTAADDR9
address_a[9] => ram_block1a21.PORTAADDR9
address_a[9] => ram_block1a22.PORTAADDR9
address_a[9] => ram_block1a23.PORTAADDR9
address_a[9] => ram_block1a24.PORTAADDR9
address_a[9] => ram_block1a25.PORTAADDR9
address_a[9] => ram_block1a26.PORTAADDR9
address_a[9] => ram_block1a27.PORTAADDR9
address_a[9] => ram_block1a28.PORTAADDR9
address_a[9] => ram_block1a29.PORTAADDR9
address_a[9] => ram_block1a30.PORTAADDR9
address_a[9] => ram_block1a31.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT
q_a[16] <= ram_block1a16.PORTADATAOUT
q_a[17] <= ram_block1a17.PORTADATAOUT
q_a[18] <= ram_block1a18.PORTADATAOUT
q_a[19] <= ram_block1a19.PORTADATAOUT
q_a[20] <= ram_block1a20.PORTADATAOUT
q_a[21] <= ram_block1a21.PORTADATAOUT
q_a[22] <= ram_block1a22.PORTADATAOUT
q_a[23] <= ram_block1a23.PORTADATAOUT
q_a[24] <= ram_block1a24.PORTADATAOUT
q_a[25] <= ram_block1a25.PORTADATAOUT
q_a[26] <= ram_block1a26.PORTADATAOUT
q_a[27] <= ram_block1a27.PORTADATAOUT
q_a[28] <= ram_block1a28.PORTADATAOUT
q_a[29] <= ram_block1a29.PORTADATAOUT
q_a[30] <= ram_block1a30.PORTADATAOUT
q_a[31] <= ram_block1a31.PORTADATAOUT


|GECKO|RAM:RAM_0
clk => reg~42.CLK
clk => reg~0.CLK
clk => reg~1.CLK
clk => reg~2.CLK
clk => reg~3.CLK
clk => reg~4.CLK
clk => reg~5.CLK
clk => reg~6.CLK
clk => reg~7.CLK
clk => reg~8.CLK
clk => reg~9.CLK
clk => reg~10.CLK
clk => reg~11.CLK
clk => reg~12.CLK
clk => reg~13.CLK
clk => reg~14.CLK
clk => reg~15.CLK
clk => reg~16.CLK
clk => reg~17.CLK
clk => reg~18.CLK
clk => reg~19.CLK
clk => reg~20.CLK
clk => reg~21.CLK
clk => reg~22.CLK
clk => reg~23.CLK
clk => reg~24.CLK
clk => reg~25.CLK
clk => reg~26.CLK
clk => reg~27.CLK
clk => reg~28.CLK
clk => reg~29.CLK
clk => reg~30.CLK
clk => reg~31.CLK
clk => reg~32.CLK
clk => reg~33.CLK
clk => reg~34.CLK
clk => reg~35.CLK
clk => reg~36.CLK
clk => reg~37.CLK
clk => reg~38.CLK
clk => reg~39.CLK
clk => reg~40.CLK
clk => reg~41.CLK
clk => reg_address[0].CLK
clk => reg_address[1].CLK
clk => reg_address[2].CLK
clk => reg_address[3].CLK
clk => reg_address[4].CLK
clk => reg_address[5].CLK
clk => reg_address[6].CLK
clk => reg_address[7].CLK
clk => reg_address[8].CLK
clk => reg_address[9].CLK
clk => reg_read.CLK
clk => reg.CLK0
cs => reg_read.IN0
cs => process_2.IN0
read => reg_read.IN1
write => process_2.IN1
address[0] => reg~9.DATAIN
address[0] => reg_address[0].DATAIN
address[0] => reg.WADDR
address[1] => reg~8.DATAIN
address[1] => reg_address[1].DATAIN
address[1] => reg.WADDR1
address[2] => reg~7.DATAIN
address[2] => reg_address[2].DATAIN
address[2] => reg.WADDR2
address[3] => reg~6.DATAIN
address[3] => reg_address[3].DATAIN
address[3] => reg.WADDR3
address[4] => reg~5.DATAIN
address[4] => reg_address[4].DATAIN
address[4] => reg.WADDR4
address[5] => reg~4.DATAIN
address[5] => reg_address[5].DATAIN
address[5] => reg.WADDR5
address[6] => reg~3.DATAIN
address[6] => reg_address[6].DATAIN
address[6] => reg.WADDR6
address[7] => reg~2.DATAIN
address[7] => reg_address[7].DATAIN
address[7] => reg.WADDR7
address[8] => reg~1.DATAIN
address[8] => reg_address[8].DATAIN
address[8] => reg.WADDR8
address[9] => reg~0.DATAIN
address[9] => reg_address[9].DATAIN
address[9] => reg.WADDR9
wrdata[0] => reg~41.DATAIN
wrdata[0] => reg.DATAIN
wrdata[1] => reg~40.DATAIN
wrdata[1] => reg.DATAIN1
wrdata[2] => reg~39.DATAIN
wrdata[2] => reg.DATAIN2
wrdata[3] => reg~38.DATAIN
wrdata[3] => reg.DATAIN3
wrdata[4] => reg~37.DATAIN
wrdata[4] => reg.DATAIN4
wrdata[5] => reg~36.DATAIN
wrdata[5] => reg.DATAIN5
wrdata[6] => reg~35.DATAIN
wrdata[6] => reg.DATAIN6
wrdata[7] => reg~34.DATAIN
wrdata[7] => reg.DATAIN7
wrdata[8] => reg~33.DATAIN
wrdata[8] => reg.DATAIN8
wrdata[9] => reg~32.DATAIN
wrdata[9] => reg.DATAIN9
wrdata[10] => reg~31.DATAIN
wrdata[10] => reg.DATAIN10
wrdata[11] => reg~30.DATAIN
wrdata[11] => reg.DATAIN11
wrdata[12] => reg~29.DATAIN
wrdata[12] => reg.DATAIN12
wrdata[13] => reg~28.DATAIN
wrdata[13] => reg.DATAIN13
wrdata[14] => reg~27.DATAIN
wrdata[14] => reg.DATAIN14
wrdata[15] => reg~26.DATAIN
wrdata[15] => reg.DATAIN15
wrdata[16] => reg~25.DATAIN
wrdata[16] => reg.DATAIN16
wrdata[17] => reg~24.DATAIN
wrdata[17] => reg.DATAIN17
wrdata[18] => reg~23.DATAIN
wrdata[18] => reg.DATAIN18
wrdata[19] => reg~22.DATAIN
wrdata[19] => reg.DATAIN19
wrdata[20] => reg~21.DATAIN
wrdata[20] => reg.DATAIN20
wrdata[21] => reg~20.DATAIN
wrdata[21] => reg.DATAIN21
wrdata[22] => reg~19.DATAIN
wrdata[22] => reg.DATAIN22
wrdata[23] => reg~18.DATAIN
wrdata[23] => reg.DATAIN23
wrdata[24] => reg~17.DATAIN
wrdata[24] => reg.DATAIN24
wrdata[25] => reg~16.DATAIN
wrdata[25] => reg.DATAIN25
wrdata[26] => reg~15.DATAIN
wrdata[26] => reg.DATAIN26
wrdata[27] => reg~14.DATAIN
wrdata[27] => reg.DATAIN27
wrdata[28] => reg~13.DATAIN
wrdata[28] => reg.DATAIN28
wrdata[29] => reg~12.DATAIN
wrdata[29] => reg.DATAIN29
wrdata[30] => reg~11.DATAIN
wrdata[30] => reg.DATAIN30
wrdata[31] => reg~10.DATAIN
wrdata[31] => reg.DATAIN31
rddata[0] <= rddata[0].DB_MAX_OUTPUT_PORT_TYPE
rddata[1] <= rddata[1].DB_MAX_OUTPUT_PORT_TYPE
rddata[2] <= rddata[2].DB_MAX_OUTPUT_PORT_TYPE
rddata[3] <= rddata[3].DB_MAX_OUTPUT_PORT_TYPE
rddata[4] <= rddata[4].DB_MAX_OUTPUT_PORT_TYPE
rddata[5] <= rddata[5].DB_MAX_OUTPUT_PORT_TYPE
rddata[6] <= rddata[6].DB_MAX_OUTPUT_PORT_TYPE
rddata[7] <= rddata[7].DB_MAX_OUTPUT_PORT_TYPE
rddata[8] <= rddata[8].DB_MAX_OUTPUT_PORT_TYPE
rddata[9] <= rddata[9].DB_MAX_OUTPUT_PORT_TYPE
rddata[10] <= rddata[10].DB_MAX_OUTPUT_PORT_TYPE
rddata[11] <= rddata[11].DB_MAX_OUTPUT_PORT_TYPE
rddata[12] <= rddata[12].DB_MAX_OUTPUT_PORT_TYPE
rddata[13] <= rddata[13].DB_MAX_OUTPUT_PORT_TYPE
rddata[14] <= rddata[14].DB_MAX_OUTPUT_PORT_TYPE
rddata[15] <= rddata[15].DB_MAX_OUTPUT_PORT_TYPE
rddata[16] <= rddata[16].DB_MAX_OUTPUT_PORT_TYPE
rddata[17] <= rddata[17].DB_MAX_OUTPUT_PORT_TYPE
rddata[18] <= rddata[18].DB_MAX_OUTPUT_PORT_TYPE
rddata[19] <= rddata[19].DB_MAX_OUTPUT_PORT_TYPE
rddata[20] <= rddata[20].DB_MAX_OUTPUT_PORT_TYPE
rddata[21] <= rddata[21].DB_MAX_OUTPUT_PORT_TYPE
rddata[22] <= rddata[22].DB_MAX_OUTPUT_PORT_TYPE
rddata[23] <= rddata[23].DB_MAX_OUTPUT_PORT_TYPE
rddata[24] <= rddata[24].DB_MAX_OUTPUT_PORT_TYPE
rddata[25] <= rddata[25].DB_MAX_OUTPUT_PORT_TYPE
rddata[26] <= rddata[26].DB_MAX_OUTPUT_PORT_TYPE
rddata[27] <= rddata[27].DB_MAX_OUTPUT_PORT_TYPE
rddata[28] <= rddata[28].DB_MAX_OUTPUT_PORT_TYPE
rddata[29] <= rddata[29].DB_MAX_OUTPUT_PORT_TYPE
rddata[30] <= rddata[30].DB_MAX_OUTPUT_PORT_TYPE
rddata[31] <= rddata[31].DB_MAX_OUTPUT_PORT_TYPE


|GECKO|buttons:buttons_0
clk => edges[0].CLK
clk => edges[1].CLK
clk => edges[2].CLK
clk => edges[3].CLK
clk => buttons_reg[0].CLK
clk => buttons_reg[1].CLK
clk => buttons_reg[2].CLK
clk => buttons_reg[3].CLK
clk => read_reg.CLK
clk => address_reg.CLK
reset_n => buttons_reg[0].PRESET
reset_n => buttons_reg[1].PRESET
reset_n => buttons_reg[2].PRESET
reset_n => buttons_reg[3].PRESET
reset_n => read_reg.ACLR
reset_n => address_reg.ACLR
reset_n => edges[0].ACLR
reset_n => edges[1].ACLR
reset_n => edges[2].ACLR
reset_n => edges[3].ACLR
cs => read_reg.IN0
cs => process_2.IN0
read => read_reg.IN1
write => process_2.IN1
address => edges.OUTPUTSELECT
address => edges.OUTPUTSELECT
address => edges.OUTPUTSELECT
address => edges.OUTPUTSELECT
address => address_reg.DATAIN
wrdata[0] => ~NO_FANOUT~
wrdata[1] => ~NO_FANOUT~
wrdata[2] => ~NO_FANOUT~
wrdata[3] => ~NO_FANOUT~
wrdata[4] => ~NO_FANOUT~
wrdata[5] => ~NO_FANOUT~
wrdata[6] => ~NO_FANOUT~
wrdata[7] => ~NO_FANOUT~
wrdata[8] => ~NO_FANOUT~
wrdata[9] => ~NO_FANOUT~
wrdata[10] => ~NO_FANOUT~
wrdata[11] => ~NO_FANOUT~
wrdata[12] => ~NO_FANOUT~
wrdata[13] => ~NO_FANOUT~
wrdata[14] => ~NO_FANOUT~
wrdata[15] => ~NO_FANOUT~
wrdata[16] => ~NO_FANOUT~
wrdata[17] => ~NO_FANOUT~
wrdata[18] => ~NO_FANOUT~
wrdata[19] => ~NO_FANOUT~
wrdata[20] => ~NO_FANOUT~
wrdata[21] => ~NO_FANOUT~
wrdata[22] => ~NO_FANOUT~
wrdata[23] => ~NO_FANOUT~
wrdata[24] => ~NO_FANOUT~
wrdata[25] => ~NO_FANOUT~
wrdata[26] => ~NO_FANOUT~
wrdata[27] => ~NO_FANOUT~
wrdata[28] => ~NO_FANOUT~
wrdata[29] => ~NO_FANOUT~
wrdata[30] => ~NO_FANOUT~
wrdata[31] => ~NO_FANOUT~
buttons[0] => rddata.DATAB
buttons[0] => buttons_reg[0].DATAIN
buttons[0] => edges.IN1
buttons[1] => rddata.DATAB
buttons[1] => buttons_reg[1].DATAIN
buttons[1] => edges.IN1
buttons[2] => rddata.DATAB
buttons[2] => buttons_reg[2].DATAIN
buttons[2] => edges.IN1
buttons[3] => rddata.DATAB
buttons[3] => buttons_reg[3].DATAIN
buttons[3] => edges.IN1
rddata[0] <= rddata[0].DB_MAX_OUTPUT_PORT_TYPE
rddata[1] <= rddata[1].DB_MAX_OUTPUT_PORT_TYPE
rddata[2] <= rddata[2].DB_MAX_OUTPUT_PORT_TYPE
rddata[3] <= rddata[3].DB_MAX_OUTPUT_PORT_TYPE
rddata[4] <= rddata[4].DB_MAX_OUTPUT_PORT_TYPE
rddata[5] <= rddata[5].DB_MAX_OUTPUT_PORT_TYPE
rddata[6] <= rddata[6].DB_MAX_OUTPUT_PORT_TYPE
rddata[7] <= rddata[7].DB_MAX_OUTPUT_PORT_TYPE
rddata[8] <= rddata[8].DB_MAX_OUTPUT_PORT_TYPE
rddata[9] <= rddata[9].DB_MAX_OUTPUT_PORT_TYPE
rddata[10] <= rddata[10].DB_MAX_OUTPUT_PORT_TYPE
rddata[11] <= rddata[11].DB_MAX_OUTPUT_PORT_TYPE
rddata[12] <= rddata[12].DB_MAX_OUTPUT_PORT_TYPE
rddata[13] <= rddata[13].DB_MAX_OUTPUT_PORT_TYPE
rddata[14] <= rddata[14].DB_MAX_OUTPUT_PORT_TYPE
rddata[15] <= rddata[15].DB_MAX_OUTPUT_PORT_TYPE
rddata[16] <= rddata[16].DB_MAX_OUTPUT_PORT_TYPE
rddata[17] <= rddata[17].DB_MAX_OUTPUT_PORT_TYPE
rddata[18] <= rddata[18].DB_MAX_OUTPUT_PORT_TYPE
rddata[19] <= rddata[19].DB_MAX_OUTPUT_PORT_TYPE
rddata[20] <= rddata[20].DB_MAX_OUTPUT_PORT_TYPE
rddata[21] <= rddata[21].DB_MAX_OUTPUT_PORT_TYPE
rddata[22] <= rddata[22].DB_MAX_OUTPUT_PORT_TYPE
rddata[23] <= rddata[23].DB_MAX_OUTPUT_PORT_TYPE
rddata[24] <= rddata[24].DB_MAX_OUTPUT_PORT_TYPE
rddata[25] <= rddata[25].DB_MAX_OUTPUT_PORT_TYPE
rddata[26] <= rddata[26].DB_MAX_OUTPUT_PORT_TYPE
rddata[27] <= rddata[27].DB_MAX_OUTPUT_PORT_TYPE
rddata[28] <= rddata[28].DB_MAX_OUTPUT_PORT_TYPE
rddata[29] <= rddata[29].DB_MAX_OUTPUT_PORT_TYPE
rddata[30] <= rddata[30].DB_MAX_OUTPUT_PORT_TYPE
rddata[31] <= rddata[31].DB_MAX_OUTPUT_PORT_TYPE