library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity RAM is
    port(
        clk     : in  std_logic;
        cs      : in  std_logic;
        read    : in  std_logic;
        write   : in  std_logic;
        address : in  std_logic_vector(9 downto 0);
        wrdata  : in  std_logic_vector(31 downto 0);
        rddata  : out std_logic_vector(31 downto 0));
end RAM;

architecture synth of RAM is

    signal reg_read    : std_logic;
    signal reg_address : std_logic_vector(9 downto 0);
	 
	 type reg_type is array(0 to 1023) of std_logic_vector(31 downto 0);
	 signal reg: reg_type := (others => (others => '0'));

begin

    -- registers
    process(clk)
    begin
        if (rising_edge(clk)) then
            reg_read    <= cs and read;
            reg_address <= address;
        end if;
    end process;

    -- read
    process(reg_read, reg_address, reg)
    begin
        rddata <= (others => 'Z');
        if (reg_read = '1') then
				rddata <= reg(to_integer(unsigned(reg_address)));
        end if;
    end process;

    -- write
    process(clk)
    begin
        if (rising_edge(clk)) then
            if (cs = '1' and write = '1') then
					reg(to_integer(unsigned(address))) <= wrdata;
            end if;
        end if;
    end process;


end synth;