library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ROM is
    port(
        clk     : in  std_logic;
        cs      : in  std_logic;
        read    : in  std_logic;
        address : in  std_logic_vector(9 downto 0);
        rddata  : out std_logic_vector(31 downto 0)
    );
end ROM;

architecture synth of ROM is

    signal reg_read    : std_logic;

    signal reg_data    : std_logic_vector(31 downto 0);
	 

	 
	 component ROM_Block
	 port(
		address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		clock		: IN STD_LOGIC  := '1';
		q        : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
	end component;

begin

	-- romblock
	romblock : ROM_Block port map(
		address => address,
		clock   => clk,
		q       => reg_data
	);

    -- registers
   process(clk)
   begin
	if (rising_edge(clk) and cs = '1' and read = '1') then
          rddata <= reg_data;
      end if;
   end process;
	 
end synth;