library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity PC is
    port(
        clk     : in  std_logic;
        reset_n : in  std_logic;
        en      : in  std_logic;
        sel_a   : in  std_logic;
        sel_imm : in  std_logic;
        add_imm : in  std_logic;
        imm     : in  std_logic_vector(15 downto 0);
        a       : in  std_logic_vector(15 downto 0);
        addr    : out std_logic_vector(31 downto 0)
    );
end PC;

architecture synth of PC is
	
	signal s_addr : std_logic_vector(31 downto 0);
	signal n_addr : std_logic_vector(31 downto 0);

begin

 inc_address : process(clk, reset_n, s_addr) is
 begin
 
	if (reset_n = '0') then
		n_addr <= (others => '0');
	elsif (rising_edge(clk)) then
		if (en = '1') then 
			if (add_imm = '1') then
				n_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(s_addr)) + to_integer(signed(imm)),32));
			else
				n_addr <= std_logic_vector(unsigned(s_addr) + 4);
			end if;
			if(sel_imm = '1') then
				n_addr <= (15 downto 0 => '0') & imm(13 downto 0) & "00";
			elsif(sel_a = '1') then
				n_addr <= ((15 downto 0 => '0') & a);
			end if;
		end if;
		n_addr(1 downto 0) <= "00";
	end if;
	
 end process;
 
 s_addr <= n_addr;
 
 addr <= (15 downto 0 => '0') & n_addr(15 downto 0);

end synth;