{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1540375606846 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1540375606862 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GECKO EP4CE30F23C8 " "Selected device EP4CE30F23C8 for design \"GECKO\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1540375606893 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1540375606971 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1540375606971 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1540375607283 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1540375607299 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F23C8 " "Device EP4CE15F23C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1540375607846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F23C8 " "Device EP4CE40F23C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1540375607846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F23C8 " "Device EP4CE55F23C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1540375607846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F23C8 " "Device EP4CE75F23C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1540375607846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F23C8 " "Device EP4CE115F23C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1540375607846 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1540375607846 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5425 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1540375607861 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5427 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1540375607861 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5429 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1540375607861 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5431 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1540375607861 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1540375607861 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1540375607893 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1540375608065 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "16 " "The Timing Analyzer is analyzing 16 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1540375609189 ""}
{ "Info" "ISTA_SDC_FOUND" "GECKO.sdc " "Reading SDC File: 'GECKO.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1540375609189 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk (Rise) clk (Rise) setup and hold " "From clk (Rise) to clk (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1540375609221 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1540375609221 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1540375609221 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1540375609361 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1540375609361 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000          clk " "  20.000          clk" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1540375609361 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1540375609361 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN T1 (CLK3, DIFFCLK_1n)) " "Automatically promoted node clk~input (placed in PIN T1 (CLK3, DIFFCLK_1n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1540375609549 ""}  } { { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 352 -24 144 368 "clk" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5415 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1540375609549 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset_n~input (placed in PIN AB11 (CLK14, DIFFCLK_6n)) " "Automatically promoted node reset_n~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1540375609549 ""}  } { { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 368 -24 144 384 "reset_n" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5416 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1540375609549 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1540375610346 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1540375610346 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1540375610346 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1540375610346 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1540375610361 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1540375610361 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1540375610361 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1540375610377 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1540375610377 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1540375610377 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1540375610377 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_BA\[0\] " "Node \"SDRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_BA\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_BA\[1\] " "Node \"SDRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_BA\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_CKE " "Node \"SDRAM_CKE\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_CKE" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_CLK " "Node \"SDRAM_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_DQM\[0\] " "Node \"SDRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_DQM\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_DQM\[1\] " "Node \"SDRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_DQM\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[0\] " "Node \"SDRAM_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[10\] " "Node \"SDRAM_D\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[11\] " "Node \"SDRAM_D\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[12\] " "Node \"SDRAM_D\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[13\] " "Node \"SDRAM_D\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[14\] " "Node \"SDRAM_D\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[15\] " "Node \"SDRAM_D\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[1\] " "Node \"SDRAM_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[2\] " "Node \"SDRAM_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[3\] " "Node \"SDRAM_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[4\] " "Node \"SDRAM_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[5\] " "Node \"SDRAM_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[6\] " "Node \"SDRAM_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[7\] " "Node \"SDRAM_D\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[8\] " "Node \"SDRAM_D\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[9\] " "Node \"SDRAM_D\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_N_CAS " "Node \"SDRAM_N_CAS\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_N_CAS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_N_CS " "Node \"SDRAM_N_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_N_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_N_RAS " "Node \"SDRAM_N_RAS\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_N_RAS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_N_WE " "Node \"SDRAM_N_WE\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_N_WE" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[0\] " "Node \"SDRAM_addr\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[10\] " "Node \"SDRAM_addr\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[11\] " "Node \"SDRAM_addr\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[12\] " "Node \"SDRAM_addr\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[1\] " "Node \"SDRAM_addr\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[2\] " "Node \"SDRAM_addr\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[3\] " "Node \"SDRAM_addr\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[4\] " "Node \"SDRAM_addr\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[5\] " "Node \"SDRAM_addr\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[6\] " "Node \"SDRAM_addr\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[7\] " "Node \"SDRAM_addr\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[8\] " "Node \"SDRAM_addr\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_addr\[9\] " "Node \"SDRAM_addr\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_addr\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[0\] " "Node \"row9\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[10\] " "Node \"row9\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[11\] " "Node \"row9\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[1\] " "Node \"row9\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[2\] " "Node \"row9\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[3\] " "Node \"row9\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[4\] " "Node \"row9\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[5\] " "Node \"row9\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[6\] " "Node \"row9\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[7\] " "Node \"row9\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[8\] " "Node \"row9\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "row9\[9\] " "Node \"row9\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row9\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540375610643 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1540375610643 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1540375610768 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1540375610783 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1540375612017 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1540375612564 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1540375612596 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1540375617876 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:05 " "Fitter placement operations ending: elapsed time is 00:00:05" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1540375617876 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1540375618783 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "44 X34_Y22 X44_Y32 " "Router estimated peak interconnect usage is 44% of the available device resources in the region that extends from location X34_Y22 to location X44_Y32" {  } { { "loc" "" { Generic "E:/cs208/quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 44% of the available device resources in the region that extends from location X34_Y22 to location X44_Y32"} { { 12 { 0 ""} 34 22 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1540375621751 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1540375621751 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1540375730746 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1540375730746 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1540375730746 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:01:51 " "Fitter routing operations ending: elapsed time is 00:01:51" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1540375730746 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 3.18 " "Total time spent on timing analysis during the Fitter is 3.18 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1540375730996 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1540375731012 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1540375731481 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1540375731481 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1540375732121 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1540375732918 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1540375733481 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "6 Cyclone IV E " "6 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk 3.3-V LVTTL T1 " "Pin clk uses I/O standard 3.3-V LVTTL at T1" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { clk } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 352 -24 144 368 "clk" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 138 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1540375733512 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "reset_n 3.3-V LVTTL AB11 " "Pin reset_n uses I/O standard 3.3-V LVTTL at AB11" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { reset_n } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "reset_n" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 368 -24 144 384 "reset_n" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 139 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1540375733512 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[0\] 3.3-V LVTTL B11 " "Pin in_buttons\[0\] uses I/O standard 3.3-V LVTTL at B11" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[0] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[0\]" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 88 1328 1552 104 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 53 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1540375733512 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[1\] 3.3-V LVTTL A11 " "Pin in_buttons\[1\] uses I/O standard 3.3-V LVTTL at A11" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[1] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[1\]" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 88 1328 1552 104 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 52 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1540375733512 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[3\] 3.3-V LVTTL A12 " "Pin in_buttons\[3\] uses I/O standard 3.3-V LVTTL at A12" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[3] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[3\]" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 88 1328 1552 104 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 50 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1540375733512 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[2\] 3.3-V LVTTL B12 " "Pin in_buttons\[2\] uses I/O standard 3.3-V LVTTL at B12" {  } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[2] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[2\]" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 88 1328 1552 104 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 51 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1540375733512 ""}  } {  } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1540375733512 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/cs208/quartus/GECKO.fit.smsg " "Generated suppressed messages file E:/cs208/quartus/GECKO.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1540375734231 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 60 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 60 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5647 " "Peak virtual memory: 5647 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1540375737074 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 24 12:08:57 2018 " "Processing ended: Wed Oct 24 12:08:57 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1540375737074 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:02:13 " "Elapsed time: 00:02:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1540375737074 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:02:21 " "Total CPU time (on all processors): 00:02:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1540375737074 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1540375737074 ""}