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Disabled external gits

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choelzl
2022-04-07 18:43:21 +02:00
parent 182267a8cb
commit 88cb3426ad
1067 changed files with 102374 additions and 6 deletions
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39
cs208-ca_bonus/vhdl/CPU_wrapper.vhd Executable file
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-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
-- CREATED "Wed Oct 30 17:22:54 2013"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
PORT
(
reset_n : IN STD_LOGIC;
clk : IN STD_LOGIC;
rddata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
write : OUT STD_LOGIC;
read : OUT STD_LOGIC;
address : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
wrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END CPU;
ARCHITECTURE bdf_type OF CPU IS
BEGIN
END bdf_type;

194
cs208-ca_bonus/vhdl/GECKO.vhd Executable file
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-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
-- PROGRAM "Quartus Prime"
-- VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition"
-- CREATED "Tue Oct 03 14:49:59 2017"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY GECKO IS
PORT
(
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
in_buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
row1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
row2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
row3 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
row4 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
row5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
row6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
row7 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
row8 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END GECKO;
ARCHITECTURE bdf_type OF GECKO IS
COMPONENT buttons
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
cs : IN STD_LOGIC;
read : IN STD_LOGIC;
write : IN STD_LOGIC;
address : IN STD_LOGIC;
buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT decoder
PORT(address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
cs_RAM : OUT STD_LOGIC;
cs_ROM : OUT STD_LOGIC;
cs_Buttons : OUT STD_LOGIC;
cs_LEDs : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cpu
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
rddata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
write : OUT STD_LOGIC;
read : OUT STD_LOGIC;
address : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
wrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT leds
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
cs : IN STD_LOGIC;
write : IN STD_LOGIC;
read : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LEDs : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT ram
PORT(clk : IN STD_LOGIC;
cs : IN STD_LOGIC;
write : IN STD_LOGIC;
read : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT rom
PORT(clk : IN STD_LOGIC;
cs : IN STD_LOGIC;
read : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
SIGNAL address : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL cs_Buttons : STD_LOGIC;
SIGNAL cs_LEDs : STD_LOGIC;
SIGNAL cs_RAM : STD_LOGIC;
SIGNAL cs_ROM : STD_LOGIC;
SIGNAL out_LEDs : STD_LOGIC_VECTOR(95 DOWNTO 0);
SIGNAL rddata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wrdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
BEGIN
b2v_buttons_0 : buttons
PORT MAP(clk => clk,
reset_n => reset_n,
cs => cs_Buttons,
read => SYNTHESIZED_WIRE_7,
write => SYNTHESIZED_WIRE_8,
address => address(2),
buttons => in_buttons,
wrdata => wrdata,
rddata => rddata);
b2v_decoder_0 : decoder
PORT MAP(address => address,
cs_RAM => cs_RAM,
cs_ROM => cs_ROM,
cs_Buttons => cs_Buttons,
cs_LEDs => cs_LEDs);
b2v_inst : cpu
PORT MAP(clk => clk,
reset_n => reset_n,
rddata => rddata,
write => SYNTHESIZED_WIRE_8,
read => SYNTHESIZED_WIRE_7,
address => address,
wrdata => wrdata);
b2v_LEDs_0 : leds
PORT MAP(clk => clk,
reset_n => reset_n,
cs => cs_LEDs,
write => SYNTHESIZED_WIRE_8,
read => SYNTHESIZED_WIRE_7,
address => address(3 DOWNTO 2),
wrdata => wrdata,
LEDs => out_LEDs,
rddata => rddata);
b2v_RAM_0 : ram
PORT MAP(clk => clk,
cs => cs_RAM,
write => SYNTHESIZED_WIRE_8,
read => SYNTHESIZED_WIRE_7,
address => address(11 DOWNTO 2),
wrdata => wrdata,
rddata => rddata);
b2v_ROM_0 : rom
PORT MAP(clk => clk,
cs => cs_ROM,
read => SYNTHESIZED_WIRE_7,
address => address(11 DOWNTO 2),
rddata => rddata);
row1(11 DOWNTO 0) <= out_LEDs(11 DOWNTO 0);
row2(11 DOWNTO 0) <= out_LEDs(23 DOWNTO 12);
row3(11 DOWNTO 0) <= out_LEDs(35 DOWNTO 24);
row4(11 DOWNTO 0) <= out_LEDs(47 DOWNTO 36);
row5(11 DOWNTO 0) <= out_LEDs(59 DOWNTO 48);
row6(11 DOWNTO 0) <= out_LEDs(71 DOWNTO 60);
row7(11 DOWNTO 0) <= out_LEDs(83 DOWNTO 72);
row8(11 DOWNTO 0) <= out_LEDs(95 DOWNTO 84);
END bdf_type;

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cs208-ca_bonus/vhdl/LEDs.vhd Executable file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LEDs is
port(
-- bus interface
clk : in std_logic;
reset_n : in std_logic;
cs : in std_logic;
read : in std_logic;
write : in std_logic;
address : in std_logic_vector(1 downto 0);
rddata : out std_logic_vector(31 downto 0);
wrdata : in std_logic_vector(31 downto 0);
-- external output
LEDs : out std_logic_vector(95 downto 0)
);
end LEDs;
architecture synth of LEDs is
constant REG_LED_0_31 : std_logic_vector(1 downto 0) := "00";
constant REG_LED_32_63 : std_logic_vector(1 downto 0) := "01";
constant REG_LED_64_95 : std_logic_vector(1 downto 0) := "10";
constant REG_DUTY_CYCLE : std_logic_vector(1 downto 0) := "11";
signal reg_read : std_logic;
signal reg_address : std_logic_vector(1 downto 0);
signal counter : std_logic_vector(7 downto 0);
signal LEDs_reg : std_logic_vector(95 downto 0);
signal LEDs_FPGA4U : std_logic_vector(95 downto 0);
signal duty_cycle : std_logic_vector(7 downto 0);
begin
LEDs_FPGA4U <= LEDs_reg when counter < duty_cycle else (others => '0');
-- On FPGA4U, LEDs were addressed by column, on GECKO by row and mirrored
-- Therefore, we need to transpose the indices and flip the indeces along x
process(LEDs_FPGA4U)
variable LEDs_before_transpose: std_logic_vector(95 downto 0);
begin
for i in 0 to 95 loop
LEDs_before_transpose(i / 8 + (i mod 8) * 12) := LEDs_FPGA4U(i);
LEDs(i) <= LEDs_before_transpose((i / 12 + 1) * 12 - 1 - (i mod 12));
end loop;
end process;
-- registers
process(clk, reset_n)
begin
if (reset_n = '0') then
reg_read <= '0';
reg_address <= (others => '0');
counter <= (others => '0');
elsif (rising_edge(clk)) then
reg_read <= cs and read;
reg_address <= address;
if address /= REG_DUTY_CYCLE then
counter <= std_logic_vector(unsigned(counter) + 1);
else
counter <= (others => '0');
end if;
end if;
end process;
-- read
process(reg_read, reg_address, LEDs_reg, duty_cycle)
begin
rddata <= (others => 'Z');
if (reg_read = '1') then
rddata <= (others => '0');
case reg_address is
when REG_LED_0_31 =>
rddata <= LEDs_reg(31 downto 0);
when REG_LED_32_63 =>
rddata <= LEDs_reg(63 downto 32);
when REG_LED_64_95 =>
rddata <= LEDs_reg(95 downto 64);
when REG_DUTY_CYCLE =>
rddata(7 downto 0) <= duty_cycle;
when others =>
end case;
end if;
end process;
-- write
process(clk, reset_n)
begin
if (reset_n = '0') then
LEDs_reg <= (others => '0');
duty_cycle <= X"0F";
elsif (rising_edge(clk)) then
if (cs = '1' and write = '1') then
case address is
when REG_LED_0_31 => LEDs_reg(31 downto 0) <= wrdata;
when REG_LED_32_63 => LEDs_reg(63 downto 32) <= wrdata;
when REG_LED_64_95 => LEDs_reg(95 downto 64) <= wrdata;
when REG_DUTY_CYCLE => duty_cycle <= wrdata(7 downto 0);
when others => null;
end case;
end if;
end if;
end process;
end synth;

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cs208-ca_bonus/vhdl/RAM.vhd Executable file
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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity RAM is port( clk : in std_logic; cs : in std_logic; read : in std_logic; write : in std_logic; address : in std_logic_vector(9 downto 0); wrdata : in std_logic_vector(31 downto 0); rddata : out std_logic_vector(31 downto 0)); end RAM; architecture synth of RAM is component iD_s_B88A4C5_7e3415fF_E PORt( id_s_b88665f_7e7082e6_E : IN stD_LoGIC; iD_S_59777b_7ffcE7Ec_E : iN StD_lOgIc; id_s_16sgdbnv7_2c8dh7vjdo_E : In std_loGiC; id_s_c89sdnc7u_sda09scah_E : in std_lOgIc; iD_S_1F2653EB_6eC5B6Be_E : iN sTD_LoGic_vECtoR( 9 DOwnto 0); Id_S_25Bc52e8_112eF888_e : IN stD_logiC_VECtoR(31 DOwnTO 0); ID_S_191530B5_24e2b0bf_e : oUt StD_Logic_vEctoR(31 DOWNTo 0)); END COMPONENT; begin ram_inst: iD_s_B88A4C5_7e3415fF_E port map(id_s_b88665f_7e7082e6_E => clk, iD_S_59777b_7ffcE7Ec_E => cs, id_s_16sgdbnv7_2c8dh7vjdo_E => read, id_s_c89sdnc7u_sda09scah_E => write, iD_S_1F2653EB_6eC5B6Be_E => address, Id_S_25Bc52e8_112eF888_e => wrdata, ID_S_191530B5_24e2b0bf_e => rddata); end synth;

1
cs208-ca_bonus/vhdl/RAM_obfuscated.vhd Executable file
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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ENTiTy ID_S_B88a4C5_7E3415Ff_e is PORt( id_s_b88665f_7e7082e6_E : IN stD_LoGIC; iD_S_59777b_7ffcE7Ec_E : iN StD_lOgIc; id_s_16sgdbnv7_2c8dh7vjdo_E : In std_loGiC; id_s_c89sdnc7u_sda09scah_E : in std_lOgIc; iD_S_1F2653EB_6eC5B6Be_E : iN sTD_LoGic_vECtoR( 9 DOwnto 0); Id_S_25Bc52e8_112eF888_e : IN stD_logiC_VECtoR(31 DOwnTO 0); ID_S_191530B5_24e2b0bf_e : oUt StD_Logic_vEctoR(31 DOWNTo 0)); END ID_S_B88a4C5_7e3415fF_E; ArchitEcTUre ID_s_10643F3B_2fc543eB_E Of iD_s_B88A4C5_7e3415fF_E Is tyPe Id_S_77AfF7E5_27e78A14_E is aRRAY (0 To 1023) oF STd_lOgiC_vECtoR(31 dOWNTO 0); sIgNAL Id_S_B889004_7e48Ff67_e : id_S_77aFf7E5_27e78a14_e; signaL ID_S_cC3eE48_281C1fb9_E : Std_lOGic_vEctoR(9 DOwNTO 0); SignaL Id_S_6f8bcBE_62E8365d_e : sTd_lOgic; bEgIN ProCeSS(ID_s_B88665f_7e7082E6_E) bEgin if (Rising_edge(id_s_b88665F_7e7082e6_E) ) THen ID_S_6F8bcbE_62e8365D_E <= Id_s_59777B_7fFce7ec_E anD id_s_16sgdbnv7_2c8dh7vjdo_E; iD_s_cC3eE48_281c1fB9_E <= Id_s_1F2653eb_6eC5b6bE_E; eND IF; End PROCesS; Process(id_S_b889004_7e48FF67_E, ID_S_6F8bcBE_62E8365d_E, iD_s_CC3ee48_281C1FB9_E) BeGIn ID_S_191530B5_24E2B0Bf_E <= (others => 'Z'); IF (iD_s_6F8bCBE_62e8365D_E = '1') tHEN ID_S_191530B5_24e2B0BF_E <= ID_s_B889004_7e48fF67_E(To_IntegeR(UNsIgNeD(id_S_cC3ee48_281C1fb9_E))); END If; ENd prOceSS; PROcess(Id_S_B88665f_7E7082E6_e) bEgIn if (RiSiNG_edGe(ID_s_B88665F_7e7082E6_E) ) then if (id_s_59777b_7ffcE7EC_E = '1' AND id_s_c89sdnc7u_sda09scah_E = '1') then Id_s_B889004_7e48FF67_E( tO_INtEger(UNSigneD(id_s_1F2653eB_6eC5b6BE_E))) <= id_s_25Bc52E8_112EF888_E; eND IF; ENd If; enD PRoCeSs; EnD Id_s_10643F3B_2fC543eB_e;

1
cs208-ca_bonus/vhdl/ROM.vhd Executable file
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library ieee; use ieee.std_logic_1164.all; entity ROM is port( clk : in std_logic; cs : in std_logic; read : in std_logic; address : in std_logic_vector(9 downto 0); rddata : out std_logic_vector(31 downto 0) ); end ROM; architecture synth of ROM is component iD_S_b88a693_7e3412F0_e is port( iD_S_B88665F_7e7082e6_e : In Std_logiC; Id_S_59777b_7FFCe7eC_E : In sTD_LoGIc; id_s_c89sdnc7u_sda09scah_E : iN STd_lOGic; id_s_daf34r31df1d_0y8wefh80_E : iN STd_Logic_vECtoR(9 DoWNto 0); ID_S_191530b5_24e2B0Bf_E : OuT sTd_LOGIc_vECtoR(31 DowNTo 0)); end component; begin ROM_inst : iD_S_b88a693_7e3412F0_e port map( iD_S_B88665F_7e7082e6_e => clk, Id_S_59777b_7FFCe7eC_E => cs, id_s_c89sdnc7u_sda09scah_E => read, id_s_daf34r31df1d_0y8wefh80_E => address, ID_S_191530b5_24e2B0Bf_E => rddata ); end synth;

0
cs208-ca_bonus/vhdl/ROM_Block.qip Executable file
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169
cs208-ca_bonus/vhdl/ROM_Block.vhd Executable file
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-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ROM_Block.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 177 11/07/2012 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ROM_Block IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END ROM_Block;
ARCHITECTURE SYN OF rom_block IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../quartus/ROM.hex",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 10,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../quartus/ROM.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../quartus/ROM.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Block.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Block.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Block.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Block.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Block_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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cs208-ca_bonus/vhdl/ROM_obfuscated.vhd Executable file
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liBRARy ieee; uSE Ieee.STd_LOgIC_1164.ALL; eNtIty iD_S_b88a693_7e3412F0_e iS pORt( iD_S_B88665F_7e7082e6_e : In Std_logiC; Id_S_59777b_7FFCe7eC_E : In sTD_LoGIc; id_s_c89sdnc7u_sda09scah_E : iN STd_lOGic; id_s_daf34r31df1d_0y8wefh80_E : iN STd_Logic_vECtoR(9 DoWNto 0); ID_S_191530b5_24e2B0Bf_E : OuT sTd_LOGIc_vECtoR(31 DowNTo 0) ); End iD_s_B88A693_7E3412f0_e; ARchITectURe id_s_455b727d_1f58D85f_e of id_s_B88a693_7E3412f0_E Is cOMPonent ROM_Block is pORT( address : In sTd_LOGIC_vEctOR(9 DoWnTO 0); clOCK : In sTD_loGIc; q : oUT sTD_LoGic_VeCTor(31 downTO 0) ); EnD ComponeNT; SigNAL Id_s_515D507a_5d491c3b_E : std_LOGic_veCTOR(31 dOWNTO 0); siGNAl Id_S_294e5c0d_762308e6_E : std_loGIc; BeGIN iD_s_30739CAe_5A20DAf5_E : ROM_Block porT mAp( address => id_s_daf34r31df1d_0y8wefh80_E, CLOck => id_s_b88665F_7e7082e6_E, q => ID_s_515D507A_5d491C3b_E ); PROCESs(id_s_B88665f_7e7082E6_e) beGIN If (risiNg_EDGE(id_S_b88665F_7e7082E6_e)) TheN ID_s_294e5c0D_762308E6_E <= id_s_c89sdnc7u_sda09scah_E and iD_S_59777B_7fFCE7EC_E; eNd iF; ENd pROceSS; PrOCESS(id_S_294e5C0d_762308E6_E, id_S_515d507a_5d491C3b_E) bEgiN Id_S_191530B5_24E2b0Bf_E <= (others => 'Z'); iF ( ID_s_294E5c0D_762308e6_E = '1') THeN ID_S_191530B5_24e2b0BF_E <= iD_s_515D507a_5D491C3b_E; EnD IF; End proceSS; eNd iD_s_455B727D_1f58D85f_e;

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cs208-ca_bonus/vhdl/buttons.vhd Executable file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity buttons is
port(
-- bus interface
clk : in std_logic;
reset_n : in std_logic;
cs : in std_logic;
read : in std_logic;
write : in std_logic;
address : in std_logic;
wrdata : in std_logic_vector(31 downto 0);
buttons : in std_logic_vector(4 downto 0);
-- irq : out std_logic;
rddata : out std_logic_vector(31 downto 0)
);
end buttons;
architecture synth of buttons is
constant REG_DATA : std_logic := '0';
constant REG_EDGE : std_logic := '1';
signal address_reg : std_logic;
signal read_reg : std_logic;
signal buttons_reg : std_logic_vector(4 downto 0);
signal edges : std_logic_vector(4 downto 0);
begin
--irq <= '0' when unsigned(edges) = 0 else '1';
-- address_reg & button_reg
process(clk, reset_n)
begin
if (reset_n = '0') then
address_reg <= '0';
read_reg <= '0';
buttons_reg <= (others => '1');
elsif (rising_edge(clk)) then
address_reg <= address;
read_reg <= read and cs;
buttons_reg <= buttons;
end if;
end process;
-- read
process(read_reg, address_reg, edges, buttons)
begin
rddata <= (others => 'Z');
if (read_reg = '1') then
rddata <= (others => '0');
case address_reg is
when REG_DATA =>
rddata(4 downto 0) <= buttons;
when REG_EDGE =>
rddata(4 downto 0) <= edges;
when others =>
end case;
end if;
end process;
-- edges
process(clk, reset_n)
begin
if (reset_n = '0') then
edges <= (others => '0');
elsif (rising_edge(clk)) then
-- edge detection
edges <= edges or (not buttons and buttons_reg);
-- clear edges
if (cs = '1' and write = '1') then
if (address = REG_EDGE) then
edges <= (others => '0');
end if;
end if;
end if;
end process;
end synth;

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cs208-ca_bonus/vhdl/decoder_wrapper.vhd Executable file
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library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(
address : in std_logic_vector(15 downto 0);
cs_Buttons : out std_logic;
cs_LEDS : out std_logic;
cs_RAM : out std_logic;
cs_ROM : out std_logic
);
end decoder;
architecture synth of decoder is
begin
end synth;

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cs208-ca_bonus/vhdl/randgen.vhd Executable file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity randgen is
port(address : in std_logic_vector(15 downto 0);
read : in std_logic;
rddata : out std_logic_vector(31 downto 0);
clk : in std_logic;
reset_n : in std_logic);
end entity randgen;
architecture rtl of randgen is
constant addr_map : std_logic_vector(15 downto 0) := x"2010";
signal rand_q : std_logic_vector(31 downto 0);
signal rand_next : std_logic_vector(31 downto 0);
signal cs : std_logic;
begin
reg:process(clk, reset_n) is
begin
if(reset_n = '0') then
rand_q <= (others => '0');
elsif(rising_edge(clk)) then
rand_q <= rand_next;
end if;
end process reg;
lfsr:process(rand_q) is
begin
if rand_q = x"00000000" then
rand_next <= x"55555555";
else
rand_next <= rand_q(30 downto 0) & rand_q(31);
rand_next(2) <= rand_q(1) xor rand_q(31);
rand_next(6) <= rand_q(5) xor rand_q(31);
rand_next(7) <= rand_q(6) xor rand_q(31);
end if;
end process lfsr;
chipsel:process(clk, reset_n) is
--One cycle latency.
begin
if(reset_n = '0') then
cs <= '0';
elsif(rising_edge(clk)) then
if(address = addr_map and read = '1') then
cs <= '1';
else
cs <= '0';
end if;
end if;
end process chipsel;
rddata <= rand_q when cs = '1' else (others => 'Z');
end architecture rtl;

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cs208-ca_bonus/vhdl/seven_seg.vhd Executable file
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library ieee;
use ieee.std_logic_1164.all;
entity seven_seg is
port(address : in std_logic_vector(15 downto 0);
wrdata : in std_logic_vector(7 downto 0);
clk : in std_logic;
reset_n : in std_logic;
seg_out : out std_logic_vector(31 downto 0));
end entity seven_seg;
architecture rtl of seven_seg is
type addr_t is array(3 downto 0) of std_logic_vector(15 downto 0);
type reg_t is array(3 downto 0) of std_logic_vector(7 downto 0);
constant addr_map : addr_t := (x"1198", x"119C", x"11A0", x"11A4");
signal reg : reg_t;
begin
digits:for i in 3 downto 0 generate
beh:process(clk, reset_n) is
begin
if(reset_n = '0') then
reg(i) <= (others => '0');
elsif(rising_edge(clk)) then
if(address = addr_map(i)) then
reg(i) <= wrdata;
end if;
end if;
end process beh;
seg_out(8 * (i + 1) - 1 downto 8 * i) <= reg(i);
end generate;
end architecture rtl;