Disabled external gits

cs208-ca/vhdl/add_sub.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity add_sub is
+    port(
+        a        : in  std_logic_vector(31 downto 0);
+        b        : in  std_logic_vector(31 downto 0);
+        sub_mode : in  std_logic;
+        carry    : out std_logic;
+        zero     : out std_logic;
+        r        : out std_logic_vector(31 downto 0)
+    );
+end add_sub;
+
+architecture synth of add_sub is
+
+	signal bsub   : std_logic_vector(31 downto 0);
+	signal temp   : unsigned(32 downto 0);
+	signal addout : std_logic_vector(32 downto 0);
+	signal tempr  : std_logic_vector(31 downto 0);
+	signal subvec : std_logic_vector(31 downto 0);
+
+begin
+	subvec <= ((31 downto 1 => '0') & sub_mode);
+	bsub   <= b xor (31 downto 0 => sub_mode);
+	temp   <= unsigned('0' & a) + unsigned('0' & bsub)+ unsigned('0' & subvec);
+	addout <= std_logic_vector(temp);
+	tempr  <= addout(31 downto 0);
+	
+	carry  <= addout(32);
+	zero   <= '1' when unsigned(tempr) = 0 else '0';
+	r      <= tempr;
+	
+end synth;