Disabled external gits
This commit is contained in:
177
cs208-ca/testbench/check_functions.vhd
Executable file
177
cs208-ca/testbench/check_functions.vhd
Executable file
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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package check_functions is
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function scheck(
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original : in std_logic_vector;
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comp : in std_logic_vector;
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name, filename : in string;
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counter : in integer;
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currenttime : in time;
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message : in string) return boolean;
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function icheck(
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original : in integer;
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comp : in integer;
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name, filename : in string;
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counter : in integer;
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currenttime : in time;
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message : in string) return boolean;
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function hcheck(
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original : in std_logic_vector;
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comp : in std_logic_vector;
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name, filename : in string;
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counter : in integer;
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currenttime : in time;
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message : in string) return boolean;
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function bcheck(
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original : in std_logic;
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comp : in std_logic;
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name, filename : in string;
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counter : in integer;
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currenttime : in time;
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message : in string) return boolean;
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end check_functions;
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package body check_functions is
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function scheck(
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original : in std_logic_vector;
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comp : in std_logic_vector;
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name, filename : in string;
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counter : in integer;
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currenttime : in time;
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message : in string) return boolean is
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variable line_output : line;
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file text_report : text is out filename;
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begin
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if (original /= comp) then
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assert false
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report "Unexpected output value for " & name
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severity error;
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line_output := new string'("Time: ");
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write(line_output, currenttime);
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write(line_output, string'(" Input File Line: "));
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write(line_output, counter);
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writeline(text_report, line_output);
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write(line_output, string'("* Error: " & name & " = '"));
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write(line_output, original);
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write(line_output, string'("' instead of '"));
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write(line_output, comp);
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write(line_output, string'("'."));
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writeline(text_report, line_output);
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write(line_output, message);
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writeline(text_report, line_output);
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writeline(text_report, line_output);
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return false;
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else
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return true;
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end if;
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end scheck;
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function icheck(
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original : in integer;
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comp : in integer;
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name, filename : in string;
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counter : in integer;
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currenttime : in time;
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message : in string) return boolean is
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variable line_output : line;
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file text_report : text is out filename;
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begin
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if (original /= comp) then
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assert false
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report "Unexpected output value for " & name
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severity error;
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line_output := new string'("Time: ");
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write(line_output, currenttime);
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write(line_output, string'(" Input File Line: "));
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write(line_output, counter);
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writeline(text_report, line_output);
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write(line_output, string'("* Error: " & name & " = "));
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write(line_output, original);
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write(line_output, string'(" instead of "));
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write(line_output, comp);
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write(line_output, string'("."));
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writeline(text_report, line_output);
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write(line_output, message);
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writeline(text_report, line_output);
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writeline(text_report, line_output);
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return false;
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else
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return true;
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end if;
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end icheck;
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function hcheck(
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original : in std_logic_vector;
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comp : in std_logic_vector;
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name, filename : in string;
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counter : in integer;
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currenttime : in time;
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message : in string) return boolean is
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variable line_output : line;
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file text_report : text is out filename;
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begin
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if (original /= comp) then
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assert false
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report "Unexpected output value for " & name
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severity error;
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line_output := new string'("Time: ");
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write(line_output, currenttime);
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write(line_output, string'(" Input File Line: "));
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write(line_output, counter);
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writeline(text_report, line_output);
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write(line_output, string'("* Error: " & name & " = 0x"));
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hwrite(line_output, original);
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write(line_output, string'(" instead of 0x"));
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hwrite(line_output, comp);
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write(line_output, string'("."));
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writeline(text_report, line_output);
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write(line_output, message);
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writeline(text_report, line_output);
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writeline(text_report, line_output);
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return false;
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else
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return true;
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end if;
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end hcheck;
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function bcheck(
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original : in std_logic;
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comp : in std_logic;
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name, filename : in string;
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counter : in integer;
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currenttime : in time;
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message : in string) return boolean is
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variable line_output : line;
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file text_report : text is out filename;
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begin
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if (original /= comp) then
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assert false
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report "Unexpected output value for " & name
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severity error;
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line_output := new string'("Time: ");
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write(line_output, currenttime);
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write(line_output, string'(" Input File Line: "));
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write(line_output, counter);
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writeline(text_report, line_output);
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write(line_output, string'("* Error: " & name & " = '"));
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write(line_output, original);
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write(line_output, string'("' instead of '"));
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write(line_output, comp);
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write(line_output, string'("'."));
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writeline(text_report, line_output);
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write(line_output, message);
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writeline(text_report, line_output);
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writeline(text_report, line_output);
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return false;
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else
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return true;
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end if;
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end bcheck;
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end check_functions;
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431
cs208-ca/testbench/tb_Controller.vhd
Executable file
431
cs208-ca/testbench/tb_Controller.vhd
Executable file
@@ -0,0 +1,431 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.check_functions.all;
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entity tb_Controller is
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generic(
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text_in : string := "Controller/in.txt"
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);
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end;
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architecture testbench of tb_Controller is
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signal finished : boolean := false;
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signal currenttime : time := 0 ns;
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constant FETCH1 : integer := 0;
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constant FETCH2 : integer := 1;
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constant DECODE : integer := 2;
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constant R_OP : integer := 3;
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constant RI_OP : integer := 4;
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constant I_OP : integer := 5;
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constant UI_OP : integer := 6;
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constant LOAD1 : integer := 7;
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constant LOAD2 : integer := 8;
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constant STORE : integer := 9;
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constant BRANCH : integer := 10;
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constant CALL : integer := 11;
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constant CALLR : integer := 12;
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constant JMP : integer := 13;
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constant BREAK : integer := 14;
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constant JMPI : integer := 15;
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constant HI_OP : integer := 16;
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signal state : integer := FETCH1;
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signal pc_counter : integer := 0;
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component controller is
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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op : in std_logic_vector(5 downto 0);
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opx : in std_logic_vector(5 downto 0);
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branch_op : out std_logic;
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imm_signed : out std_logic;
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ir_en : out std_logic;
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pc_add_imm : out std_logic;
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pc_en : out std_logic;
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pc_sel_a : out std_logic;
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pc_sel_imm : out std_logic;
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rf_wren : out std_logic;
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sel_addr : out std_logic;
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sel_b : out std_logic;
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sel_mem : out std_logic;
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sel_pc : out std_logic;
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sel_ra : out std_logic;
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sel_rC : out std_logic;
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read : out std_logic;
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write : out std_logic;
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op_alu : out std_logic_vector(5 downto 0)
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);
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end component;
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constant CLK_PERIOD : time := 5 ns;
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signal clk : std_logic := '0';
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signal reset_n : std_logic := '0';
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signal op : std_logic_vector(5 downto 0);
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signal opx : std_logic_vector(5 downto 0);
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signal branch_op : std_logic;
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signal imm_signed : std_logic;
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signal ir_en : std_logic;
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signal pc_add_imm : std_logic;
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signal pc_en : std_logic;
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signal pc_sel_a : std_logic;
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signal pc_sel_imm : std_logic;
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signal rf_wren : std_logic;
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signal sel_addr : std_logic;
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signal sel_b : std_logic;
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signal sel_mem : std_logic;
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signal sel_pc : std_logic;
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signal sel_ra : std_logic;
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signal sel_rC : std_logic;
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signal reads : std_logic;
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signal write : std_logic;
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signal op_alu : std_logic_vector(5 downto 0);
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signal reg_read : std_logic;
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signal sel_addr_reg : std_logic;
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function to_integer(x : std_logic) return integer is
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begin
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if x = '0' then
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return 0;
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else
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return 1;
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end if;
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end function to_integer;
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begin
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controller_0 : controller port map(
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clk => clk,
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reset_n => reset_n,
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op => op,
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opx => opx,
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branch_op => branch_op,
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imm_signed => imm_signed,
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ir_en => ir_en,
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pc_add_imm => pc_add_imm,
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pc_en => pc_en,
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pc_sel_a => pc_sel_a,
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pc_sel_imm => pc_sel_imm,
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rf_wren => rf_wren,
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sel_addr => sel_addr,
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sel_b => sel_b,
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sel_mem => sel_mem,
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sel_pc => sel_pc,
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sel_ra => sel_ra,
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sel_rC => sel_rC,
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read => reads,
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write => write,
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op_alu => op_alu
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);
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check : process
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constant filename : string := "Controller/report.txt";
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file text_report : text is out filename;
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file text_input : text is in text_in;
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variable line_output : line;
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variable line_input : line;
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variable counter : integer := 0;
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variable timeout : integer := 0;
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variable success : boolean := true;
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variable op_alu_mask : std_logic_vector(5 downto 0);
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variable op_alu_cmp : std_logic_vector(5 downto 0);
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variable INT : integer;
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variable SINGLE_BIT : std_logic;
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variable NIBBLE : std_logic_vector(7 downto 0);
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begin
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line_input := new string'("");
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if (endfile(text_input)) then
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finished <= true;
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line_output := new string'("===================================================================");
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writeline(output, line_output);
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if (success) then
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line_output := new string'("Simulation is successful");
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else
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line_output := new string'("Errors encountered during simulation. Refer to the report.txt file.");
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end if;
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writeline(output, line_output);
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line_output := new string'("===================================================================");
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writeline(output, line_output);
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wait;
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end if;
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counter := counter + 1;
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readline(text_input, line_input);
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if (line_input'length /= 0) then
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if (line_input(1) = '-') then -- Print message
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line_output := line_input;
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writeline(output, line_input);
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elsif (line_input(1) /= '#') then
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wait until clk = '1';
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read(line_input, SINGLE_BIT);
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reset_n <= SINGLE_BIT;
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hread(line_input, NIBBLE);
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op <= NIBBLE(5 downto 0);
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hread(line_input, NIBBLE);
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opx <= NIBBLE(5 downto 0);
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read(line_input, INT);
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state <= INT;
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read(line_input, op_alu_mask);
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read(line_input, op_alu_cmp);
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wait until clk = '0';
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-- op_alu
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if (unsigned(op_alu_mask) /= 0) then
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success := scheck(op_alu and op_alu_mask, op_alu_cmp and op_alu_mask, "op_alu", filename, counter, currenttime, " Verify the op_alu generation.") and success;
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end if;
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-- valid instruction when ir_en
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if (sel_addr_reg = '1') then
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success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " The IR has been enabled too soon.") and success;
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end if;
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-- unconditional branch
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if (state = BRANCH and unsigned(op) = 6) then
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if (pc_en = '0') then
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success := bcheck(branch_op, '1', "branch_op", filename, counter, currenttime, " During BRANCH, branch_op has to be 1.") and success;
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if (op_alu /= "011001" and (op_alu /= "011100" and op_alu /= "011101")) then
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assert false
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report "br: Make sure that with the given op_alu value, the ALU will always return 1."
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severity WARNING;
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end if;
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end if;
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end if;
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case state is
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when FETCH1 =>
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During FETCH, write has to be 0.") and success;
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success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During FETCH, rf_wren has to be 0.") and success;
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success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During FETCH, branch_op has to be 0.") and success;
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if (pc_en = '1') then
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success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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success := bcheck(pc_sel_a, '0', "pc_sel_a", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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success := bcheck(pc_sel_imm, '0', "pc_sel_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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end if;
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when FETCH2 =>
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timeout := 0;
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loop
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During FETCH, write has to be 0.") and success;
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success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During FETCH, rf_wren has to be 0.") and success;
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success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During FETCH, branch_op has to be 0.") and success;
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if (pc_en = '1') then
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success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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success := bcheck(pc_sel_a, '0', "pc_sel_a", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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success := bcheck(pc_sel_imm, '0', "pc_sel_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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end if;
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if (ir_en = '0') then
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if (timeout = 10) then
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finished <= true;
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line_output := new string'("===================================================================");
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writeline(output, line_output);
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line_output := new string'("IR has not been activated... Simulation aborted.");
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writeline(output, line_output);
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line_output := new string'("===================================================================");
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writeline(output, line_output);
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wait;
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end if;
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else
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success := bcheck(reg_read, '1', "read", filename, counter, currenttime, " Before activating ir_en, read has to be activated.") and success;
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exit;
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end if;
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wait until clk = '0';
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timeout := timeout + 1;
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end loop;
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when DECODE =>
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success := icheck((pc_counter + to_integer(pc_en)), 1, "PC enable count", filename, counter, currenttime, " Before the Execute states, the PC must be enabled only once.") and success;
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During DECODE, write has to be 0.") and success;
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success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During DECODE, rf_wren has to be 0.") and success;
|
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success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During FETCH, branch_op has to be 0.") and success;
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if (pc_en = '1') then
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success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
|
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success := bcheck(pc_sel_a, '0', "pc_sel_a", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
|
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success := bcheck(pc_sel_imm, '0', "pc_sel_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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end if;
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when R_OP =>
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During R_OP, write has to be 0.") and success;
|
||||
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During R_OP, pc_en has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During R_OP, ir_en has to be 0.") and success;
|
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success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During R_OP, branch_op has to be 0.") and success;
|
||||
success := bcheck(sel_mem, '0', "sel_mem", filename, counter, currenttime, " During R_OP, sel_mem has to be 0.") and success;
|
||||
success := bcheck(sel_pc, '0', "sel_pc", filename, counter, currenttime, " During R_OP, sel_pc has to be 0.") and success;
|
||||
success := bcheck(sel_ra, '0', "sel_ra", filename, counter, currenttime, " During R_OP, sel_ra has to be 0.") and success;
|
||||
|
||||
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During R_OP, rf_wren has to be 1.") and success;
|
||||
success := bcheck(sel_rC, '1', "sel_rC", filename, counter, currenttime, " During R_OP, sel_rC has to be 1.") and success;
|
||||
success := bcheck(sel_b, '1', "sel_b", filename, counter, currenttime, " During R_OP, sel_b has to be 1.") and success;
|
||||
when RI_OP =>
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During RI_OP, write has to be 0.") and success;
|
||||
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During RI_OP, pc_en has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During RI_OP, ir_en has to be 0.") and success;
|
||||
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During RI_OP, branch_op has to be 0.") and success;
|
||||
success := bcheck(sel_mem, '0', "sel_mem", filename, counter, currenttime, " During RI_OP, sel_mem has to be 0.") and success;
|
||||
success := bcheck(sel_pc, '0', "sel_pc", filename, counter, currenttime, " During RI_OP, sel_pc has to be 0.") and success;
|
||||
success := bcheck(sel_b, '0', "sel_b", filename, counter, currenttime, " During RI_OP, sel_b has to be 0.") and success;
|
||||
success := bcheck(sel_ra, '0', "sel_ra", filename, counter, currenttime, " During RI_OP, sel_ra has to be 0.") and success;
|
||||
|
||||
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During RI_OP, rf_wren has to be 1.") and success;
|
||||
success := bcheck(sel_rC, '1', "sel_rC", filename, counter, currenttime, " During RI_OP, sel_rC has to be 1.") and success;
|
||||
when I_OP =>
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During I_OP, write has to be 0.") and success;
|
||||
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During I_OP, pc_en has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During I_OP, ir_en has to be 0.") and success;
|
||||
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During I_OP, branch_op has to be 0.") and success;
|
||||
success := bcheck(sel_mem, '0', "sel_mem", filename, counter, currenttime, " During I_OP, sel_mem has to be 0.") and success;
|
||||
success := bcheck(sel_pc, '0', "sel_pc", filename, counter, currenttime, " During I_OP, sel_pc has to be 0.") and success;
|
||||
success := bcheck(sel_b, '0', "sel_b", filename, counter, currenttime, " During I_OP, sel_b has to be 0.") and success;
|
||||
success := bcheck(sel_ra, '0', "sel_ra", filename, counter, currenttime, " During I_OP, sel_ra has to be 0.") and success;
|
||||
success := bcheck(sel_rC, '0', "sel_rC", filename, counter, currenttime, " During I_OP, sel_rC has to be 0.") and success;
|
||||
success := bcheck(imm_signed, '1', "imm_signed", filename, counter, currenttime, " During UI_OP, imm_signed has to be 1.") and success;
|
||||
|
||||
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During I_OP, rf_wren has to be 1.") and success;
|
||||
when UI_OP =>
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During UI_OP, write has to be 0.") and success;
|
||||
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During UI_OP, pc_en has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During UI_OP, ir_en has to be 0.") and success;
|
||||
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During UI_OP, branch_op has to be 0.") and success;
|
||||
success := bcheck(sel_mem, '0', "sel_mem", filename, counter, currenttime, " During UI_OP, sel_mem has to be 0.") and success;
|
||||
success := bcheck(sel_pc, '0', "sel_pc", filename, counter, currenttime, " During UI_OP, sel_pc has to be 0.") and success;
|
||||
success := bcheck(sel_b, '0', "sel_b", filename, counter, currenttime, " During UI_OP, sel_b has to be 0.") and success;
|
||||
success := bcheck(sel_ra, '0', "sel_ra", filename, counter, currenttime, " During UI_OP, sel_ra has to be 0.") and success;
|
||||
success := bcheck(sel_rC, '0', "sel_rC", filename, counter, currenttime, " During UI_OP, sel_rC has to be 0.") and success;
|
||||
success := bcheck(imm_signed, '0', "imm_signed", filename, counter, currenttime, " During UI_OP, imm_signed has to be 0.") and success;
|
||||
|
||||
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During UI_OP, rf_wren has to be 1.") and success;
|
||||
when LOAD1 =>
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During LOAD1, write has to be 0.") and success;
|
||||
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During LOAD1, pc_en has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During LOAD1, ir_en has to be 0.") and success;
|
||||
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During LOAD1, branch_op has to be 0.") and success;
|
||||
success := bcheck(sel_b, '0', "sel_b", filename, counter, currenttime, " During LOAD1, sel_b has to be 0.") and success;
|
||||
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During LOAD1, rf_wren has to be 0.") and success;
|
||||
|
||||
success := bcheck(reads, '1', "read", filename, counter, currenttime, " During LOAD1, read has to be 1.") and success;
|
||||
success := bcheck(sel_addr, '1', "sel_addr", filename, counter, currenttime, " During LOAD1, sel_addr has to be 1.") and success;
|
||||
success := bcheck(imm_signed, '1', "imm_signed", filename, counter, currenttime, " During LOAD1, imm_signed has to be 1.") and success;
|
||||
when LOAD2 =>
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During LOAD2, write has to be 0.") and success;
|
||||
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During LOAD2, pc_en has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During LOAD2, ir_en has to be 0.") and success;
|
||||
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During LOAD2, branch_op has to be 0.") and success;
|
||||
success := bcheck(sel_pc, '0', "sel_pc", filename, counter, currenttime, " During LOAD2, sel_pc has to be 0.") and success;
|
||||
success := bcheck(sel_ra, '0', "sel_ra", filename, counter, currenttime, " During LOAD2, sel_ra has to be 0.") and success;
|
||||
success := bcheck(sel_rC, '0', "sel_rC", filename, counter, currenttime, " During LOAD2, sel_rC has to be 0.") and success;
|
||||
|
||||
success := bcheck(sel_mem, '1', "sel_mem", filename, counter, currenttime, " During LOAD2, sel_mem has to be 1.") and success;
|
||||
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During LOAD2, rf_wren has to be 1.") and success;
|
||||
when STORE =>
|
||||
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During STORE, pc_en has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During STORE, ir_en has to be 0.") and success;
|
||||
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During STORE, branch_op has to be 0.") and success;
|
||||
success := bcheck(sel_b, '0', "sel_b", filename, counter, currenttime, " During STORE, sel_b has to be 0.") and success;
|
||||
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During STORE, rf_wren has to be 0.") and success;
|
||||
|
||||
success := bcheck(sel_addr, '1', "sel_addr", filename, counter, currenttime, " During STORE, sel_addr has to be 1.") and success;
|
||||
success := bcheck(imm_signed, '1', "imm_signed", filename, counter, currenttime, " During STORE, imm_signed has to be 1.") and success;
|
||||
success := bcheck(write, '1', "write", filename, counter, currenttime, " During STORE, write has to be 1.") and success;
|
||||
when BRANCH =>
|
||||
if (unsigned(op) /= 6) then
|
||||
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During BRANCH, pc_en has to be 0.") and success;
|
||||
success := bcheck(branch_op, '1', "branch_op", filename, counter, currenttime, " During BRANCH, branch_op has to be 1.") and success;
|
||||
end if;
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During BRANCH, write has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During BRANCH, ir_en has to be 0.") and success;
|
||||
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During BRANCH, rf_wren has to be 0.") and success;
|
||||
|
||||
success := bcheck(branch_op, '1', "branch_op", filename, counter, currenttime, " During BRANCH, branch_op has to be 1.") and success;
|
||||
--success := bcheck(imm_signed, '1', "imm_signed", filename, counter, currenttime, " During BRANCH, imm_signed has to be 1.") and success;
|
||||
success := bcheck(sel_b, '1', "sel_b", filename, counter, currenttime, " During BRANCH, sel_b has to be 1.") and success;
|
||||
success := bcheck(pc_add_imm, '1', "pc_add_imm", filename, counter, currenttime, " During BRANCH, pc_add_imm has to be 1.") and success;
|
||||
when CALL =>
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During CALL, write has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During CALL, ir_en has to be 0.") and success;
|
||||
success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " During CALL, pc_add_imm has to be 0.") and success;
|
||||
success := bcheck(pc_sel_a, '0', "pc_sel_a", filename, counter, currenttime, " During CALL, pc_sel_a has to be 0.") and success;
|
||||
success := bcheck(sel_rC, '0', "sel_rC", filename, counter, currenttime, " During CALL, sel_rC has to be 0.") and success;
|
||||
|
||||
success := bcheck(pc_sel_imm, '1', "pc_sel_imm", filename, counter, currenttime, " During CALL, pc_sel_imm has to be 1.") and success;
|
||||
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During CALL, rf_wren has to be 1.") and success;
|
||||
success := bcheck(pc_en, '1', "pc_en", filename, counter, currenttime, " During CALL, pc_en has to be 1.") and success;
|
||||
success := bcheck(sel_pc, '1', "sel_pc", filename, counter, currenttime, " During CALL, sel_pc has to be 1.") and success;
|
||||
success := bcheck(sel_ra, '1', "sel_ra", filename, counter, currenttime, " During CALL, sel_ra has to be 1.") and success;
|
||||
when CALLR =>
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During CALLR, write has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During CALLR, ir_en has to be 0.") and success;
|
||||
success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " During CALLR, pc_add_imm has to be 0.") and success;
|
||||
success := bcheck(pc_sel_imm, '0', "pc_sel_imm", filename, counter, currenttime, " During CALLR, pc_sel_imm has to be 0.") and success;
|
||||
|
||||
success := bcheck(pc_sel_a, '1', "pc_sel_a", filename, counter, currenttime, " During CALLR, pc_sel_a has to be 1.") and success;
|
||||
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During CALLR, rf_wren has to be 1.") and success;
|
||||
success := bcheck(pc_en, '1', "pc_en", filename, counter, currenttime, " During CALLR, pc_en has to be 1.") and success;
|
||||
success := bcheck(sel_pc, '1', "sel_pc", filename, counter, currenttime, " During CALLR, sel_pc has to be 1.") and success;
|
||||
success := bcheck(sel_rC or sel_ra, '1', "sel_rC", filename, counter, currenttime, " During CALLR, sel_rC or sel_ra has to be 1.") and success;
|
||||
when JMP =>
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During JMP, write has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During JMP, ir_en has to be 0.") and success;
|
||||
success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " During JMP, pc_add_imm has to be 0.") and success;
|
||||
success := bcheck(pc_sel_imm, '0', "pc_sel_imm", filename, counter, currenttime, " During JMP, pc_sel_imm has to be 0.") and success;
|
||||
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During JMP, rf_wren has to be 0.") and success;
|
||||
|
||||
success := bcheck(pc_sel_a, '1', "pc_sel_a", filename, counter, currenttime, " During JMP, pc_sel_a has to be 1.") and success;
|
||||
success := bcheck(pc_en, '1', "pc_en", filename, counter, currenttime, " During JMP, pc_en has to be 1.") and success;
|
||||
when BREAK =>
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During BREAK, write has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During BREAK, ir_en has to be 0.") and success;
|
||||
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During BREAK, rf_wren has to be 0.") and success;
|
||||
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During BREAK, pc_en has to be 0.") and success;
|
||||
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During BREAK, branch_op has to be 0.") and success;
|
||||
when JMPI =>
|
||||
success := bcheck(write, '0', "write", filename, counter, currenttime, " During JMPI, write has to be 0.") and success;
|
||||
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During JMPI, ir_en has to be 0.") and success;
|
||||
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During JMPI, branch_op has to be 0.") and success;
|
||||
success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " During JMPI, pc_add_imm has to be 0.") and success;
|
||||
success := bcheck(pc_sel_a, '0', "pc_sel_a", filename, counter, currenttime, " During JMPI, pc_sel_a has to be 0.") and success;
|
||||
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During JMPI, rf_wren has to be 0.") and success;
|
||||
|
||||
success := bcheck(pc_sel_imm, '1', "pc_sel_imm", filename, counter, currenttime, " During JMPI, pc_sel_imm has to be 1.") and success;
|
||||
success := bcheck(pc_en, '1', "pc_en", filename, counter, currenttime, " During JMPI, pc_en has to be 1.") and success;
|
||||
when others =>
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(reset_n, clk)
|
||||
begin
|
||||
if (reset_n = '0') then
|
||||
pc_counter <= 0;
|
||||
elsif (rising_edge(clk)) then
|
||||
sel_addr_reg <= sel_addr;
|
||||
reg_read <= reads;
|
||||
if (pc_en = '1' and (state < DECODE)) then
|
||||
pc_counter <= pc_counter + 1;
|
||||
elsif (state >= DECODE) then
|
||||
pc_counter <= 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
if (finished) then
|
||||
wait;
|
||||
else
|
||||
clk <= not clk;
|
||||
wait for CLK_PERIOD / 2;
|
||||
currenttime <= currenttime + CLK_PERIOD / 2;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end testbench;
|
||||
108
cs208-ca/testbench/tb_Extend.vhd
Executable file
108
cs208-ca/testbench/tb_Extend.vhd
Executable file
@@ -0,0 +1,108 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
use std.textio.all;
|
||||
|
||||
use work.check_functions.all;
|
||||
|
||||
entity tb_Extend is
|
||||
end;
|
||||
|
||||
architecture testbench of tb_Extend is
|
||||
signal finished : boolean := false;
|
||||
signal currenttime : time := 0 ns;
|
||||
|
||||
component extend is
|
||||
port(
|
||||
imm16 : in std_logic_vector(15 downto 0);
|
||||
signed : in std_logic;
|
||||
imm32 : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
constant CLK_PERIOD : time := 5 ns;
|
||||
|
||||
signal clk : std_logic := '0';
|
||||
signal signed : std_logic := '0';
|
||||
|
||||
signal imm16 : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal imm32 : std_logic_vector(31 downto 0);
|
||||
|
||||
begin
|
||||
extend_0 : extend port map(
|
||||
signed => signed,
|
||||
imm16 => imm16,
|
||||
imm32 => imm32
|
||||
);
|
||||
|
||||
check : process
|
||||
constant filename : string := "Extend/report.txt";
|
||||
file text_report : text is out filename;
|
||||
variable line_output : line;
|
||||
file text_input : text is in "Extend/in.txt";
|
||||
variable line_input : line;
|
||||
variable counter : integer := 0;
|
||||
|
||||
variable success : boolean := true;
|
||||
|
||||
variable valid : std_logic;
|
||||
variable imm32_cmp : std_logic_vector(31 downto 0);
|
||||
|
||||
variable SINGLE_BIT : std_logic;
|
||||
variable HWORD : std_logic_vector(15 downto 0);
|
||||
begin
|
||||
line_input := new string'("");
|
||||
|
||||
if (endfile(text_input)) then
|
||||
finished <= true;
|
||||
line_output := new string'("===================================================================");
|
||||
writeline(output, line_output);
|
||||
if (success) then
|
||||
line_output := new string'("Simulation is successful");
|
||||
else
|
||||
line_output := new string'("Errors encountered during simulation. Refer to the report.txt file.");
|
||||
end if;
|
||||
writeline(output, line_output);
|
||||
line_output := new string'("===================================================================");
|
||||
writeline(output, line_output);
|
||||
wait;
|
||||
end if;
|
||||
counter := counter + 1;
|
||||
|
||||
readline(text_input, line_input);
|
||||
|
||||
if (line_input'length /= 0) then
|
||||
if (line_input(1) = '-') then -- Print message
|
||||
line_output := line_input;
|
||||
writeline(output, line_input);
|
||||
elsif (line_input(1) /= '#') then
|
||||
wait until clk = '1';
|
||||
|
||||
read(line_input, SINGLE_BIT);
|
||||
signed <= SINGLE_BIT;
|
||||
|
||||
hread(line_input, HWORD);
|
||||
imm16 <= HWORD;
|
||||
|
||||
wait until clk = '0';
|
||||
|
||||
hread(line_input, imm32_cmp);
|
||||
|
||||
success := hcheck(imm32, imm32_cmp, "imm32", filename, counter, currenttime, "") and success;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
if (finished) then
|
||||
wait;
|
||||
else
|
||||
clk <= not clk;
|
||||
wait for CLK_PERIOD / 2;
|
||||
currenttime <= currenttime + CLK_PERIOD / 2;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end testbench;
|
||||
45
cs208-ca/testbench/tb_GECKO.vhd
Executable file
45
cs208-ca/testbench/tb_GECKO.vhd
Executable file
@@ -0,0 +1,45 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity tb_GECKO is
|
||||
end;
|
||||
|
||||
architecture testbench of tb_GECKO is
|
||||
constant CLK_PERIOD : time := 40 ns;
|
||||
|
||||
signal clk : std_logic := '0';
|
||||
signal reset_n : std_logic := '0';
|
||||
signal in_buttons : std_logic_vector(3 downto 0);
|
||||
|
||||
begin
|
||||
gecko_0 : ENTITY work.gecko(bdf_type) port map(
|
||||
clk => clk,
|
||||
reset_n => reset_n,
|
||||
row1 => open,
|
||||
row2 => open,
|
||||
row3 => open,
|
||||
row4 => open,
|
||||
row5 => open,
|
||||
row6 => open,
|
||||
row7 => open,
|
||||
row8 => open,
|
||||
in_buttons => in_buttons
|
||||
);
|
||||
|
||||
in_buttons <= (others => '0');
|
||||
|
||||
process
|
||||
begin
|
||||
clk <= not clk;
|
||||
wait for CLK_PERIOD / 2;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
reset_n <= '0';
|
||||
wait for CLK_PERIOD / 2;
|
||||
reset_n <= '1';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
end testbench;
|
||||
111
cs208-ca/testbench/tb_IR.vhd
Executable file
111
cs208-ca/testbench/tb_IR.vhd
Executable file
@@ -0,0 +1,111 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
use std.textio.all;
|
||||
|
||||
use work.check_functions.all;
|
||||
|
||||
entity tb_IR is
|
||||
end;
|
||||
|
||||
architecture testbench of tb_IR is
|
||||
signal finished : boolean := false;
|
||||
signal currenttime : time := 0 ns;
|
||||
|
||||
component IR is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
enable : in std_logic;
|
||||
D : in std_logic_vector(31 downto 0);
|
||||
Q : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
constant CLK_PERIOD : time := 5 ns;
|
||||
|
||||
signal clk : std_logic := '0';
|
||||
signal enable : std_logic := '0';
|
||||
|
||||
signal D : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal Q : std_logic_vector(31 downto 0);
|
||||
|
||||
begin
|
||||
ir_0 : IR port map(
|
||||
clk => clk,
|
||||
enable => enable,
|
||||
D => D,
|
||||
Q => Q
|
||||
);
|
||||
|
||||
check : process
|
||||
constant filename : string := "IR/report.txt";
|
||||
file text_report : text is out filename;
|
||||
variable line_output : line;
|
||||
file text_input : text is in "IR/in.txt";
|
||||
variable line_input : line;
|
||||
variable counter : integer := 0;
|
||||
|
||||
variable success : boolean := true;
|
||||
|
||||
variable valid : std_logic;
|
||||
variable Q_cmp : std_logic_vector(31 downto 0);
|
||||
|
||||
variable SINGLE_BIT : std_logic;
|
||||
variable WORD : std_logic_vector(31 downto 0);
|
||||
begin
|
||||
line_input := new string'("");
|
||||
|
||||
if (endfile(text_input)) then
|
||||
finished <= true;
|
||||
line_output := new string'("===================================================================");
|
||||
writeline(output, line_output);
|
||||
if (success) then
|
||||
line_output := new string'("Simulation is successful");
|
||||
else
|
||||
line_output := new string'("Errors encountered during simulation. Refer to the report.txt file.");
|
||||
end if;
|
||||
writeline(output, line_output);
|
||||
line_output := new string'("===================================================================");
|
||||
writeline(output, line_output);
|
||||
wait;
|
||||
end if;
|
||||
counter := counter + 1;
|
||||
|
||||
readline(text_input, line_input);
|
||||
|
||||
if (line_input'length /= 0) then
|
||||
if (line_input(1) = '-') then -- Print message
|
||||
line_output := line_input;
|
||||
writeline(output, line_input);
|
||||
elsif (line_input(1) /= '#') then
|
||||
wait until clk = '1';
|
||||
|
||||
read(line_input, SINGLE_BIT);
|
||||
enable <= SINGLE_BIT;
|
||||
hread(line_input, WORD);
|
||||
D <= WORD;
|
||||
|
||||
wait until clk = '0';
|
||||
|
||||
read(line_input, valid);
|
||||
hread(line_input, Q_cmp);
|
||||
|
||||
if (valid = '1') then
|
||||
success := hcheck(Q, Q_cmp, "Q", filename, counter, currenttime, "") and success;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
if (finished) then
|
||||
wait;
|
||||
else
|
||||
clk <= not clk;
|
||||
wait for CLK_PERIOD / 2;
|
||||
currenttime <= currenttime + CLK_PERIOD / 2;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end testbench;
|
||||
137
cs208-ca/testbench/tb_PC.vhd
Executable file
137
cs208-ca/testbench/tb_PC.vhd
Executable file
@@ -0,0 +1,137 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
use std.textio.all;
|
||||
|
||||
use work.check_functions.all;
|
||||
|
||||
entity tb_PC is
|
||||
end;
|
||||
|
||||
architecture testbench of tb_PC is
|
||||
signal finished : boolean := false;
|
||||
signal currenttime : time := 0 ns;
|
||||
|
||||
component PC is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset_n : in std_logic;
|
||||
en : in std_logic;
|
||||
sel_a : in std_logic;
|
||||
sel_imm : in std_logic;
|
||||
add_imm : in std_logic;
|
||||
imm : in std_logic_vector(15 downto 0);
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
addr : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
constant CLK_PERIOD : time := 5 ns;
|
||||
|
||||
signal clk : std_logic := '0';
|
||||
signal reset_n : std_logic := '0';
|
||||
signal en : std_logic := '0';
|
||||
signal sel_a : std_logic := '0';
|
||||
signal sel_imm : std_logic := '0';
|
||||
signal add_imm : std_logic := '0';
|
||||
|
||||
signal imm : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal a : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal addr : std_logic_vector(31 downto 0);
|
||||
|
||||
begin
|
||||
pc_0 : PC port map(
|
||||
clk => clk,
|
||||
reset_n => reset_n,
|
||||
en => en,
|
||||
sel_a => sel_a,
|
||||
sel_imm => sel_imm,
|
||||
add_imm => add_imm,
|
||||
imm => imm,
|
||||
a => a,
|
||||
addr => addr
|
||||
);
|
||||
|
||||
check : process
|
||||
constant filename : string := "PC/report.txt";
|
||||
file text_report : text is out filename;
|
||||
variable line_output : line;
|
||||
file text_input : text is in "PC/in.txt";
|
||||
variable line_input : line;
|
||||
variable counter : integer := 0;
|
||||
|
||||
variable success : boolean := true;
|
||||
|
||||
variable valid : std_logic;
|
||||
variable addr_cmp : std_logic_vector(31 downto 0);
|
||||
|
||||
variable SINGLE_BIT : std_logic;
|
||||
variable HWORD : std_logic_vector(15 downto 0);
|
||||
begin
|
||||
line_input := new string'("");
|
||||
|
||||
if (endfile(text_input)) then
|
||||
finished <= true;
|
||||
line_output := new string'("===================================================================");
|
||||
writeline(output, line_output);
|
||||
if (success) then
|
||||
line_output := new string'("Simulation is successful");
|
||||
else
|
||||
line_output := new string'("Errors encountered during simulation. Refer to the report.txt file.");
|
||||
end if;
|
||||
writeline(output, line_output);
|
||||
line_output := new string'("===================================================================");
|
||||
writeline(output, line_output);
|
||||
wait;
|
||||
end if;
|
||||
counter := counter + 1;
|
||||
|
||||
readline(text_input, line_input);
|
||||
|
||||
if (line_input'length /= 0) then
|
||||
if (line_input(1) = '-') then -- Print message
|
||||
line_output := line_input;
|
||||
writeline(output, line_input);
|
||||
elsif (line_input(1) /= '#') then
|
||||
wait until clk = '1';
|
||||
|
||||
read(line_input, SINGLE_BIT);
|
||||
reset_n <= SINGLE_BIT;
|
||||
read(line_input, SINGLE_BIT);
|
||||
en <= SINGLE_BIT;
|
||||
read(line_input, SINGLE_BIT);
|
||||
sel_a <= SINGLE_BIT;
|
||||
read(line_input, SINGLE_BIT);
|
||||
sel_imm <= SINGLE_BIT;
|
||||
read(line_input, SINGLE_BIT);
|
||||
add_imm <= SINGLE_BIT;
|
||||
|
||||
hread(line_input, HWORD);
|
||||
imm <= HWORD;
|
||||
hread(line_input, HWORD);
|
||||
a <= HWORD;
|
||||
|
||||
wait until clk = '0';
|
||||
|
||||
read(line_input, valid);
|
||||
hread(line_input, addr_cmp);
|
||||
|
||||
if (valid = '1' and addr_cmp /= addr) then
|
||||
success := hcheck(addr, addr_cmp, "addr", filename, counter, currenttime, "") and success;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
if (finished) then
|
||||
wait;
|
||||
else
|
||||
clk <= not clk;
|
||||
wait for CLK_PERIOD / 2;
|
||||
currenttime <= currenttime + CLK_PERIOD / 2;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end testbench;
|
||||
Reference in New Issue
Block a user