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choelzl
2022-04-07 18:43:21 +02:00
parent 182267a8cb
commit 88cb3426ad
1067 changed files with 102374 additions and 6 deletions
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232
cs208-ca/modelsim/Controller/in.txt Executable file
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# 1 2 3 4 5 6
# reset_n:OP:OPX:state:op_alu_mask:op_alu
-=Controller test:======================================================
0 00 00 0 000000 000000
--R_OP test:------------------------------------------------------------
#--rol
# 1 00 00 0 000000 000000
# 1 00 00 1 000000 000000
# 1 3A 03 2 000000 000000
# 1 3A 03 3 110111 110000
#--nor
1 00 00 1 000000 000000
1 3A 06 2 000000 000000
1 3A 06 3 110011 100000
#--cmple
1 00 00 1 000000 000000
1 3A 08 2 000000 000000
1 3A 08 3 111111 011001
#--ror
# 1 00 00 1 000000 000000
# 1 3A 0B 2 000000 000000
# 1 3A 0B 3 110111 110001
#--and
1 00 00 1 000000 000000
1 3A 0E 2 000000 000000
1 3A 0E 3 110011 100001
#--cmpgt
1 00 00 1 000000 000000
1 3A 10 2 000000 000000
1 3A 10 3 111111 011010
#--sll
1 00 00 1 000000 000000
1 3A 13 2 000000 000000
1 3A 13 3 110111 110010
#--or
1 00 00 1 000000 000000
1 3A 16 2 000000 000000
1 3A 16 3 110011 100010
#--cmpne
# 1 00 00 1 000000 000000
# 1 3A 18 2 000000 000000
# 1 3A 18 3 111111 011011
#--srl
1 00 00 1 000000 000000
1 3A 1B 2 000000 000000
1 3A 1B 3 110111 110011
#--xnor
1 00 00 1 000000 000000
1 3A 1E 2 000000 000000
1 3A 1E 3 110011 100011
#--cmpeq
# 1 00 00 1 000000 000000
# 1 3A 20 2 000000 000000
# 1 3A 20 3 111111 011100
#--cmpleu
# 1 00 00 1 000000 000000
# 1 3A 28 2 000000 000000
# 1 3A 28 3 111111 011101
#--cmpgtu
# 1 00 00 1 000000 000000
# 1 3A 30 2 000000 000000
# 1 3A 30 3 111111 011110
#--add
1 00 00 1 000000 000000
1 3A 31 2 000000 000000
1 3A 31 3 111000 000000
#--sub
1 00 00 1 000000 000000
1 3A 39 2 000000 000000
1 3A 39 3 111000 001000
#--sra
1 00 00 1 000000 000000
1 3A 3B 2 000000 000000
1 3A 3B 3 110111 110111
--RI_OP test:-----------------------------------------------------------
#--roli
# 1 00 00 1 000000 000000
# 1 3A 02 2 000000 000000
# 1 3A 02 4 110111 110000
#--slli
1 00 00 1 000000 000000
1 3A 12 2 000000 000000
1 3A 12 4 110111 110010
#--srli
1 00 00 1 000000 000000
1 3A 1A 2 000000 000000
1 3A 1A 4 110111 110011
#--srai
1 00 00 1 000000 000000
1 3A 3A 2 000000 000000
1 3A 3A 4 110111 110111
--I_OP test:------------------------------------------------------------
#--addi
1 00 00 1 000000 000000
1 04 00 2 000000 000000
1 04 00 5 111000 000000
#--cmplei
# 1 00 00 1 000000 000000
# 1 08 00 2 000000 000000
# 1 08 00 5 111111 011001
#--cmpgti
# 1 00 00 1 000000 000000
# 1 10 00 2 000000 000000
# 1 10 00 5 111111 011010
#--cmpnei
# 1 00 00 1 000000 000000
# 1 18 00 2 000000 000000
# 1 18 00 5 111111 011011
#--cmpeqi
# 1 00 00 1 000000 000000
# 1 20 00 2 000000 000000
# 1 20 00 5 111111 011100
--UI_OP test:-----------------------------------------------------------
#--andi
1 00 00 1 000000 000000
1 0C 00 2 000000 000000
1 0C 00 6 110011 100001
#--ori
1 00 00 1 000000 000000
1 14 00 2 000000 000000
1 14 00 6 110011 100010
#--xnori
1 00 00 1 000000 000000
1 1C 00 2 000000 000000
1 1C 00 6 110011 100011
#--cmpleui
# 1 00 00 1 000000 000000
# 1 28 00 2 000000 000000
# 1 28 00 6 111111 011101
#--cmpgtui
# 1 00 00 1 000000 000000
# 1 30 00 2 000000 000000
# 1 30 00 6 111111 011110
--LOAD test:------------------------------------------------------------
#--ldw
1 00 00 1 000000 000000
1 17 00 2 000000 000000
1 17 00 7 111000 000000
1 17 00 8 000000 000000
--STORE test:-----------------------------------------------------------
#--stw
1 00 00 1 000000 000000
1 15 00 2 000000 000000
1 15 00 9 111000 000000
--BRANCH test:----------------------------------------------------------
#--br
1 00 00 1 000000 000000
1 06 00 2 000000 000000
1 06 00 10 000000 000000
#--ble
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 0E 00 2 000000 000000
1 0E 00 10 111111 011001
#--bgt
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 16 00 2 000000 000000
1 16 00 10 111111 011010
#--bne
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 1E 00 2 000000 000000
1 1E 00 10 111111 011011
#--beq
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 26 00 2 000000 000000
1 26 00 10 111111 011100
#--bleu
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 2E 00 2 000000 000000
1 2E 00 10 111111 011101
#--bgtu
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 36 00 2 000000 000000
1 36 00 10 111111 011110
--CALL test:------------------------------------------------------------
#--call
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 00 00 2 000000 000000
1 00 00 11 000000 000000
--CALLR test:-----------------------------------------------------------
#--callr
# 1 00 00 0 000000 000000
# 1 00 00 1 000000 000000
# 1 3A 1D 2 000000 000000
# 1 3A 1D 12 000000 000000
--JMP test:-------------------------------------------------------------
#--ret
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 05 2 000000 000000
1 3A 05 13 000000 000000
#--jmp
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 0D 2 000000 000000
1 3A 0D 13 000000 000000
--JMPI test:--------------------------------------------------
#--jmpi
# 1 00 00 0 000000 000000
# 1 00 00 1 000000 000000
# 1 01 00 2 000000 000000
# 1 01 00 15 000000 000000
#--(optional)HI_OP test:-------------------------------------------------
##--andhi
# 1 00 00 0 000000 000000
# 1 00 00 1 000000 000000
# 1 2C 00 2 000000 000000
# 1 2C 00 16 110011 100001
##--orhi
# 1 00 00 1 000000 000000
# 1 34 00 2 000000 000000
# 1 34 00 16 110011 100010
##--xnorhi
# 1 00 00 1 000000 000000
# 1 3C 00 2 000000 000000
# 1 3C 00 16 110011 100011
--BREAK test:-----------------------------------------------------------
#--break
1 00 00 1 000000 000000
1 3A 34 2 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000

40
cs208-ca/modelsim/Controller/in0.txt Executable file
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# 1 2 3 4 5 6
# reset_n:OP:OPX:state:op_alu_mask:op_alu
-=Controller test:======================================================
-=Testing the first version of the CPU==================================
0 00 00 0 000000 000000
--and
1 00 00 1 000000 000000
1 3A 0E 2 000000 000000
1 3A 0E 3 110011 100001
--srl
1 00 00 1 000000 000000
1 3A 1B 2 000000 000000
1 3A 1B 3 110111 110011
--addi
1 00 00 1 000000 000000
1 04 00 2 000000 000000
1 04 00 5 111000 000000
--ldw
1 00 00 1 000000 000000
1 17 00 2 000000 000000
1 17 00 7 111000 000000
1 17 00 8 000000 000000
--stw
1 00 00 1 000000 000000
1 15 00 2 000000 000000
1 15 00 9 111000 000000
--break
1 00 00 1 000000 000000
1 3A 34 2 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
0 00 00 0 000000 000000
--and
1 00 00 1 000000 000000
1 3A 0E 2 000000 000000
1 3A 0E 3 110011 100001

232
cs208-ca/modelsim/Controller/in_complete.txt Executable file
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# 1 2 3 4 5 6
# reset_n:OP:OPX:state:op_alu_mask:op_alu
-=Controller test:======================================================
0 00 00 0 000000 000000
--R_OP test:------------------------------------------------------------
#--rol
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 03 2 000000 000000
1 3A 03 3 110111 110000
#--nor
1 00 00 1 000000 000000
1 3A 06 2 000000 000000
1 3A 06 3 110011 100000
#--cmple
1 00 00 1 000000 000000
1 3A 08 2 000000 000000
1 3A 08 3 111111 011001
#--ror
1 00 00 1 000000 000000
1 3A 0B 2 000000 000000
1 3A 0B 3 110111 110001
#--and
1 00 00 1 000000 000000
1 3A 0E 2 000000 000000
1 3A 0E 3 110011 100001
#--cmpgt
1 00 00 1 000000 000000
1 3A 10 2 000000 000000
1 3A 10 3 111111 011010
#--sll
1 00 00 1 000000 000000
1 3A 13 2 000000 000000
1 3A 13 3 110111 110010
#--or
1 00 00 1 000000 000000
1 3A 16 2 000000 000000
1 3A 16 3 110011 100010
#--cmpne
1 00 00 1 000000 000000
1 3A 18 2 000000 000000
1 3A 18 3 111111 011011
#--srl
1 00 00 1 000000 000000
1 3A 1B 2 000000 000000
1 3A 1B 3 110111 110011
#--xnor
1 00 00 1 000000 000000
1 3A 1E 2 000000 000000
1 3A 1E 3 110011 100011
#--cmpeq
1 00 00 1 000000 000000
1 3A 20 2 000000 000000
1 3A 20 3 111111 011100
#--cmpleu
1 00 00 1 000000 000000
1 3A 28 2 000000 000000
1 3A 28 3 111111 011101
#--cmpgtu
1 00 00 1 000000 000000
1 3A 30 2 000000 000000
1 3A 30 3 111111 011110
#--add
1 00 00 1 000000 000000
1 3A 31 2 000000 000000
1 3A 31 3 111000 000000
#--sub
1 00 00 1 000000 000000
1 3A 39 2 000000 000000
1 3A 39 3 111000 001000
#--sra
1 00 00 1 000000 000000
1 3A 3B 2 000000 000000
1 3A 3B 3 110111 110111
--RI_OP test:-----------------------------------------------------------
#--roli
1 00 00 1 000000 000000
1 3A 02 2 000000 000000
1 3A 02 4 110111 110000
#--slli
1 00 00 1 000000 000000
1 3A 12 2 000000 000000
1 3A 12 4 110111 110010
#--srli
1 00 00 1 000000 000000
1 3A 1A 2 000000 000000
1 3A 1A 4 110111 110011
#--srai
1 00 00 1 000000 000000
1 3A 3A 2 000000 000000
1 3A 3A 4 110111 110111
--I_OP test:------------------------------------------------------------
#--addi
1 00 00 1 000000 000000
1 04 00 2 000000 000000
1 04 00 5 111000 000000
#--cmplei
1 00 00 1 000000 000000
1 08 00 2 000000 000000
1 08 00 5 111111 011001
#--cmpgti
1 00 00 1 000000 000000
1 10 00 2 000000 000000
1 10 00 5 111111 011010
#--cmpnei
1 00 00 1 000000 000000
1 18 00 2 000000 000000
1 18 00 5 111111 011011
#--cmpeqi
1 00 00 1 000000 000000
1 20 00 2 000000 000000
1 20 00 5 111111 011100
--UI_OP test:-----------------------------------------------------------
#--andi
1 00 00 1 000000 000000
1 0C 00 2 000000 000000
1 0C 00 6 110011 100001
#--ori
1 00 00 1 000000 000000
1 14 00 2 000000 000000
1 14 00 6 110011 100010
#--xnori
1 00 00 1 000000 000000
1 1C 00 2 000000 000000
1 1C 00 6 110011 100011
#--cmpleui
1 00 00 1 000000 000000
1 28 00 2 000000 000000
1 28 00 6 111111 011101
#--cmpgtui
1 00 00 1 000000 000000
1 30 00 2 000000 000000
1 30 00 6 111111 011110
--LOAD test:------------------------------------------------------------
#--ldw
1 00 00 1 000000 000000
1 17 00 2 000000 000000
1 17 00 7 111000 000000
1 17 00 8 000000 000000
--STORE test:-----------------------------------------------------------
#--stw
1 00 00 1 000000 000000
1 15 00 2 000000 000000
1 15 00 9 111000 000000
--BRANCH test:----------------------------------------------------------
#--br
1 00 00 1 000000 000000
1 06 00 2 000000 000000
1 06 00 10 000000 000000
#--ble
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 0E 00 2 000000 000000
1 0E 00 10 111111 011001
#--bgt
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 16 00 2 000000 000000
1 16 00 10 111111 011010
#--bne
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 1E 00 2 000000 000000
1 1E 00 10 111111 011011
#--beq
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 26 00 2 000000 000000
1 26 00 10 111111 011100
#--bleu
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 2E 00 2 000000 000000
1 2E 00 10 111111 011101
#--bgtu
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 36 00 2 000000 000000
1 36 00 10 111111 011110
--CALL test:------------------------------------------------------------
#--call
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 00 00 2 000000 000000
1 00 00 11 000000 000000
--CALLR test:-----------------------------------------------------------
#--callr
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 1D 2 000000 000000
1 3A 1D 12 000000 000000
--JMP test:-------------------------------------------------------------
#--ret
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 05 2 000000 000000
1 3A 05 13 000000 000000
#--jmp
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 0D 2 000000 000000
1 3A 0D 13 000000 000000
--JMPI test:--------------------------------------------------
#--jmpi
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 01 00 2 000000 000000
1 01 00 15 000000 000000
#--(optional)HI_OP test:-------------------------------------------------
##--andhi
# 1 00 00 0 000000 000000
# 1 00 00 1 000000 000000
# 1 2C 00 2 000000 000000
# 1 2C 00 16 110011 100001
##--orhi
# 1 00 00 1 000000 000000
# 1 34 00 2 000000 000000
# 1 34 00 16 110011 100010
##--xnorhi
# 1 00 00 1 000000 000000
# 1 3C 00 2 000000 000000
# 1 3C 00 16 110011 100011
--BREAK test:-----------------------------------------------------------
#--break
1 00 00 1 000000 000000
1 3A 34 2 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000

0
cs208-ca/modelsim/Controller/report.txt Executable file
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7
cs208-ca/modelsim/IR/in.txt Executable file
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# 1 2 3 4
# en D (vQ) Q
1 00A000A0 0 00000000
1 55CC7722 1 00A000A0
0 00000000 1 55CC7722
1 00000000 1 55CC7722
0 00000000 1 00000000

0
cs208-ca/modelsim/IR/report.txt Executable file
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24
cs208-ca/modelsim/PC/in.txt Executable file
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# 1 2 3 4 5 6 7 8 9
# reset_n:en:sel_a:sel_imm:add_imm:imm: a: (v)addr
- Program Counter test:
0 0 0 0 0 0000 0000 0 00000000
1 1 0 0 0 7FFF 7FFF 1 00000000
1 1 0 0 0 7FFF 7FFF 1 00000004
- reset_n test...
0 1 1 1 1 7FFF 7FFF 1 00000000
1 1 0 0 0 7FFF 7FFF 1 00000000
1 1 0 0 0 7FFF 7FFF 1 00000004
1 1 0 1 0 15A0 7FFF 1 00000008
- sel_imm test...
1 1 1 0 0 7FFF AA50 1 00005680
- sel_a test...
1 1 0 0 1 00A0 7FFF 1 0000AA50
- add_imm test...
1 1 0 0 1 FFB0 7FFF 1 0000AAF0
1 0 1 1 1 7FFF 7FFF 1 0000AAA0
- enable test...
1 1 0 0 0 7FFF 7FFF 1 0000AAA0
- pc+4 test...
1 1 0 0 0 7FFF 7FFF 1 0000AAA4
1 1 0 0 0 7FFF 7FFF 1 0000AAA8
1 1 0 0 0 7FFF 7FFF 1 0000AAAC

0
cs208-ca/modelsim/PC/report.txt Executable file
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7
cs208-ca/modelsim/extend/in.txt Executable file
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@@ -0,0 +1,7 @@
# 1 2 3
# signed:imm16:imm32
- Extend unit test:
0 7123 00007123
1 7456 00007456
0 8789 00008789
1 8ABC FFFF8ABC

0
cs208-ca/modelsim/extend/report.txt Executable file
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273
cs208-ca/modelsim/multicycle_niosII.cr.mti Executable file
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../vhdl/ROM_Block.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ROM_Block.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ROM_Block
-- Compiling architecture SYN of rom_block
} {} {}} ../vhdl/comparator.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/comparator.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity comparator
-- Compiling architecture synth of comparator
} {} {}} ../testbench/check_functions.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/check_functions.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Compiling package check_functions
-- Compiling package body check_functions
-- Loading package check_functions
** Warning: E:/cs208/testbench/check_functions.vhd(49): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(59): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(65): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(67): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(68): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(83): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(93): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(99): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(101): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(102): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(117): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(127): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(133): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(135): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(136): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(151): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(161): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(167): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(169): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(170): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
} {} {}} ../vhdl/extend.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/extend.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity extend
-- Compiling architecture synth of extend
} {} {}} ../vhdl/mux2x5.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x5.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x5
-- Compiling architecture synth of mux2x5
} {} {}} ../vhdl/ALU.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ALU.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ALU
-- Compiling architecture bdf_type of ALU
} {} {}} ../vhdl/add_sub.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/add_sub.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity add_sub
-- Compiling architecture synth of add_sub
} {} {}} ../vhdl/PC.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/PC.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity PC
-- Compiling architecture synth of PC
} {} {}} ../vhdl/multiplexer.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/multiplexer.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity multiplexer
-- Compiling architecture synth of multiplexer
} {} {}} ../vhdl/IR.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/IR.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity IR
-- Compiling architecture synth of IR
} {} {}} ../vhdl/controller.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/controller.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity controller
-- Compiling architecture synth of controller
} {} {}} ../vhdl/register_file.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/register_file.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity register_file
-- Compiling architecture synth of register_file
} {} {}} ../vhdl/ROM.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ROM.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity ROM
-- Compiling architecture synth of ROM
} {} {}} ../vhdl/buttons.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/buttons.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity buttons
-- Compiling architecture synth of buttons
} {} {}} ../testbench/tb_Extend.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_Extend.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_Extend
-- Compiling architecture testbench of tb_Extend
** Warning: E:/cs208/testbench/tb_Extend.vhd(40): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_Extend.vhd(42): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
} {} {}} ../vhdl/RAM.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/RAM.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity RAM
-- Compiling architecture synth of RAM
} {} {}} ../vhdl/LEDs.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/LEDs.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity LEDs
-- Compiling architecture synth of LEDs
} {} {}} ../vhdl/CPU.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/CPU.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity CPU
-- Compiling architecture bdf_type of CPU
} {} {}} ../testbench/tb_GECKO.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_GECKO.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity tb_GECKO
-- Compiling architecture testbench of tb_GECKO
-- Loading entity GECKO
} {} {}} ../vhdl/GECKO.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/GECKO.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity GECKO
-- Compiling architecture bdf_type of GECKO
} {} {}} ../vhdl/mux2x32.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x32.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x32
-- Compiling architecture synth of mux2x32
} {} {}} ../testbench/tb_IR.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_IR.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_IR
-- Compiling architecture testbench of tb_IR
** Warning: E:/cs208/testbench/tb_IR.vhd(42): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_IR.vhd(44): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
} {} {}} ../testbench/tb_PC.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_PC.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_PC
-- Compiling architecture testbench of tb_PC
** Warning: E:/cs208/testbench/tb_PC.vhd(57): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_PC.vhd(59): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
} {} {}} ../vhdl/mux2x16.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x16.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x16
-- Compiling architecture synth of mux2x16
} {} {}} ../testbench/tb_Controller.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_Controller.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_Controller
-- Compiling architecture testbench of tb_Controller
** Warning: E:/cs208/testbench/tb_Controller.vhd(129): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_Controller.vhd(130): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
} {} {}} ../vhdl/logic_unit.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/logic_unit.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity logic_unit
-- Compiling architecture synth of logic_unit
} {} {}} ../vhdl/shift_unit.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/shift_unit.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity shift_unit
-- Compiling architecture synth of shift_unit
} {} {}} ../vhdl/decoder.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/decoder.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity decoder
-- Compiling architecture synth of decoder
} {} {}}

518
cs208-ca/modelsim/multicycle_niosII.mpf Executable file
View File

@@ -0,0 +1,518 @@
; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
; Altera Primitive libraries
;
; VHDL Section
;
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
maxii = $MODEL_TECH/../altera/vhdl/maxii
maxv = $MODEL_TECH/../altera/vhdl/maxv
fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
sgate = $MODEL_TECH/../altera/vhdl/sgate
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
arriav = $MODEL_TECH/../altera/vhdl/arriav
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
twentynm = $MODEL_TECH/../altera/vhdl/twentynm
twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
fourteennm = $MODEL_TECH/../altera/vhdl/fourteennm
;
; Verilog Section
;
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
fourteennm_ver = $MODEL_TECH/../altera/verilog/fourteennm
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Default or value of 3 or 2008 for VHDL-2008.
VHDL93 = 2002
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
; Turns on lint-style checking.
; Show_Lint = 1
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
; Default run length
RunLength = 100 ps
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
; VSIM Startup command
; Startup = do startup.do
; File for saving command transcript
TranscriptFile = transcript
; File for saving command history
; CommandHistory = cmdhist.log
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
[lmc]
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 28
Project_File_0 = ../testbench/check_functions.vhd
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_1 = ../vhdl/extend.vhd
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_2 = ../vhdl/ROM_Block.vhd
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 26 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_3 = ../vhdl/comparator.vhd
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_4 = ../vhdl/mux2x5.vhd
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_5 = ../vhdl/ALU.vhd
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_6 = ../vhdl/add_sub.vhd
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_7 = ../vhdl/PC.vhd
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540372638 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_8 = ../vhdl/IR.vhd
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_9 = ../vhdl/multiplexer.vhd
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_10 = ../vhdl/controller.vhd
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540374794 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_11 = ../vhdl/register_file.vhd
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540371264 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_12 = ../vhdl/ROM.vhd
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540375298 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_13 = ../testbench/tb_Extend.vhd
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_14 = ../vhdl/buttons.vhd
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_15 = ../vhdl/RAM.vhd
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540375470 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_16 = ../vhdl/LEDs.vhd
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540372438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 20 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_17 = ../testbench/tb_GECKO.vhd
Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_18 = ../vhdl/CPU.vhd
Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_19 = ../vhdl/GECKO.vhd
Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_20 = ../vhdl/mux2x32.vhd
Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_21 = ../testbench/tb_IR.vhd
Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_22 = ../testbench/tb_PC.vhd
Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_23 = ../testbench/tb_Controller.vhd
Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_24 = ../vhdl/mux2x16.vhd
Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_25 = ../vhdl/shift_unit.vhd
Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_26 = ../vhdl/logic_unit.vhd
Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_27 = ../vhdl/decoder.vhd
Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540372776 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
TDB_DoubleClick = Edit
TDB_CustomDoubleClick =
UPF_DoubleClick = Edit
UPF_CustomDoubleClick =
PCF_DoubleClick = Edit
PCF_CustomDoubleClick =
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick =
VRM_DoubleClick = Edit
VRM_CustomDoubleClick =
DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 10
Project_Minor_Version = 5

12
cs208-ca/modelsim/test_Controller.do Executable file
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@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/controller.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_Controller.vhd
vsim -Gtext_in=Controller/in.txt tb_Controller
add wave -hex controller_0/*
run -all

12
cs208-ca/modelsim/test_Controller0.do Executable file
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@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/controller.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_Controller.vhd
vsim -Gtext_in=Controller/in0.txt tb_Controller
add wave -hex controller_0/*
run -all

12
cs208-ca/modelsim/test_Controller_complete.do Executable file
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@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/controller.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_Controller.vhd
vsim -Gtext_in=Controller/in_complete.txt tb_Controller
add wave -hex controller_0/*
run -all

12
cs208-ca/modelsim/test_Extend.do Executable file
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@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/extend.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_Extend.vhd
vsim tb_Extend
add wave -hex extend_0/*
run -all

12
cs208-ca/modelsim/test_IR.do Executable file
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@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/IR.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_IR.vhd
vsim tb_IR
add wave -hex ir_0/*
run -all

12
cs208-ca/modelsim/test_PC.do Executable file
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@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/PC.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_PC.vhd
vsim tb_PC
add wave -hex pc_0/*
run -all

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cs208-ca/modelsim/vsim.wlf Executable file
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1140
cs208-ca/modelsim/work/_info Executable file
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cs208-ca/modelsim/work/_lib.qdb Executable file
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cs208-ca/modelsim/work/_lib1_104.qdb Executable file
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cs208-ca/modelsim/work/_lib1_104.qpg Executable file
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cs208-ca/modelsim/work/_lib1_104.qtl Executable file
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4
cs208-ca/modelsim/work/_vmake Executable file
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@@ -0,0 +1,4 @@
m255
K4
z0
cModel Technology