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choelzl
2022-04-07 18:43:21 +02:00
parent 182267a8cb
commit 88cb3426ad
1067 changed files with 102374 additions and 6 deletions
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1
cs208-ca

Submodule cs208-ca deleted from 66918b1813

25
cs208-ca/LICENSE Executable file
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This is free and unencumbered software released into the public domain.
Anyone is free to copy, modify, publish, use, compile, sell, or
distribute this software, either in source code form or as a compiled
binary, for any purpose, commercial or non-commercial, and by any
means.
In jurisdictions that recognize copyright laws, the author or authors
of this software dedicate any and all copyright interest in the
software to the public domain. We make this dedication for the benefit
of the public at large and to the detriment of our heirs and
successors. We intend this dedication to be an overt act of
relinquishment in perpetuity of all present and future rights to this
software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
For more information, please refer to <https://unlicense.org>

232
cs208-ca/modelsim/Controller/in.txt Executable file
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# 1 2 3 4 5 6
# reset_n:OP:OPX:state:op_alu_mask:op_alu
-=Controller test:======================================================
0 00 00 0 000000 000000
--R_OP test:------------------------------------------------------------
#--rol
# 1 00 00 0 000000 000000
# 1 00 00 1 000000 000000
# 1 3A 03 2 000000 000000
# 1 3A 03 3 110111 110000
#--nor
1 00 00 1 000000 000000
1 3A 06 2 000000 000000
1 3A 06 3 110011 100000
#--cmple
1 00 00 1 000000 000000
1 3A 08 2 000000 000000
1 3A 08 3 111111 011001
#--ror
# 1 00 00 1 000000 000000
# 1 3A 0B 2 000000 000000
# 1 3A 0B 3 110111 110001
#--and
1 00 00 1 000000 000000
1 3A 0E 2 000000 000000
1 3A 0E 3 110011 100001
#--cmpgt
1 00 00 1 000000 000000
1 3A 10 2 000000 000000
1 3A 10 3 111111 011010
#--sll
1 00 00 1 000000 000000
1 3A 13 2 000000 000000
1 3A 13 3 110111 110010
#--or
1 00 00 1 000000 000000
1 3A 16 2 000000 000000
1 3A 16 3 110011 100010
#--cmpne
# 1 00 00 1 000000 000000
# 1 3A 18 2 000000 000000
# 1 3A 18 3 111111 011011
#--srl
1 00 00 1 000000 000000
1 3A 1B 2 000000 000000
1 3A 1B 3 110111 110011
#--xnor
1 00 00 1 000000 000000
1 3A 1E 2 000000 000000
1 3A 1E 3 110011 100011
#--cmpeq
# 1 00 00 1 000000 000000
# 1 3A 20 2 000000 000000
# 1 3A 20 3 111111 011100
#--cmpleu
# 1 00 00 1 000000 000000
# 1 3A 28 2 000000 000000
# 1 3A 28 3 111111 011101
#--cmpgtu
# 1 00 00 1 000000 000000
# 1 3A 30 2 000000 000000
# 1 3A 30 3 111111 011110
#--add
1 00 00 1 000000 000000
1 3A 31 2 000000 000000
1 3A 31 3 111000 000000
#--sub
1 00 00 1 000000 000000
1 3A 39 2 000000 000000
1 3A 39 3 111000 001000
#--sra
1 00 00 1 000000 000000
1 3A 3B 2 000000 000000
1 3A 3B 3 110111 110111
--RI_OP test:-----------------------------------------------------------
#--roli
# 1 00 00 1 000000 000000
# 1 3A 02 2 000000 000000
# 1 3A 02 4 110111 110000
#--slli
1 00 00 1 000000 000000
1 3A 12 2 000000 000000
1 3A 12 4 110111 110010
#--srli
1 00 00 1 000000 000000
1 3A 1A 2 000000 000000
1 3A 1A 4 110111 110011
#--srai
1 00 00 1 000000 000000
1 3A 3A 2 000000 000000
1 3A 3A 4 110111 110111
--I_OP test:------------------------------------------------------------
#--addi
1 00 00 1 000000 000000
1 04 00 2 000000 000000
1 04 00 5 111000 000000
#--cmplei
# 1 00 00 1 000000 000000
# 1 08 00 2 000000 000000
# 1 08 00 5 111111 011001
#--cmpgti
# 1 00 00 1 000000 000000
# 1 10 00 2 000000 000000
# 1 10 00 5 111111 011010
#--cmpnei
# 1 00 00 1 000000 000000
# 1 18 00 2 000000 000000
# 1 18 00 5 111111 011011
#--cmpeqi
# 1 00 00 1 000000 000000
# 1 20 00 2 000000 000000
# 1 20 00 5 111111 011100
--UI_OP test:-----------------------------------------------------------
#--andi
1 00 00 1 000000 000000
1 0C 00 2 000000 000000
1 0C 00 6 110011 100001
#--ori
1 00 00 1 000000 000000
1 14 00 2 000000 000000
1 14 00 6 110011 100010
#--xnori
1 00 00 1 000000 000000
1 1C 00 2 000000 000000
1 1C 00 6 110011 100011
#--cmpleui
# 1 00 00 1 000000 000000
# 1 28 00 2 000000 000000
# 1 28 00 6 111111 011101
#--cmpgtui
# 1 00 00 1 000000 000000
# 1 30 00 2 000000 000000
# 1 30 00 6 111111 011110
--LOAD test:------------------------------------------------------------
#--ldw
1 00 00 1 000000 000000
1 17 00 2 000000 000000
1 17 00 7 111000 000000
1 17 00 8 000000 000000
--STORE test:-----------------------------------------------------------
#--stw
1 00 00 1 000000 000000
1 15 00 2 000000 000000
1 15 00 9 111000 000000
--BRANCH test:----------------------------------------------------------
#--br
1 00 00 1 000000 000000
1 06 00 2 000000 000000
1 06 00 10 000000 000000
#--ble
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 0E 00 2 000000 000000
1 0E 00 10 111111 011001
#--bgt
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 16 00 2 000000 000000
1 16 00 10 111111 011010
#--bne
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 1E 00 2 000000 000000
1 1E 00 10 111111 011011
#--beq
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 26 00 2 000000 000000
1 26 00 10 111111 011100
#--bleu
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 2E 00 2 000000 000000
1 2E 00 10 111111 011101
#--bgtu
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 36 00 2 000000 000000
1 36 00 10 111111 011110
--CALL test:------------------------------------------------------------
#--call
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 00 00 2 000000 000000
1 00 00 11 000000 000000
--CALLR test:-----------------------------------------------------------
#--callr
# 1 00 00 0 000000 000000
# 1 00 00 1 000000 000000
# 1 3A 1D 2 000000 000000
# 1 3A 1D 12 000000 000000
--JMP test:-------------------------------------------------------------
#--ret
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 05 2 000000 000000
1 3A 05 13 000000 000000
#--jmp
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 0D 2 000000 000000
1 3A 0D 13 000000 000000
--JMPI test:--------------------------------------------------
#--jmpi
# 1 00 00 0 000000 000000
# 1 00 00 1 000000 000000
# 1 01 00 2 000000 000000
# 1 01 00 15 000000 000000
#--(optional)HI_OP test:-------------------------------------------------
##--andhi
# 1 00 00 0 000000 000000
# 1 00 00 1 000000 000000
# 1 2C 00 2 000000 000000
# 1 2C 00 16 110011 100001
##--orhi
# 1 00 00 1 000000 000000
# 1 34 00 2 000000 000000
# 1 34 00 16 110011 100010
##--xnorhi
# 1 00 00 1 000000 000000
# 1 3C 00 2 000000 000000
# 1 3C 00 16 110011 100011
--BREAK test:-----------------------------------------------------------
#--break
1 00 00 1 000000 000000
1 3A 34 2 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000

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cs208-ca/modelsim/Controller/in0.txt Executable file
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# 1 2 3 4 5 6
# reset_n:OP:OPX:state:op_alu_mask:op_alu
-=Controller test:======================================================
-=Testing the first version of the CPU==================================
0 00 00 0 000000 000000
--and
1 00 00 1 000000 000000
1 3A 0E 2 000000 000000
1 3A 0E 3 110011 100001
--srl
1 00 00 1 000000 000000
1 3A 1B 2 000000 000000
1 3A 1B 3 110111 110011
--addi
1 00 00 1 000000 000000
1 04 00 2 000000 000000
1 04 00 5 111000 000000
--ldw
1 00 00 1 000000 000000
1 17 00 2 000000 000000
1 17 00 7 111000 000000
1 17 00 8 000000 000000
--stw
1 00 00 1 000000 000000
1 15 00 2 000000 000000
1 15 00 9 111000 000000
--break
1 00 00 1 000000 000000
1 3A 34 2 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
0 00 00 0 000000 000000
--and
1 00 00 1 000000 000000
1 3A 0E 2 000000 000000
1 3A 0E 3 110011 100001

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cs208-ca/modelsim/Controller/in_complete.txt Executable file
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# 1 2 3 4 5 6
# reset_n:OP:OPX:state:op_alu_mask:op_alu
-=Controller test:======================================================
0 00 00 0 000000 000000
--R_OP test:------------------------------------------------------------
#--rol
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 03 2 000000 000000
1 3A 03 3 110111 110000
#--nor
1 00 00 1 000000 000000
1 3A 06 2 000000 000000
1 3A 06 3 110011 100000
#--cmple
1 00 00 1 000000 000000
1 3A 08 2 000000 000000
1 3A 08 3 111111 011001
#--ror
1 00 00 1 000000 000000
1 3A 0B 2 000000 000000
1 3A 0B 3 110111 110001
#--and
1 00 00 1 000000 000000
1 3A 0E 2 000000 000000
1 3A 0E 3 110011 100001
#--cmpgt
1 00 00 1 000000 000000
1 3A 10 2 000000 000000
1 3A 10 3 111111 011010
#--sll
1 00 00 1 000000 000000
1 3A 13 2 000000 000000
1 3A 13 3 110111 110010
#--or
1 00 00 1 000000 000000
1 3A 16 2 000000 000000
1 3A 16 3 110011 100010
#--cmpne
1 00 00 1 000000 000000
1 3A 18 2 000000 000000
1 3A 18 3 111111 011011
#--srl
1 00 00 1 000000 000000
1 3A 1B 2 000000 000000
1 3A 1B 3 110111 110011
#--xnor
1 00 00 1 000000 000000
1 3A 1E 2 000000 000000
1 3A 1E 3 110011 100011
#--cmpeq
1 00 00 1 000000 000000
1 3A 20 2 000000 000000
1 3A 20 3 111111 011100
#--cmpleu
1 00 00 1 000000 000000
1 3A 28 2 000000 000000
1 3A 28 3 111111 011101
#--cmpgtu
1 00 00 1 000000 000000
1 3A 30 2 000000 000000
1 3A 30 3 111111 011110
#--add
1 00 00 1 000000 000000
1 3A 31 2 000000 000000
1 3A 31 3 111000 000000
#--sub
1 00 00 1 000000 000000
1 3A 39 2 000000 000000
1 3A 39 3 111000 001000
#--sra
1 00 00 1 000000 000000
1 3A 3B 2 000000 000000
1 3A 3B 3 110111 110111
--RI_OP test:-----------------------------------------------------------
#--roli
1 00 00 1 000000 000000
1 3A 02 2 000000 000000
1 3A 02 4 110111 110000
#--slli
1 00 00 1 000000 000000
1 3A 12 2 000000 000000
1 3A 12 4 110111 110010
#--srli
1 00 00 1 000000 000000
1 3A 1A 2 000000 000000
1 3A 1A 4 110111 110011
#--srai
1 00 00 1 000000 000000
1 3A 3A 2 000000 000000
1 3A 3A 4 110111 110111
--I_OP test:------------------------------------------------------------
#--addi
1 00 00 1 000000 000000
1 04 00 2 000000 000000
1 04 00 5 111000 000000
#--cmplei
1 00 00 1 000000 000000
1 08 00 2 000000 000000
1 08 00 5 111111 011001
#--cmpgti
1 00 00 1 000000 000000
1 10 00 2 000000 000000
1 10 00 5 111111 011010
#--cmpnei
1 00 00 1 000000 000000
1 18 00 2 000000 000000
1 18 00 5 111111 011011
#--cmpeqi
1 00 00 1 000000 000000
1 20 00 2 000000 000000
1 20 00 5 111111 011100
--UI_OP test:-----------------------------------------------------------
#--andi
1 00 00 1 000000 000000
1 0C 00 2 000000 000000
1 0C 00 6 110011 100001
#--ori
1 00 00 1 000000 000000
1 14 00 2 000000 000000
1 14 00 6 110011 100010
#--xnori
1 00 00 1 000000 000000
1 1C 00 2 000000 000000
1 1C 00 6 110011 100011
#--cmpleui
1 00 00 1 000000 000000
1 28 00 2 000000 000000
1 28 00 6 111111 011101
#--cmpgtui
1 00 00 1 000000 000000
1 30 00 2 000000 000000
1 30 00 6 111111 011110
--LOAD test:------------------------------------------------------------
#--ldw
1 00 00 1 000000 000000
1 17 00 2 000000 000000
1 17 00 7 111000 000000
1 17 00 8 000000 000000
--STORE test:-----------------------------------------------------------
#--stw
1 00 00 1 000000 000000
1 15 00 2 000000 000000
1 15 00 9 111000 000000
--BRANCH test:----------------------------------------------------------
#--br
1 00 00 1 000000 000000
1 06 00 2 000000 000000
1 06 00 10 000000 000000
#--ble
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 0E 00 2 000000 000000
1 0E 00 10 111111 011001
#--bgt
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 16 00 2 000000 000000
1 16 00 10 111111 011010
#--bne
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 1E 00 2 000000 000000
1 1E 00 10 111111 011011
#--beq
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 26 00 2 000000 000000
1 26 00 10 111111 011100
#--bleu
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 2E 00 2 000000 000000
1 2E 00 10 111111 011101
#--bgtu
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 36 00 2 000000 000000
1 36 00 10 111111 011110
--CALL test:------------------------------------------------------------
#--call
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 00 00 2 000000 000000
1 00 00 11 000000 000000
--CALLR test:-----------------------------------------------------------
#--callr
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 1D 2 000000 000000
1 3A 1D 12 000000 000000
--JMP test:-------------------------------------------------------------
#--ret
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 05 2 000000 000000
1 3A 05 13 000000 000000
#--jmp
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 3A 0D 2 000000 000000
1 3A 0D 13 000000 000000
--JMPI test:--------------------------------------------------
#--jmpi
1 00 00 0 000000 000000
1 00 00 1 000000 000000
1 01 00 2 000000 000000
1 01 00 15 000000 000000
#--(optional)HI_OP test:-------------------------------------------------
##--andhi
# 1 00 00 0 000000 000000
# 1 00 00 1 000000 000000
# 1 2C 00 2 000000 000000
# 1 2C 00 16 110011 100001
##--orhi
# 1 00 00 1 000000 000000
# 1 34 00 2 000000 000000
# 1 34 00 16 110011 100010
##--xnorhi
# 1 00 00 1 000000 000000
# 1 3C 00 2 000000 000000
# 1 3C 00 16 110011 100011
--BREAK test:-----------------------------------------------------------
#--break
1 00 00 1 000000 000000
1 3A 34 2 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000
1 00 00 14 000000 000000

0
cs208-ca/modelsim/Controller/report.txt Executable file
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cs208-ca/modelsim/IR/in.txt Executable file
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# 1 2 3 4
# en D (vQ) Q
1 00A000A0 0 00000000
1 55CC7722 1 00A000A0
0 00000000 1 55CC7722
1 00000000 1 55CC7722
0 00000000 1 00000000

0
cs208-ca/modelsim/IR/report.txt Executable file
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24
cs208-ca/modelsim/PC/in.txt Executable file
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# 1 2 3 4 5 6 7 8 9
# reset_n:en:sel_a:sel_imm:add_imm:imm: a: (v)addr
- Program Counter test:
0 0 0 0 0 0000 0000 0 00000000
1 1 0 0 0 7FFF 7FFF 1 00000000
1 1 0 0 0 7FFF 7FFF 1 00000004
- reset_n test...
0 1 1 1 1 7FFF 7FFF 1 00000000
1 1 0 0 0 7FFF 7FFF 1 00000000
1 1 0 0 0 7FFF 7FFF 1 00000004
1 1 0 1 0 15A0 7FFF 1 00000008
- sel_imm test...
1 1 1 0 0 7FFF AA50 1 00005680
- sel_a test...
1 1 0 0 1 00A0 7FFF 1 0000AA50
- add_imm test...
1 1 0 0 1 FFB0 7FFF 1 0000AAF0
1 0 1 1 1 7FFF 7FFF 1 0000AAA0
- enable test...
1 1 0 0 0 7FFF 7FFF 1 0000AAA0
- pc+4 test...
1 1 0 0 0 7FFF 7FFF 1 0000AAA4
1 1 0 0 0 7FFF 7FFF 1 0000AAA8
1 1 0 0 0 7FFF 7FFF 1 0000AAAC

0
cs208-ca/modelsim/PC/report.txt Executable file
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7
cs208-ca/modelsim/extend/in.txt Executable file
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# 1 2 3
# signed:imm16:imm32
- Extend unit test:
0 7123 00007123
1 7456 00007456
0 8789 00008789
1 8ABC FFFF8ABC

0
cs208-ca/modelsim/extend/report.txt Executable file
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273
cs208-ca/modelsim/multicycle_niosII.cr.mti Executable file
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../vhdl/ROM_Block.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ROM_Block.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ROM_Block
-- Compiling architecture SYN of rom_block
} {} {}} ../vhdl/comparator.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/comparator.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity comparator
-- Compiling architecture synth of comparator
} {} {}} ../testbench/check_functions.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/check_functions.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Compiling package check_functions
-- Compiling package body check_functions
-- Loading package check_functions
** Warning: E:/cs208/testbench/check_functions.vhd(49): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(59): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(65): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(67): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(68): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: E:/cs208/testbench/check_functions.vhd(83): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(93): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(99): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(101): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(102): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: E:/cs208/testbench/check_functions.vhd(117): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(127): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(133): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(135): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(136): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(151): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/check_functions.vhd(161): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(167): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(169): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: E:/cs208/testbench/check_functions.vhd(170): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
} {} {}} ../vhdl/extend.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/extend.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity extend
-- Compiling architecture synth of extend
} {} {}} ../vhdl/mux2x5.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x5.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x5
-- Compiling architecture synth of mux2x5
} {} {}} ../vhdl/ALU.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ALU.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ALU
-- Compiling architecture bdf_type of ALU
} {} {}} ../vhdl/add_sub.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/add_sub.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity add_sub
-- Compiling architecture synth of add_sub
} {} {}} ../vhdl/PC.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/PC.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity PC
-- Compiling architecture synth of PC
} {} {}} ../vhdl/multiplexer.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/multiplexer.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity multiplexer
-- Compiling architecture synth of multiplexer
} {} {}} ../vhdl/IR.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/IR.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity IR
-- Compiling architecture synth of IR
} {} {}} ../vhdl/controller.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/controller.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity controller
-- Compiling architecture synth of controller
} {} {}} ../vhdl/register_file.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/register_file.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity register_file
-- Compiling architecture synth of register_file
} {} {}} ../vhdl/ROM.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/ROM.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity ROM
-- Compiling architecture synth of ROM
} {} {}} ../vhdl/buttons.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/buttons.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity buttons
-- Compiling architecture synth of buttons
} {} {}} ../testbench/tb_Extend.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_Extend.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_Extend
-- Compiling architecture testbench of tb_Extend
** Warning: E:/cs208/testbench/tb_Extend.vhd(40): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_Extend.vhd(42): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
} {} {}} ../vhdl/RAM.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/RAM.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity RAM
-- Compiling architecture synth of RAM
} {} {}} ../vhdl/LEDs.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/LEDs.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity LEDs
-- Compiling architecture synth of LEDs
} {} {}} ../vhdl/CPU.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/CPU.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity CPU
-- Compiling architecture bdf_type of CPU
} {} {}} ../testbench/tb_GECKO.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_GECKO.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity tb_GECKO
-- Compiling architecture testbench of tb_GECKO
-- Loading entity GECKO
} {} {}} ../vhdl/GECKO.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/GECKO.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity GECKO
-- Compiling architecture bdf_type of GECKO
} {} {}} ../vhdl/mux2x32.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x32.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x32
-- Compiling architecture synth of mux2x32
} {} {}} ../testbench/tb_IR.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_IR.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_IR
-- Compiling architecture testbench of tb_IR
** Warning: E:/cs208/testbench/tb_IR.vhd(42): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_IR.vhd(44): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
} {} {}} ../testbench/tb_PC.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_PC.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_PC
-- Compiling architecture testbench of tb_PC
** Warning: E:/cs208/testbench/tb_PC.vhd(57): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_PC.vhd(59): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
} {} {}} ../vhdl/mux2x16.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/mux2x16.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x16
-- Compiling architecture synth of mux2x16
} {} {}} ../testbench/tb_Controller.vhd {2 {vcom -work work -2002 -explicit -stats=none E:/cs208/testbench/tb_Controller.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_Controller
-- Compiling architecture testbench of tb_Controller
** Warning: E:/cs208/testbench/tb_Controller.vhd(129): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: E:/cs208/testbench/tb_Controller.vhd(130): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
} {} {}} ../vhdl/logic_unit.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/logic_unit.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity logic_unit
-- Compiling architecture synth of logic_unit
} {} {}} ../vhdl/shift_unit.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/shift_unit.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity shift_unit
-- Compiling architecture synth of shift_unit
} {} {}} ../vhdl/decoder.vhd {1 {vcom -work work -2002 -explicit -stats=none E:/cs208/vhdl/decoder.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity decoder
-- Compiling architecture synth of decoder
} {} {}}

518
cs208-ca/modelsim/multicycle_niosII.mpf Executable file
View File

@@ -0,0 +1,518 @@
; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
; Altera Primitive libraries
;
; VHDL Section
;
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
maxii = $MODEL_TECH/../altera/vhdl/maxii
maxv = $MODEL_TECH/../altera/vhdl/maxv
fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
sgate = $MODEL_TECH/../altera/vhdl/sgate
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
arriav = $MODEL_TECH/../altera/vhdl/arriav
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
twentynm = $MODEL_TECH/../altera/vhdl/twentynm
twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
fourteennm = $MODEL_TECH/../altera/vhdl/fourteennm
;
; Verilog Section
;
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
fourteennm_ver = $MODEL_TECH/../altera/verilog/fourteennm
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Default or value of 3 or 2008 for VHDL-2008.
VHDL93 = 2002
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
; Turns on lint-style checking.
; Show_Lint = 1
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
; Default run length
RunLength = 100 ps
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
; VSIM Startup command
; Startup = do startup.do
; File for saving command transcript
TranscriptFile = transcript
; File for saving command history
; CommandHistory = cmdhist.log
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
[lmc]
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 28
Project_File_0 = ../testbench/check_functions.vhd
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_1 = ../vhdl/extend.vhd
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_2 = ../vhdl/ROM_Block.vhd
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 26 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_3 = ../vhdl/comparator.vhd
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_4 = ../vhdl/mux2x5.vhd
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_5 = ../vhdl/ALU.vhd
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_6 = ../vhdl/add_sub.vhd
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_7 = ../vhdl/PC.vhd
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540372638 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_8 = ../vhdl/IR.vhd
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_9 = ../vhdl/multiplexer.vhd
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_10 = ../vhdl/controller.vhd
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540374794 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_11 = ../vhdl/register_file.vhd
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540371264 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_12 = ../vhdl/ROM.vhd
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540375298 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_13 = ../testbench/tb_Extend.vhd
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_14 = ../vhdl/buttons.vhd
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_15 = ../vhdl/RAM.vhd
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540375470 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_16 = ../vhdl/LEDs.vhd
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540372438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 20 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_17 = ../testbench/tb_GECKO.vhd
Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_18 = ../vhdl/CPU.vhd
Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_19 = ../vhdl/GECKO.vhd
Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_20 = ../vhdl/mux2x32.vhd
Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_21 = ../testbench/tb_IR.vhd
Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_22 = ../testbench/tb_PC.vhd
Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_23 = ../testbench/tb_Controller.vhd
Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_24 = ../vhdl/mux2x16.vhd
Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_25 = ../vhdl/shift_unit.vhd
Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_26 = ../vhdl/logic_unit.vhd
Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540165438 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_27 = ../vhdl/decoder.vhd
Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1540372776 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
TDB_DoubleClick = Edit
TDB_CustomDoubleClick =
UPF_DoubleClick = Edit
UPF_CustomDoubleClick =
PCF_DoubleClick = Edit
PCF_CustomDoubleClick =
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick =
VRM_DoubleClick = Edit
VRM_CustomDoubleClick =
DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 10
Project_Minor_Version = 5

12
cs208-ca/modelsim/test_Controller.do Executable file
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@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/controller.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_Controller.vhd
vsim -Gtext_in=Controller/in.txt tb_Controller
add wave -hex controller_0/*
run -all

12
cs208-ca/modelsim/test_Controller0.do Executable file
View File

@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/controller.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_Controller.vhd
vsim -Gtext_in=Controller/in0.txt tb_Controller
add wave -hex controller_0/*
run -all

12
cs208-ca/modelsim/test_Controller_complete.do Executable file
View File

@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/controller.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_Controller.vhd
vsim -Gtext_in=Controller/in_complete.txt tb_Controller
add wave -hex controller_0/*
run -all

12
cs208-ca/modelsim/test_Extend.do Executable file
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@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/extend.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_Extend.vhd
vsim tb_Extend
add wave -hex extend_0/*
run -all

12
cs208-ca/modelsim/test_IR.do Executable file
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@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/IR.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_IR.vhd
vsim tb_IR
add wave -hex ir_0/*
run -all

12
cs208-ca/modelsim/test_PC.do Executable file
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@@ -0,0 +1,12 @@
vlib work
vmap work work
vcom -93 ../vhdl/PC.vhd
vcom -93 ../testbench/check_functions.vhd
vcom -93 ../testbench/tb_PC.vhd
vsim tb_PC
add wave -hex pc_0/*
run -all

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cs208-ca/modelsim/vsim.wlf Executable file
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1140
cs208-ca/modelsim/work/_info Executable file
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BIN
cs208-ca/modelsim/work/_lib.qdb Executable file
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BIN
cs208-ca/modelsim/work/_lib1_104.qdb Executable file
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cs208-ca/modelsim/work/_lib1_104.qpg Executable file
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cs208-ca/modelsim/work/_lib1_104.qtl Executable file
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4
cs208-ca/modelsim/work/_vmake Executable file
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@@ -0,0 +1,4 @@
m255
K4
z0
cModel Technology

518
cs208-ca/quartus/ALU.bdf Executable file
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@@ -0,0 +1,518 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(pt 416 128)
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(connector
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(junction (pt 432 -120))
(junction (pt 496 -64))

63
cs208-ca/quartus/ALU.bsf Executable file
View File

@@ -0,0 +1,63 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 64 64 152 176)
(text "ALU" (rect 5 0 29 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 96 25 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "A" (rect 8 16 17 30)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 24 32)(line_width 3))
)
(port
(pt 0 80)
(input)
(text "b[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "B" (rect 8 64 16 78)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 24 80)(line_width 3))
)
(port
(pt 48 0)
(input)
(text "op[5..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "OP" (rect 56 8 70 24)(font "Arial" (font_size 8))(vertical))
(line (pt 48 0)(pt 48 32)(line_width 3))
)
(port
(pt 88 56)
(output)
(text "s[31..0]" (rect -48 0 -6 14)(font "Arial" (font_size 8)))
(text "S" (rect 72 40 80 54)(font "Arial" (font_size 8)))
(line (pt 88 56)(pt 64 56)(line_width 3))
)
(drawing
(line (pt 24 48)(pt 40 56)(line_width 1))
(line (pt 40 56)(pt 24 64)(line_width 1))
(line (pt 24 64)(pt 24 96)(line_width 1))
(line (pt 24 48)(pt 24 16)(line_width 1))
(line (pt 64 72)(pt 64 40)(line_width 1))
(line (pt 64 40)(pt 24 16)(line_width 1))
(line (pt 64 72)(pt 24 96)(line_width 1))
)
)

1411
cs208-ca/quartus/CPU.bdf Executable file
View File

File diff suppressed because it is too large Load Diff

78
cs208-ca/quartus/CPU.bsf Executable file
View File

@@ -0,0 +1,78 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 64 48 272 176)
(text "CPU" (rect 5 0 28 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 112 25 124)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 16 15 30)(font "Arial" (font_size 8)))
(text "clk" (rect 21 27 36 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "reset_n" (rect 0 16 43 30)(font "Arial" (font_size 8)))
(text "reset_n" (rect 21 43 64 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 208 96)
(input)
(text "rddata[31..0]" (rect 0 16 71 30)(font "Arial" (font_size 8)))
(text "rddata[31..0]" (rect 113 88 184 102)(font "Arial" (font_size 8)))
(line (pt 192 96)(pt 208 96)(line_width 3))
)
(port
(pt 208 48)
(output)
(text "write" (rect 0 16 29 30)(font "Arial" (font_size 8)))
(text "write" (rect 158 43 187 57)(font "Arial" (font_size 8)))
(line (pt 208 48)(pt 192 48)(line_width 1))
)
(port
(pt 208 80)
(output)
(text "wrdata[31..0]" (rect 0 16 76 30)(font "Arial" (font_size 8)))
(text "wrdata[31..0]" (rect 111 75 187 89)(font "Arial" (font_size 8)))
(line (pt 208 80)(pt 192 80)(line_width 3))
)
(port
(pt 208 64)
(output)
(text "address[15..0]" (rect 0 16 82 30)(font "Arial" (font_size 8)))
(text "address[15..0]" (rect 105 59 187 73)(font "Arial" (font_size 8)))
(line (pt 208 64)(pt 192 64)(line_width 3))
)
(port
(pt 208 32)
(output)
(text "read" (rect 158 24 183 38)(font "Arial" (font_size 8)))
(text "read" (rect 158 24 183 38)(font "Arial" (font_size 8)))
(line (pt 208 32)(pt 192 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 192 112)(line_width 1))
)
)

91
cs208-ca/quartus/GECKO.asm.rpt Executable file
View File

@@ -0,0 +1,91 @@
Assembler report for GECKO
Wed Oct 24 12:09:01 2018
Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: E:/cs208/quartus/GECKO.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Oct 24 12:09:01 2018 ;
; Revision Name ; GECKO ;
; Top-level Entity Name ; GECKO ;
; Family ; Cyclone IV E ;
; Device ; EP4CE30F23C8 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+----------------------------+
; Assembler Generated Files ;
+----------------------------+
; File Name ;
+----------------------------+
; E:/cs208/quartus/GECKO.sof ;
+----------------------------+
+------------------------------------------------------+
; Assembler Device Options: E:/cs208/quartus/GECKO.sof ;
+----------------+-------------------------------------+
; Option ; Setting ;
+----------------+-------------------------------------+
; JTAG usercode ; 0x00430753 ;
; Checksum ; 0x00430753 ;
+----------------+-------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
Info: Processing started: Wed Oct 24 12:08:58 2018
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GECKO -c GECKO
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4707 megabytes
Info: Processing ended: Wed Oct 24 12:09:01 2018
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02

967
cs208-ca/quartus/GECKO.bdf Executable file
View File

@@ -0,0 +1,967 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
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(pt 1248 208)
)
(connector
(pt 1192 224)
(pt 1248 224)
)
(connector
(pt 1192 240)
(pt 1248 240)
)
(connector
(pt 1208 256)
(pt 1248 256)
)
(connector
(pt 1120 -200)
(pt 1120 -184)
(bus)
)
(connector
(pt 1120 -184)
(pt 1120 -168)
(bus)
)
(connector
(pt 1120 -168)
(pt 1120 -152)
(bus)
)
(connector
(pt 1120 -152)
(pt 1120 -136)
(bus)
)
(connector
(pt 1120 -136)
(pt 1120 -120)
(bus)
)
(connector
(pt 1120 -120)
(pt 1120 -104)
(bus)
)
(connector
(pt 1120 -104)
(pt 1120 -88)
(bus)
)
(connector
(pt 1328 96)
(pt 1328 160)
(bus)
)
(connector
(text "out_LEDs[95..0]" (rect 1096 1 1110 124)(font "Arial" )(vertical))
(pt 1120 -88)
(pt 1120 160)
(bus)
)
(connector
(text "out_LEDs[95..84]" (rect 1120 -216 1252 -202)(font "Arial" ))
(pt 1120 -200)
(pt 1192 -200)
(bus)
)
(connector
(text "out_LEDs[83..72]" (rect 1120 -200 1252 -186)(font "Arial" ))
(pt 1120 -184)
(pt 1192 -184)
(bus)
)
(connector
(text "out_LEDs[71..60]" (rect 1120 -184 1252 -170)(font "Arial" ))
(pt 1120 -168)
(pt 1192 -168)
(bus)
)
(connector
(text "out_LEDs[59..48]" (rect 1120 -168 1252 -154)(font "Arial" ))
(pt 1120 -152)
(pt 1192 -152)
(bus)
)
(connector
(text "out_LEDs[47..36]" (rect 1120 -152 1252 -138)(font "Arial" ))
(pt 1120 -136)
(pt 1192 -136)
(bus)
)
(connector
(text "out_LEDs[35..24]" (rect 1120 -136 1252 -122)(font "Arial" ))
(pt 1120 -120)
(pt 1192 -120)
(bus)
)
(connector
(text "out_LEDs[23..12]" (rect 1120 -120 1252 -106)(font "Arial" ))
(pt 1120 -104)
(pt 1192 -104)
(bus)
)
(connector
(text "out_LEDs[11..0]" (rect 1120 -104 1243 -90)(font "Arial" ))
(pt 1120 -88)
(pt 1192 -88)
(bus)
)
(junction (pt 784 376))
(junction (pt 1008 376))
(junction (pt 464 392))
(junction (pt 672 392))
(junction (pt 880 392))
(junction (pt 1104 392))
(junction (pt 896 408))
(junction (pt 1120 408))
(junction (pt 688 424))
(junction (pt 912 424))
(junction (pt 1136 424))
(junction (pt 600 360))
(junction (pt 768 360))
(junction (pt 992 360))
(junction (pt 1120 -184))
(junction (pt 1120 -168))
(junction (pt 1120 -152))
(junction (pt 1120 -136))
(junction (pt 1120 -120))
(junction (pt 1120 -104))
(junction (pt 1120 -88))

1
cs208-ca/quartus/GECKO.done Executable file
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Wed Oct 24 12:09:12 2018

2197
cs208-ca/quartus/GECKO.fit.rpt Executable file
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File diff suppressed because it is too large Load Diff

8
cs208-ca/quartus/GECKO.fit.smsg Executable file
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Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

16
cs208-ca/quartus/GECKO.fit.summary Executable file
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Fitter Status : Successful - Wed Oct 24 12:08:53 2018
Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Lite Edition
Revision Name : GECKO
Top-level Entity Name : GECKO
Family : Cyclone IV E
Device : EP4CE30F23C8
Timing Models : Final
Total logic elements : 2,710 / 28,848 ( 9 % )
Total combinational functions : 2,508 / 28,848 ( 9 % )
Dedicated logic registers : 1,180 / 28,848 ( 4 % )
Total registers : 1180
Total pins : 102 / 329 ( 31 % )
Total virtual pins : 0
Total memory bits : 65,536 / 608,256 ( 11 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

127
cs208-ca/quartus/GECKO.flow.rpt Executable file
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Flow report for GECKO
Wed Oct 24 12:09:10 2018
Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Wed Oct 24 12:09:01 2018 ;
; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Lite Edition ;
; Revision Name ; GECKO ;
; Top-level Entity Name ; GECKO ;
; Family ; Cyclone IV E ;
; Device ; EP4CE30F23C8 ;
; Timing Models ; Final ;
; Total logic elements ; 2,710 / 28,848 ( 9 % ) ;
; Total combinational functions ; 2,508 / 28,848 ( 9 % ) ;
; Dedicated logic registers ; 1,180 / 28,848 ( 4 % ) ;
; Total registers ; 1180 ;
; Total pins ; 102 / 329 ( 31 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 65,536 / 608,256 ( 11 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/24/2018 12:06:16 ;
; Main task ; Compilation ;
; Revision Name ; GECKO ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 10995770589196.154037557603964 ; -- ; -- ; -- ;
; ENABLE_SIGNALTAP ; Off ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; SMART_RECOMPILE ; On ; Off ; -- ; -- ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_palace ;
; USE_SIGNALTAP_FILE ; stp1.stp ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:27 ; 1.0 ; 4843 MB ; 00:00:39 ;
; Fitter ; 00:02:09 ; 1.0 ; 5647 MB ; 00:02:20 ;
; Assembler ; 00:00:03 ; 1.0 ; 4707 MB ; 00:00:02 ;
; Timing Analyzer ; 00:00:08 ; 1.2 ; 4847 MB ; 00:00:05 ;
; Total ; 00:02:47 ; -- ; -- ; 00:03:06 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; ICIN3PC41 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; ICIN3PC41 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; ICIN3PC41 ; Windows 10 ; 10.0 ; x86_64 ;
; Timing Analyzer ; ICIN3PC41 ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off GECKO -c GECKO
quartus_fit --read_settings_files=off --write_settings_files=off GECKO -c GECKO
quartus_asm --read_settings_files=off --write_settings_files=off GECKO -c GECKO
quartus_sta GECKO -c GECKO

8
cs208-ca/quartus/GECKO.jdi Executable file
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<sld_project_info>
<project>
<hash md5_digest_80b="ff312d1fe4f04416975e"/>
</project>
<file_info>
<file device="EP4CE30F23C8" path="GECKO.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

891
cs208-ca/quartus/GECKO.map.rpt Executable file
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Analysis & Synthesis report for GECKO
Wed Oct 24 12:06:43 2018
Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. State Machine - |GECKO|CPU:inst|controller:controller_0|s_cur
10. User-Specified and Inferred Latches
11. Registers Removed During Synthesis
12. Removed Registers Triggering Further Register Optimizations
13. General Register Statistics
14. Inverted Register Statistics
15. Registers Packed Into Inferred Megafunctions
16. Multiplexer Restructuring Statistics (Restructuring Performed)
17. Source assignments for ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated
18. Source assignments for RAM:RAM_0|altsyncram:reg_rtl_0|altsyncram_u781:auto_generated
19. Parameter Settings for User Entity Instance: ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component
20. Parameter Settings for Inferred Entity Instance: RAM:RAM_0|altsyncram:reg_rtl_0
21. altsyncram Parameter Settings by Entity Instance
22. Post-Synthesis Netlist Statistics for Top Partition
23. Elapsed Time Per Partition
24. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Oct 24 12:06:43 2018 ;
; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Lite Edition ;
; Revision Name ; GECKO ;
; Top-level Entity Name ; GECKO ;
; Family ; Cyclone IV E ;
; Total logic elements ; 3,537 ;
; Total combinational functions ; 2,508 ;
; Dedicated logic registers ; 1,180 ;
; Total registers ; 1180 ;
; Total pins ; 102 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 65,536 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP4CE30F23C8 ; ;
; Top-level entity name ; GECKO ; GECKO ;
; Family name ; Cyclone IV E ; Cyclone V ;
; Use smart compilation ; On ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.1% ;
; Processor 3 ; 0.0% ;
; Processor 4 ; 0.0% ;
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------+---------+
; GECKO.bdf ; yes ; User Block Diagram/Schematic File ; E:/cs208/quartus/GECKO.bdf ; ;
; ALU.bdf ; yes ; User Block Diagram/Schematic File ; E:/cs208/quartus/ALU.bdf ; ;
; CPU.bdf ; yes ; User Block Diagram/Schematic File ; E:/cs208/quartus/CPU.bdf ; ;
; ../vhdl/add_sub.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/add_sub.vhd ; ;
; ../vhdl/buttons.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/buttons.vhd ; ;
; ../vhdl/comparator.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/comparator.vhd ; ;
; ../vhdl/controller.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/controller.vhd ; ;
; ../vhdl/decoder.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/decoder.vhd ; ;
; ../vhdl/extend.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/extend.vhd ; ;
; ../vhdl/IR.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/IR.vhd ; ;
; ../vhdl/LEDs.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/LEDs.vhd ; ;
; ../vhdl/logic_unit.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/logic_unit.vhd ; ;
; ../vhdl/multiplexer.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/multiplexer.vhd ; ;
; ../vhdl/mux2x5.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/mux2x5.vhd ; ;
; ../vhdl/mux2x16.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/mux2x16.vhd ; ;
; ../vhdl/mux2x32.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/mux2x32.vhd ; ;
; ../vhdl/PC.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/PC.vhd ; ;
; ../vhdl/RAM.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/RAM.vhd ; ;
; ../vhdl/register_file.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/register_file.vhd ; ;
; ../vhdl/ROM.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/ROM.vhd ; ;
; ../vhdl/ROM_Block.vhd ; yes ; User Wizard-Generated File ; E:/cs208/vhdl/ROM_Block.vhd ; ;
; ../vhdl/shift_unit.vhd ; yes ; User VHDL File ; E:/cs208/vhdl/shift_unit.vhd ; ;
; ROM.hex ; yes ; User Hexadecimal (Intel-Format) File ; E:/cs208/quartus/ROM.hex ; ;
; altsyncram.tdf ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; aglobal180.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/aglobal180.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altram.inc ; ;
; altdpram.inc ; yes ; Megafunction ; c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altdpram.inc ; ;
; db/altsyncram_rna1.tdf ; yes ; Auto-Generated Megafunction ; E:/cs208/quartus/db/altsyncram_rna1.tdf ; ;
; db/altsyncram_u781.tdf ; yes ; Auto-Generated Megafunction ; E:/cs208/quartus/db/altsyncram_u781.tdf ; ;
; db/gecko.ram0_ram_15119.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; E:/cs208/quartus/db/gecko.ram0_ram_15119.hdl.mif ; ;
+----------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------+---------+
+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-----------+
; Resource ; Usage ;
+---------------------------------------------+-----------+
; Estimated Total logic elements ; 3,537 ;
; ; ;
; Total combinational functions ; 2508 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 1959 ;
; -- 3 input functions ; 377 ;
; -- <=2 input functions ; 172 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 2448 ;
; -- arithmetic mode ; 60 ;
; ; ;
; Total registers ; 1180 ;
; -- Dedicated logic registers ; 1180 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 102 ;
; Total memory bits ; 65536 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Maximum fan-out node ; clk~input ;
; Maximum fan-out ; 1244 ;
; Total fan-out ; 13957 ;
; Average fan-out ; 3.53 ;
+---------------------------------------------+-----------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------+-----------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------+-----------------+--------------+
; |GECKO ; 2508 (113) ; 1180 (0) ; 65536 ; 0 ; 0 ; 0 ; 102 ; 0 ; |GECKO ; GECKO ; work ;
; |CPU:inst| ; 2248 (3) ; 1054 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst ; CPU ; work ;
; |ALU:alu_0| ; 495 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0 ; ALU ; work ;
; |add_sub:add_sub_0| ; 77 (77) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0|add_sub:add_sub_0 ; add_sub ; work ;
; |comparator:comparator_0| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0|comparator:comparator_0 ; comparator ; work ;
; |logic_unit:logic_unit_0| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0|logic_unit:logic_unit_0 ; logic_unit ; work ;
; |multiplexer:multiplexer_0| ; 81 (81) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0|multiplexer:multiplexer_0 ; multiplexer ; work ;
; |shift_unit:shift_unit_0| ; 322 (322) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0 ; shift_unit ; work ;
; |IR:IR_0| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|IR:IR_0 ; IR ; work ;
; |PC:PC_0| ; 42 (42) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|PC:PC_0 ; PC ; work ;
; |controller:controller_0| ; 183 (183) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|controller:controller_0 ; controller ; work ;
; |mux2x16:mux_addr| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|mux2x16:mux_addr ; mux2x16 ; work ;
; |mux2x32:mux_b| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|mux2x32:mux_b ; mux2x32 ; work ;
; |mux2x32:mux_data| ; 140 (140) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|mux2x32:mux_data ; mux2x32 ; work ;
; |mux2x5:mux_aw| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|mux2x5:mux_aw ; mux2x5 ; work ;
; |register_file:register_file_0| ; 1334 (1334) ; 992 (992) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|CPU:inst|register_file:register_file_0 ; register_file ; work ;
; |LEDs:LEDs_0| ; 122 (122) ; 115 (115) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|LEDs:LEDs_0 ; LEDs ; work ;
; |RAM:RAM_0| ; 2 (2) ; 1 (1) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|RAM:RAM_0 ; RAM ; work ;
; |altsyncram:reg_rtl_0| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|RAM:RAM_0|altsyncram:reg_rtl_0 ; altsyncram ; work ;
; |altsyncram_u781:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|RAM:RAM_0|altsyncram:reg_rtl_0|altsyncram_u781:auto_generated ; altsyncram_u781 ; work ;
; |ROM:ROM_0| ; 4 (4) ; 1 (1) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|ROM:ROM_0 ; ROM ; work ;
; |ROM_Block:romblock| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|ROM:ROM_0|ROM_Block:romblock ; ROM_Block ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component ; altsyncram ; work ;
; |altsyncram_rna1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated ; altsyncram_rna1 ; work ;
; |buttons:buttons_0| ; 8 (8) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|buttons:buttons_0 ; buttons ; work ;
; |decoder:decoder_0| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GECKO|decoder:decoder_0 ; decoder ; work ;
+----------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------+-----------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+-------+---------------------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+-------+---------------------------------+
; RAM:RAM_0|altsyncram:reg_rtl_0|altsyncram_u781:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 1024 ; 32 ; -- ; -- ; 32768 ; db/GECKO.ram0_RAM_15119.hdl.mif ;
; ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 1024 ; 32 ; -- ; -- ; 32768 ; ../quartus/ROM.hex ;
+--------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+-------+---------------------------------+
Encoding Type: One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |GECKO|CPU:inst|controller:controller_0|s_cur ;
+--------------+-------------+-------------+------------+-----------+-------------+------------+--------------+-------------+------------+-------------+-------------+-------------+------------+--------------+--------------+--------------+
; Name ; s_cur.RI_OP ; s_cur.UI_OP ; s_cur.JMPI ; s_cur.JMP ; s_cur.CALLR ; s_cur.CALL ; s_cur.BRANCH ; s_cur.LOAD2 ; s_cur.I_OP ; s_cur.LOAD1 ; s_cur.BREAK ; s_cur.STORE ; s_cur.R_OP ; s_cur.DECODE ; s_cur.FETCH2 ; s_cur.FETCH1 ;
+--------------+-------------+-------------+------------+-----------+-------------+------------+--------------+-------------+------------+-------------+-------------+-------------+------------+--------------+--------------+--------------+
; s_cur.FETCH1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; s_cur.FETCH2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; s_cur.DECODE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; s_cur.R_OP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; s_cur.STORE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.BREAK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.LOAD1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.I_OP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.LOAD2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.BRANCH ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.CALL ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.CALLR ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.JMP ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.JMPI ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.UI_OP ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; s_cur.RI_OP ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+--------------+-------------+-------------+------------+-----------+-------------+------------+--------------+-------------+------------+-------------+-------------+-------------+------------+--------------+--------------+--------------+
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; CPU:inst|controller:controller_0|s_next.R_OP_1618 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.BRANCH_1408 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.STORE_1583 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.LOAD1_1513 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.I_OP_1478 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.LOAD2_1443 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.CALL_1373 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.CALLR_1338 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.RI_OP_1198 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.UI_OP_1233 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.FETCH2_1688 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.JMP_1303 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.JMPI_1268 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.FETCH1_1723 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.DECODE_1653 ; GND ; yes ;
; CPU:inst|controller:controller_0|s_next.BREAK_1548 ; GND ; yes ;
; Number of user-specified and inferred latches = 16 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+--------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------------------+----------------------------------------+
; CPU:inst|register_file:register_file_0|reg[0][0] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][1] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][2] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][3] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][4] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][5] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][6] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][7] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][8] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][9] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][10] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][11] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][12] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][13] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][14] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][15] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][16] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][17] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][18] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][19] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][20] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][21] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][22] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][23] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][24] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][25] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][26] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][27] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][28] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][29] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][30] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|register_file:register_file_0|reg[0][31] ; Stuck at GND due to stuck port data_in ;
; CPU:inst|PC:PC_0|n_addr[0,1] ; Stuck at GND due to stuck port data_in ;
; buttons:buttons_0|read_reg ; Lost fanout ;
; CPU:inst|PC:PC_0|n_addr[16..31] ; Lost fanout ;
; Total Number of Removed Registers = 51 ; ;
+---------------------------------------------------+----------------------------------------+
+------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+---------------------------------------------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+---------------------------------------------------+---------------------------+----------------------------------------+
; CPU:inst|register_file:register_file_0|reg[0][31] ; Stuck at GND ; buttons:buttons_0|read_reg ;
; ; due to stuck port data_in ; ;
+---------------------------------------------------+---------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 1180 ;
; Number of registers using Synchronous Clear ; 8 ;
; Number of registers using Synchronous Load ; 14 ;
; Number of registers using Asynchronous Clear ; 154 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 1142 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; LEDs:LEDs_0|duty_cycle[3] ; 2 ;
; LEDs:LEDs_0|duty_cycle[2] ; 2 ;
; LEDs:LEDs_0|duty_cycle[1] ; 2 ;
; LEDs:LEDs_0|duty_cycle[0] ; 2 ;
; buttons:buttons_0|buttons_reg[0] ; 1 ;
; buttons:buttons_0|buttons_reg[1] ; 1 ;
; buttons:buttons_0|buttons_reg[3] ; 1 ;
; buttons:buttons_0|buttons_reg[2] ; 1 ;
; Total number of inverted registers = 8 ; ;
+----------------------------------------+---------+
+----------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions ;
+-----------------------------+---------------------+------+
; Register Name ; Megafunction ; Type ;
+-----------------------------+---------------------+------+
; RAM:RAM_0|reg_address[0..9] ; RAM:RAM_0|reg_rtl_0 ; RAM ;
+-----------------------------+---------------------+------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------+
; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GECKO|CPU:inst|PC:PC_0|n_addr[22] ;
; 3:1 ; 14 bits ; 28 LEs ; 28 LEs ; 0 LEs ; Yes ; |GECKO|CPU:inst|PC:PC_0|n_addr[15] ;
; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0|v ;
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0|v ;
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0|v ;
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|ALU:alu_0|shift_unit:shift_unit_0|v ;
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|mux2x32:mux_data|o[1] ;
; 3:1 ; 14 bits ; 28 LEs ; 28 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|mux2x32:mux_data|o[9] ;
; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|mux2x5:mux_aw|o[0] ;
; 32:1 ; 32 bits ; 672 LEs ; 640 LEs ; 32 LEs ; No ; |GECKO|CPU:inst|register_file:register_file_0|Mux1 ;
; 32:1 ; 32 bits ; 672 LEs ; 640 LEs ; 32 LEs ; No ; |GECKO|CPU:inst|register_file:register_file_0|Mux48 ;
; 7:1 ; 24 bits ; 96 LEs ; 72 LEs ; 24 LEs ; No ; |GECKO|rddata[17] ;
; 7:1 ; 4 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |GECKO|rddata[6] ;
; 8:1 ; 4 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GECKO|rddata[1] ;
; 14:1 ; 15 bits ; 135 LEs ; 90 LEs ; 45 LEs ; No ; |GECKO|CPU:inst|ALU:alu_0|multiplexer:multiplexer_0|o[4] ;
; 16:1 ; 14 bits ; 140 LEs ; 126 LEs ; 14 LEs ; No ; |GECKO|CPU:inst|mux2x32:mux_data|o[29] ;
; 16:1 ; 2 bits ; 20 LEs ; 6 LEs ; 14 LEs ; No ; |GECKO|CPU:inst|controller:controller_0|s_next.JMPI ;
; 22:1 ; 2 bits ; 28 LEs ; 28 LEs ; 0 LEs ; No ; |GECKO|CPU:inst|controller:controller_0|op_alu[1] ;
; 23:1 ; 2 bits ; 30 LEs ; 24 LEs ; 6 LEs ; No ; |GECKO|CPU:inst|controller:controller_0|op_alu[4] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------------------------------------+
+--------------------------------------------------------------------------------------+
; Source assignments for RAM:RAM_0|altsyncram:reg_rtl_0|altsyncram_u781:auto_generated ;
+---------------------------------+--------------------+------+------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------+
+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+-----------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+-----------------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 32 ; Signed Integer ;
; WIDTHAD_A ; 10 ; Signed Integer ;
; NUMWORDS_A ; 1024 ; Signed Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; ../quartus/ROM.hex ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_rna1 ; Untyped ;
+------------------------------------+----------------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: RAM:RAM_0|altsyncram:reg_rtl_0 ;
+------------------------------------+---------------------------------+----------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+---------------------------------+----------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
; WIDTH_A ; 32 ; Untyped ;
; WIDTHAD_A ; 10 ; Untyped ;
; NUMWORDS_A ; 1024 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; db/GECKO.ram0_RAM_15119.hdl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_u781 ; Untyped ;
+------------------------------------+---------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+--------------------------------------------------------------+
; Name ; Value ;
+-------------------------------------------+--------------------------------------------------------------+
; Number of entity instances ; 2 ;
; Entity Instance ; ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 32 ;
; -- NUMWORDS_A ; 1024 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; RAM:RAM_0|altsyncram:reg_rtl_0 ;
; -- OPERATION_MODE ; SINGLE_PORT ;
; -- WIDTH_A ; 32 ;
; -- NUMWORDS_A ; 1024 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+--------------------------------------------------------------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; boundary_port ; 102 ;
; cycloneiii_ff ; 1180 ;
; CLR ; 28 ;
; CLR SCLR ; 8 ;
; ENA ; 1024 ;
; ENA CLR ; 104 ;
; ENA CLR SLD ; 14 ;
; plain ; 2 ;
; cycloneiii_lcell_comb ; 2508 ;
; arith ; 60 ;
; 2 data inputs ; 8 ;
; 3 data inputs ; 52 ;
; normal ; 2448 ;
; 0 data inputs ; 1 ;
; 1 data inputs ; 10 ;
; 2 data inputs ; 153 ;
; 3 data inputs ; 325 ;
; 4 data inputs ; 1959 ;
; cycloneiii_ram_block ; 64 ;
; ; ;
; Max LUT depth ; 22.50 ;
; Average LUT depth ; 16.46 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:10 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
Info: Processing started: Wed Oct 24 12:06:15 2018
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GECKO -c GECKO
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file gecko.bdf
Info (12023): Found entity 1: GECKO
Info (12021): Found 1 design units, including 1 entities, in source file alu.bdf
Info (12023): Found entity 1: ALU
Info (12021): Found 1 design units, including 1 entities, in source file cpu.bdf
Info (12023): Found entity 1: CPU
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/add_sub.vhd
Info (12022): Found design unit 1: add_sub-synth File: E:/cs208/vhdl/add_sub.vhd Line: 16
Info (12023): Found entity 1: add_sub File: E:/cs208/vhdl/add_sub.vhd Line: 5
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/buttons.vhd
Info (12022): Found design unit 1: buttons-synth File: E:/cs208/vhdl/buttons.vhd Line: 22
Info (12023): Found entity 1: buttons File: E:/cs208/vhdl/buttons.vhd Line: 5
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/comparator.vhd
Info (12022): Found design unit 1: comparator-synth File: E:/cs208/vhdl/comparator.vhd Line: 16
Info (12023): Found entity 1: comparator File: E:/cs208/vhdl/comparator.vhd Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/controller.vhd
Info (12022): Found design unit 1: controller-synth File: E:/cs208/vhdl/controller.vhd Line: 39
Info (12023): Found entity 1: controller File: E:/cs208/vhdl/controller.vhd Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/decoder.vhd
Info (12022): Found design unit 1: decoder-synth File: E:/cs208/vhdl/decoder.vhd Line: 14
Info (12023): Found entity 1: decoder File: E:/cs208/vhdl/decoder.vhd Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/extend.vhd
Info (12022): Found design unit 1: extend-synth File: E:/cs208/vhdl/extend.vhd Line: 12
Info (12023): Found entity 1: extend File: E:/cs208/vhdl/extend.vhd Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/ir.vhd
Info (12022): Found design unit 1: IR-synth File: E:/cs208/vhdl/IR.vhd Line: 13
Info (12023): Found entity 1: IR File: E:/cs208/vhdl/IR.vhd Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/leds.vhd
Info (12022): Found design unit 1: LEDs-synth File: E:/cs208/vhdl/LEDs.vhd Line: 22
Info (12023): Found entity 1: LEDs File: E:/cs208/vhdl/LEDs.vhd Line: 5
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/logic_unit.vhd
Info (12022): Found design unit 1: logic_unit-synth File: E:/cs208/vhdl/logic_unit.vhd Line: 13
Info (12023): Found entity 1: logic_unit File: E:/cs208/vhdl/logic_unit.vhd Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/multiplexer.vhd
Info (12022): Found design unit 1: multiplexer-synth File: E:/cs208/vhdl/multiplexer.vhd Line: 15
Info (12023): Found entity 1: multiplexer File: E:/cs208/vhdl/multiplexer.vhd Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x5.vhd
Info (12022): Found design unit 1: mux2x5-synth File: E:/cs208/vhdl/mux2x5.vhd Line: 13
Info (12023): Found entity 1: mux2x5 File: E:/cs208/vhdl/mux2x5.vhd Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x16.vhd
Info (12022): Found design unit 1: mux2x16-synth File: E:/cs208/vhdl/mux2x16.vhd Line: 13
Info (12023): Found entity 1: mux2x16 File: E:/cs208/vhdl/mux2x16.vhd Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x32.vhd
Info (12022): Found design unit 1: mux2x32-synth File: E:/cs208/vhdl/mux2x32.vhd Line: 13
Info (12023): Found entity 1: mux2x32 File: E:/cs208/vhdl/mux2x32.vhd Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/pc.vhd
Info (12022): Found design unit 1: PC-synth File: E:/cs208/vhdl/PC.vhd Line: 19
Info (12023): Found entity 1: PC File: E:/cs208/vhdl/PC.vhd Line: 5
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/ram.vhd
Info (12022): Found design unit 1: RAM-synth File: E:/cs208/vhdl/RAM.vhd Line: 16
Info (12023): Found entity 1: RAM File: E:/cs208/vhdl/RAM.vhd Line: 5
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/register_file.vhd
Info (12022): Found design unit 1: register_file-synth File: E:/cs208/vhdl/register_file.vhd Line: 18
Info (12023): Found entity 1: register_file File: E:/cs208/vhdl/register_file.vhd Line: 5
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/rom.vhd
Info (12022): Found design unit 1: ROM-synth File: E:/cs208/vhdl/ROM.vhd Line: 15
Info (12023): Found entity 1: ROM File: E:/cs208/vhdl/ROM.vhd Line: 5
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/rom_block.vhd
Info (12022): Found design unit 1: rom_block-SYN File: E:/cs208/vhdl/ROM_Block.vhd Line: 52
Info (12023): Found entity 1: ROM_Block File: E:/cs208/vhdl/ROM_Block.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /cs208/vhdl/shift_unit.vhd
Info (12022): Found design unit 1: shift_unit-synth File: E:/cs208/vhdl/shift_unit.vhd Line: 14
Info (12023): Found entity 1: shift_unit File: E:/cs208/vhdl/shift_unit.vhd Line: 5
Info (12127): Elaborating entity "GECKO" for the top level hierarchy
Info (12128): Elaborating entity "LEDs" for hierarchy "LEDs:LEDs_0"
Info (12128): Elaborating entity "decoder" for hierarchy "decoder:decoder_0"
Info (12128): Elaborating entity "CPU" for hierarchy "CPU:inst"
Info (12128): Elaborating entity "controller" for hierarchy "CPU:inst|controller:controller_0"
Info (10041): Inferred latch for "s_next.RI_OP" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.UI_OP" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.JMPI" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.JMP" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.CALLR" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.CALL" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.BRANCH" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.LOAD2" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.I_OP" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.LOAD1" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.BREAK" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.STORE" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.R_OP" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.DECODE" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.FETCH2" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (10041): Inferred latch for "s_next.FETCH1" at controller.vhd(58) File: E:/cs208/vhdl/controller.vhd Line: 58
Info (12128): Elaborating entity "IR" for hierarchy "CPU:inst|IR:IR_0"
Info (12128): Elaborating entity "mux2x16" for hierarchy "CPU:inst|mux2x16:mux_addr"
Info (12128): Elaborating entity "PC" for hierarchy "CPU:inst|PC:PC_0"
Info (12128): Elaborating entity "ALU" for hierarchy "CPU:inst|ALU:alu_0"
Info (12128): Elaborating entity "multiplexer" for hierarchy "CPU:inst|ALU:alu_0|multiplexer:multiplexer_0"
Info (12128): Elaborating entity "add_sub" for hierarchy "CPU:inst|ALU:alu_0|add_sub:add_sub_0"
Info (12128): Elaborating entity "comparator" for hierarchy "CPU:inst|ALU:alu_0|comparator:comparator_0"
Info (12128): Elaborating entity "logic_unit" for hierarchy "CPU:inst|ALU:alu_0|logic_unit:logic_unit_0"
Info (12128): Elaborating entity "shift_unit" for hierarchy "CPU:inst|ALU:alu_0|shift_unit:shift_unit_0"
Info (12128): Elaborating entity "register_file" for hierarchy "CPU:inst|register_file:register_file_0"
Info (12128): Elaborating entity "mux2x5" for hierarchy "CPU:inst|mux2x5:mux_aw"
Info (12128): Elaborating entity "mux2x32" for hierarchy "CPU:inst|mux2x32:mux_data"
Info (12128): Elaborating entity "extend" for hierarchy "CPU:inst|extend:extend_0"
Info (12128): Elaborating entity "ROM" for hierarchy "ROM:ROM_0"
Info (12128): Elaborating entity "ROM_Block" for hierarchy "ROM:ROM_0|ROM_Block:romblock" File: E:/cs208/vhdl/ROM.vhd Line: 33
Info (12128): Elaborating entity "altsyncram" for hierarchy "ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component" File: E:/cs208/vhdl/ROM_Block.vhd Line: 85
Info (12130): Elaborated megafunction instantiation "ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component" File: E:/cs208/vhdl/ROM_Block.vhd Line: 85
Info (12133): Instantiated megafunction "ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component" with the following parameter: File: E:/cs208/vhdl/ROM_Block.vhd Line: 85
Info (12134): Parameter "address_aclr_a" = "NONE"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "../quartus/ROM.hex"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "1024"
Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
Info (12134): Parameter "widthad_a" = "10"
Info (12134): Parameter "width_a" = "32"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_rna1.tdf
Info (12023): Found entity 1: altsyncram_rna1 File: E:/cs208/quartus/db/altsyncram_rna1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_rna1" for hierarchy "ROM:ROM_0|ROM_Block:romblock|altsyncram:altsyncram_component|altsyncram_rna1:auto_generated" File: c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "RAM" for hierarchy "RAM:RAM_0"
Info (12128): Elaborating entity "buttons" for hierarchy "buttons:buttons_0"
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
Warning (13048): Converted tri-state node "rddata[31]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[30]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[29]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[28]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[27]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[26]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[25]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[24]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[23]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[22]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[21]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[20]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[19]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[18]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[17]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[16]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[15]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[14]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[13]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[12]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[11]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[10]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[9]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[8]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[7]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[6]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[5]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[4]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[3]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[2]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[1]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Warning (13048): Converted tri-state node "rddata[0]" into a selector File: E:/cs208/vhdl/IR.vhd Line: 21
Info (19000): Inferred 1 megafunctions from design logic
Info (276029): Inferred altsyncram megafunction from the following design logic: "RAM:RAM_0|reg_rtl_0"
Info (286033): Parameter OPERATION_MODE set to SINGLE_PORT
Info (286033): Parameter WIDTH_A set to 32
Info (286033): Parameter WIDTHAD_A set to 10
Info (286033): Parameter NUMWORDS_A set to 1024
Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_ACLR_A set to NONE
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter INIT_FILE set to db/GECKO.ram0_RAM_15119.hdl.mif
Info (12130): Elaborated megafunction instantiation "RAM:RAM_0|altsyncram:reg_rtl_0"
Info (12133): Instantiated megafunction "RAM:RAM_0|altsyncram:reg_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "SINGLE_PORT"
Info (12134): Parameter "WIDTH_A" = "32"
Info (12134): Parameter "WIDTHAD_A" = "10"
Info (12134): Parameter "NUMWORDS_A" = "1024"
Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "INIT_FILE" = "db/GECKO.ram0_RAM_15119.hdl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_u781.tdf
Info (12023): Found entity 1: altsyncram_u781 File: E:/cs208/quartus/db/altsyncram_u781.tdf Line: 27
Info (13000): Registers with preset signals will power-up high File: E:/cs208/vhdl/LEDs.vhd Line: 90
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info (286030): Timing-Driven Synthesis is running
Info (17049): 17 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 3816 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 6 input pins
Info (21059): Implemented 96 output pins
Info (21061): Implemented 3650 logic cells
Info (21064): Implemented 64 RAM segments
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 34 warnings
Info: Peak virtual memory: 4843 megabytes
Info: Processing ended: Wed Oct 24 12:06:43 2018
Info: Elapsed time: 00:00:28
Info: Total CPU time (on all processors): 00:00:39

14
cs208-ca/quartus/GECKO.map.summary Executable file
View File

@@ -0,0 +1,14 @@
Analysis & Synthesis Status : Successful - Wed Oct 24 12:06:43 2018
Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Lite Edition
Revision Name : GECKO
Top-level Entity Name : GECKO
Family : Cyclone IV E
Total logic elements : 3,537
Total combinational functions : 2,508
Dedicated logic registers : 1,180
Total registers : 1180
Total pins : 102
Total virtual pins : 0
Total memory bits : 65,536
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0

74
cs208-ca/quartus/GECKO.mif_update.rpt Executable file
View File

@@ -0,0 +1,74 @@
MIF/HEX Update report for GECKO
Mon Oct 22 11:19:54 2018
Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. MIF/HEX Update Summary
3. MIF/HEX Update Processed Files
4. MIF/HEX Update Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+---------------------------------------------------------------+
; MIF/HEX Update Summary ;
+-----------------------+---------------------------------------+
; MIF/HEX Update Status ; Successful - Mon Oct 22 11:19:54 2018 ;
; Revision Name ; GECKO ;
; Top-level Entity Name ; GECKO ;
; Family ; Cyclone IV E ;
; Device ; EP4CE30F23C8 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------+
; MIF/HEX Update Processed Files ;
+--------------------------------------------------+
; File Name ;
+--------------------------------------------------+
; E:/cs208/quartus/ROM.hex ;
; E:/cs208/quartus/db/gecko.ram0_ram_15119.hdl.mif ;
+--------------------------------------------------+
+-------------------------+
; MIF/HEX Update Messages ;
+-------------------------+
Info: *******************************************************************
Info: Running Quartus Prime MIF/HEX Update
Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
Info: Processing started: Mon Oct 22 11:19:52 2018
Info: Command: quartus_cdb GECKO -c GECKO --update_mif
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (39024): Processed the following Memory Initialization File(s)
Info (39025): Processed Memory Initialization File E:/cs208/quartus/ROM.hex File: E:/cs208/quartus/ROM.hex Line: 0
Info (39025): Processed Memory Initialization File E:/cs208/quartus/db/gecko.ram0_ram_15119.hdl.mif File: E:/cs208/quartus/db/gecko.ram0_ram_15119.hdl.mif Line: 0
Info: Quartus Prime MIF/HEX Update was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4754 megabytes
Info: Processing ended: Mon Oct 22 11:19:54 2018
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

554
cs208-ca/quartus/GECKO.pin Executable file
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-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
CHIP "GECKO" ASSIGNED TO AN: EP4CE30F23C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
VCCIO8 : A2 : power : : 3.3V : 8 :
row8[11] : A3 : output : 3.3-V LVTTL : : 8 : Y
row5[11] : A4 : output : 3.3-V LVTTL : : 8 : Y
row6[10] : A5 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
row7[9] : A7 : output : 3.3-V LVTTL : : 8 : Y
row5[9] : A8 : output : 3.3-V LVTTL : : 8 : Y
row7[8] : A9 : output : 3.3-V LVTTL : : 8 : Y
row5[8] : A10 : output : 3.3-V LVTTL : : 8 : Y
in_buttons[1] : A11 : input : 3.3-V LVTTL : : 8 : Y
in_buttons[3] : A12 : input : 3.3-V LVTTL : : 7 : Y
row8[7] : A13 : output : 3.3-V LVTTL : : 7 : Y
row5[7] : A14 : output : 3.3-V LVTTL : : 7 : Y
row8[6] : A15 : output : 3.3-V LVTTL : : 7 : Y
row5[6] : A16 : output : 3.3-V LVTTL : : 7 : Y
row8[5] : A17 : output : 3.3-V LVTTL : : 7 : Y
row5[5] : A18 : output : 3.3-V LVTTL : : 7 : Y
row8[4] : A19 : output : 3.3-V LVTTL : : 7 : Y
row6[3] : A20 : output : 3.3-V LVTTL : : 7 : Y
VCCIO7 : A21 : power : : 3.3V : 7 :
GND : A22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 2 :
GND : AA2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 :
VCCIO3 : AA6 : power : : 3.3V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
GND+ : AA11 : : : : 3 :
GND+ : AA12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 :
GND : AA22 : gnd : : : :
GND : AB1 : gnd : : : :
VCCIO3 : AB2 : power : : 3.3V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 :
GND : AB6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
reset_n : AB11 : input : 3.3-V LVTTL : : 3 : Y
GND+ : AB12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
VCCIO4 : AB21 : power : : 3.3V : 4 :
GND : AB22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 1 :
row7[11] : B3 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
row3[11] : B5 : output : 3.3-V LVTTL : : 8 : Y
row8[10] : B6 : output : 3.3-V LVTTL : : 8 : Y
row6[9] : B7 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
row6[8] : B9 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
in_buttons[0] : B11 : input : 3.3-V LVTTL : : 8 : Y
in_buttons[2] : B12 : input : 3.3-V LVTTL : : 7 : Y
row7[7] : B13 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 :
row7[6] : B15 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 :
row7[5] : B17 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
row7[4] : B19 : output : 3.3-V LVTTL : : 7 : Y
row5[4] : B20 : output : 3.3-V LVTTL : : 7 : Y
row8[3] : B21 : output : 3.3-V LVTTL : : 6 : Y
row5[3] : B22 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
row6[11] : C3 : output : 3.3-V LVTTL : : 8 : Y
row4[11] : C4 : output : 3.3-V LVTTL : : 8 : Y
GND : C5 : gnd : : : :
row7[10] : C6 : output : 3.3-V LVTTL : : 8 : Y
row5[10] : C7 : output : 3.3-V LVTTL : : 8 : Y
row8[9] : C8 : output : 3.3-V LVTTL : : 8 : Y
GND : C9 : gnd : : : :
row8[8] : C10 : output : 3.3-V LVTTL : : 8 : Y
GND : C11 : gnd : : : :
GND : C12 : gnd : : : :
row6[7] : C13 : output : 3.3-V LVTTL : : 7 : Y
GND : C14 : gnd : : : :
row6[6] : C15 : output : 3.3-V LVTTL : : 7 : Y
GND : C16 : gnd : : : :
row6[5] : C17 : output : 3.3-V LVTTL : : 7 : Y
GND : C18 : gnd : : : :
row6[4] : C19 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 :
row7[3] : C21 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 :
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
GND : D3 : gnd : : : :
VCCIO1 : D4 : power : : 3.3V : 1 :
VCCIO8 : D5 : power : : 3.3V : 8 :
row1[11] : D6 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
GND : D8 : gnd : : : :
VCCIO8 : D9 : power : : 3.3V : 8 :
row3[5] : D10 : output : 3.3-V LVTTL : : 8 : Y
VCCIO8 : D11 : power : : 3.3V : 8 :
VCCIO7 : D12 : power : : 3.3V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 :
VCCIO7 : D14 : power : : 3.3V : 7 :
row4[1] : D15 : output : 3.3-V LVTTL : : 7 : Y
VCCIO7 : D16 : power : : 3.3V : 7 :
row3[0] : D17 : output : 3.3-V LVTTL : : 7 : Y
VCCIO7 : D18 : power : : 3.3V : 7 :
row1[0] : D19 : output : 3.3-V LVTTL : : 7 : Y
row6[2] : D20 : output : 3.3-V LVTTL : : 6 : Y
row7[2] : D21 : output : 3.3-V LVTTL : : 6 : Y
row8[2] : D22 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1 :
row2[11] : E5 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 :
row4[10] : E7 : output : 3.3-V LVTTL : : 8 : Y
VCCIO8 : E8 : power : : 3.3V : 8 :
row2[7] : E9 : output : 3.3-V LVTTL : : 8 : Y
row1[7] : E10 : output : 3.3-V LVTTL : : 8 : Y
row3[8] : E11 : output : 3.3-V LVTTL : : 7 : Y
row4[4] : E12 : output : 3.3-V LVTTL : : 7 : Y
row4[3] : E13 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 :
row3[1] : E15 : output : 3.3-V LVTTL : : 7 : Y
row7[0] : E16 : output : 3.3-V LVTTL : : 7 : Y
VCCD_PLL2 : E17 : power : : 1.2V : :
GNDA2 : E18 : gnd : : : :
VCCIO6 : E19 : power : : 3.3V : 6 :
GND : E20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 :
row5[2] : E22 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
GND : F3 : gnd : : : :
VCCIO1 : F4 : power : : 3.3V : 1 :
GNDA3 : F5 : gnd : : : :
VCCD_PLL3 : F6 : power : : 1.2V : :
row4[7] : F7 : output : 3.3-V LVTTL : : 8 : Y
row2[10] : F8 : output : 3.3-V LVTTL : : 8 : Y
row4[5] : F9 : output : 3.3-V LVTTL : : 8 : Y
row1[9] : F10 : output : 3.3-V LVTTL : : 8 : Y
row2[8] : F11 : output : 3.3-V LVTTL : : 7 : Y
GND : F12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 7 :
row1[3] : F14 : output : 3.3-V LVTTL : : 7 : Y
row2[1] : F15 : output : 3.3-V LVTTL : : 7 : Y
row6[0] : F16 : output : 3.3-V LVTTL : : 7 : Y
row2[0] : F17 : output : 3.3-V LVTTL : : 6 : Y
VCCA2 : F18 : power : : 2.5V : :
row1[10] : F19 : output : 3.3-V LVTTL : : 6 : Y
row6[1] : F20 : output : 3.3-V LVTTL : : 6 : Y
row8[1] : F21 : output : 3.3-V LVTTL : : 6 : Y
row7[1] : F22 : output : 3.3-V LVTTL : : 6 : Y
GND+ : G1 : : : : 1 :
GND : G2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
VCCA3 : G6 : power : : 2.5V : :
row3[7] : G7 : output : 3.3-V LVTTL : : 8 : Y
row3[10] : G8 : output : 3.3-V LVTTL : : 8 : Y
row4[9] : G9 : output : 3.3-V LVTTL : : 8 : Y
row2[9] : G10 : output : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
VCCINT : G12 : power : : 1.2V : :
row3[6] : G13 : output : 3.3-V LVTTL : : 7 : Y
row1[6] : G14 : output : 3.3-V LVTTL : : 7 : Y
row1[5] : G15 : output : 3.3-V LVTTL : : 7 : Y
row1[4] : G16 : output : 3.3-V LVTTL : : 7 : Y
row2[3] : G17 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 6 :
VCCIO6 : G19 : power : : 3.3V : 6 :
GND : G20 : gnd : : : :
GND+ : G21 : : : : 6 :
GND+ : G22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : : : : 1 :
GND : H3 : gnd : : : :
VCCIO1 : H4 : power : : 3.3V : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 1 :
VCCINT : H9 : power : : 1.2V : :
row3[9] : H10 : output : 3.3-V LVTTL : : 8 : Y
row4[8] : H11 : output : 3.3-V LVTTL : : 8 : Y
GND : H12 : gnd : : : :
GND : H13 : gnd : : : :
row2[5] : H14 : output : 3.3-V LVTTL : : 7 : Y
row2[4] : H15 : output : 3.3-V LVTTL : : 7 : Y
row3[3] : H16 : output : 3.3-V LVTTL : : 6 : Y
row4[2] : H17 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 :
row3[2] : H19 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 :
row5[1] : H21 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1 :
GND : J9 : gnd : : : :
VCCINT : J10 : power : : 1.2V : :
VCCINT : J11 : power : : 1.2V : :
VCCINT : J12 : power : : 1.2V : :
VCCINT : J13 : power : : 1.2V : :
VCCINT : J14 : power : : 1.2V : :
GND : J15 : gnd : : : :
VCCINT : J16 : power : : 1.2V : :
row3[4] : J17 : output : 3.3-V LVTTL : : 6 : Y
row2[6] : J18 : output : 3.3-V LVTTL : : 6 : Y
GND : J19 : gnd : : : :
VCCIO6 : J20 : power : : 3.3V : 6 :
row2[2] : J21 : output : 3.3-V LVTTL : : 6 : Y
row1[2] : J22 : output : 3.3-V LVTTL : : 6 : Y
~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : input : 3.3-V LVTTL : : 1 : N
~ALTERA_DCLK~ : K2 : output : 3.3-V LVTTL : : 1 : N
GND : K3 : gnd : : : :
VCCIO1 : K4 : power : : 3.3V : 1 :
nCONFIG : K5 : : : : 1 :
nSTATUS : K6 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
VCCINT : K9 : power : : 1.2V : :
GND : K10 : gnd : : : :
GND : K11 : gnd : : : :
GND : K12 : gnd : : : :
GND : K13 : gnd : : : :
VCCINT : K14 : power : : 1.2V : :
VCCINT : K15 : power : : 1.2V : :
GND : K16 : gnd : : : :
row4[6] : K17 : output : 3.3-V LVTTL : : 6 : Y
row1[8] : K18 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 :
MSEL3 : K20 : : : : 6 :
row1[1] : K21 : output : 3.3-V LVTTL : : 6 : Y
row4[0] : K22 : output : 3.3-V LVTTL : : 6 : Y
TMS : L1 : input : : : 1 :
TCK : L2 : input : : : 1 :
nCE : L3 : : : : 1 :
TDO : L4 : output : : : 1 :
TDI : L5 : input : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
VCCINT : L9 : power : : 1.2V : :
GND : L10 : gnd : : : :
GND : L11 : gnd : : : :
GND : L12 : gnd : : : :
GND : L13 : gnd : : : :
VCCINT : L14 : power : : 1.2V : :
GND : L15 : gnd : : : :
VCCINT : L16 : power : : 1.2V : :
MSEL2 : L17 : : : : 6 :
MSEL1 : L18 : : : : 6 :
VCCIO6 : L19 : power : : 3.3V : 6 :
GND : L20 : gnd : : : :
row5[0] : L21 : output : 3.3-V LVTTL : : 6 : Y
row8[0] : L22 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 :
VCCINT : M9 : power : : 1.2V : :
GND : M10 : gnd : : : :
GND : M11 : gnd : : : :
GND : M12 : gnd : : : :
GND : M13 : gnd : : : :
VCCINT : M14 : power : : 1.2V : :
VCCINT : M15 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M16 : : : : 5 :
MSEL0 : M17 : : : : 6 :
CONF_DONE : M18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 :
GND : N3 : gnd : : : :
VCCIO2 : N4 : power : : 3.3V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 :
VCCINT : N9 : power : : 1.2V : :
GND : N10 : gnd : : : :
GND : N11 : gnd : : : :
GND : N12 : gnd : : : :
GND : N13 : gnd : : : :
VCCINT : N14 : power : : 1.2V : :
GND : N15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N17 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P7 : : : : 2 :
GND : P8 : gnd : : : :
VCCINT : P9 : power : : 1.2V : :
VCCINT : P10 : power : : 1.2V : :
VCCINT : P11 : power : : 1.2V : :
VCCINT : P12 : power : : 1.2V : :
VCCINT : P13 : power : : 1.2V : :
VCCINT : P14 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P17 : : : : 5 :
VCCIO5 : P18 : power : : 3.3V : 5 :
GND : P19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
GND : R3 : gnd : : : :
VCCIO2 : R4 : power : : 3.3V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
VCCINT : R8 : power : : 1.2V : :
GND : R9 : gnd : : : :
VCCINT : R10 : power : : 1.2V : :
GND : R11 : gnd : : : :
VCCINT : R12 : power : : 1.2V : :
GND : R13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R17 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
clk : T1 : input : 3.3-V LVTTL : : 2 : Y
GND+ : T2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 :
VCCA1 : T6 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 :
VCCIO5 : T19 : power : : 3.3V : 5 :
GND : T20 : gnd : : : :
GND+ : T21 : : : : 5 :
GND+ : T22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
GND : U3 : gnd : : : :
VCCIO2 : U4 : power : : 3.3V : 2 :
GNDA1 : U5 : gnd : : : :
VCCD_PLL1 : U6 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4 :
VCCA4 : U18 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 :
VCCD_PLL4 : V17 : power : : 1.2V : :
GNDA4 : V18 : gnd : : : :
VCCIO5 : V19 : power : : 3.3V : 5 :
GND : V20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
GND : W3 : gnd : : : :
VCCIO2 : W4 : power : : 3.3V : 2 :
VCCIO3 : W5 : power : : 3.3V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 :
VCCIO3 : W9 : power : : 3.3V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 :
VCCIO3 : W11 : power : : 3.3V : 3 :
VCCIO4 : W12 : power : : 3.3V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 :
VCCIO4 : W16 : power : : 3.3V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 :
VCCIO4 : W18 : power : : 3.3V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 :
GND : Y5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 :
GND : Y9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
GND : Y11 : gnd : : : :
GND : Y12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 :
VCCIO4 : Y14 : power : : 3.3V : 4 :
GND : Y15 : gnd : : : :
GND : Y16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
GND : Y18 : gnd : : : :
VCCIO5 : Y19 : power : : 3.3V : 5 :
GND : Y20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :

31
cs208-ca/quartus/GECKO.qpf Executable file
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@@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
# Date created = 14:21:29 October 03, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "16.0"
DATE = "14:21:29 October 03, 2017"
# Revisions
PROJECT_REVISION = "GECKO"

232
cs208-ca/quartus/GECKO.qsf Executable file
View File

@@ -0,0 +1,232 @@
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# system_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE30F23C8
set_global_assignment -name TOP_LEVEL_ENTITY GECKO
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:20:58 OCTOBER 03, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_location_assignment PIN_D6 -to row1[11]
set_location_assignment PIN_F19 -to row1[10]
set_location_assignment PIN_F10 -to row1[9]
set_location_assignment PIN_K18 -to row1[8]
set_location_assignment PIN_E10 -to row1[7]
set_location_assignment PIN_G14 -to row1[6]
set_location_assignment PIN_G15 -to row1[5]
set_location_assignment PIN_G16 -to row1[4]
set_location_assignment PIN_F14 -to row1[3]
set_location_assignment PIN_J22 -to row1[2]
set_location_assignment PIN_K21 -to row1[1]
set_location_assignment PIN_D19 -to row1[0]
set_location_assignment PIN_E5 -to row2[11]
set_location_assignment PIN_F8 -to row2[10]
set_location_assignment PIN_G10 -to row2[9]
set_location_assignment PIN_F11 -to row2[8]
set_location_assignment PIN_E9 -to row2[7]
set_location_assignment PIN_J18 -to row2[6]
set_location_assignment PIN_H14 -to row2[5]
set_location_assignment PIN_H15 -to row2[4]
set_location_assignment PIN_G17 -to row2[3]
set_location_assignment PIN_J21 -to row2[2]
set_location_assignment PIN_F15 -to row2[1]
set_location_assignment PIN_F17 -to row2[0]
set_location_assignment PIN_B5 -to row3[11]
set_location_assignment PIN_G8 -to row3[10]
set_location_assignment PIN_H10 -to row3[9]
set_location_assignment PIN_E11 -to row3[8]
set_location_assignment PIN_G7 -to row3[7]
set_location_assignment PIN_G13 -to row3[6]
set_location_assignment PIN_D10 -to row3[5]
set_location_assignment PIN_J17 -to row3[4]
set_location_assignment PIN_H16 -to row3[3]
set_location_assignment PIN_H19 -to row3[2]
set_location_assignment PIN_E15 -to row3[1]
set_location_assignment PIN_D17 -to row3[0]
set_location_assignment PIN_C4 -to row4[11]
set_location_assignment PIN_E7 -to row4[10]
set_location_assignment PIN_G9 -to row4[9]
set_location_assignment PIN_H11 -to row4[8]
set_location_assignment PIN_F7 -to row4[7]
set_location_assignment PIN_K17 -to row4[6]
set_location_assignment PIN_F9 -to row4[5]
set_location_assignment PIN_E12 -to row4[4]
set_location_assignment PIN_E13 -to row4[3]
set_location_assignment PIN_H17 -to row4[2]
set_location_assignment PIN_D15 -to row4[1]
set_location_assignment PIN_K22 -to row4[0]
set_location_assignment PIN_A4 -to row5[11]
set_location_assignment PIN_C7 -to row5[10]
set_location_assignment PIN_A8 -to row5[9]
set_location_assignment PIN_A10 -to row5[8]
set_location_assignment PIN_A14 -to row5[7]
set_location_assignment PIN_A16 -to row5[6]
set_location_assignment PIN_A18 -to row5[5]
set_location_assignment PIN_B20 -to row5[4]
set_location_assignment PIN_B22 -to row5[3]
set_location_assignment PIN_E22 -to row5[2]
set_location_assignment PIN_H21 -to row5[1]
set_location_assignment PIN_L21 -to row5[0]
set_location_assignment PIN_C3 -to row6[11]
set_location_assignment PIN_A5 -to row6[10]
set_location_assignment PIN_B7 -to row6[9]
set_location_assignment PIN_B9 -to row6[8]
set_location_assignment PIN_C13 -to row6[7]
set_location_assignment PIN_C15 -to row6[6]
set_location_assignment PIN_C17 -to row6[5]
set_location_assignment PIN_C19 -to row6[4]
set_location_assignment PIN_A20 -to row6[3]
set_location_assignment PIN_D20 -to row6[2]
set_location_assignment PIN_F20 -to row6[1]
set_location_assignment PIN_F16 -to row6[0]
set_location_assignment PIN_B3 -to row7[11]
set_location_assignment PIN_C6 -to row7[10]
set_location_assignment PIN_A7 -to row7[9]
set_location_assignment PIN_A9 -to row7[8]
set_location_assignment PIN_B13 -to row7[7]
set_location_assignment PIN_B15 -to row7[6]
set_location_assignment PIN_B17 -to row7[5]
set_location_assignment PIN_B19 -to row7[4]
set_location_assignment PIN_C21 -to row7[3]
set_location_assignment PIN_D21 -to row7[2]
set_location_assignment PIN_F22 -to row7[1]
set_location_assignment PIN_E16 -to row7[0]
set_location_assignment PIN_A3 -to row8[11]
set_location_assignment PIN_B6 -to row8[10]
set_location_assignment PIN_C8 -to row8[9]
set_location_assignment PIN_C10 -to row8[8]
set_location_assignment PIN_A13 -to row8[7]
set_location_assignment PIN_A15 -to row8[6]
set_location_assignment PIN_A17 -to row8[5]
set_location_assignment PIN_A19 -to row8[4]
set_location_assignment PIN_B21 -to row8[3]
set_location_assignment PIN_D22 -to row8[2]
set_location_assignment PIN_F21 -to row8[1]
set_location_assignment PIN_L22 -to row8[0]
set_location_assignment PIN_B4 -to row9[11]
set_location_assignment PIN_A6 -to row9[10]
set_location_assignment PIN_B8 -to row9[9]
set_location_assignment PIN_B10 -to row9[8]
set_location_assignment PIN_B14 -to row9[7]
set_location_assignment PIN_B16 -to row9[6]
set_location_assignment PIN_B18 -to row9[5]
set_location_assignment PIN_C20 -to row9[4]
set_location_assignment PIN_C22 -to row9[3]
set_location_assignment PIN_E21 -to row9[2]
set_location_assignment PIN_H22 -to row9[1]
set_location_assignment PIN_H20 -to row9[0]
set_location_assignment PIN_N5 -to SDRAM_addr[0]
set_location_assignment PIN_N6 -to SDRAM_addr[1]
set_location_assignment PIN_P4 -to SDRAM_addr[2]
set_location_assignment PIN_P5 -to SDRAM_addr[3]
set_location_assignment PIN_W6 -to SDRAM_addr[4]
set_location_assignment PIN_V7 -to SDRAM_addr[5]
set_location_assignment PIN_V6 -to SDRAM_addr[6]
set_location_assignment PIN_V5 -to SDRAM_addr[7]
set_location_assignment PIN_V1 -to SDRAM_addr[8]
set_location_assignment PIN_V4 -to SDRAM_addr[9]
set_location_assignment PIN_U2 -to SDRAM_addr[10]
set_location_assignment PIN_U8 -to SDRAM_addr[11]
set_location_assignment PIN_V2 -to SDRAM_addr[12]
set_location_assignment PIN_M6 -to SDRAM_BA[0]
set_location_assignment PIN_M7 -to SDRAM_BA[1]
set_location_assignment PIN_M1 -to SDRAM_D[0]
set_location_assignment PIN_M2 -to SDRAM_D[1]
set_location_assignment PIN_M3 -to SDRAM_D[2]
set_location_assignment PIN_N1 -to SDRAM_D[3]
set_location_assignment PIN_N2 -to SDRAM_D[4]
set_location_assignment PIN_P1 -to SDRAM_D[5]
set_location_assignment PIN_P2 -to SDRAM_D[6]
set_location_assignment PIN_P3 -to SDRAM_D[7]
set_location_assignment PIN_W1 -to SDRAM_D[8]
set_location_assignment PIN_W2 -to SDRAM_D[9]
set_location_assignment PIN_Y1 -to SDRAM_D[10]
set_location_assignment PIN_Y2 -to SDRAM_D[11]
set_location_assignment PIN_Y3 -to SDRAM_D[12]
set_location_assignment PIN_AA1 -to SDRAM_D[13]
set_location_assignment PIN_AB3 -to SDRAM_D[14]
set_location_assignment PIN_AA4 -to SDRAM_D[15]
set_location_assignment PIN_R1 -to SDRAM_DQM[0]
set_location_assignment PIN_V3 -to SDRAM_DQM[1]
set_location_assignment PIN_U7 -to SDRAM_CKE
set_location_assignment PIN_AA3 -to SDRAM_CLK
set_location_assignment PIN_M5 -to SDRAM_N_CAS
set_location_assignment PIN_M4 -to SDRAM_N_RAS
set_location_assignment PIN_U1 -to SDRAM_N_CS
set_location_assignment PIN_R2 -to SDRAM_N_WE
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_location_assignment PIN_AB11 -to reset_n
set_location_assignment PIN_T1 -to clk
set_location_assignment PIN_B11 -to IN_BUTTONS[0]
set_location_assignment PIN_A11 -to IN_BUTTONS[1]
set_location_assignment PIN_B12 -to IN_BUTTONS[2]
set_location_assignment PIN_A12 -to IN_BUTTONS[3]
set_global_assignment -name SDC_FILE GECKO.sdc
set_global_assignment -name BDF_FILE GECKO.bdf
set_global_assignment -name BDF_FILE ALU.bdf
set_global_assignment -name BDF_FILE CPU.bdf
set_global_assignment -name VHDL_FILE ../vhdl/add_sub.vhd
set_global_assignment -name VHDL_FILE ../vhdl/buttons.vhd
set_global_assignment -name VHDL_FILE ../vhdl/comparator.vhd
set_global_assignment -name VHDL_FILE ../vhdl/controller.vhd
set_global_assignment -name VHDL_FILE ../vhdl/decoder.vhd
set_global_assignment -name VHDL_FILE ../vhdl/extend.vhd
set_global_assignment -name VHDL_FILE ../vhdl/IR.vhd
set_global_assignment -name VHDL_FILE ../vhdl/LEDs.vhd
set_global_assignment -name VHDL_FILE ../vhdl/logic_unit.vhd
set_global_assignment -name VHDL_FILE ../vhdl/multiplexer.vhd
set_global_assignment -name VHDL_FILE ../vhdl/mux2x5.vhd
set_global_assignment -name VHDL_FILE ../vhdl/mux2x16.vhd
set_global_assignment -name VHDL_FILE ../vhdl/mux2x32.vhd
set_global_assignment -name VHDL_FILE ../vhdl/PC.vhd
set_global_assignment -name VHDL_FILE ../vhdl/RAM.vhd
set_global_assignment -name VHDL_FILE ../vhdl/register_file.vhd
set_global_assignment -name VHDL_FILE ../vhdl/ROM.vhd
set_global_assignment -name VHDL_FILE ../vhdl/ROM_Block.vhd
set_global_assignment -name VHDL_FILE ../vhdl/shift_unit.vhd
set_global_assignment -name HEX_FILE ROM.hex
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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cs208-ca/quartus/GECKO.qws Executable file
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3
cs208-ca/quartus/GECKO.sdc Executable file
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create_clock -name clk -period 20.000 [get_ports {clk}]
set_false_path -from [get_ports {in_buttons[0] in_buttons[1] in_buttons[2] in_buttons[3] reset_n}]
set_false_path -to [get_ports {row1[0] row1[1] row1[2] row1[3] row1[4] row1[5] row1[6] row1[7] row1[8] row1[9] row1[10] row1[11] row2[0] row2[1] row2[2] row2[3] row2[4] row2[5] row2[6] row2[7] row2[8] row2[9] row2[10] row2[11] row3[0] row3[1] row3[2] row3[3] row3[4] row3[5] row3[6] row3[7] row3[8] row3[9] row3[10] row3[11] row4[0] row4[1] row4[2] row4[3] row4[4] row4[5] row4[6] row4[7] row4[8] row4[9] row4[10] row4[11] row5[0] row5[1] row5[2] row5[3] row5[4] row5[5] row5[6] row5[7] row5[8] row5[9] row5[10] row5[11] row6[0] row6[1] row6[2] row6[3] row6[4] row6[5] row6[6] row6[7] row6[8] row6[9] row6[10] row6[11] row7[0] row7[1] row7[2] row7[3] row7[4] row7[5] row7[6] row7[7] row7[8] row7[9] row7[10] row7[11] row8[0] row8[1] row8[2] row8[3] row8[4] row8[5] row8[6] row8[7] row8[8] row8[9] row8[10] row8[11]}]

3
cs208-ca/quartus/GECKO.sdc.bak Executable file
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create_clock -name clk -period 20.000 [get_ports {clk}]
set_false_path -from [get_ports {in_buttons[0] in_buttons[1] in_buttons[2] in_buttons[3] reset_n}]
set_false_path -to [get_ports {row1[0] row1[1] row1[2] row1[3] row1[4] row1[5] row1[6] row1[7] row1[8] row1[9] row1[10] row1[11] row2[0] row2[1] row2[2] row2[3] row2[4] row2[5] row2[6] row2[7] row2[8] row2[9] row2[10] row2[11] row3[0] row3[1] row3[2] row3[3] row3[4] row3[5] row3[6] row3[7] row3[8] row3[9] row3[10] row3[11] row4[0] row4[1] row4[2] row4[3] row4[4] row4[5] row4[6] row4[7] row4[8] row4[9] row4[10] row4[11] row5[0] row5[1] row5[2] row5[3] row5[4] row5[5] row5[6] row5[7] row5[8] row5[9] row5[10] row5[11] row6[0] row6[1] row6[2] row6[3] row6[4] row6[5] row6[6] row6[7] row6[8] row6[9] row6[10] row6[11] row7[0] row7[1] row7[2] row7[3] row7[4] row7[5] row7[6] row7[7] row7[8] row7[9] row7[10] row7[11] row8[0] row8[1] row8[2] row8[3] row8[4] row8[5] row8[6] row8[7] row8[8] row8[9] row8[10] row8[11]}]

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cs208-ca/quartus/GECKO.sld Executable file
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<sld_project_info/>

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cs208-ca/quartus/GECKO.sof Executable file
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cs208-ca/quartus/GECKO.sta.rpt Executable file
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cs208-ca/quartus/GECKO.sta.summary Executable file
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------------------------------------------------------------
Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'clk'
Slack : -3.122
TNS : -642.494
Type : Slow 1200mV 85C Model Hold 'clk'
Slack : 0.452
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk'
Slack : 9.624
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'clk'
Slack : -1.929
TNS : -259.589
Type : Slow 1200mV 0C Model Hold 'clk'
Slack : 0.400
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk'
Slack : 9.619
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'clk'
Slack : 10.032
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'clk'
Slack : 0.186
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk'
Slack : 9.207
TNS : 0.000
------------------------------------------------------------

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cs208-ca/quartus/GECKO_assignment_defaults.qdf Executable file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
# Date created = 08:37:03 October 03, 2017
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus Prime software and is used
# to preserve global assignments across Quartus Prime versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Stratix 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name DISABLE_OCP_HW_EVAL Off
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY -value "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x1" -family "Stratix 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS Off -family "Stratix 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Stratix 10"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Stratix 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off
set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS OFF -family "Stratix 10"
set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS ON -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000001
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000010
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000100
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0001000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0010000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

57
cs208-ca/quartus/IR.bsf Executable file
View File

@@ -0,0 +1,57 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 64 64 176 160)
(text "IR" (rect 5 0 16 12)(font "Arial" ))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "enable" (rect 0 0 31 12)(font "Arial" ))
(text "enable" (rect 21 43 52 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "D[31..0]" (rect 0 0 40 12)(font "Arial" ))
(text "D[31..0]" (rect 21 59 61 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 112 32)
(output)
(text "Q[31..0]" (rect -24 0 16 12)(font "Arial" ))
(text "Q[31..0]" (rect 51 27 91 39)(font "Arial" ))
(line (pt 112 32)(pt 96 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 96 80)(line_width 1))
)
)

92
cs208-ca/quartus/LEDs.bsf Executable file
View File

@@ -0,0 +1,92 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 64 64 200 240)
(text "LEDs" (rect 5 0 32 12)(font "Arial" ))
(text "inst" (rect 8 160 25 172)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "reset_n" (rect 0 0 36 12)(font "Arial" ))
(text "reset_n" (rect 21 43 57 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "cs" (rect 0 0 11 12)(font "Arial" ))
(text "cs" (rect 21 59 32 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "write" (rect 0 0 22 12)(font "Arial" ))
(text "write" (rect 21 91 43 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 64 176)
(input)
(text "address[1..0]" (rect 0 16 64 28)(font "Arial" ))
(text "address[1..0]" (rect 56 88 68 152)(font "Arial" )(vertical))
(line (pt 64 176)(pt 64 160)(line_width 3))
)
(port
(pt 80 176)
(input)
(text "wrdata[31..0]" (rect 0 16 63 28)(font "Arial" ))
(text "wrdata[31..0]" (rect 72 89 84 152)(font "Arial" )(vertical))
(line (pt 80 176)(pt 80 160)(line_width 3))
)
(port
(pt 0 80)
(input)
(text "read" (rect 0 0 21 12)(font "Arial" ))
(text "read" (rect 21 75 42 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 96 176)
(output)
(text "rddata[31..0]" (rect 0 16 62 28)(font "Arial" ))
(text "rddata[31..0]" (rect 88 90 100 152)(font "Arial" )(vertical))
(line (pt 96 176)(pt 96 160)(line_width 3))
)
(port
(pt 136 56)
(output)
(text "LEDs[95..0]" (rect 0 0 59 12)(font "Arial" ))
(text "LEDs[95..0]" (rect 61 48 120 60)(font "Arial" ))
(line (pt 136 56)(pt 120 56)(line_width 3))
)
(drawing
(rectangle (rect 16 16 120 160)(line_width 1))
)
)

92
cs208-ca/quartus/PC.bsf Executable file
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@@ -0,0 +1,92 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 64 64 224 240)
(text "PC" (rect 5 0 20 12)(font "Arial" ))
(text "inst" (rect 8 160 25 172)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "reset_n" (rect 0 0 36 12)(font "Arial" ))
(text "reset_n" (rect 21 43 57 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "en" (rect 0 0 11 12)(font "Arial" ))
(text "en" (rect 21 59 32 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "sel_a" (rect 0 0 25 12)(font "Arial" ))
(text "sel_a" (rect 21 75 46 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "sel_imm" (rect 0 0 41 12)(font "Arial" ))
(text "sel_imm" (rect 21 91 62 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "add_imm" (rect 0 0 44 12)(font "Arial" ))
(text "add_imm" (rect 21 107 65 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "imm[15..0]" (rect 0 0 53 12)(font "Arial" ))
(text "imm[15..0]" (rect 21 123 74 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 0 144)
(input)
(text "a[15..0]" (rect 0 0 37 12)(font "Arial" ))
(text "a[15..0]" (rect 21 139 58 151)(font "Arial" ))
(line (pt 0 144)(pt 16 144)(line_width 3))
)
(port
(pt 160 88)
(output)
(text "addr[31..0]" (rect 0 0 53 12)(font "Arial" ))
(text "addr[31..0]" (rect 86 83 139 95)(font "Arial" ))
(line (pt 160 88)(pt 144 88)(line_width 3))
)
(drawing
(rectangle (rect 16 16 144 160)(line_width 1))
)
)

78
cs208-ca/quartus/RAM.bsf Executable file
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@@ -0,0 +1,78 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 64 64 208 184)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "cs" (rect 0 0 11 12)(font "Arial" ))
(text "cs" (rect 21 43 32 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "write" (rect 0 0 22 12)(font "Arial" ))
(text "write" (rect 21 75 43 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 80 120)
(input)
(text "wrdata[31..0]" (rect 0 -8 63 4)(font "Arial" ))
(text "wrdata[31..0]" (rect 72 35 84 98)(font "Arial" )(vertical))
(line (pt 80 120)(pt 80 104)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "read" (rect 24 56 49 70)(font "Arial" (font_size 8)))
(text "read" (rect 21 58 42 70)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 64 120)
(input)
(text "address[9..0]" (rect 0 -8 64 4)(font "Arial" ))
(text "address[9..0]" (rect 56 32 68 96)(font "Arial" )(vertical))
(line (pt 64 120)(pt 64 104)(line_width 3))
)
(port
(pt 96 120)
(output)
(text "rddata[31..0]" (rect 0 -8 62 4)(font "Arial" ))
(text "rddata[31..0]" (rect 88 36 100 98)(font "Arial" )(vertical))
(line (pt 96 120)(pt 96 104)(line_width 3))
)
(drawing
(rectangle (rect 16 16 128 104)(line_width 1))
)
)

64
cs208-ca/quartus/ROM.bsf Executable file
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@@ -0,0 +1,64 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 64 64 184 184)
(text "ROM" (rect 5 0 29 12)(font "Arial" ))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "cs" (rect 0 0 11 12)(font "Arial" ))
(text "cs" (rect 21 43 32 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "read" (rect 24 56 49 70)(font "Arial" (font_size 8)))
(text "read" (rect 16 56 37 68)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 56 120)
(input)
(text "address[9..0]" (rect 0 24 64 36)(font "Arial" ))
(text "address[9..0]" (rect 48 32 60 96)(font "Arial" )(vertical))
(line (pt 56 120)(pt 56 104)(line_width 3))
)
(port
(pt 72 120)
(output)
(text "rddata[31..0]" (rect 0 24 62 36)(font "Arial" ))
(text "rddata[31..0]" (rect 64 36 76 98)(font "Arial" )(vertical))
(line (pt 72 120)(pt 72 104)(line_width 3))
)
(drawing
(rectangle (rect 16 16 104 104)(line_width 1))
)
)

1025
cs208-ca/quartus/ROM.hex Executable file
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1025
cs208-ca/quartus/ROMwa.hex Executable file
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71
cs208-ca/quartus/add_sub.bsf Executable file
View File

@@ -0,0 +1,71 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 64 64 320 160)
(text "add_sub" (rect 5 0 46 12)(font "Arial" ))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a[31..0]" (rect 0 0 37 12)(font "Arial" ))
(text "a[31..0]" (rect 21 27 58 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "b[31..0]" (rect 0 0 37 12)(font "Arial" ))
(text "b[31..0]" (rect 21 43 58 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "sub_mode" (rect 0 0 50 12)(font "Arial" ))
(text "sub_mode" (rect 21 59 71 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 72 96)
(output)
(text "carry" (rect 104 0 129 12)(font "Arial" ))
(text "carry" (rect 64 47 76 72)(font "Arial" )(vertical))
(line (pt 72 96)(pt 72 80)(line_width 1))
)
(port
(pt 128 96)
(output)
(text "zero" (rect 104 0 124 12)(font "Arial" ))
(text "zero" (rect 120 52 132 72)(font "Arial" )(vertical))
(line (pt 128 96)(pt 128 80)(line_width 1))
)
(port
(pt 256 48)
(output)
(text "r[31..0]" (rect 112 0 147 12)(font "Arial" ))
(text "r[31..0]" (rect 198 43 233 55)(font "Arial" ))
(line (pt 256 48)(pt 240 48)(line_width 3))
)
(drawing
(rectangle (rect 16 16 240 80)(line_width 1))
)
)

78
cs208-ca/quartus/comparator.bsf Executable file
View File

@@ -0,0 +1,78 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 64 64 320 168)
(text "comparator" (rect 5 0 60 12)(font "Arial" ))
(text "inst" (rect 8 88 25 100)(font "Arial" ))
(port
(pt 72 0)
(input)
(text "carry" (rect 0 0 25 12)(font "Arial" ))
(text "carry" (rect 64 16 76 41)(font "Arial" )(vertical))
(line (pt 72 0)(pt 72 16))
)
(port
(pt 128 0)
(input)
(text "zero" (rect 0 0 20 12)(font "Arial" ))
(text "zero" (rect 120 16 132 36)(font "Arial" )(vertical))
(line (pt 128 0)(pt 128 16))
)
(port
(pt 0 64)
(input)
(text "op[2..0]" (rect 0 0 37 12)(font "Arial" ))
(text "op[2..0]" (rect 21 59 58 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 0 32)
(input)
(text "a_31" (rect 0 0 23 12)(font "Arial" ))
(text "a_31" (rect 21 27 44 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "b_31" (rect 0 0 23 12)(font "Arial" ))
(text "b_31" (rect 21 43 44 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 184 0)
(input)
(text "diff_31" (rect 0 0 35 12)(font "Arial" ))
(text "diff_31" (rect 176 16 188 51)(font "Arial" )(vertical))
(line (pt 184 0)(pt 184 16))
)
(port
(pt 256 48)
(output)
(text "r" (rect 166 64 170 78)(font "Arial" (font_size 8)))
(text "r" (rect 224 40 227 52)(font "Arial" ))
(line (pt 256 48)(pt 240 48)(color 128 0 255))
)
(drawing
(rectangle (rect 16 16 240 80))
)
)

176
cs208-ca/quartus/controller.bsf Executable file
View File

@@ -0,0 +1,176 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 64 64 224 384)
(text "controller" (rect 5 0 49 12)(font "Arial" ))
(text "inst" (rect 8 304 25 316)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "reset_n" (rect 0 0 36 12)(font "Arial" ))
(text "reset_n" (rect 21 43 57 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "op[5..0]" (rect 0 0 37 12)(font "Arial" ))
(text "op[5..0]" (rect 21 59 58 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 0 80)
(input)
(text "opx[5..0]" (rect 0 0 43 12)(font "Arial" ))
(text "opx[5..0]" (rect 21 75 64 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 3))
)
(port
(pt 160 32)
(output)
(text "branch_op" (rect 0 0 50 12)(font "Arial" ))
(text "branch_op" (rect 89 27 139 39)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 1))
)
(port
(pt 160 48)
(output)
(text "imm_signed" (rect 0 0 59 12)(font "Arial" ))
(text "imm_signed" (rect 80 43 139 55)(font "Arial" ))
(line (pt 160 48)(pt 144 48)(line_width 1))
)
(port
(pt 160 64)
(output)
(text "ir_en" (rect 0 0 23 12)(font "Arial" ))
(text "ir_en" (rect 116 59 139 71)(font "Arial" ))
(line (pt 160 64)(pt 144 64)(line_width 1))
)
(port
(pt 160 80)
(output)
(text "pc_add_imm" (rect 0 0 62 12)(font "Arial" ))
(text "pc_add_imm" (rect 77 75 139 87)(font "Arial" ))
(line (pt 160 80)(pt 144 80)(line_width 1))
)
(port
(pt 160 96)
(output)
(text "pc_en" (rect 0 0 29 12)(font "Arial" ))
(text "pc_en" (rect 110 91 139 103)(font "Arial" ))
(line (pt 160 96)(pt 144 96)(line_width 1))
)
(port
(pt 160 112)
(output)
(text "pc_sel_a" (rect 0 0 43 12)(font "Arial" ))
(text "pc_sel_a" (rect 96 107 139 119)(font "Arial" ))
(line (pt 160 112)(pt 144 112)(line_width 1))
)
(port
(pt 160 128)
(output)
(text "pc_sel_imm" (rect 0 0 59 12)(font "Arial" ))
(text "pc_sel_imm" (rect 80 123 139 135)(font "Arial" ))
(line (pt 160 128)(pt 144 128)(line_width 1))
)
(port
(pt 160 144)
(output)
(text "rf_wren" (rect 0 0 36 12)(font "Arial" ))
(text "rf_wren" (rect 103 139 139 151)(font "Arial" ))
(line (pt 160 144)(pt 144 144)(line_width 1))
)
(port
(pt 160 160)
(output)
(text "sel_addr" (rect 0 0 41 12)(font "Arial" ))
(text "sel_addr" (rect 98 155 139 167)(font "Arial" ))
(line (pt 160 160)(pt 144 160)(line_width 1))
)
(port
(pt 160 176)
(output)
(text "sel_b" (rect 0 0 25 12)(font "Arial" ))
(text "sel_b" (rect 114 171 139 183)(font "Arial" ))
(line (pt 160 176)(pt 144 176)(line_width 1))
)
(port
(pt 160 192)
(output)
(text "sel_mem" (rect 0 0 44 12)(font "Arial" ))
(text "sel_mem" (rect 95 187 139 199)(font "Arial" ))
(line (pt 160 192)(pt 144 192)(line_width 1))
)
(port
(pt 160 208)
(output)
(text "sel_pc" (rect 0 0 31 12)(font "Arial" ))
(text "sel_pc" (rect 108 203 139 215)(font "Arial" ))
(line (pt 160 208)(pt 144 208)(line_width 1))
)
(port
(pt 160 224)
(output)
(text "sel_ra" (rect 0 0 29 12)(font "Arial" ))
(text "sel_ra" (rect 110 219 139 231)(font "Arial" ))
(line (pt 160 224)(pt 144 224)(line_width 1))
)
(port
(pt 160 240)
(output)
(text "sel_rC" (rect 0 0 31 12)(font "Arial" ))
(text "sel_rC" (rect 108 235 139 247)(font "Arial" ))
(line (pt 160 240)(pt 144 240)(line_width 1))
)
(port
(pt 160 272)
(output)
(text "write" (rect 0 0 22 12)(font "Arial" ))
(text "write" (rect 117 267 139 279)(font "Arial" ))
(line (pt 160 272)(pt 144 272)(line_width 1))
)
(port
(pt 160 288)
(output)
(text "op_alu[5..0]" (rect 0 0 57 12)(font "Arial" ))
(text "op_alu[5..0]" (rect 82 283 139 295)(font "Arial" ))
(line (pt 160 288)(pt 144 288)(line_width 3))
)
(port
(pt 160 256)
(output)
(text "read" (rect 110 248 135 262)(font "Arial" (font_size 8)))
(text "read" (rect 118 248 139 260)(font "Arial" ))
(line (pt 160 256)(pt 144 256)(line_width 1))
)
(drawing
(rectangle (rect 16 16 144 304)(line_width 1))
)
)

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cs208-ca/quartus/db/GECKO.(0).cnf.cdb Executable file
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cs208-ca/quartus/db/GECKO.(19).cnf.cdb Executable file
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cs208-ca/quartus/db/GECKO.(2).cnf.cdb Executable file
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