Disabled external gits

2022-04-07 18:46:57 +02:00
parent 88cb3426ad
commit 15e7120d6d
5316 changed files with 4563444 additions and 6 deletions
@@ -0,0 +1,147 @@
+//--------------------------------------------------------------------------//
+// Title:        de0_nano_soc_baseline.v                                       //
+// Rev:          Rev 0.1                                                    //
+// Last Revised: 09/14/2015                                                 //
+//--------------------------------------------------------------------------//
+// Description: Baseline design file contains DE0 Nano SoC    				 //
+//              Board pins and I/O Standards.                               //
+//--------------------------------------------------------------------------//
+//Copyright 2015 Altera Corporation. All rights reserved.  Altera products
+//are protected under numerous U.S. and foreign patents, maskwork rights,
+//copyrights and other intellectual property laws.
+//                 
+//This reference design file, and your use thereof, is subject to and
+//governed by the terms and conditions of the applicable Altera Reference
+//Design License Agreement.  By using this reference design file, you
+//indicate your acceptance of such terms and conditions between you and
+//Altera Corporation.  In the event that you do not agree with such terms and
+//conditions, you may not use the reference design file. Please promptly                         
+//destroy any copies you have made.
+//
+//This reference design file being provided on an "as-is" basis and as an
+//accommodation and therefore all warranties, representations or guarantees
+//of any kind (whether express, implied or statutory) including, without
+//limitation, warranties of merchantability, non-infringement, or fitness for
+//a particular purpose, are specifically disclaimed.  By making this
+//reference design file available, Altera expressly does not recommend,
+//suggest or require that this reference design file be used in combination 
+//with any other product not provided by Altera
+//----------------------------------------------------------------------------
+
+//Group Enable Definitions
+//This lists every pinout group
+//Users can enable any group by uncommenting the corresponding line below:
+//`define enable_ADC
+//`define enable_ARDUINO
+//`define enable_GPIO0
+//`define enable_GPIO1
+//`define enable_HPS
+
+module de0_nano_soc_baseline(
+
+
+	//////////// CLOCK //////////
+	input 		          		FPGA_CLK_50,
+	input 		          		FPGA_CLK2_50,
+	input 		          		FPGA_CLK3_50,
+
+`ifdef enable_ADC
+	//////////// ADC //////////
+	/* 3.3-V LVTTL */
+	output		          		ADC_CONVST,
+	output		          		ADC_SCLK,
+	output		          		ADC_SDI,
+	input 		          		ADC_SDO,
+`endif
+	
+`ifdef enable_ARDUINO
+	//////////// ARDUINO ////////////
+	/* 3.3-V LVTTL */
+	inout					[15:0]	ARDUINO_IO,
+	inout								ARDUINO_RESET_N,
+`endif
+	
+`ifdef enable_GPIO0
+	//////////// GPIO 0 ////////////
+	/* 3.3-V LVTTL */
+	inout				[35:0]		GPIO_0,
+`endif
+
+`ifdef enable_GPIO1	
+	//////////// GPIO 1 ////////////
+	/* 3.3-V LVTTL */
+	inout				[35:0]		GPIO_1,
+`endif
+
+`ifdef enable_HPS
+	//////////// HPS //////////
+	/* 3.3-V LVTTL */
+	inout 		          		HPS_CONV_USB_N,
+	
+	/* SSTL-15 Class I */
+	output		    [14:0]		HPS_DDR3_ADDR,
+	output		     [2:0]		HPS_DDR3_BA,
+	output		          		HPS_DDR3_CAS_N,
+	output		          		HPS_DDR3_CKE,
+	output		          		HPS_DDR3_CS_N,
+	output		     [3:0]		HPS_DDR3_DM,
+	inout 		    [31:0]		HPS_DDR3_DQ,
+	output		          		HPS_DDR3_ODT,
+	output		          		HPS_DDR3_RAS_N,
+	output		          		HPS_DDR3_RESET_N,
+	input 		          		HPS_DDR3_RZQ,
+	output		          		HPS_DDR3_WE_N,
+	/* DIFFERENTIAL 1.5-V SSTL CLASS I */
+	output		          		HPS_DDR3_CK_N,
+	output		          		HPS_DDR3_CK_P,
+	inout 		     [3:0]		HPS_DDR3_DQS_N,
+	inout 		     [3:0]		HPS_DDR3_DQS_P,
+	
+	/* 3.3-V LVTTL */
+	output		          		HPS_ENET_GTX_CLK,
+	inout 		          		HPS_ENET_INT_N,
+	output		          		HPS_ENET_MDC,
+	inout 		          		HPS_ENET_MDIO,
+	input 		          		HPS_ENET_RX_CLK,
+	input 		     [3:0]		HPS_ENET_RX_DATA,
+	input 		          		HPS_ENET_RX_DV,
+	output		     [3:0]		HPS_ENET_TX_DATA,
+	output		          		HPS_ENET_TX_EN,
+	inout 		          		HPS_GSENSOR_INT,
+	inout 		          		HPS_I2C0_SCLK,
+	inout 		          		HPS_I2C0_SDAT,
+	inout 		          		HPS_I2C1_SCLK,
+	inout 		          		HPS_I2C1_SDAT,
+	inout 		          		HPS_KEY,
+	inout 		          		HPS_LED,
+	inout 		          		HPS_LTC_GPIO,
+	output		          		HPS_SD_CLK,
+	inout 		          		HPS_SD_CMD,
+	inout 		     [3:0]		HPS_SD_DATA,
+	output		          		HPS_SPIM_CLK,
+	input 		          		HPS_SPIM_MISO,
+	output		          		HPS_SPIM_MOSI,
+	inout 		          		HPS_SPIM_SS,
+	input 		          		HPS_UART_RX,
+	output		          		HPS_UART_TX,
+	input 		          		HPS_USB_CLKOUT,
+	inout 		     [7:0]		HPS_USB_DATA,
+	input 		          		HPS_USB_DIR,
+	input 		          		HPS_USB_NXT,
+	output		          		HPS_USB_STP,
+`endif
+	
+	//////////// KEY ////////////
+	/* 3.3-V LVTTL */
+	input				[1:0]			KEY,
+	
+	//////////// LED ////////////
+	/* 3.3-V LVTTL */
+	output			[7:0]			LED,
+	
+	//////////// SW ////////////
+	/* 3.3-V LVTTL */
+	input				[3:0]			SW
+
+);
+endmodule
@@ -0,0 +1,4 @@
+platform_setup.tcl
+filelist.txt
+de0_nano_soc_baseline.v
+de0_nano_soc_baseline.v
@@ -0,0 +1,6 @@
+{
+	"common_dir" : "/data/adu/17.0/Lite/CycloneV/Atlas_SoC_DE0_Nano/de0_nano_soc_baseline_project/",
+	"acds_version" : "Version 17.0.0",
+	"platform" : "linux",
+	"os" : "Red Hat"
+}
@@ -0,0 +1,8 @@
+This devkits directory contains development kit baseline example designs.
+
+HOW TO SETUP PIN ASSIGNMENTS
+1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows.
+2) Type command 'source platform_setup.tcl' in the Tcl console.
+3) Type command 'setup_project' in the Tcl console.
+   - Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file.
+