Disabled external gits
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//--------------------------------------------------------------------------//
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// Title: de0_nano_soc_baseline.v //
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// Rev: Rev 0.1 //
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// Last Revised: 09/14/2015 //
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//--------------------------------------------------------------------------//
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// Description: Baseline design file contains DE0 Nano SoC //
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// Board pins and I/O Standards. //
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//--------------------------------------------------------------------------//
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//Copyright 2015 Altera Corporation. All rights reserved. Altera products
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//are protected under numerous U.S. and foreign patents, maskwork rights,
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//copyrights and other intellectual property laws.
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//
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//This reference design file, and your use thereof, is subject to and
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//governed by the terms and conditions of the applicable Altera Reference
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//Design License Agreement. By using this reference design file, you
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//indicate your acceptance of such terms and conditions between you and
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//Altera Corporation. In the event that you do not agree with such terms and
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//conditions, you may not use the reference design file. Please promptly
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//destroy any copies you have made.
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//
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//This reference design file being provided on an "as-is" basis and as an
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//accommodation and therefore all warranties, representations or guarantees
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//of any kind (whether express, implied or statutory) including, without
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//limitation, warranties of merchantability, non-infringement, or fitness for
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//a particular purpose, are specifically disclaimed. By making this
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//reference design file available, Altera expressly does not recommend,
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//suggest or require that this reference design file be used in combination
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//with any other product not provided by Altera
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//----------------------------------------------------------------------------
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//Group Enable Definitions
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//This lists every pinout group
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//Users can enable any group by uncommenting the corresponding line below:
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//`define enable_ADC
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//`define enable_ARDUINO
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//`define enable_GPIO0
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//`define enable_GPIO1
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//`define enable_HPS
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module de0_nano_soc_baseline(
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//////////// CLOCK //////////
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input FPGA_CLK_50,
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input FPGA_CLK2_50,
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input FPGA_CLK3_50,
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`ifdef enable_ADC
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//////////// ADC //////////
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/* 3.3-V LVTTL */
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output ADC_CONVST,
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output ADC_SCLK,
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output ADC_SDI,
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input ADC_SDO,
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`endif
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`ifdef enable_ARDUINO
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//////////// ARDUINO ////////////
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/* 3.3-V LVTTL */
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inout [15:0] ARDUINO_IO,
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inout ARDUINO_RESET_N,
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`endif
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`ifdef enable_GPIO0
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//////////// GPIO 0 ////////////
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/* 3.3-V LVTTL */
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inout [35:0] GPIO_0,
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`endif
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`ifdef enable_GPIO1
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//////////// GPIO 1 ////////////
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/* 3.3-V LVTTL */
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inout [35:0] GPIO_1,
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`endif
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`ifdef enable_HPS
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//////////// HPS //////////
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/* 3.3-V LVTTL */
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inout HPS_CONV_USB_N,
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/* SSTL-15 Class I */
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output [14:0] HPS_DDR3_ADDR,
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output [2:0] HPS_DDR3_BA,
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output HPS_DDR3_CAS_N,
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output HPS_DDR3_CKE,
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output HPS_DDR3_CS_N,
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output [3:0] HPS_DDR3_DM,
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inout [31:0] HPS_DDR3_DQ,
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output HPS_DDR3_ODT,
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output HPS_DDR3_RAS_N,
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output HPS_DDR3_RESET_N,
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input HPS_DDR3_RZQ,
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output HPS_DDR3_WE_N,
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/* DIFFERENTIAL 1.5-V SSTL CLASS I */
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output HPS_DDR3_CK_N,
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output HPS_DDR3_CK_P,
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inout [3:0] HPS_DDR3_DQS_N,
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inout [3:0] HPS_DDR3_DQS_P,
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/* 3.3-V LVTTL */
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output HPS_ENET_GTX_CLK,
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inout HPS_ENET_INT_N,
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output HPS_ENET_MDC,
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inout HPS_ENET_MDIO,
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input HPS_ENET_RX_CLK,
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input [3:0] HPS_ENET_RX_DATA,
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input HPS_ENET_RX_DV,
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output [3:0] HPS_ENET_TX_DATA,
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output HPS_ENET_TX_EN,
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inout HPS_GSENSOR_INT,
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inout HPS_I2C0_SCLK,
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inout HPS_I2C0_SDAT,
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inout HPS_I2C1_SCLK,
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inout HPS_I2C1_SDAT,
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inout HPS_KEY,
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inout HPS_LED,
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inout HPS_LTC_GPIO,
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output HPS_SD_CLK,
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inout HPS_SD_CMD,
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inout [3:0] HPS_SD_DATA,
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output HPS_SPIM_CLK,
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input HPS_SPIM_MISO,
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output HPS_SPIM_MOSI,
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inout HPS_SPIM_SS,
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input HPS_UART_RX,
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output HPS_UART_TX,
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input HPS_USB_CLKOUT,
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inout [7:0] HPS_USB_DATA,
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input HPS_USB_DIR,
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input HPS_USB_NXT,
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output HPS_USB_STP,
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`endif
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//////////// KEY ////////////
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/* 3.3-V LVTTL */
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input [1:0] KEY,
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//////////// LED ////////////
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/* 3.3-V LVTTL */
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output [7:0] LED,
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//////////// SW ////////////
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/* 3.3-V LVTTL */
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input [3:0] SW
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);
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endmodule
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@ -0,0 +1,4 @@
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platform_setup.tcl
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filelist.txt
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de0_nano_soc_baseline.v
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de0_nano_soc_baseline.v
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@ -0,0 +1,6 @@
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{
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"common_dir" : "/data/adu/17.0/Lite/CycloneV/Atlas_SoC_DE0_Nano/de0_nano_soc_baseline_project/",
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"acds_version" : "Version 17.0.0",
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"platform" : "linux",
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"os" : "Red Hat"
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}
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8
cs473-es/lab3/hw/quartus/devkits/readme.txt
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8
cs473-es/lab3/hw/quartus/devkits/readme.txt
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This devkits directory contains development kit baseline example designs.
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HOW TO SETUP PIN ASSIGNMENTS
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1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows.
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2) Type command 'source platform_setup.tcl' in the Tcl console.
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3) Type command 'setup_project' in the Tcl console.
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- Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file.
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