Disabled external gits
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141
cs473-es/lab3/hw/hdl/LCDController/LCDDriver_tb.vhd
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141
cs473-es/lab3/hw/hdl/LCDController/LCDDriver_tb.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity LCDDriver_tb is
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end LCDDriver_tb;
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architecture test of LCDDriver_tb is
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constant CLK_PERIOD : time := 20 ns;
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constant N_LED_MAX : integer := 255;
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signal clk : std_logic := '0';
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signal rst_n : std_logic := '1';
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signal data_in : std_logic_vector(15 downto 0) := (others=> '0');
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signal empty_in : std_logic := '1';
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signal refresh_in : std_logic := '0';
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signal cmd_en_in : std_logic := '0';
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signal cmd_dcx_in : std_logic := '0';
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signal cmd_data_in : std_logic_vector(7 downto 0) := (others => '0');
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signal m_finished_in : std_logic := '0';
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signal data_out : std_logic_vector(15 downto 0);
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signal rd_n : std_logic;
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signal wr_n : std_logic;
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signal rs : std_logic;
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signal cs_n : std_logic;
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signal lcd_rdreq : std_logic;
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signal rdreq_cnt : integer := 0;
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signal busy : std_logic;
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begin
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-- Instantiate DUT
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dut : entity work.LCDDriver
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generic map (
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F_CLK => 50000000
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)
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port map(
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clk => clk,
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rst_n => rst_n,
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data_in => data_in,
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empty_in => empty_in,
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refresh_in => refresh_in,
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cmd_en_in => cmd_en_in,
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cmd_dcx_in => cmd_dcx_in,
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cmd_data_in => cmd_data_in,
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m_finished_in => m_finished_in,
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data_out => data_out,
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rd_n => rd_n,
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wr_n => wr_n,
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rs => rs,
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cs_n => cs_n,
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lcd_rdreq => lcd_rdreq,
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busy => busy
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);
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-- Clocking process
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clk_generation : process
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begin
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clk <= not clk;
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wait for CLK_PERIOD / 2;
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end process;
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process (lcd_rdreq) begin
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if rising_edge(lcd_rdreq) then
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if (rdreq_cnt = 0) then
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data_in <= "1111111111111111";
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elsif (rdreq_cnt = 1) then
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data_in <= "1111000000001111";
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elsif (rdreq_cnt = 2) then
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data_in <= "1111111100000000";
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elsif (rdreq_cnt = 3) then
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data_in <= "0000000011111111";
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else
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data_in <= "0000000000000000";
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end if;
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rdreq_cnt <= rdreq_cnt + 1;
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end if;
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end process;
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tb : process
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procedure wait_ready is
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begin
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if busy = '1' then
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wait until busy = '0';
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end if;
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end procedure wait_ready;
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procedure finish is
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begin
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wait until falling_edge(clk);
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wait_ready;
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wait;
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end procedure finish ;
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begin
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-- Reset
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rst_n <= '0';
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wait for CLK_PERIOD * 2.5;
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rst_n <= '1';
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wait for CLK_PERIOD * 2;
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wait_ready;
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-- Test CMD
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cmd_en_in <= '1';
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cmd_dcx_in <= '1';
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cmd_data_in <= "11010011";
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wait for CLK_PERIOD * 2.5;
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cmd_en_in <= '0';
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wait_ready;
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-- Test REFRESH
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refresh_in <= '1';
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wait for CLK_PERIOD * 2.5;
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refresh_in <= '0';
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wait for CLK_PERIOD * 4;
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empty_in <= '0';
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wait until rdreq_cnt = 4;
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empty_in <= '1';
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--m_finished_in => m_finished_in,
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wait_ready;
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-- Test finished
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finish;
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end process;
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end;
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