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Disabled external gits

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This commit is contained in:
choelzl
2022-04-07 18:46:57 +02:00
parent 88cb3426ad
commit 15e7120d6d
5316 changed files with 4563444 additions and 6 deletions
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178
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-- #############################################################################
-- DE0_Nano_SoC_LT24_top_level.vhd
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.2
-- Creation date : 11/06/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_LT24_top_level is
port(
-- -- ADC
-- ADC_CONVST : out std_logic;
-- ADC_SCK : out std_logic;
-- ADC_SDI : out std_logic;
-- ADC_SDO : in std_logic;
-- -- ARDUINO
-- ARDUINO_IO : inout std_logic_vector(15 downto 0);
-- ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
-- FPGA_CLK2_50 : in std_logic;
-- FPGA_CLK3_50 : in std_logic;
-- -- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- -- LED
-- LED : out std_logic_vector(7 downto 0);
-- -- SW
-- SW : in std_logic_vector(3 downto 0);
-- GPIO_0
-- GPIO_0_LT24_ADC_BUSY : in std_logic;
-- GPIO_0_LT24_ADC_CS_N : out std_logic;
-- GPIO_0_LT24_ADC_DCLK : out std_logic;
-- GPIO_0_LT24_ADC_DIN : out std_logic;
-- GPIO_0_LT24_ADC_DOUT : in std_logic;
-- GPIO_0_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_0_LT24_CS_N : out std_logic;
GPIO_0_LT24_D : out std_logic_vector(15 downto 0);
GPIO_0_LT24_LCD_ON : out std_logic;
GPIO_0_LT24_RD_N : out std_logic;
GPIO_0_LT24_RESET_N : out std_logic;
GPIO_0_LT24_RS : out std_logic;
GPIO_0_LT24_WR_N : out std_logic;
-- GPIO_1
--GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
--HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic
--HPS_ENET_GTX_CLK : out std_logic;
--HPS_ENET_INT_N : inout std_logic;
--HPS_ENET_MDC : out std_logic;
--HPS_ENET_MDIO : inout std_logic;
--HPS_ENET_RX_CLK : in std_logic;
--HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
--HPS_ENET_RX_DV : in std_logic;
--HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
--HPS_ENET_TX_EN : out std_logic;
--HPS_GSENSOR_INT : inout std_logic;
--HPS_I2C0_SCLK : inout std_logic;
--HPS_I2C0_SDAT : inout std_logic;
--HPS_I2C1_SCLK : inout std_logic;
--HPS_I2C1_SDAT : inout std_logic;
--HPS_KEY_N : inout std_logic;
--HPS_LED : inout std_logic;
--HPS_LTC_GPIO : inout std_logic;
--HPS_SD_CLK : out std_logic;
--HPS_SD_CMD : inout std_logic;
--HPS_SD_DATA : inout std_logic_vector(3 downto 0)
--HPS_SPIM_CLK : out std_logic;
--HPS_SPIM_MISO : in std_logic;
--HPS_SPIM_MOSI : out std_logic;
--HPS_SPIM_SS : inout std_logic;
--HPS_UART_RX : in std_logic;
--HPS_UART_TX : out std_logic
--HPS_USB_CLKOUT : in std_logic;
--HPS_USB_DATA : inout std_logic_vector(7 downto 0);
--HPS_USB_DIR : in std_logic;
--HPS_USB_NXT : in std_logic;
--HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_LT24_top_level;
architecture rtl of DE0_Nano_SoC_LT24_top_level is
component system is
port (
clk_clk : in std_logic;
hps_memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
hps_memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
hps_memory_mem_ck : out std_logic; -- mem_ck
hps_memory_mem_ck_n : out std_logic; -- mem_ck_n
hps_memory_mem_cke : out std_logic; -- mem_cke
hps_memory_mem_cs_n : out std_logic; -- mem_cs_n
hps_memory_mem_ras_n : out std_logic; -- mem_ras_n
hps_memory_mem_cas_n : out std_logic; -- mem_cas_n
hps_memory_mem_we_n : out std_logic; -- mem_we_n
hps_memory_mem_reset_n : out std_logic; -- mem_reset_n
hps_memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
hps_memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
hps_memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
hps_memory_mem_odt : out std_logic; -- mem_odt
hps_memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
hps_memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
lcdcontroller_0_lt24_data : out std_logic_vector(15 downto 0);
lcdcontroller_0_lt24_rd_n : out std_logic;
lcdcontroller_0_lt24_wr_n : out std_logic;
lcdcontroller_0_lt24_rs : out std_logic;
lcdcontroller_0_lt24_cs_n : out std_logic;
lcdcontroller_0_lt24_reset_n : out std_logic;
lcdcontroller_0_lt24_lcd_on : out std_logic;
reset_reset_n : in std_logic
);
end component system;
begin
u0 : component system
port map (
clk_clk => FPGA_CLK1_50,
hps_memory_mem_a => HPS_DDR3_ADDR,
hps_memory_mem_ba => HPS_DDR3_BA,
hps_memory_mem_ck => HPS_DDR3_CK_P,
hps_memory_mem_ck_n => HPS_DDR3_CK_N,
hps_memory_mem_cke => HPS_DDR3_CKE,
hps_memory_mem_cs_n => HPS_DDR3_CS_N,
hps_memory_mem_ras_n => HPS_DDR3_RAS_N,
hps_memory_mem_cas_n => HPS_DDR3_CAS_N,
hps_memory_mem_we_n => HPS_DDR3_WE_N,
hps_memory_mem_reset_n => HPS_DDR3_RESET_N,
hps_memory_mem_dq => HPS_DDR3_DQ,
hps_memory_mem_dqs => HPS_DDR3_DQS_P,
hps_memory_mem_dqs_n => HPS_DDR3_DQS_N,
hps_memory_mem_odt => HPS_DDR3_ODT,
hps_memory_mem_dm => HPS_DDR3_DM,
hps_memory_oct_rzqin => HPS_DDR3_RZQ,
reset_reset_n => KEY_N(0),
lcdcontroller_0_lt24_data => GPIO_0_LT24_D,
lcdcontroller_0_lt24_cs_n => GPIO_0_LT24_CS_N,
lcdcontroller_0_lt24_rd_n => GPIO_0_LT24_RD_N,
lcdcontroller_0_lt24_wr_n => GPIO_0_LT24_WR_N,
lcdcontroller_0_lt24_rs => GPIO_0_LT24_RS,
lcdcontroller_0_lt24_reset_n => GPIO_0_LT24_RESET_N,
lcdcontroller_0_lt24_lcd_on => GPIO_0_LT24_LCD_ON
);
end;

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-- #############################################################################
-- DE0_Nano_SoC_TRDB_D5M_LT24_top_level.vhd
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.3
-- Creation date : 11/06/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_TRDB_D5M_LT24_top_level is
port(
-- ADC
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0_LT24_ADC_BUSY : in std_logic;
GPIO_0_LT24_ADC_CS_N : out std_logic;
GPIO_0_LT24_ADC_DCLK : out std_logic;
GPIO_0_LT24_ADC_DIN : out std_logic;
GPIO_0_LT24_ADC_DOUT : in std_logic;
GPIO_0_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_0_LT24_CS_N : out std_logic;
GPIO_0_LT24_D : out std_logic_vector(15 downto 0);
GPIO_0_LT24_LCD_ON : out std_logic;
GPIO_0_LT24_RD_N : out std_logic;
GPIO_0_LT24_RESET_N : out std_logic;
GPIO_0_LT24_RS : out std_logic;
GPIO_0_LT24_WR_N : out std_logic;
-- GPIO_1
GPIO_1_D5M_D : in std_logic_vector(11 downto 0);
GPIO_1_D5M_FVAL : in std_logic;
GPIO_1_D5M_LVAL : in std_logic;
GPIO_1_D5M_PIXCLK : in std_logic;
GPIO_1_D5M_RESET_N : out std_logic;
GPIO_1_D5M_SCLK : inout std_logic;
GPIO_1_D5M_SDATA : inout std_logic;
GPIO_1_D5M_STROBE : in std_logic;
GPIO_1_D5M_TRIGGER : out std_logic;
GPIO_1_D5M_XCLKIN : out std_logic;
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_TRDB_D5M_LT24_top_level;
architecture rtl of DE0_Nano_SoC_TRDB_D5M_LT24_top_level is
begin
end;

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-- #############################################################################
-- DE0_Nano_SoC_TRDB_D5M_VGA_top_level.vhd
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.2
-- Creation date : 11/06/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_TRDB_D5M_VGA_top_level is
port(
-- ADC
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0_VGA_VIDEO_R : out std_logic_vector(7 downto 0);
GPIO_0_VGA_VIDEO_G : out std_logic_vector(7 downto 0);
GPIO_0_VGA_VIDEO_B : out std_logic_vector(7 downto 0);
GPIO_0_VGA_VIDEO_HSYNC : out std_logic;
GPIO_0_VGA_VIDEO_VSYNC : out std_logic;
GPIO_0_VGA_VIDEO_CLK : out std_logic;
GPIO_0_VGA_CAM_PAL_VGA_SCL : out std_logic;
GPIO_0_VGA_CAM_PAL_VGA_SDA : inout std_logic;
GPIO_0_VGA_BOARD_ID : inout std_logic;
-- GPIO_1
GPIO_1_D5M_D : in std_logic_vector(11 downto 0);
GPIO_1_D5M_FVAL : in std_logic;
GPIO_1_D5M_LVAL : in std_logic;
GPIO_1_D5M_PIXCLK : in std_logic;
GPIO_1_D5M_RESET_N : out std_logic;
GPIO_1_D5M_SCLK : inout std_logic;
GPIO_1_D5M_SDATA : inout std_logic;
GPIO_1_D5M_STROBE : in std_logic;
GPIO_1_D5M_TRIGGER : out std_logic;
GPIO_1_D5M_XCLKIN : out std_logic;
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_TRDB_D5M_VGA_top_level;
architecture rtl of DE0_Nano_SoC_TRDB_D5M_VGA_top_level is
begin
end;

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-- #############################################################################
-- DE0_Nano_SoC_TRDB_D5M_top_level.vhd
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.3
-- Creation date : 11/06/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_TRDB_D5M_top_level is
port(
-- ADC
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
GPIO_1_D5M_D : in std_logic_vector(11 downto 0);
GPIO_1_D5M_FVAL : in std_logic;
GPIO_1_D5M_LVAL : in std_logic;
GPIO_1_D5M_PIXCLK : in std_logic;
GPIO_1_D5M_RESET_N : out std_logic;
GPIO_1_D5M_SCLK : inout std_logic;
GPIO_1_D5M_SDATA : inout std_logic;
GPIO_1_D5M_STROBE : in std_logic;
GPIO_1_D5M_TRIGGER : out std_logic;
GPIO_1_D5M_XCLKIN : out std_logic;
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_TRDB_D5M_top_level;
architecture rtl of DE0_Nano_SoC_TRDB_D5M_top_level is
begin
end;

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-- #############################################################################
-- DE0_Nano_SoC_top_level.vhd
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.1
-- Creation date : 11/06/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_top_level is
port(
-- ADC
--ADC_CONVST : out std_logic;
--ADC_SCK : out std_logic;
--ADC_SDI : out std_logic;
--ADC_SDO : in std_logic;
-- ARDUINO
--ARDUINO_IO : inout std_logic_vector(15 downto 0);
--ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
--FPGA_CLK2_50 : in std_logic;
--FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
--LED : out std_logic_vector(7 downto 0);
-- SW
--SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0 : inout std_logic_vector(35 downto 0)
-- GPIO_1
--GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
--HPS_CONV_USB_N : inout std_logic;
--HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
--HPS_DDR3_BA : out std_logic_vector(2 downto 0);
--HPS_DDR3_CAS_N : out std_logic;
--HPS_DDR3_CK_N : out std_logic;
--HPS_DDR3_CK_P : out std_logic;
--HPS_DDR3_CKE : out std_logic;
--HPS_DDR3_CS_N : out std_logic;
--HPS_DDR3_DM : out std_logic_vector(3 downto 0);
--HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
--HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
--HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
--HPS_DDR3_ODT : out std_logic;
--HPS_DDR3_RAS_N : out std_logic;
--HPS_DDR3_RESET_N : out std_logic;
--HPS_DDR3_RZQ : in std_logic;
--HPS_DDR3_WE_N : out std_logic;
--HPS_ENET_GTX_CLK : out std_logic;
--HPS_ENET_INT_N : inout std_logic;
--HPS_ENET_MDC : out std_logic;
--HPS_ENET_MDIO : inout std_logic;
--HPS_ENET_RX_CLK : in std_logic;
--HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
--HPS_ENET_RX_DV : in std_logic;
--HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
--HPS_ENET_TX_EN : out std_logic;
--HPS_GSENSOR_INT : inout std_logic;
--HPS_I2C0_SCLK : inout std_logic;
--HPS_I2C0_SDAT : inout std_logic;
--HPS_I2C1_SCLK : inout std_logic;
--HPS_I2C1_SDAT : inout std_logic;
--HPS_KEY_N : inout std_logic;
--HPS_LED : inout std_logic;
--HPS_LTC_GPIO : inout std_logic;
--HPS_SD_CLK : out std_logic;
--HPS_SD_CMD : inout std_logic;
--HPS_SD_DATA : inout std_logic_vector(3 downto 0);
--HPS_SPIM_CLK : out std_logic;
--HPS_SPIM_MISO : in std_logic;
--HPS_SPIM_MOSI : out std_logic;
--HPS_SPIM_SS : inout std_logic;
--HPS_UART_RX : in std_logic;
--HPS_UART_TX : out std_logic;
--HPS_USB_CLKOUT : in std_logic;
--HPS_USB_DATA : inout std_logic_vector(7 downto 0);
--HPS_USB_DIR : in std_logic;
--HPS_USB_NXT : in std_logic;
--HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_top_level;
architecture rtl of DE0_Nano_SoC_top_level is
component system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
ws28xx_0_conduit_end_ws : out std_logic := 'X' -- export
);
end component system;
begin
u0 : component system
port map (
clk_clk => FPGA_CLK1_50, -- clk.clk
reset_reset_n => KEY_N(0), -- reset.reset_n
ws28xx_0_conduit_end_ws => GPIO_0(0) -- ws28xx_0_conduit_end.export
);
end;

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-- #############################################################################
-- DE0_Nano_Soc_7_segment_extension_board.vhd
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Florian Depraz
-- : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.0
-- Creation date : 27/10/2016
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_Soc_7_segment_extension is
port(
-- ADC
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0 : inout std_logic_vector(35 downto 0);
-- Extension board 7 segments
SelSeg : out std_logic_vector(7 downto 0);
Reset_Led : out std_logic;
nSelDig : out std_logic_vector(5 downto 0);
SwLed : in std_logic_vector(7 downto 0);
nButton : in std_logic_vector(3 downto 0)
LedButton : out std_logic_vector(3 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_Soc_7_segment_extension;
architecture rtl of DE0_Nano_Soc_7_segment_extension is
begin
end;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity ClkGen is
generic (
F_CLK : natural; -- Hz
F_OUT : natural; -- Hz
F_MIN : natural; -- Hz
F_MAX : natural -- Hz
);
port (
clk : in std_logic;
rst_n : in std_logic;
clk_o : out std_logic;
en : in std_logic
);
end ClkGen;
architecture Behavioral of ClkGen is
constant CNT_MAX : integer := integer(floor(real(F_CLK) / real(F_OUT))) - 1;
constant F_ACTUAL : integer := (F_CLK/natural(CNT_MAX+1));
signal counter_reg, counter_next: integer range CNT_MAX downto 0;
begin
assert F_MIN <= F_ACTUAL report "Invalid Timings for ClkGen ("&integer'image(F_ACTUAL)&"hz < "&integer'image(F_MIN)&"hz)" severity error;
assert F_MAX >= F_ACTUAL report "Invalid Timings for ClkGen ("&integer'image(F_ACTUAL)&"hz > "&integer'image(F_MAX)&"hz)" severity error;
assert F_MIN <= F_OUT and F_OUT <= F_MAX report "Invalid Timings for ClkGen (F_MIN<=F_OUT<=F_MAX)." severity error;
counter_next <= CNT_MAX when counter_reg = 0 else counter_reg - 1;
process(clk, rst_n) begin
if rising_edge(clk) then
if rst_n = '0' then
counter_reg <= CNT_MAX;
else
if en = '1' then
counter_reg <= counter_next;
end if;
end if;
end if;
end process;
clk_o <= '1' when counter_reg = 0 and en = '1' else '0';
end Behavioral; -- Behavioral

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-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity LCDAvalonMaster is
generic (
NWORDS_MAX : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
waitreq : in std_logic;
readdata : in std_logic_vector(31 downto 0);
readdatavalid : in std_logic;
address : out std_logic_vector(31 downto 0);
burstcount : out std_logic_vector(4 downto 0);
am_read : out std_logic;
refresh : in std_logic;
fifo_almost_empty : in std_logic;
fifo_data : out std_logic_vector(31 downto 0);
fifo_wr_req : out std_logic;
baseaddress : in std_logic_vector(31 downto 0);
nwords : in std_logic_vector(integer(ceil(log2(real(NWORDS_MAX)))) downto 0)
);
end LCDAvalonMaster;
architecture behavioral of LCDAvalonMaster is
-- Generic constants
constant BURST_COUNT : integer := 16;
constant BURST_COUNT_SLV : std_logic_vector(burstcount'left downto 0) := std_logic_vector(to_unsigned(BURST_COUNT, burstcount'length));
-- Type definitions
type State is (S_READY, S_BURSTREQ, S_BURSTRD, S_FIFOWAIT);
subtype BurstCounter is integer range 0 to BURST_COUNT;
subtype WordCounter is integer range 0 to NWORDS_MAX;
-- Inferred registers
signal rdaddr_reg, rdaddr_next : std_logic_vector(31 downto 0);
signal state_reg, state_next : State;
signal burstcnt_reg, burstcnt_next : BurstCounter; -- Counts # of words read during a single burst
signal wordcnt_reg, wordcnt_next : WordCounter; -- Counts # of words read during a refresh cycle
begin
-- PROCESS state machine
process(all) begin
state_next <= state_reg;
rdaddr_next <= rdaddr_reg;
burstcnt_next <= burstcnt_reg;
wordcnt_next <= wordcnt_reg;
-- Avalon master default output signals
burstcount <= BURST_COUNT_SLV;
am_read <= '0';
case state_reg is
when S_READY =>
-- ====================== AM STATE: READY ======================
if refresh = '1' then
wordcnt_next <= integer(to_integer(unsigned(nwords)));
state_next <= S_BURSTREQ;
end if;
when S_BURSTREQ =>
-- ================== AM STATE: BURST REQUEST ==================
am_read <= '1';
if waitreq = '0' then
-- Burst was accepted,
state_next <= S_BURSTRD;
-- Calculate the # of words we plan to read during this burst
-- and update counters accordingly.
if wordcnt_reg < BURST_COUNT then
burstcnt_next <= wordcnt_reg;
wordcnt_next <= 0;
else
burstcnt_next <= BURST_COUNT;
wordcnt_next <= wordcnt_reg - BURST_COUNT;
end if;
end if;
when S_BURSTRD =>
-- ==================== AM STATE: BURST READ ===================
if readdatavalid = '1' then
if burstcnt_reg = 1 then
-- Got last word, burst read finished
if wordcnt_reg = 0 then
-- All nwords read
state_next <= S_READY;
else
-- < nwords read
state_next <= S_FIFOWAIT;
end if;
else
burstcnt_next <= burstcnt_reg - 1;
end if;
end if;
when S_FIFOWAIT =>
-- ==================== AM STATE: FIFO WAIT ====================
-- Await the assertion of fifo_almost_empty until reinitiating a
-- burst read
if fifo_almost_empty = '1' then
state_next <= S_BURSTREQ;
end if;
end case;
end process;
-- FIFO data transfer routing
fifo_wr_req <= '1' when state_reg = S_BURSTRD and readdatavalid = '1' else '0';
fifo_data <= readdata when state_reg = S_BURSTRD else (others => 'Z');
address <= std_logic_vector(unsigned(baseaddress) + resize((unsigned(nwords) - wordcnt_reg) * 4, address'length)) when state_reg = S_BURSTREQ else (others => 'Z');
-- Clocking process/register inferrence
process(clk) begin
if rising_edge(clk) then
if rst_n = '0' then
rdaddr_reg <= (others => '0');
state_reg <= S_READY;
burstcnt_reg <= BURST_COUNT;
wordcnt_reg <= 0;
else
rdaddr_reg <= rdaddr_next;
state_reg <= state_next;
burstcnt_reg <= burstcnt_next;
wordcnt_reg <= wordcnt_next;
end if;
end if;
end process;
end behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity LCDAvalonMaster_tb is
end LCDAvalonMaster_tb;
architecture test of LCDAvalonMaster_tb is
constant CLK_PERIOD : time := 20 ns;
constant N_LED_MAX : integer := 255;
-- 20 = 1 full burst + 1 non full burst
constant NWORDS : natural := 20;
constant NWORDS_MAX :natural := (320*240)/2;
signal clk : std_logic := '0';
signal rst_n : std_logic;
signal waitreq, readdatavalid, refresh, fifo_almost_empty : std_logic;
signal readdata : std_logic_vector(31 downto 0);
signal baseaddress : std_logic_vector(31 downto 0);
signal nwords_sig : std_logic_vector(integer(floor(log2(real(NWORDS_MAX)))) downto 0);
begin
nwords_sig <= std_logic_vector(to_unsigned(NWORDS, nwords_sig'length));
-- Instantiate DUT
dut : entity work.LCDAvalonMaster
generic map (
NWORDS_MAX => NWORDS_MAX
)
port map(
clk => clk,
rst_n => rst_n,
waitreq => waitreq,
readdatavalid => readdatavalid,
refresh => refresh,
fifo_almost_empty => fifo_almost_empty,
readdata => readdata,
baseaddress => baseaddress,
nwords => nwords_sig
);
-- Clocking process
clk_generation : process
begin
clk <= not clk;
wait for CLK_PERIOD / 2;
end process;
-- Testbench
tb : process
begin
while true loop
-- Dummy signals from bus
readdata <= X"12341234";
readdatavalid <= '0';
waitreq <= '1';
baseaddress <= X"10000000";
fifo_almost_empty <= '0';
-- Reset
rst_n <= '0';
wait for CLK_PERIOD * 2.5;
rst_n <= '1';
wait for CLK_PERIOD * 2;
-- Initiate a refresh cycle
wait until rising_edge(clk);
refresh <= '1';
wait for CLK_PERIOD;
refresh <= '0';
-- Wait until bus grant
wait for CLK_PERIOD * 3;
waitreq <= '0';
wait for CLK_PERIOD;
-- Emulate that new read data is valid each cycle of the burst
readdatavalid <= '1';
for i in 1 to 16 loop
wait for CLK_PERIOD;
end loop;
readdatavalid <= '0';
wait for CLK_PERIOD * 5;
-- Assert fifo_almost empty; should repromt another transfer
fifo_almost_empty <= '1';
wait for CLK_period;
fifo_almost_empty <= '0';
wait for CLK_PERIOD * 2;
readdatavalid <= '1';
for i in 1 to 16 loop
wait for CLK_PERIOD;
end loop;
-- Test finished
wait for CLK_PERIOD * 5;
end loop;
end process;
end;

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-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
LIBRARY altera_mf;
use altera_mf.altera_mf_components.all;
entity LCDController is
port(
clk : in std_logic;
rst_n : in std_logic;
-- Avalon slave interface
avalon_slave_address : in std_logic_vector (3 downto 0);
avalon_slave_write : in std_logic;
avalon_slave_writedata : in std_logic_vector(31 downto 0);
avalon_slave_read : in std_logic;
avalon_slave_readdata : out std_logic_vector(31 downto 0);
avalon_slave_waitrequest : out std_logic;
av_irq : out std_logic;
-- Avalon master interface
avalon_master_waitreq : in std_logic;
avalon_master_readdata : in std_logic_vector(31 downto 0);
avalon_master_readdatavalid : in std_logic;
avalon_master_address : out std_logic_vector(31 downto 0);
avalon_master_burstcount : out std_logic_vector(4 downto 0);
avalon_master_read : out std_logic;
-- LT24 conduit interface
lt24_rd_n : out std_logic;
lt24_wr_n : out std_logic;
lt24_rs : out std_logic;
lt24_cs_n : out std_logic;
lt24_data : out std_logic_vector(15 downto 0);
lt24_reset_n : out std_logic;
lt24_lcd_on : out std_logic
);
end LCDController;
architecture comp of LCDController is
-- Type definitions
type State is (S_READY, S_REFRESHING);
type IRQ_CTRL is record
enabled : boolean;
clear_on_refresh : boolean;
irq0_active : std_logic;
end record IRQ_CTRL;
-- Generic constants
constant F_CLK : natural := 50*10**6;
constant ZERO_ADDR : std_logic_vector(31 downto 0) := (others => '0');
constant MAX_H : natural := 240;
constant MAX_W : natural := 320;
constant N_PIXELS : natural := MAX_H * MAX_W;
constant PIXEL_WIDTH : natural := 16;
constant AVM_BURST_LEN : natural := 256;
constant IRQ_CTRL_DEFAULT : IRQ_CTRL := (
enabled => true,
clear_on_refresh => true,
irq0_active => '0'
);
-- Avalon slave programmable interface constants
constant A_WRITEREG : natural := 0;
constant A_WRITEDATA : natural := 1;
constant A_WRITEBASE : natural := 2;
constant A_REFRESH : natural := 3;
constant A_SETENABLED : natural := 4;
constant A_SETHEIGHT : natural := 5;
constant A_SETWIDTH : natural := 6;
constant A_WRITEIRQ : natural := 7;
constant A_SETIRQ : natural := 8;
constant A_CLEARIRQ : natural := 9;
constant A_ISBUSY : natural := 10;
constant LAST_avalon_slave_ADDR : natural := A_ISBUSY;
signal avalon_slave_address_int : integer range 0 to LAST_avalon_slave_ADDR;
-- FIFO configuration parameters
constant FIFO_N_ALMOST_EMPTY : natural := 32;
constant FIFO_WIDTH : natural := 32;
constant FIFO_SIZE : natural := AVM_BURST_LEN + FIFO_N_ALMOST_EMPTY;
constant PIXELS_PER_WORD : natural := FIFO_WIDTH / PIXEL_WIDTH;
constant NWORDS_MAX : natural := N_PIXELS / PIXELS_PER_WORD;
-- FIFO signals
signal fifo_almost_empty : std_logic;
signal fifo_wr_req : std_logic;
signal fifo_data_in, fifo_data_out : std_logic_vector(FIFO_WIDTH - 1 downto 0);
signal fifo_rd_req : std_logic;
signal fifo_empty : std_logic;
-- Inferred registers
signal baseaddr_reg, baseaddr_next : std_logic_vector(31 downto 0);
signal state_reg, state_next : State;
signal lcd_on_reg, lcd_on_next : std_logic := '1';
signal lcd_rst_reg, lcd_rst_next : std_logic := '0';
signal width_reg, width_next : integer range 0 to MAX_W;
signal height_reg, height_next : integer range 0 to MAX_H;
signal irq_ctrl_reg, irq_ctrl_next : IRQ_CTRL;
-- LCD Driver interfacing signals
signal lcd_cmd_en : std_logic;
signal lcd_cmd_dcx : std_logic;
signal lcd_cmd_data : std_logic_vector(7 downto 0);
signal lcd_busy : std_logic;
signal lcd_req : std_logic;
signal lcd_data : std_logic_vector(15 downto 0);
signal lcd_empty : std_logic;
-- LCDController state signals
signal refresh : std_logic;
-- # of words required by the fifo to gather all pixels in an image based on
-- current width and height values
signal av_nwords : std_logic_vector(integer(ceil(log2(real(NWORDS_MAX)))) downto 0);
function writeIRQCtrl(v : in std_logic_vector(2 downto 0)) return IRQ_CTRL is
variable res : IRQ_CTRL;
begin
res.enabled := v(0) = '1';
res.clear_on_refresh := v(1) = '1';
res.irq0_active := v(2);
return res;
end writeIRQCtrl;
function setIRQCtrl(current: in IRQ_CTRL; v : in std_logic_vector(2 downto 0)) return IRQ_CTRL is
variable res : IRQ_CTRL;
begin
res := current;
res.enabled := current.enabled or v(0) = '1';
res.clear_on_refresh := current.clear_on_refresh or v(1) = '1';
res.irq0_active := current.irq0_active or v(2);
return res;
end setIRQCtrl;
function clearIRQCtrl(current: in IRQ_CTRL; v : in std_logic_vector(2 downto 0)) return IRQ_CTRL is
variable res : IRQ_CTRL;
begin
res := current;
res.enabled := current.enabled and not v(0) = '1';
res.clear_on_refresh := current.clear_on_refresh and not v(1) = '1';
res.irq0_active := current.irq0_active and not v(2);
return res;
end clearIRQCtrl;
--Component declaration, required for altera library IP
component scfifo
generic (
almost_empty_value : natural;
lpm_numwords : natural;
lpm_width : natural;
lpm_widthu : natural
);
port(
aclr : in std_logic;
almost_empty : out std_logic;
clock : in std_logic;
data : in std_logic_vector(lpm_width-1 downto 0);
empty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
wrreq : in std_logic
);
end component;
begin
-- ENTITY LCDDriver:
lcddriver_ent : entity work.LCDDriver
generic map (
F_CLK => F_CLK
)
port map (
clk => clk,
rst_n => rst_n,
data_in => lcd_data,
empty_in => lcd_empty,
refresh_in => refresh,
cmd_en_in => lcd_cmd_en,
cmd_dcx_in => lcd_cmd_dcx,
cmd_data_in => lcd_cmd_data,
data_out => lt24_data,
rd_n => lt24_rd_n,
wr_n => lt24_wr_n,
rs => lt24_rs,
cs_n => lt24_cs_n,
lcd_rdreq => lcd_req,
busy => lcd_busy
);
-- ENTITY PixTrans:
pixtrans_ent : entity work.PixTrans
generic map (
MAX_H => MAX_H,
MAX_W => MAX_W
)
port map (
clk => clk,
rst_n => rst_n,
lcd_req => lcd_req,
data => lcd_data,
empty => lcd_empty,
fifo_req => fifo_rd_req,
fifo_q => fifo_data_out,
fifo_empty => fifo_empty,
w => width_reg,
h => height_reg
);
-- ENTITY Avalon master:
avalon_master_ent : entity work.LCDAvalonMaster
generic map (
NWORDS_MAX => NWORDS_MAX
)
port map (
clk => clk,
rst_n => rst_n,
waitreq => avalon_master_waitreq,
readdata => avalon_master_readdata,
readdatavalid => avalon_master_readdatavalid,
address => avalon_master_address,
burstcount => avalon_master_burstcount,
am_read => avalon_master_read,
refresh => refresh,
fifo_almost_empty => fifo_almost_empty,
fifo_data => fifo_data_in,
fifo_wr_req => fifo_wr_req,
baseaddress => baseaddr_reg,
nwords => av_nwords
);
-- ENTITY FIFO
fifo_ent : scfifo
generic map (
lpm_widthu => 9,
lpm_width => FIFO_WIDTH,
lpm_numwords => FIFO_SIZE,
almost_empty_value => FIFO_N_ALMOST_EMPTY
)
port map (
clock => clk,
data => fifo_data_in,
q => fifo_data_out,
wrreq => fifo_wr_req,
rdreq => fifo_rd_req,
empty => fifo_empty,
almost_empty => fifo_almost_empty,
sclr => not rst_n,
aclr => '0'
);
-- PROCESS Avalon slave interface
avalon_slave_address_int <= to_integer(unsigned(avalon_slave_address));
process(all) begin
state_next <= state_reg;
height_next <= height_reg;
width_next <= width_reg;
irq_ctrl_next <= irq_ctrl_reg;
refresh <= '0';
lcd_cmd_en <= '0';
lcd_cmd_dcx <= '0';
baseaddr_next <= baseaddr_reg;
lcd_on_next <= lcd_on_reg;
lcd_rst_next <= lcd_rst_reg;
avalon_slave_readdata <= (others => 'Z');
-- Avalon slave interface
if avalon_slave_write = '1' then
case avalon_slave_address_int is
when A_WRITEREG =>
lcd_cmd_en <= '1';
lcd_cmd_dcx <= '0';
when A_WRITEDATA =>
lcd_cmd_en <= '1';
lcd_cmd_dcx <= '1';
when A_WRITEBASE =>
baseaddr_next <= avalon_slave_writedata;
when A_REFRESH =>
if state_reg = S_READY then
refresh <= '1';
state_next <= S_REFRESHING;
if irq_ctrl_reg.clear_on_refresh then
irq_ctrl_next.irq0_active <= '0';
end if;
end if;
when A_SETENABLED =>
lcd_on_next <= avalon_slave_writedata(0);
lcd_rst_next <= avalon_slave_writedata(1);
when A_SETHEIGHT =>
height_next <= to_integer(unsigned(avalon_slave_writedata));
when A_SETWIDTH =>
width_next <= to_integer(unsigned(avalon_slave_writedata));
when A_WRITEIRQ =>
irq_ctrl_next <= writeIRQCtrl(avalon_slave_writedata(2 downto 0));
when A_SETIRQ =>
irq_ctrl_next <= setIRQCtrl(irq_ctrl_reg, avalon_slave_writedata(2 downto 0));
when A_CLEARIRQ =>
irq_ctrl_next <= clearIRQCtrl(irq_ctrl_reg, avalon_slave_writedata(2 downto 0));
when others => null;
end case;
end if;
if avalon_slave_read = '1' then
case avalon_slave_address_int is
when A_ISBUSY =>
avalon_slave_readdata <= (avalon_slave_readdata'left downto 1 => '0') & lcd_busy;
when others =>
null;
end case;
end if;
-- LCD Controller state handling
if (state_reg = S_REFRESHING) and lcd_busy = '0' then
state_next <= S_READY;
if irq_ctrl_reg.enabled then
irq_ctrl_next.irq0_active <= '1'; -- register that we are now finished
end if;
end if;
end process;
av_irq <= irq_ctrl_reg.irq0_active;
-- LCDController top level signals and functional units
lcd_cmd_data <= avalon_slave_writedata(7 downto 0);
av_nwords <= std_logic_vector(to_unsigned((height_reg * width_reg) / 2, av_nwords'length));
-- Output logic
lt24_reset_n <= not lcd_rst_reg;
lt24_lcd_on <= lcd_on_reg;
avalon_slave_waitrequest <= '1' when (lcd_busy='1' or state_reg /= S_READY) else '0';
-- Clocking process/register inferrence
process(clk) begin
if rising_edge(clk) then
if rst_n = '0' then
baseaddr_reg <= (others => '0');
state_reg <= S_READY;
height_reg <= MAX_H;
width_reg <= MAX_W;
irq_ctrl_reg <= IRQ_CTRL_DEFAULT;
lcd_on_reg <= '1';
else
state_reg <= state_next;
baseaddr_reg <= baseaddr_next;
height_reg <= height_next;
width_reg <= width_next;
irq_ctrl_reg <= irq_ctrl_next;
lcd_on_reg <= lcd_on_next;
lcd_rst_reg <= lcd_rst_next;
end if;
end if;
end process;
end comp;

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# TCL File Generated by Component Editor 18.1
# Wed Jan 06 17:21:08 CET 2021
# DO NOT MODIFY
#
# LCDController "LCDController" v1.0
# 2021.01.06.17:21:08
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module LCDController
#
set_module_property DESCRIPTION ""
set_module_property NAME LCDController
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME LCDController
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL LCDController
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file LCDController.vhd VHDL PATH LCDController.vhd TOP_LEVEL_FILE
add_fileset_file ClkGen.vhd VHDL PATH ClkGen.vhd
add_fileset_file LCDAvalonMaster.vhd VHDL PATH LCDAvalonMaster.vhd
add_fileset_file LCDDriver.vhd VHDL PATH LCDDriver.vhd
add_fileset_file PixTrans.vhd VHDL PATH PixTrans.vhd
#
# parameters
#
#
# display items
#
#
# connection point avalon_slave
#
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock_sink
set_interface_property avalon_slave associatedReset reset_sink
set_interface_property avalon_slave bitsPerSymbol 8
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave burstcountUnits WORDS
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave maximumPendingWriteTransactions 0
set_interface_property avalon_slave readLatency 0
set_interface_property avalon_slave readWaitStates 0
set_interface_property avalon_slave readWaitTime 0
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
set_interface_property avalon_slave ENABLED true
set_interface_property avalon_slave EXPORT_OF ""
set_interface_property avalon_slave PORT_NAME_MAP ""
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
add_interface_port avalon_slave avalon_slave_address address Input 4
add_interface_port avalon_slave avalon_slave_write write Input 1
add_interface_port avalon_slave avalon_slave_writedata writedata Input 32
add_interface_port avalon_slave avalon_slave_read read Input 1
add_interface_port avalon_slave avalon_slave_readdata readdata Output 32
add_interface_port avalon_slave avalon_slave_waitrequest waitrequest Output 1
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
#
# connection point clock_sink
#
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""
add_interface_port clock_sink clk clk Input 1
#
# connection point reset_sink
#
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock_sink
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
add_interface_port reset_sink rst_n reset_n Input 1
#
# connection point avalon_master
#
add_interface avalon_master avalon start
set_interface_property avalon_master addressUnits SYMBOLS
set_interface_property avalon_master associatedClock clock_sink
set_interface_property avalon_master associatedReset reset_sink
set_interface_property avalon_master bitsPerSymbol 8
set_interface_property avalon_master burstOnBurstBoundariesOnly false
set_interface_property avalon_master burstcountUnits WORDS
set_interface_property avalon_master doStreamReads false
set_interface_property avalon_master doStreamWrites false
set_interface_property avalon_master holdTime 0
set_interface_property avalon_master linewrapBursts false
set_interface_property avalon_master maximumPendingReadTransactions 0
set_interface_property avalon_master maximumPendingWriteTransactions 0
set_interface_property avalon_master readLatency 0
set_interface_property avalon_master readWaitTime 1
set_interface_property avalon_master setupTime 0
set_interface_property avalon_master timingUnits Cycles
set_interface_property avalon_master writeWaitTime 0
set_interface_property avalon_master ENABLED true
set_interface_property avalon_master EXPORT_OF ""
set_interface_property avalon_master PORT_NAME_MAP ""
set_interface_property avalon_master CMSIS_SVD_VARIABLES ""
set_interface_property avalon_master SVD_ADDRESS_GROUP ""
add_interface_port avalon_master avalon_master_address address Output 32
add_interface_port avalon_master avalon_master_burstcount burstcount Output 5
add_interface_port avalon_master avalon_master_read read Output 1
add_interface_port avalon_master avalon_master_readdata readdata Input 32
add_interface_port avalon_master avalon_master_readdatavalid readdatavalid Input 1
add_interface_port avalon_master avalon_master_waitreq waitrequest Input 1
#
# connection point irq
#
add_interface irq interrupt end
set_interface_property irq associatedAddressablePoint avalon_slave
set_interface_property irq associatedClock clock_sink
set_interface_property irq associatedReset reset_sink
set_interface_property irq bridgedReceiverOffset ""
set_interface_property irq bridgesToReceiver ""
set_interface_property irq ENABLED true
set_interface_property irq EXPORT_OF ""
set_interface_property irq PORT_NAME_MAP ""
set_interface_property irq CMSIS_SVD_VARIABLES ""
set_interface_property irq SVD_ADDRESS_GROUP ""
add_interface_port irq av_irq irq Output 1
#
# connection point LT24
#
add_interface LT24 conduit end
set_interface_property LT24 associatedClock clock_sink
set_interface_property LT24 associatedReset reset_sink
set_interface_property LT24 ENABLED true
set_interface_property LT24 EXPORT_OF ""
set_interface_property LT24 PORT_NAME_MAP ""
set_interface_property LT24 CMSIS_SVD_VARIABLES ""
set_interface_property LT24 SVD_ADDRESS_GROUP ""
add_interface_port LT24 lt24_cs_n cs_n Output 1
add_interface_port LT24 lt24_data data Output 16
add_interface_port LT24 lt24_lcd_on lcd_on Output 1
add_interface_port LT24 lt24_rd_n rd_n Output 1
add_interface_port LT24 lt24_reset_n reset_n Output 1
add_interface_port LT24 lt24_rs rs Output 1
add_interface_port LT24 lt24_wr_n wr_n Output 1

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.env.finish;
entity LCDController_tb is
end LCDController_tb;
architecture test of LCDController_tb is
constant CLK_PERIOD : time := 20 ns;
signal clk : std_logic := '0';
signal rst_n : std_logic;
signal waitreq, readdatavalid, fifo_almost_empty : std_logic;
-- Avalon slave interface
signal avalon_slave_address : std_logic_vector (3 downto 0);
signal avalon_slave_write : std_logic;
signal avalon_slave_writedata : std_logic_vector(31 downto 0);
signal avalon_slave_read : std_logic;
signal avalon_slave_readdata : std_logic_vector(31 downto 0);
-- Avalon master interface
signal avalon_master_waitreq : std_logic;
signal avalon_master_readdata : std_logic_vector(31 downto 0);
signal avalon_master_readdatavalid : std_logic;
signal avalon_master_read : std_logic;
signal irq : std_logic;
begin
-- Instantiate DUT
dut : entity work.LCDController
port map(
clk => clk,
rst_n => rst_n,
av_irq => irq,
avalon_slave_address => avalon_slave_address,
avalon_slave_write => avalon_slave_write,
avalon_slave_writedata => avalon_slave_writedata,
avalon_slave_read => avalon_slave_read,
avalon_slave_readdata => avalon_slave_readdata,
avalon_master_waitreq => avalon_master_waitreq,
avalon_master_readdata => avalon_master_readdata,
avalon_master_readdatavalid => avalon_master_readdatavalid,
avalon_master_read => avalon_master_read
);
-- Clocking process
clk_generation : process
begin
clk <= not clk;
wait for CLK_PERIOD / 2;
end process;
-- Testbench
tb : process
begin
avalon_slave_address <= "0011";
avalon_slave_write <= '0';
avalon_slave_writedata <= (others => 'Z');
-- Dummy signals from bus
avalon_master_readdata <= X"12341234";
avalon_master_readdatavalid <= '0';
avalon_master_waitreq <= '1';
-- Reset
rst_n <= '0';
wait for CLK_PERIOD * 2.5;
rst_n <= '1';
wait for CLK_PERIOD * 2;
-- Initiate CMD cycle
avalon_slave_address <= "0000";
wait until rising_edge(clk);
avalon_slave_writedata <= (27 downto 0 => '0') & "1000";
avalon_slave_write <= '1';
wait until rising_edge(clk);
avalon_slave_write <= '0';
wait for CLK_PERIOD * 20;
avalon_slave_address <= "0001";
wait until rising_edge(clk);
avalon_slave_writedata <= (27 downto 0 => '0') & "1111";
avalon_slave_write <= '1';
wait until rising_edge(clk);
avalon_slave_write <= '0';
wait for CLK_PERIOD * 20;
-- Loop refreshing
loop
wait for CLK_PERIOD * 50;
-- Initiate a refresh cycle
avalon_slave_address <= "0011";
wait until rising_edge(clk);
avalon_slave_write <= '1';
wait until rising_edge(clk);
avalon_slave_write <= '0';
-- Wait until bus grant
wait for CLK_PERIOD * 3;
avalon_master_waitreq <= '0';
wait for CLK_PERIOD;
-- Emulate that new read data is valid each cycle of the burst
avalon_master_readdatavalid <= '1';
for i in 0 to 15 loop
avalon_master_readdata <= std_logic_vector(to_unsigned(i*2 + ((i*2+1)*2**16), avalon_master_readdata'length));
wait for CLK_PERIOD;
end loop;
-- burst finished
avalon_master_readdatavalid <= '0';
loop
-- Wait until the previous 16 words have been shifted to LCD and new pixels
-- are requested
wait until avalon_master_read = '1' or irq = '1';
exit when irq = '1';
-- Wait some time for bus grant...
wait for CLK_PERIOD * 3;
-- Start providing some data
avalon_master_readdatavalid <= '1';
for i in 0 to 15 loop
avalon_master_readdata <= std_logic_vector(to_unsigned(i*2 + ((i*2+1)*2**16), avalon_master_readdata'length));
wait for CLK_PERIOD;
end loop;
avalon_master_readdatavalid <= '0';
end loop;
end loop;
end process;
end;

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-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity LCDDriver is
generic (
F_CLK : natural -- Board frequency in Hz
);
port (
clk : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector(15 downto 0);
empty_in : in std_logic;
refresh_in : in std_logic;
cmd_en_in : in std_logic;
cmd_dcx_in : in std_logic;
cmd_data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(15 downto 0);
rd_n : out std_logic;
wr_n : out std_logic;
rs : out std_logic;
cs_n : out std_logic;
lcd_rdreq : out std_logic;
busy : out std_logic
);
end LCDDriver;
architecture Behavioral of LCDDriver is
constant F_LCD : natural := natural(real(25)*10**(6.0));
constant F_LCD_MIN : natural := natural(real(12.5)*10**(6.0));
constant F_LCD_MAX : natural := natural(real(30)*10**(6.0));
constant lcd_clk_en : std_logic := '1' ;
signal lcd_clk : std_logic;
type GState is (tx, cmd, ready, std_wait,cmd_wait);
type SNDState is (init, wrx, tx, done);
signal snds_reg, snds_next : SNDState;
signal gs_reg, gs_next : GState;
signal data_reg : std_logic_vector(15 downto 0);
signal cmd_dcx_reg : std_logic := '1';
signal cmd_data_reg : std_logic_vector(7 downto 0);
signal rdreq_limiter : std_logic;
begin
busy <= '0' when gs_reg = ready else '1';
--Global State Process
process (all) begin
gs_next <= gs_reg;
snds_next <= snds_reg;
case gs_reg is
when ready =>
if cmd_en_in = '1' then
if lcd_clk = '1' then
gs_next <= cmd;
snds_next <= wrx;
else
gs_next <= cmd_wait;
end if;
elsif refresh_in = '1' then
gs_next <= std_wait;
end if;
when cmd_wait =>
if lcd_clk = '1' then
gs_next <= cmd;
snds_next <= wrx;
end if;
when std_wait =>
if empty_in = '0' then
if lcd_clk = '1' then
gs_next <= tx;
snds_next <= init;
end if;
end if;
when tx =>
if snds_reg = done then
gs_next <= ready;
end if;
when cmd =>
if snds_reg = done then
gs_next <= ready;
end if;
end case;
if (gs_reg = cmd or gs_reg = tx) then
case snds_reg is
when wrx =>
snds_next <= tx;
when tx =>
if gs_reg = cmd then
snds_next <= done;
elsif gs_reg = tx then
if empty_in = '1' then
snds_next <= done;
else
snds_next <= wrx;
end if;
end if;
when init =>
snds_next <= wrx;
when others =>
null;
end case;
end if;
end process;
rs <= cmd_dcx_reg when gs_reg = cmd else '1'; -- DCX when CMD else Keep high
cs_n <= not rst_n; -- Chip Select
wr_n <= '0' when (gs_reg = cmd or gs_reg = tx) and
snds_reg = wrx else '1'; -- Write data on rising edge
rd_n <= '1'; -- Unused, Read data on rising edge
data_out <= data_reg when gs_reg = tx else
"00000000" & cmd_data_reg when gs_reg = cmd else
(others => '0');
lcd_rdreq <= '1' when (gs_reg = ready and gs_next = std_wait) or
(snds_reg /= init and snds_next = init) or
(rdreq_limiter = '0' and gs_reg = tx and snds_reg = tx) else '0';
-- Clock Sync & State Handler
process (clk, rst_n) begin
if rst_n = '0' then
gs_reg <= ready;
snds_reg <= wrx;
data_reg <= (others => '0');
cmd_dcx_reg <= '0';
cmd_data_reg <= (others => '0');
elsif rising_edge(clk) then
gs_reg <= gs_next;
if lcd_clk = '1' then
snds_reg <= snds_next; -- We run the SND at 25Mhz to respect state timings
if (snds_reg = tx or snds_reg = init) then
data_reg <= data_in;
end if;
if (snds_reg = wrx) then
rdreq_limiter <= '0';
end if;
end if;
if lcd_rdreq = '1' then
rdreq_limiter <= '1';
end if;
if gs_reg = ready and (cmd_en_in = '1') then
cmd_dcx_reg <= cmd_dcx_in;
cmd_data_reg <= cmd_data_in;
end if;
end if;
end process;
-- WS output clock
clkgen_ent : entity work.ClkGen
generic map (
F_CLK => F_CLK,
F_OUT => integer(F_LCD),
F_MIN => integer(F_LCD_MIN),
F_MAX => integer(F_LCD_MAX)
)
port map (
clk => clk,
rst_n => rst_n,
clk_o => lcd_clk,
en => lcd_clk_en
);
end Behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity LCDDriver_tb is
end LCDDriver_tb;
architecture test of LCDDriver_tb is
constant CLK_PERIOD : time := 20 ns;
constant N_LED_MAX : integer := 255;
signal clk : std_logic := '0';
signal rst_n : std_logic := '1';
signal data_in : std_logic_vector(15 downto 0) := (others=> '0');
signal empty_in : std_logic := '1';
signal refresh_in : std_logic := '0';
signal cmd_en_in : std_logic := '0';
signal cmd_dcx_in : std_logic := '0';
signal cmd_data_in : std_logic_vector(7 downto 0) := (others => '0');
signal m_finished_in : std_logic := '0';
signal data_out : std_logic_vector(15 downto 0);
signal rd_n : std_logic;
signal wr_n : std_logic;
signal rs : std_logic;
signal cs_n : std_logic;
signal lcd_rdreq : std_logic;
signal rdreq_cnt : integer := 0;
signal busy : std_logic;
begin
-- Instantiate DUT
dut : entity work.LCDDriver
generic map (
F_CLK => 50000000
)
port map(
clk => clk,
rst_n => rst_n,
data_in => data_in,
empty_in => empty_in,
refresh_in => refresh_in,
cmd_en_in => cmd_en_in,
cmd_dcx_in => cmd_dcx_in,
cmd_data_in => cmd_data_in,
m_finished_in => m_finished_in,
data_out => data_out,
rd_n => rd_n,
wr_n => wr_n,
rs => rs,
cs_n => cs_n,
lcd_rdreq => lcd_rdreq,
busy => busy
);
-- Clocking process
clk_generation : process
begin
clk <= not clk;
wait for CLK_PERIOD / 2;
end process;
process (lcd_rdreq) begin
if rising_edge(lcd_rdreq) then
if (rdreq_cnt = 0) then
data_in <= "1111111111111111";
elsif (rdreq_cnt = 1) then
data_in <= "1111000000001111";
elsif (rdreq_cnt = 2) then
data_in <= "1111111100000000";
elsif (rdreq_cnt = 3) then
data_in <= "0000000011111111";
else
data_in <= "0000000000000000";
end if;
rdreq_cnt <= rdreq_cnt + 1;
end if;
end process;
tb : process
procedure wait_ready is
begin
if busy = '1' then
wait until busy = '0';
end if;
end procedure wait_ready;
procedure finish is
begin
wait until falling_edge(clk);
wait_ready;
wait;
end procedure finish ;
begin
-- Reset
rst_n <= '0';
wait for CLK_PERIOD * 2.5;
rst_n <= '1';
wait for CLK_PERIOD * 2;
wait_ready;
-- Test CMD
cmd_en_in <= '1';
cmd_dcx_in <= '1';
cmd_data_in <= "11010011";
wait for CLK_PERIOD * 2.5;
cmd_en_in <= '0';
wait_ready;
-- Test REFRESH
refresh_in <= '1';
wait for CLK_PERIOD * 2.5;
refresh_in <= '0';
wait for CLK_PERIOD * 4;
empty_in <= '0';
wait until rdreq_cnt = 4;
empty_in <= '1';
--m_finished_in => m_finished_in,
wait_ready;
-- Test finished
finish;
end process;
end;

157
cs473-es/lab3/hw/hdl/LCDController/PixTrans.vhd Normal file
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-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PixTrans is
generic (
MAX_H : natural;
MAX_W : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
lcd_req : in std_logic;
data : out std_logic_vector(15 downto 0);
empty : out std_logic;
fifo_req : out std_logic;
fifo_q : in std_logic_vector(31 downto 0);
fifo_empty : in std_logic;
-- Currently configured width/height of the buffer
w : in natural;
h : in natural
);
end PixTrans;
architecture behavioral of PixTrans is
subtype Pixel is std_logic_vector(15 downto 0);
-- Generic constants
constant BLANK : Pixel := "0000000000000000"; --(others => '0');
-- Type definitions
type PIXEL_SOURCE is (S_BLANK, S_FIFO, S_BUFFER);
-- Inferred registers
signal pixbuf_reg, pixbuf_next : Pixel;
signal pixbufvalid_reg, pixbufvalid_next : boolean;
signal pos_x_reg, pos_x_next : integer range 1 to MAX_W;
signal pos_y_reg, pos_y_next : integer range 1 to MAX_H;
signal pix_src_reg, pix_src_next : PIXEL_SOURCE;
signal finished_next, finished_reg : std_logic;
-- Convenience signals
signal inBlankArea_reg, inBlankArea_next : boolean;
signal lcd_req_delayed_reg : std_logic;
begin
-- Update cursor
process(all) begin
finished_next <= finished_reg;
pos_y_next <= pos_y_reg;
pos_x_next <= pos_x_reg;
if lcd_req_delayed_reg = '1' then
if pos_x_reg = MAX_W and pos_y_reg = MAX_H then
pos_x_next <= 1;
pos_y_next <= 1;
elsif pos_x_reg = MAX_W then
pos_x_next <= 1;
pos_y_next <= pos_y_reg + 1;
else
pos_x_next <= pos_x_reg + 1;
end if;
if pos_x_reg = MAX_W and pos_y_reg = MAX_H then
finished_next <= '1' and not finished_reg;
else
finished_next <= '0';
end if;
end if;
inBlankArea_next <= pos_y_next > h or pos_x_next > w;
end process;
-- Data process
process(all) begin
pix_src_next <= pix_src_reg;
pixbufvalid_next <= pixbufvalid_reg;
-- FIFO output signals
fifo_req <= '0';
if lcd_req_delayed_reg = '1' then
if inBlankArea_next then
pix_src_next <= S_BLANK;
elsif pixbufvalid_reg then
-- Has valid pixel in pixel buffer
pix_src_next <= S_BUFFER;
pixbufvalid_next <= false;
else
fifo_req <= '1';
-- fifo_req should be kept high until pixel is available
if fifo_empty = '0' then
-- Must request pixel from FIFO
pix_src_next <= S_FIFO;
pixbufvalid_next <= true;
end if;
end if;
end if;
end process;
-- Data request multiplexer (pixel source)
with pix_src_reg select data <=
BLANK when S_BLANK,
fifo_q(15 downto 0) when S_FIFO,
pixbuf_reg when S_BUFFER;
-- Fill pixel buffer with the upper half word of the input FIFO word when
-- reading from the fifo
pixbuf_next <= fifo_q(31 downto 16) when pix_src_reg = S_FIFO else pixbuf_reg;
-- LCD Controller empty signal
process(all) begin
if fifo_empty = '1' then
empty <= '1';
else
empty <= finished_reg;
end if;
end process;
-- Clocking process/register inferrence
process(clk) begin
if rising_edge(clk) then
if rst_n = '0' then
pos_x_reg <= 1;
pos_y_reg <= 1;
pixbuf_reg <= BLANK;
pixbufvalid_reg <= false;
pix_src_reg <= S_BLANK;
inBlankArea_reg <= false;
finished_reg <= '0';
lcd_req_delayed_reg <= '0';
else
pos_x_reg <= pos_x_next;
pos_y_reg <= pos_y_next;
pixbuf_reg <= pixbuf_next;
pixbufvalid_reg <= pixbufvalid_next;
pix_src_reg <= pix_src_next;
inBlankArea_reg <= inBlankArea_next;
finished_reg <= finished_next;
lcd_req_delayed_reg <= lcd_req;
end if;
end if;
end process;
end behavioral ; -- behavioral

90
cs473-es/lab3/hw/hdl/LCDController/PixTrans_tb.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity PixTrans_tb is
end PixTrans_tb;
architecture test of PixTrans_tb is
constant CLK_PERIOD : time := 20 ns;
constant N_LED_MAX : integer := 255;
constant MAX_H : natural := 4;
constant MAX_W : natural := 4;
constant ACTUAL_H : natural := 2;
constant ACTUAL_W : natural := 2;
signal clk : std_logic := '0';
signal rst_n : std_logic;
signal fifo_empty, lcd_req : std_logic;
signal fifo_q : std_logic_vector(31 downto 0);
signal w, h : natural;
begin
w <= ACTUAL_W;
h <= ACTUAL_H;
-- Instantiate DUT
dut : entity work.PixTrans
generic map (
MAX_H => MAX_H,
MAX_W => MAX_W
)
port map(
clk => clk,
rst_n => rst_n,
lcd_req => lcd_req,
fifo_q => fifo_q,
fifo_empty => fifo_empty,
w => w,
h => h
);
-- Clocking process
clk_generation : process
begin
clk <= not clk;
wait for CLK_PERIOD / 2;
end process;
-- Testbench
tb : process
procedure getPixel is
begin
wait until rising_edge(clk);
lcd_req <= '1';
wait for CLK_PERIOD;
wait until rising_edge(clk);
lcd_req <= '0';
wait for CLK_PERIOD*3;
end procedure getPixel;
begin
-- Just let the FIFO interface always provide data
fifo_q <= X"FFFF" & X"F0F0";
fifo_empty <= '0';
lcd_req <= '0';
-- Reset
rst_n <= '0';
wait for CLK_PERIOD * 2.5;
rst_n <= '1';
wait for CLK_PERIOD * 2;
-- Get some pixels
for i in 1 to MAX_H*MAX_W loop
report "hello";
getPixel;
end loop;
-- Test finished
wait;
end process;
end;

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cs473-es/lab3/hw/modelsim/LCDController.mpf Normal file
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; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
; Altera Primitive libraries
;
; VHDL Section
;
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
maxii = $MODEL_TECH/../altera/vhdl/maxii
maxv = $MODEL_TECH/../altera/vhdl/maxv
fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
sgate = $MODEL_TECH/../altera/vhdl/sgate
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
arriav = $MODEL_TECH/../altera/vhdl/arriav
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
twentynm = $MODEL_TECH/../altera/vhdl/twentynm
twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
;
; Verilog Section
;
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Default or value of 3 or 2008 for VHDL-2008.
VHDL93 = 2002
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
; Turns on lint-style checking.
; Show_Lint = 1
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
; Default run length
RunLength = 100 us
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
; VSIM Startup command
; Startup = do startup.do
; File for saving command transcript
TranscriptFile = transcript
; File for saving command history
; CommandHistory = cmdhist.log
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
[lmc]
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 9
Project_File_0 = /home/morten/Work/cs-473/lab3/hw/hdl/LCDController/LCDController.vhd
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1609269952 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_1 = /home/morten/Work/cs-473/lab3/hw/hdl/LCDController/LCDDriver.vhd
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1609269788 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_2 = /home/morten/Work/cs-473/lab3/hw/hdl/LCDController/ClkGen.vhd
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607688416 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_3 = /home/morten/Work/cs-473/lab3/hw/hdl/LCDController/LCDAvalonMaster.vhd
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607684735 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_4 = /home/morten/Work/cs-473/lab3/hw/hdl/LCDController/LCDController_tb.vhd
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1609270120 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_5 = /home/morten/Work/cs-473/lab3/hw/hdl/LCDController/LCDDriver_tb.vhd
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1608717413 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_6 = /home/morten/Work/cs-473/lab3/hw/hdl/LCDController/PixTrans.vhd
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607684735 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_7 = /home/morten/Work/cs-473/lab3/hw/hdl/LCDController/LCDAvalonMaster_tb.vhd
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607085260 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_8 = /home/morten/Work/cs-473/lab3/hw/hdl/LCDController/PixTrans_tb.vhd
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607076300 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
TDB_DoubleClick = Edit
TDB_CustomDoubleClick =
UPF_DoubleClick = Edit
UPF_CustomDoubleClick =
PCF_DoubleClick = Edit
PCF_CustomDoubleClick =
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick =
VRM_DoubleClick = Edit
VRM_CustomDoubleClick =
DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 10
Project_Minor_Version = 5

54
cs473-es/lab3/hw/quartus/.gitignore vendored Normal file
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system/**/*
# A gitignore for Altera Quartus II that tries to ignore almost all of the
# automatically Quartus-generated files. This primarily leaves the project,
# settings, source, and constraint files to be added. The files ignored do not
# include the bulk of the MegaFunction Wizard generated files which enables
# a cloned repository to be used (usually) immediately without regenerating
# Altera IP blocks.
# Need to keep all HDL files and timing constraint files
# *.vhd
# *.v
# *.sdc
# ignore Quartus II generated folders
*_sim
db
greybox_tmp
incremental_db
simulation
testbench
timing
synthesis
.qsys_edit
# ignore Quartus II generated files
*_generation_script*
*_inst.vhd
*.bak
*.cmp
*.done
*.eqn
*.hex
*.html
*.jdi
*.jpg
*.mif
*.pin
*.pof
*.ptf.*
*.qar
*.qarlog
*.qws
*.rpt
*.smsg
*.sof
*.sopc_builder
*.summary
*.tcl
*.txt # Explicitly add any text files used
*~
*example*
*sopc_*
PLLJ_PLLSPE_INFO.txt # The generated PLL specification file

94
cs473-es/lab3/hw/quartus/c5_pin_model_dump.txt Normal file
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io_4iomodule_c5_index: 42gpio_index: 2
io_4iomodule_c5_index: 41gpio_index: 369
io_4iomodule_c5_index: 27gpio_index: 6
io_4iomodule_c5_index: 1gpio_index: 365
io_4iomodule_c5_index: 22gpio_index: 10
io_4iomodule_c5_index: 6gpio_index: 361
io_4iomodule_c5_index: 28gpio_index: 14
io_4iomodule_c5_index: 24gpio_index: 357
io_4iomodule_c5_index: 21gpio_index: 19
io_4iomodule_c5_index: 25gpio_index: 353
io_4iomodule_c5_index: 23gpio_index: 22
io_4iomodule_c5_index: 15gpio_index: 349
io_4iomodule_c5_index: 13gpio_index: 27
io_4iomodule_c5_index: 34gpio_index: 345
io_4iomodule_c5_index: 39gpio_index: 30
io_4iomodule_c5_index: 19gpio_index: 341
io_4iomodule_c5_index: 5gpio_index: 35
io_4iomodule_c5_index: 10gpio_index: 337
io_4iomodule_c5_index: 9gpio_index: 38
io_4iomodule_c5_index: 36gpio_index: 333
io_4iomodule_c5_index: 17gpio_index: 43
io_4iomodule_c5_index: 40gpio_index: 329
io_4iomodule_c5_index: 16gpio_index: 46
io_4iomodule_c5_index: 43gpio_index: 325
io_4iomodule_a_index: 13gpio_index: 321
io_4iomodule_c5_index: 2gpio_index: 51
io_4iomodule_a_index: 15gpio_index: 317
io_4iomodule_a_index: 8gpio_index: 313
io_4iomodule_c5_index: 32gpio_index: 54
io_4iomodule_a_index: 5gpio_index: 309
io_4iomodule_c5_index: 8gpio_index: 59
io_4iomodule_a_index: 11gpio_index: 305
io_4iomodule_c5_index: 4gpio_index: 62
io_4iomodule_a_index: 3gpio_index: 301
io_4iomodule_c5_index: 30gpio_index: 67
io_4iomodule_a_index: 7gpio_index: 297
io_4iomodule_c5_index: 0gpio_index: 70
io_4iomodule_a_index: 0gpio_index: 293
io_4iomodule_c5_index: 31gpio_index: 75
io_4iomodule_a_index: 12gpio_index: 289
io_4iomodule_c5_index: 26gpio_index: 78
io_4iomodule_a_index: 4gpio_index: 285
io_4iomodule_a_index: 10gpio_index: 281
io_4iomodule_c5_index: 3gpio_index: 83
io_4iomodule_a_index: 16gpio_index: 277
io_4iomodule_c5_index: 18gpio_index: 86
io_4iomodule_c5_index: 37gpio_index: 91
io_4iomodule_a_index: 14gpio_index: 273
io_4iomodule_a_index: 1gpio_index: 269
io_4iomodule_c5_index: 33gpio_index: 94
io_4iomodule_c5_index: 20gpio_index: 99
io_4iomodule_a_index: 2gpio_index: 265
io_4iomodule_c5_index: 7gpio_index: 102
io_4iomodule_a_index: 9gpio_index: 261
io_4iomodule_a_index: 6gpio_index: 257
io_4iomodule_c5_index: 11gpio_index: 107
io_4iomodule_a_index: 17gpio_index: 253
io_4iomodule_c5_index: 38gpio_index: 110
io_4iomodule_c5_index: 14gpio_index: 115
io_4iomodule_c5_index: 29gpio_index: 118
io_4iomodule_c5_index: 12gpio_index: 123
io_4iomodule_c5_index: 35gpio_index: 126
io_4iomodule_h_c5_index: 0gpio_index: 129
io_4iomodule_h_c5_index: 1gpio_index: 133
io_4iomodule_h_c5_index: 3gpio_index: 137
io_4iomodule_h_c5_index: 2gpio_index: 141
io_4iomodule_h_index: 20gpio_index: 144
io_4iomodule_h_index: 24gpio_index: 148
io_4iomodule_h_index: 12gpio_index: 152
io_4iomodule_h_index: 10gpio_index: 156
io_4iomodule_h_index: 0gpio_index: 160
io_4iomodule_vref_h_index: 0gpio_index: 164
io_4iomodule_h_index: 22gpio_index: 167
io_4iomodule_h_index: 6gpio_index: 171
io_4iomodule_h_index: 16gpio_index: 175
io_4iomodule_h_index: 2gpio_index: 179
io_4iomodule_h_index: 5gpio_index: 183
io_4iomodule_h_index: 3gpio_index: 187
io_4iomodule_h_index: 14gpio_index: 191
io_4iomodule_h_index: 7gpio_index: 195
io_4iomodule_h_index: 18gpio_index: 199
io_4iomodule_h_index: 11gpio_index: 203
io_4iomodule_h_index: 9gpio_index: 207
io_4iomodule_h_index: 13gpio_index: 211
io_4iomodule_h_index: 23gpio_index: 215
io_4iomodule_vref_h_index: 1gpio_index: 219
io_4iomodule_h_index: 21gpio_index: 222
io_4iomodule_h_index: 8gpio_index: 226
io_4iomodule_h_index: 25gpio_index: 230
io_4iomodule_h_index: 1gpio_index: 234
io_4iomodule_h_index: 15gpio_index: 238
io_4iomodule_h_index: 19gpio_index: 242
io_4iomodule_h_index: 17gpio_index: 246
io_4iomodule_h_index: 4gpio_index: 250

147
cs473-es/lab3/hw/quartus/devkits/de0_nano_soc_baseline/de0_nano_soc_baseline.v Normal file
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//--------------------------------------------------------------------------//
// Title: de0_nano_soc_baseline.v //
// Rev: Rev 0.1 //
// Last Revised: 09/14/2015 //
//--------------------------------------------------------------------------//
// Description: Baseline design file contains DE0 Nano SoC //
// Board pins and I/O Standards. //
//--------------------------------------------------------------------------//
//Copyright 2015 Altera Corporation. All rights reserved. Altera products
//are protected under numerous U.S. and foreign patents, maskwork rights,
//copyrights and other intellectual property laws.
//
//This reference design file, and your use thereof, is subject to and
//governed by the terms and conditions of the applicable Altera Reference
//Design License Agreement. By using this reference design file, you
//indicate your acceptance of such terms and conditions between you and
//Altera Corporation. In the event that you do not agree with such terms and
//conditions, you may not use the reference design file. Please promptly
//destroy any copies you have made.
//
//This reference design file being provided on an "as-is" basis and as an
//accommodation and therefore all warranties, representations or guarantees
//of any kind (whether express, implied or statutory) including, without
//limitation, warranties of merchantability, non-infringement, or fitness for
//a particular purpose, are specifically disclaimed. By making this
//reference design file available, Altera expressly does not recommend,
//suggest or require that this reference design file be used in combination
//with any other product not provided by Altera
//----------------------------------------------------------------------------
//Group Enable Definitions
//This lists every pinout group
//Users can enable any group by uncommenting the corresponding line below:
//`define enable_ADC
//`define enable_ARDUINO
//`define enable_GPIO0
//`define enable_GPIO1
//`define enable_HPS
module de0_nano_soc_baseline(
//////////// CLOCK //////////
input FPGA_CLK_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
`ifdef enable_ADC
//////////// ADC //////////
/* 3.3-V LVTTL */
output ADC_CONVST,
output ADC_SCLK,
output ADC_SDI,
input ADC_SDO,
`endif
`ifdef enable_ARDUINO
//////////// ARDUINO ////////////
/* 3.3-V LVTTL */
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
`endif
`ifdef enable_GPIO0
//////////// GPIO 0 ////////////
/* 3.3-V LVTTL */
inout [35:0] GPIO_0,
`endif
`ifdef enable_GPIO1
//////////// GPIO 1 ////////////
/* 3.3-V LVTTL */
inout [35:0] GPIO_1,
`endif
`ifdef enable_HPS
//////////// HPS //////////
/* 3.3-V LVTTL */
inout HPS_CONV_USB_N,
/* SSTL-15 Class I */
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
/* DIFFERENTIAL 1.5-V SSTL CLASS I */
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
/* 3.3-V LVTTL */
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout HPS_GSENSOR_INT,
inout HPS_I2C0_SCLK,
inout HPS_I2C0_SDAT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
//////////// KEY ////////////
/* 3.3-V LVTTL */
input [1:0] KEY,
//////////// LED ////////////
/* 3.3-V LVTTL */
output [7:0] LED,
//////////// SW ////////////
/* 3.3-V LVTTL */
input [3:0] SW
);
endmodule

4
cs473-es/lab3/hw/quartus/devkits/de0_nano_soc_baseline/filelist.txt Normal file
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platform_setup.tcl
filelist.txt
de0_nano_soc_baseline.v
de0_nano_soc_baseline.v

6
cs473-es/lab3/hw/quartus/devkits/de0_nano_soc_baseline/qar_info.json Normal file
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{
"common_dir" : "/data/adu/17.0/Lite/CycloneV/Atlas_SoC_DE0_Nano/de0_nano_soc_baseline_project/",
"acds_version" : "Version 17.0.0",
"platform" : "linux",
"os" : "Red Hat"
}

8
cs473-es/lab3/hw/quartus/devkits/readme.txt Normal file
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This devkits directory contains development kit baseline example designs.
HOW TO SETUP PIN ASSIGNMENTS
1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows.
2) Type command 'source platform_setup.tcl' in the Tcl console.
3) Type command 'setup_project' in the Tcl console.
- Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file.

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cs473-es/lab3/hw/quartus/lab3.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 14:31:51 November 25, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "14:31:51 November 25, 2020"
# Revisions
PROJECT_REVISION = "lab3"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 14:31:51 November 25, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# lab3_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA4U23C6
set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_SoC_LT24_top_level
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:31:51 NOVEMBER 25, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "Atlas-SoC (DE0-Nano-SoC)"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_P -tag __hps_sdram_p0
set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_P -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_N -tag __hps_sdram_p0
set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_N -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[10] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[11] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[12] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[13] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[14] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[3] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[4] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[5] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[6] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[7] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[8] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[9] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CAS_N -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CKE -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CS_N -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ODT -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RAS_N -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_WE_N -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RESET_N -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[4] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[5] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[6] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[7] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[8] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[9] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[10] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[11] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[12] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[13] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[14] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[15] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[16] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[17] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[18] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[19] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[20] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[21] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[22] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[23] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[24] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[25] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[26] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[27] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[28] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[29] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[30] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[31] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[10] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[11] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[12] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[13] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[14] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[4] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[5] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[6] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[7] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[8] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[9] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CAS_N -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CKE -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CS_N -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ODT -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RAS_N -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_WE_N -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RESET_N -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_P -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_N -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -tag __hps_sdram_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -tag __hps_sdram_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to u0|hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to u0|hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name ECO_REGENERATE_REPORT ON
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_AG13 -to ARDUINO_IO[0]
set_location_assignment PIN_AG13 -to ARDUINO_IO_0
set_location_assignment PIN_AF13 -to ARDUINO_IO[1]
set_location_assignment PIN_AF13 -to ARDUINO_IO_1
set_location_assignment PIN_AG10 -to ARDUINO_IO[2]
set_location_assignment PIN_AG10 -to ARDUINO_IO_2
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_AG9 -to ARDUINO_IO_3
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U14 -to ARDUINO_IO_4
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_U13 -to ARDUINO_IO_5
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AG8 -to ARDUINO_IO_6
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AH8 -to ARDUINO_IO_7
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AF17 -to ARDUINO_IO_8
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_location_assignment PIN_AE15 -to ARDUINO_IO_9
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_location_assignment PIN_AF15 -to ARDUINO_IO_10
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_location_assignment PIN_AG16 -to ARDUINO_IO_11
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_location_assignment PIN_AH11 -to ARDUINO_IO_12
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_location_assignment PIN_AH12 -to ARDUINO_IO_13
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_location_assignment PIN_AH9 -to ARDUINO_IO_14
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
set_location_assignment PIN_AG11 -to ARDUINO_IO_15
set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_8
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_9
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_10
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_11
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_12
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_13
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_14
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO_15
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_C6 -to HPS_CONV_USB_N
set_location_assignment PIN_C28 -to HPS_DDR3_ADDR[0]
set_location_assignment PIN_C28 -to HPS_DDR3_ADDR_0
set_location_assignment PIN_B28 -to HPS_DDR3_ADDR[1]
set_location_assignment PIN_B28 -to HPS_DDR3_ADDR_1
set_location_assignment PIN_E26 -to HPS_DDR3_ADDR[2]
set_location_assignment PIN_E26 -to HPS_DDR3_ADDR_2
set_location_assignment PIN_D26 -to HPS_DDR3_ADDR[3]
set_location_assignment PIN_D26 -to HPS_DDR3_ADDR_3
set_location_assignment PIN_J21 -to HPS_DDR3_ADDR[4]
set_location_assignment PIN_J21 -to HPS_DDR3_ADDR_4
set_location_assignment PIN_J20 -to HPS_DDR3_ADDR[5]
set_location_assignment PIN_J20 -to HPS_DDR3_ADDR_5
set_location_assignment PIN_C26 -to HPS_DDR3_ADDR[6]
set_location_assignment PIN_C26 -to HPS_DDR3_ADDR_6
set_location_assignment PIN_B26 -to HPS_DDR3_ADDR[7]
set_location_assignment PIN_B26 -to HPS_DDR3_ADDR_7
set_location_assignment PIN_F26 -to HPS_DDR3_ADDR[8]
set_location_assignment PIN_F26 -to HPS_DDR3_ADDR_8
set_location_assignment PIN_F25 -to HPS_DDR3_ADDR[9]
set_location_assignment PIN_F25 -to HPS_DDR3_ADDR_9
set_location_assignment PIN_A24 -to HPS_DDR3_ADDR[10]
set_location_assignment PIN_A24 -to HPS_DDR3_ADDR_10
set_location_assignment PIN_B24 -to HPS_DDR3_ADDR[11]
set_location_assignment PIN_B24 -to HPS_DDR3_ADDR_11
set_location_assignment PIN_D24 -to HPS_DDR3_ADDR[12]
set_location_assignment PIN_D24 -to HPS_DDR3_ADDR_12
set_location_assignment PIN_C24 -to HPS_DDR3_ADDR[13]
set_location_assignment PIN_C24 -to HPS_DDR3_ADDR_13
set_location_assignment PIN_G23 -to HPS_DDR3_ADDR[14]
set_location_assignment PIN_G23 -to HPS_DDR3_ADDR_14
set_location_assignment PIN_A27 -to HPS_DDR3_BA[0]
set_location_assignment PIN_A27 -to HPS_DDR3_BA_0
set_location_assignment PIN_H25 -to HPS_DDR3_BA[1]
set_location_assignment PIN_H25 -to HPS_DDR3_BA_1
set_location_assignment PIN_G25 -to HPS_DDR3_BA[2]
set_location_assignment PIN_G25 -to HPS_DDR3_BA_2
set_location_assignment PIN_A26 -to HPS_DDR3_CAS_N
set_location_assignment PIN_L28 -to HPS_DDR3_CKE
set_location_assignment PIN_N20 -to HPS_DDR3_CK_N
set_location_assignment PIN_N21 -to HPS_DDR3_CK_P
set_location_assignment PIN_L21 -to HPS_DDR3_CS_N
set_location_assignment PIN_G28 -to HPS_DDR3_DM[0]
set_location_assignment PIN_G28 -to HPS_DDR3_DM_0
set_location_assignment PIN_P28 -to HPS_DDR3_DM[1]
set_location_assignment PIN_P28 -to HPS_DDR3_DM_1
set_location_assignment PIN_W28 -to HPS_DDR3_DM[2]
set_location_assignment PIN_W28 -to HPS_DDR3_DM_2
set_location_assignment PIN_AB28 -to HPS_DDR3_DM[3]
set_location_assignment PIN_AB28 -to HPS_DDR3_DM_3
set_location_assignment PIN_J25 -to HPS_DDR3_DQ[0]
set_location_assignment PIN_J25 -to HPS_DDR3_DQ_0
set_location_assignment PIN_J24 -to HPS_DDR3_DQ[1]
set_location_assignment PIN_J24 -to HPS_DDR3_DQ_1
set_location_assignment PIN_E28 -to HPS_DDR3_DQ[2]
set_location_assignment PIN_E28 -to HPS_DDR3_DQ_2
set_location_assignment PIN_D27 -to HPS_DDR3_DQ[3]
set_location_assignment PIN_D27 -to HPS_DDR3_DQ_3
set_location_assignment PIN_J26 -to HPS_DDR3_DQ[4]
set_location_assignment PIN_J26 -to HPS_DDR3_DQ_4
set_location_assignment PIN_K26 -to HPS_DDR3_DQ[5]
set_location_assignment PIN_K26 -to HPS_DDR3_DQ_5
set_location_assignment PIN_G27 -to HPS_DDR3_DQ[6]
set_location_assignment PIN_G27 -to HPS_DDR3_DQ_6
set_location_assignment PIN_F28 -to HPS_DDR3_DQ[7]
set_location_assignment PIN_F28 -to HPS_DDR3_DQ_7
set_location_assignment PIN_K25 -to HPS_DDR3_DQ[8]
set_location_assignment PIN_K25 -to HPS_DDR3_DQ_8
set_location_assignment PIN_L25 -to HPS_DDR3_DQ[9]
set_location_assignment PIN_L25 -to HPS_DDR3_DQ_9
set_location_assignment PIN_J27 -to HPS_DDR3_DQ[10]
set_location_assignment PIN_J27 -to HPS_DDR3_DQ_10
set_location_assignment PIN_J28 -to HPS_DDR3_DQ[11]
set_location_assignment PIN_J28 -to HPS_DDR3_DQ_11
set_location_assignment PIN_M27 -to HPS_DDR3_DQ[12]
set_location_assignment PIN_M27 -to HPS_DDR3_DQ_12
set_location_assignment PIN_M26 -to HPS_DDR3_DQ[13]
set_location_assignment PIN_M26 -to HPS_DDR3_DQ_13
set_location_assignment PIN_M28 -to HPS_DDR3_DQ[14]
set_location_assignment PIN_M28 -to HPS_DDR3_DQ_14
set_location_assignment PIN_N28 -to HPS_DDR3_DQ[15]
set_location_assignment PIN_N28 -to HPS_DDR3_DQ_15
set_location_assignment PIN_N24 -to HPS_DDR3_DQ[16]
set_location_assignment PIN_N24 -to HPS_DDR3_DQ_16
set_location_assignment PIN_N25 -to HPS_DDR3_DQ[17]
set_location_assignment PIN_N25 -to HPS_DDR3_DQ_17
set_location_assignment PIN_T28 -to HPS_DDR3_DQ[18]
set_location_assignment PIN_T28 -to HPS_DDR3_DQ_18
set_location_assignment PIN_U28 -to HPS_DDR3_DQ[19]
set_location_assignment PIN_U28 -to HPS_DDR3_DQ_19
set_location_assignment PIN_N26 -to HPS_DDR3_DQ[20]
set_location_assignment PIN_N26 -to HPS_DDR3_DQ_20
set_location_assignment PIN_N27 -to HPS_DDR3_DQ[21]
set_location_assignment PIN_N27 -to HPS_DDR3_DQ_21
set_location_assignment PIN_R27 -to HPS_DDR3_DQ[22]
set_location_assignment PIN_R27 -to HPS_DDR3_DQ_22
set_location_assignment PIN_V27 -to HPS_DDR3_DQ[23]
set_location_assignment PIN_V27 -to HPS_DDR3_DQ_23
set_location_assignment PIN_R26 -to HPS_DDR3_DQ[24]
set_location_assignment PIN_R26 -to HPS_DDR3_DQ_24
set_location_assignment PIN_R25 -to HPS_DDR3_DQ[25]
set_location_assignment PIN_R25 -to HPS_DDR3_DQ_25
set_location_assignment PIN_AA28 -to HPS_DDR3_DQ[26]
set_location_assignment PIN_AA28 -to HPS_DDR3_DQ_26
set_location_assignment PIN_W26 -to HPS_DDR3_DQ[27]
set_location_assignment PIN_W26 -to HPS_DDR3_DQ_27
set_location_assignment PIN_R24 -to HPS_DDR3_DQ[28]
set_location_assignment PIN_R24 -to HPS_DDR3_DQ_28
set_location_assignment PIN_T24 -to HPS_DDR3_DQ[29]
set_location_assignment PIN_T24 -to HPS_DDR3_DQ_29
set_location_assignment PIN_Y27 -to HPS_DDR3_DQ[30]
set_location_assignment PIN_Y27 -to HPS_DDR3_DQ_30
set_location_assignment PIN_AA27 -to HPS_DDR3_DQ[31]
set_location_assignment PIN_AA27 -to HPS_DDR3_DQ_31
set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N[0]
set_location_assignment PIN_R16 -to HPS_DDR3_DQS_N_0
set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N[1]
set_location_assignment PIN_R18 -to HPS_DDR3_DQS_N_1
set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N[2]
set_location_assignment PIN_T18 -to HPS_DDR3_DQS_N_2
set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N[3]
set_location_assignment PIN_T20 -to HPS_DDR3_DQS_N_3
set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P[0]
set_location_assignment PIN_R17 -to HPS_DDR3_DQS_P_0
set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P[1]
set_location_assignment PIN_R19 -to HPS_DDR3_DQS_P_1
set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P[2]
set_location_assignment PIN_T19 -to HPS_DDR3_DQS_P_2
set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P[3]
set_location_assignment PIN_U19 -to HPS_DDR3_DQS_P_3
set_location_assignment PIN_D28 -to HPS_DDR3_ODT
set_location_assignment PIN_A25 -to HPS_DDR3_RAS_N
set_location_assignment PIN_V28 -to HPS_DDR3_RESET_N
set_location_assignment PIN_D25 -to HPS_DDR3_RZQ
set_location_assignment PIN_E25 -to HPS_DDR3_WE_N
set_location_assignment PIN_J15 -to HPS_ENET_GTX_CLK
set_location_assignment PIN_B14 -to HPS_ENET_INT_N
set_location_assignment PIN_A13 -to HPS_ENET_MDC
set_location_assignment PIN_E16 -to HPS_ENET_MDIO
set_location_assignment PIN_J12 -to HPS_ENET_RX_CLK
set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA[0]
set_location_assignment PIN_A14 -to HPS_ENET_RX_DATA_0
set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA[1]
set_location_assignment PIN_A11 -to HPS_ENET_RX_DATA_1
set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA[2]
set_location_assignment PIN_C15 -to HPS_ENET_RX_DATA_2
set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA[3]
set_location_assignment PIN_A9 -to HPS_ENET_RX_DATA_3
set_location_assignment PIN_J13 -to HPS_ENET_RX_DV
set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA[0]
set_location_assignment PIN_A16 -to HPS_ENET_TX_DATA_0
set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA[1]
set_location_assignment PIN_J14 -to HPS_ENET_TX_DATA_1
set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA[2]
set_location_assignment PIN_A15 -to HPS_ENET_TX_DATA_2
set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA[3]
set_location_assignment PIN_D17 -to HPS_ENET_TX_DATA_3
set_location_assignment PIN_A12 -to HPS_ENET_TX_EN
set_location_assignment PIN_A17 -to HPS_GSENSOR_INT
set_location_assignment PIN_C18 -to HPS_I2C0_SCLK
set_location_assignment PIN_A19 -to HPS_I2C0_SDAT
set_location_assignment PIN_K18 -to HPS_I2C1_SCLK
set_location_assignment PIN_A21 -to HPS_I2C1_SDAT
set_location_assignment PIN_J18 -to HPS_KEY_N
set_location_assignment PIN_A20 -to HPS_LED
set_location_assignment PIN_H13 -to HPS_LTC_GPIO
set_location_assignment PIN_B8 -to HPS_SD_CLK
set_location_assignment PIN_D14 -to HPS_SD_CMD
set_location_assignment PIN_C13 -to HPS_SD_DATA[0]
set_location_assignment PIN_C13 -to HPS_SD_DATA_0
set_location_assignment PIN_B6 -to HPS_SD_DATA[1]
set_location_assignment PIN_B6 -to HPS_SD_DATA_1
set_location_assignment PIN_B11 -to HPS_SD_DATA[2]
set_location_assignment PIN_B11 -to HPS_SD_DATA_2
set_location_assignment PIN_B9 -to HPS_SD_DATA[3]
set_location_assignment PIN_B9 -to HPS_SD_DATA_3
set_location_assignment PIN_C19 -to HPS_SPIM_CLK
set_location_assignment PIN_B19 -to HPS_SPIM_MISO
set_location_assignment PIN_B16 -to HPS_SPIM_MOSI
set_location_assignment PIN_C16 -to HPS_SPIM_SS
set_location_assignment PIN_A22 -to HPS_UART_RX
set_location_assignment PIN_B21 -to HPS_UART_TX
set_location_assignment PIN_G4 -to HPS_USB_CLKOUT
set_location_assignment PIN_C10 -to HPS_USB_DATA[0]
set_location_assignment PIN_C10 -to HPS_USB_DATA_0
set_location_assignment PIN_F5 -to HPS_USB_DATA[1]
set_location_assignment PIN_F5 -to HPS_USB_DATA_1
set_location_assignment PIN_C9 -to HPS_USB_DATA[2]
set_location_assignment PIN_C9 -to HPS_USB_DATA_2
set_location_assignment PIN_C4 -to HPS_USB_DATA[3]
set_location_assignment PIN_C4 -to HPS_USB_DATA_3
set_location_assignment PIN_C8 -to HPS_USB_DATA[4]
set_location_assignment PIN_C8 -to HPS_USB_DATA_4
set_location_assignment PIN_D4 -to HPS_USB_DATA[5]
set_location_assignment PIN_D4 -to HPS_USB_DATA_5
set_location_assignment PIN_C7 -to HPS_USB_DATA[6]
set_location_assignment PIN_C7 -to HPS_USB_DATA_6
set_location_assignment PIN_F4 -to HPS_USB_DATA[7]
set_location_assignment PIN_F4 -to HPS_USB_DATA_7
set_location_assignment PIN_E5 -to HPS_USB_DIR
set_location_assignment PIN_D5 -to HPS_USB_NXT
set_location_assignment PIN_C5 -to HPS_USB_STP
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_1
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_2
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_3
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_4
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_5
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_6
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_7
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_8
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_9
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_10
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_11
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_12
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_13
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR_14
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_1
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA_2
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_1
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_2
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM_3
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_1
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_2
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_3
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_4
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_5
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_6
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_7
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_8
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_9
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_10
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_11
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_12
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_13
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_14
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_15
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_16
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_17
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_18
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_19
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_20
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_21
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_22
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_23
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_24
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_25
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_26
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_27
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_28
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_29
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_30
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ_31
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_1
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_2
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N_3
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_1
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_2
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
set_location_assignment PIN_AH17 -to KEY_N[0]
set_location_assignment PIN_AH17 -to KEY_N_0
set_location_assignment PIN_AH16 -to KEY_N[1]
set_location_assignment PIN_AH16 -to KEY_N_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY_N_1
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_W15 -to LED_0
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_AA24 -to LED_1
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V16 -to LED_2
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_V15 -to LED_3
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AF26 -to LED_4
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_AE26 -to LED_5
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_Y16 -to LED_6
set_location_assignment PIN_AA23 -to LED[7]
set_location_assignment PIN_AA23 -to LED_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_7
set_location_assignment PIN_L10 -to SW[0]
set_location_assignment PIN_L10 -to SW_0
set_location_assignment PIN_L9 -to SW[1]
set_location_assignment PIN_L9 -to SW_1
set_location_assignment PIN_H6 -to SW[2]
set_location_assignment PIN_H6 -to SW_2
set_location_assignment PIN_H5 -to SW[3]
set_location_assignment PIN_H5 -to SW_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW_3
set_location_assignment PIN_W12 -to GPIO_0_LT24_ADC_BUSY
set_location_assignment PIN_AF11 -to GPIO_0_LT24_ADC_CS_N
set_location_assignment PIN_Y8 -to GPIO_0_LT24_ADC_DCLK
set_location_assignment PIN_AF8 -to GPIO_0_LT24_ADC_DIN
set_location_assignment PIN_AF7 -to GPIO_0_LT24_ADC_DOUT
set_location_assignment PIN_V12 -to GPIO_0_LT24_ADC_PENIRQ_N
set_location_assignment PIN_AF6 -to GPIO_0_LT24_CS_N
set_location_assignment PIN_Y5 -to GPIO_0_LT24_D[0]
set_location_assignment PIN_Y5 -to GPIO_0_LT24_D_0
set_location_assignment PIN_Y4 -to GPIO_0_LT24_D[1]
set_location_assignment PIN_Y4 -to GPIO_0_LT24_D_1
set_location_assignment PIN_W8 -to GPIO_0_LT24_D[2]
set_location_assignment PIN_W8 -to GPIO_0_LT24_D_2
set_location_assignment PIN_AB4 -to GPIO_0_LT24_D[3]
set_location_assignment PIN_AB4 -to GPIO_0_LT24_D_3
set_location_assignment PIN_AH6 -to GPIO_0_LT24_D[4]
set_location_assignment PIN_AH6 -to GPIO_0_LT24_D_4
set_location_assignment PIN_AH4 -to GPIO_0_LT24_D[5]
set_location_assignment PIN_AH4 -to GPIO_0_LT24_D_5
set_location_assignment PIN_AG5 -to GPIO_0_LT24_D[6]
set_location_assignment PIN_AG5 -to GPIO_0_LT24_D_6
set_location_assignment PIN_AH3 -to GPIO_0_LT24_D[7]
set_location_assignment PIN_AH3 -to GPIO_0_LT24_D_7
set_location_assignment PIN_AH2 -to GPIO_0_LT24_D[8]
set_location_assignment PIN_AH2 -to GPIO_0_LT24_D_8
set_location_assignment PIN_AF4 -to GPIO_0_LT24_D[9]
set_location_assignment PIN_AF4 -to GPIO_0_LT24_D_9
set_location_assignment PIN_AG6 -to GPIO_0_LT24_D[10]
set_location_assignment PIN_AG6 -to GPIO_0_LT24_D_10
set_location_assignment PIN_AF5 -to GPIO_0_LT24_D[11]
set_location_assignment PIN_AF5 -to GPIO_0_LT24_D_11
set_location_assignment PIN_AE4 -to GPIO_0_LT24_D[12]
set_location_assignment PIN_AE4 -to GPIO_0_LT24_D_12
set_location_assignment PIN_T13 -to GPIO_0_LT24_D[13]
set_location_assignment PIN_T13 -to GPIO_0_LT24_D_13
set_location_assignment PIN_T11 -to GPIO_0_LT24_D[14]
set_location_assignment PIN_T11 -to GPIO_0_LT24_D_14
set_location_assignment PIN_AE7 -to GPIO_0_LT24_D[15]
set_location_assignment PIN_AE7 -to GPIO_0_LT24_D_15
set_location_assignment PIN_AE12 -to GPIO_0_LT24_LCD_ON
set_location_assignment PIN_T8 -to GPIO_0_LT24_RD_N
set_location_assignment PIN_AE11 -to GPIO_0_LT24_RESET_N
set_location_assignment PIN_AH5 -to GPIO_0_LT24_RS
set_location_assignment PIN_T12 -to GPIO_0_LT24_WR_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_ADC_BUSY
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_ADC_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_ADC_DCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_ADC_DIN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_ADC_DOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_ADC_PENIRQ_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_8
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_9
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_10
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_11
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_12
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_13
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_14
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_D_15
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_LCD_ON
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_RD_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_RESET_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_RS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_LT24_WR_N
set_location_assignment PIN_AG18 -to GPIO_1_D5M_D[0]
set_location_assignment PIN_AG18 -to GPIO_1_D5M_D_0
set_location_assignment PIN_AC23 -to GPIO_1_D5M_D[1]
set_location_assignment PIN_AC23 -to GPIO_1_D5M_D_1
set_location_assignment PIN_AF20 -to GPIO_1_D5M_D[2]
set_location_assignment PIN_AF20 -to GPIO_1_D5M_D_2
set_location_assignment PIN_AG19 -to GPIO_1_D5M_D[3]
set_location_assignment PIN_AG19 -to GPIO_1_D5M_D_3
set_location_assignment PIN_AG20 -to GPIO_1_D5M_D[4]
set_location_assignment PIN_AG20 -to GPIO_1_D5M_D_4
set_location_assignment PIN_AF21 -to GPIO_1_D5M_D[5]
set_location_assignment PIN_AF21 -to GPIO_1_D5M_D_5
set_location_assignment PIN_AE22 -to GPIO_1_D5M_D[6]
set_location_assignment PIN_AE22 -to GPIO_1_D5M_D_6
set_location_assignment PIN_AF23 -to GPIO_1_D5M_D[7]
set_location_assignment PIN_AF23 -to GPIO_1_D5M_D_7
set_location_assignment PIN_AH24 -to GPIO_1_D5M_D[8]
set_location_assignment PIN_AH24 -to GPIO_1_D5M_D_8
set_location_assignment PIN_AG26 -to GPIO_1_D5M_D[9]
set_location_assignment PIN_AG26 -to GPIO_1_D5M_D_9
set_location_assignment PIN_AH27 -to GPIO_1_D5M_D[10]
set_location_assignment PIN_AH27 -to GPIO_1_D5M_D_10
set_location_assignment PIN_AG28 -to GPIO_1_D5M_D[11]
set_location_assignment PIN_AG28 -to GPIO_1_D5M_D_11
set_location_assignment PIN_AD19 -to GPIO_1_D5M_FVAL
set_location_assignment PIN_AF18 -to GPIO_1_D5M_LVAL
set_location_assignment PIN_Y15 -to GPIO_1_D5M_PIXCLK
set_location_assignment PIN_AF25 -to GPIO_1_D5M_RESET_N
set_location_assignment PIN_AE24 -to GPIO_1_D5M_SCLK
set_location_assignment PIN_AE20 -to GPIO_1_D5M_SDATA
set_location_assignment PIN_AE19 -to GPIO_1_D5M_STROBE
set_location_assignment PIN_AG23 -to GPIO_1_D5M_TRIGGER
set_location_assignment PIN_AG24 -to GPIO_1_D5M_XCLKIN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_8
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_9
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_10
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_D_11
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_FVAL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_LVAL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_PIXCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_RESET_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_SDATA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_STROBE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_TRIGGER
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_D5M_XCLKIN
set_global_assignment -name QSYS_FILE system.qsys
set_global_assignment -name VHDL_FILE ../hdl/LCDController/PixTrans.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../hdl/LCDController/LCDDriver.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../hdl/LCDController/LCDAvalonMaster.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../hdl/LCDController/LCDController.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../hdl/LCDController/ClkGen.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../hdl/DE0_Nano_SoC_LT24_top_level.vhd -hdl_version VHDL_2008
set_global_assignment -name TCL_SCRIPT_FILE ../hdl/LCDController/LCDController_hw.tcl
set_global_assignment -name TCL_SCRIPT_FILE pin_assignment_DE0_Nano_SoC_TRDB_D5M_LT24.tcl
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

1219
cs473-es/lab3/hw/quartus/system.qsys Normal file
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87129
cs473-es/lab3/hw/quartus/system.sopcinfo Normal file
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