Disabled external gits

cs473-es/lab2/ch/hw/hdl/WS28XX/ClkGen.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity ClkGen is
+    generic (
+        F_OUT : natural; -- Hz
+        F_CLK : natural  -- Hz
+    );
+    port (
+        clk : in std_logic;
+        rst_n : in std_logic;
+        clk_o : out std_logic;
+        en : in std_logic
+    );
+end ClkGen;
+
+architecture Behavioral of ClkGen is
+    constant CNT_MAX : integer := integer(floor(real(F_CLK) / real(F_OUT))) - 1;
+    signal counter_reg, counter_next: integer range CNT_MAX downto 0;
+begin
+    counter_next <= CNT_MAX when counter_reg = 0 else counter_reg - 1;
+    process(clk, rst_n) begin
+        if rising_edge(clk) then
+            if rst_n = '0' then
+                counter_reg <= CNT_MAX;
+            else
+                if en = '1' then
+                    counter_reg <= counter_next;
+                end if;
+            end if;
+        end if;
+    end process;
+    clk_o <= '1' when counter_reg = 0 and en = '1' else '0';
+end Behavioral; -- Behavioral